1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * i.MX drm driver - Television Encoder (TVEv2)
4 *
5 * Copyright (C) 2013 Philipp Zabel, Pengutronix
6 */
7
8 #include <linux/clk-provider.h>
9 #include <linux/clk.h>
10 #include <linux/component.h>
11 #include <linux/i2c.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/videodev2.h>
17
18 #include <video/imx-ipu-v3.h>
19
20 #include <drm/drm_atomic_helper.h>
21 #include <drm/drm_fb_helper.h>
22 #include <drm/drm_managed.h>
23 #include <drm/drm_probe_helper.h>
24 #include <drm/drm_simple_kms_helper.h>
25
26 #include "imx-drm.h"
27
28 #define TVE_COM_CONF_REG 0x00
29 #define TVE_TVDAC0_CONT_REG 0x28
30 #define TVE_TVDAC1_CONT_REG 0x2c
31 #define TVE_TVDAC2_CONT_REG 0x30
32 #define TVE_CD_CONT_REG 0x34
33 #define TVE_INT_CONT_REG 0x64
34 #define TVE_STAT_REG 0x68
35 #define TVE_TST_MODE_REG 0x6c
36 #define TVE_MV_CONT_REG 0xdc
37
38 /* TVE_COM_CONF_REG */
39 #define TVE_SYNC_CH_2_EN BIT(22)
40 #define TVE_SYNC_CH_1_EN BIT(21)
41 #define TVE_SYNC_CH_0_EN BIT(20)
42 #define TVE_TV_OUT_MODE_MASK (0x7 << 12)
43 #define TVE_TV_OUT_DISABLE (0x0 << 12)
44 #define TVE_TV_OUT_CVBS_0 (0x1 << 12)
45 #define TVE_TV_OUT_CVBS_2 (0x2 << 12)
46 #define TVE_TV_OUT_CVBS_0_2 (0x3 << 12)
47 #define TVE_TV_OUT_SVIDEO_0_1 (0x4 << 12)
48 #define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2 (0x5 << 12)
49 #define TVE_TV_OUT_YPBPR (0x6 << 12)
50 #define TVE_TV_OUT_RGB (0x7 << 12)
51 #define TVE_TV_STAND_MASK (0xf << 8)
52 #define TVE_TV_STAND_HD_1080P30 (0xc << 8)
53 #define TVE_P2I_CONV_EN BIT(7)
54 #define TVE_INP_VIDEO_FORM BIT(6)
55 #define TVE_INP_YCBCR_422 (0x0 << 6)
56 #define TVE_INP_YCBCR_444 (0x1 << 6)
57 #define TVE_DATA_SOURCE_MASK (0x3 << 4)
58 #define TVE_DATA_SOURCE_BUS1 (0x0 << 4)
59 #define TVE_DATA_SOURCE_BUS2 (0x1 << 4)
60 #define TVE_DATA_SOURCE_EXT (0x2 << 4)
61 #define TVE_DATA_SOURCE_TESTGEN (0x3 << 4)
62 #define TVE_IPU_CLK_EN_OFS 3
63 #define TVE_IPU_CLK_EN BIT(3)
64 #define TVE_DAC_SAMP_RATE_OFS 1
65 #define TVE_DAC_SAMP_RATE_WIDTH 2
66 #define TVE_DAC_SAMP_RATE_MASK (0x3 << 1)
67 #define TVE_DAC_FULL_RATE (0x0 << 1)
68 #define TVE_DAC_DIV2_RATE (0x1 << 1)
69 #define TVE_DAC_DIV4_RATE (0x2 << 1)
70 #define TVE_EN BIT(0)
71
72 /* TVE_TVDACx_CONT_REG */
73 #define TVE_TVDAC_GAIN_MASK (0x3f << 0)
74
75 /* TVE_CD_CONT_REG */
76 #define TVE_CD_CH_2_SM_EN BIT(22)
77 #define TVE_CD_CH_1_SM_EN BIT(21)
78 #define TVE_CD_CH_0_SM_EN BIT(20)
79 #define TVE_CD_CH_2_LM_EN BIT(18)
80 #define TVE_CD_CH_1_LM_EN BIT(17)
81 #define TVE_CD_CH_0_LM_EN BIT(16)
82 #define TVE_CD_CH_2_REF_LVL BIT(10)
83 #define TVE_CD_CH_1_REF_LVL BIT(9)
84 #define TVE_CD_CH_0_REF_LVL BIT(8)
85 #define TVE_CD_EN BIT(0)
86
87 /* TVE_INT_CONT_REG */
88 #define TVE_FRAME_END_IEN BIT(13)
89 #define TVE_CD_MON_END_IEN BIT(2)
90 #define TVE_CD_SM_IEN BIT(1)
91 #define TVE_CD_LM_IEN BIT(0)
92
93 /* TVE_TST_MODE_REG */
94 #define TVE_TVDAC_TEST_MODE_MASK (0x7 << 0)
95
96 #define IMX_TVE_DAC_VOLTAGE 2750000
97
98 enum {
99 TVE_MODE_TVOUT,
100 TVE_MODE_VGA,
101 };
102
103 struct imx_tve_encoder {
104 struct drm_connector connector;
105 struct drm_encoder encoder;
106 struct imx_tve *tve;
107 };
108
109 struct imx_tve {
110 struct device *dev;
111 int mode;
112 int di_hsync_pin;
113 int di_vsync_pin;
114
115 struct regmap *regmap;
116 struct regulator *dac_reg;
117 struct i2c_adapter *ddc;
118 struct clk *clk;
119 struct clk *di_sel_clk;
120 struct clk_hw clk_hw_di;
121 struct clk *di_clk;
122 };
123
con_to_tve(struct drm_connector * c)124 static inline struct imx_tve *con_to_tve(struct drm_connector *c)
125 {
126 return container_of(c, struct imx_tve_encoder, connector)->tve;
127 }
128
enc_to_tve(struct drm_encoder * e)129 static inline struct imx_tve *enc_to_tve(struct drm_encoder *e)
130 {
131 return container_of(e, struct imx_tve_encoder, encoder)->tve;
132 }
133
tve_enable(struct imx_tve * tve)134 static void tve_enable(struct imx_tve *tve)
135 {
136 clk_prepare_enable(tve->clk);
137 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, TVE_EN);
138
139 /* clear interrupt status register */
140 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
141
142 /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */
143 if (tve->mode == TVE_MODE_VGA)
144 regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
145 else
146 regmap_write(tve->regmap, TVE_INT_CONT_REG,
147 TVE_CD_SM_IEN |
148 TVE_CD_LM_IEN |
149 TVE_CD_MON_END_IEN);
150 }
151
tve_disable(struct imx_tve * tve)152 static void tve_disable(struct imx_tve *tve)
153 {
154 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, 0);
155 clk_disable_unprepare(tve->clk);
156 }
157
tve_setup_tvout(struct imx_tve * tve)158 static int tve_setup_tvout(struct imx_tve *tve)
159 {
160 return -ENOTSUPP;
161 }
162
tve_setup_vga(struct imx_tve * tve)163 static int tve_setup_vga(struct imx_tve *tve)
164 {
165 unsigned int mask;
166 unsigned int val;
167 int ret;
168
169 /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */
170 ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
171 TVE_TVDAC_GAIN_MASK, 0x0a);
172 if (ret)
173 return ret;
174
175 ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
176 TVE_TVDAC_GAIN_MASK, 0x0a);
177 if (ret)
178 return ret;
179
180 ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
181 TVE_TVDAC_GAIN_MASK, 0x0a);
182 if (ret)
183 return ret;
184
185 /* set configuration register */
186 mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
187 val = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444;
188 mask |= TVE_TV_STAND_MASK | TVE_P2I_CONV_EN;
189 val |= TVE_TV_STAND_HD_1080P30 | 0;
190 mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
191 val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN;
192 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
193 if (ret)
194 return ret;
195
196 /* set test mode (as documented) */
197 return regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
198 TVE_TVDAC_TEST_MODE_MASK, 1);
199 }
200
imx_tve_connector_get_modes(struct drm_connector * connector)201 static int imx_tve_connector_get_modes(struct drm_connector *connector)
202 {
203 struct imx_tve *tve = con_to_tve(connector);
204 struct edid *edid;
205 int ret = 0;
206
207 if (!tve->ddc)
208 return 0;
209
210 edid = drm_get_edid(connector, tve->ddc);
211 if (edid) {
212 drm_connector_update_edid_property(connector, edid);
213 ret = drm_add_edid_modes(connector, edid);
214 kfree(edid);
215 }
216
217 return ret;
218 }
219
imx_tve_connector_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)220 static int imx_tve_connector_mode_valid(struct drm_connector *connector,
221 struct drm_display_mode *mode)
222 {
223 struct imx_tve *tve = con_to_tve(connector);
224 unsigned long rate;
225
226 /* pixel clock with 2x oversampling */
227 rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
228 if (rate == mode->clock)
229 return MODE_OK;
230
231 /* pixel clock without oversampling */
232 rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
233 if (rate == mode->clock)
234 return MODE_OK;
235
236 dev_warn(tve->dev, "ignoring mode %dx%d\n",
237 mode->hdisplay, mode->vdisplay);
238
239 return MODE_BAD;
240 }
241
imx_tve_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * orig_mode,struct drm_display_mode * mode)242 static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
243 struct drm_display_mode *orig_mode,
244 struct drm_display_mode *mode)
245 {
246 struct imx_tve *tve = enc_to_tve(encoder);
247 unsigned long rounded_rate;
248 unsigned long rate;
249 int div = 1;
250 int ret;
251
252 /*
253 * FIXME
254 * we should try 4k * mode->clock first,
255 * and enable 4x oversampling for lower resolutions
256 */
257 rate = 2000UL * mode->clock;
258 clk_set_rate(tve->clk, rate);
259 rounded_rate = clk_get_rate(tve->clk);
260 if (rounded_rate >= rate)
261 div = 2;
262 clk_set_rate(tve->di_clk, rounded_rate / div);
263
264 ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
265 if (ret < 0) {
266 dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
267 ret);
268 }
269
270 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
271 TVE_IPU_CLK_EN, TVE_IPU_CLK_EN);
272
273 if (tve->mode == TVE_MODE_VGA)
274 ret = tve_setup_vga(tve);
275 else
276 ret = tve_setup_tvout(tve);
277 if (ret)
278 dev_err(tve->dev, "failed to set configuration: %d\n", ret);
279 }
280
imx_tve_encoder_enable(struct drm_encoder * encoder)281 static void imx_tve_encoder_enable(struct drm_encoder *encoder)
282 {
283 struct imx_tve *tve = enc_to_tve(encoder);
284
285 tve_enable(tve);
286 }
287
imx_tve_encoder_disable(struct drm_encoder * encoder)288 static void imx_tve_encoder_disable(struct drm_encoder *encoder)
289 {
290 struct imx_tve *tve = enc_to_tve(encoder);
291
292 tve_disable(tve);
293 }
294
imx_tve_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)295 static int imx_tve_atomic_check(struct drm_encoder *encoder,
296 struct drm_crtc_state *crtc_state,
297 struct drm_connector_state *conn_state)
298 {
299 struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
300 struct imx_tve *tve = enc_to_tve(encoder);
301
302 imx_crtc_state->bus_format = MEDIA_BUS_FMT_GBR888_1X24;
303 imx_crtc_state->di_hsync_pin = tve->di_hsync_pin;
304 imx_crtc_state->di_vsync_pin = tve->di_vsync_pin;
305
306 return 0;
307 }
308
309 static const struct drm_connector_funcs imx_tve_connector_funcs = {
310 .fill_modes = drm_helper_probe_single_connector_modes,
311 .destroy = imx_drm_connector_destroy,
312 .reset = drm_atomic_helper_connector_reset,
313 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
314 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
315 };
316
317 static const struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
318 .get_modes = imx_tve_connector_get_modes,
319 .mode_valid = imx_tve_connector_mode_valid,
320 };
321
322 static const struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
323 .mode_set = imx_tve_encoder_mode_set,
324 .enable = imx_tve_encoder_enable,
325 .disable = imx_tve_encoder_disable,
326 .atomic_check = imx_tve_atomic_check,
327 };
328
imx_tve_irq_handler(int irq,void * data)329 static irqreturn_t imx_tve_irq_handler(int irq, void *data)
330 {
331 struct imx_tve *tve = data;
332 unsigned int val;
333
334 regmap_read(tve->regmap, TVE_STAT_REG, &val);
335
336 /* clear interrupt status register */
337 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
338
339 return IRQ_HANDLED;
340 }
341
clk_tve_di_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)342 static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
343 unsigned long parent_rate)
344 {
345 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
346 unsigned int val;
347 int ret;
348
349 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
350 if (ret < 0)
351 return 0;
352
353 switch (val & TVE_DAC_SAMP_RATE_MASK) {
354 case TVE_DAC_DIV4_RATE:
355 return parent_rate / 4;
356 case TVE_DAC_DIV2_RATE:
357 return parent_rate / 2;
358 case TVE_DAC_FULL_RATE:
359 default:
360 return parent_rate;
361 }
362
363 return 0;
364 }
365
clk_tve_di_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)366 static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
367 unsigned long *prate)
368 {
369 unsigned long div;
370
371 div = *prate / rate;
372 if (div >= 4)
373 return *prate / 4;
374 else if (div >= 2)
375 return *prate / 2;
376 return *prate;
377 }
378
clk_tve_di_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)379 static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
380 unsigned long parent_rate)
381 {
382 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
383 unsigned long div;
384 u32 val;
385 int ret;
386
387 div = parent_rate / rate;
388 if (div >= 4)
389 val = TVE_DAC_DIV4_RATE;
390 else if (div >= 2)
391 val = TVE_DAC_DIV2_RATE;
392 else
393 val = TVE_DAC_FULL_RATE;
394
395 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
396 TVE_DAC_SAMP_RATE_MASK, val);
397
398 if (ret < 0) {
399 dev_err(tve->dev, "failed to set divider: %d\n", ret);
400 return ret;
401 }
402
403 return 0;
404 }
405
406 static const struct clk_ops clk_tve_di_ops = {
407 .round_rate = clk_tve_di_round_rate,
408 .set_rate = clk_tve_di_set_rate,
409 .recalc_rate = clk_tve_di_recalc_rate,
410 };
411
tve_clk_init(struct imx_tve * tve,void __iomem * base)412 static int tve_clk_init(struct imx_tve *tve, void __iomem *base)
413 {
414 const char *tve_di_parent[1];
415 struct clk_init_data init = {
416 .name = "tve_di",
417 .ops = &clk_tve_di_ops,
418 .num_parents = 1,
419 .flags = 0,
420 };
421
422 tve_di_parent[0] = __clk_get_name(tve->clk);
423 init.parent_names = (const char **)&tve_di_parent;
424
425 tve->clk_hw_di.init = &init;
426 tve->di_clk = devm_clk_register(tve->dev, &tve->clk_hw_di);
427 if (IS_ERR(tve->di_clk)) {
428 dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
429 PTR_ERR(tve->di_clk));
430 return PTR_ERR(tve->di_clk);
431 }
432
433 return 0;
434 }
435
imx_tve_disable_regulator(void * data)436 static void imx_tve_disable_regulator(void *data)
437 {
438 struct imx_tve *tve = data;
439
440 regulator_disable(tve->dac_reg);
441 }
442
imx_tve_readable_reg(struct device * dev,unsigned int reg)443 static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
444 {
445 return (reg % 4 == 0) && (reg <= 0xdc);
446 }
447
448 static struct regmap_config tve_regmap_config = {
449 .reg_bits = 32,
450 .val_bits = 32,
451 .reg_stride = 4,
452
453 .readable_reg = imx_tve_readable_reg,
454
455 .fast_io = true,
456
457 .max_register = 0xdc,
458 };
459
460 static const char * const imx_tve_modes[] = {
461 [TVE_MODE_TVOUT] = "tvout",
462 [TVE_MODE_VGA] = "vga",
463 };
464
of_get_tve_mode(struct device_node * np)465 static int of_get_tve_mode(struct device_node *np)
466 {
467 const char *bm;
468 int ret, i;
469
470 ret = of_property_read_string(np, "fsl,tve-mode", &bm);
471 if (ret < 0)
472 return ret;
473
474 for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
475 if (!strcasecmp(bm, imx_tve_modes[i]))
476 return i;
477
478 return -EINVAL;
479 }
480
imx_tve_bind(struct device * dev,struct device * master,void * data)481 static int imx_tve_bind(struct device *dev, struct device *master, void *data)
482 {
483 struct drm_device *drm = data;
484 struct imx_tve *tve = dev_get_drvdata(dev);
485 struct imx_tve_encoder *tvee;
486 struct drm_encoder *encoder;
487 struct drm_connector *connector;
488 int encoder_type;
489 int ret;
490
491 encoder_type = tve->mode == TVE_MODE_VGA ?
492 DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
493
494 tvee = drmm_simple_encoder_alloc(drm, struct imx_tve_encoder, encoder,
495 encoder_type);
496 if (IS_ERR(tvee))
497 return PTR_ERR(tvee);
498
499 tvee->tve = tve;
500 encoder = &tvee->encoder;
501 connector = &tvee->connector;
502
503 ret = imx_drm_encoder_parse_of(drm, encoder, tve->dev->of_node);
504 if (ret)
505 return ret;
506
507 drm_encoder_helper_add(encoder, &imx_tve_encoder_helper_funcs);
508
509 drm_connector_helper_add(connector, &imx_tve_connector_helper_funcs);
510 ret = drm_connector_init_with_ddc(drm, connector,
511 &imx_tve_connector_funcs,
512 DRM_MODE_CONNECTOR_VGA, tve->ddc);
513 if (ret)
514 return ret;
515
516 return drm_connector_attach_encoder(connector, encoder);
517 }
518
519 static const struct component_ops imx_tve_ops = {
520 .bind = imx_tve_bind,
521 };
522
imx_tve_probe(struct platform_device * pdev)523 static int imx_tve_probe(struct platform_device *pdev)
524 {
525 struct device *dev = &pdev->dev;
526 struct device_node *np = dev->of_node;
527 struct device_node *ddc_node;
528 struct imx_tve *tve;
529 struct resource *res;
530 void __iomem *base;
531 unsigned int val;
532 int irq;
533 int ret;
534
535 tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
536 if (!tve)
537 return -ENOMEM;
538
539 tve->dev = dev;
540
541 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
542 if (ddc_node) {
543 tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
544 of_node_put(ddc_node);
545 }
546
547 tve->mode = of_get_tve_mode(np);
548 if (tve->mode != TVE_MODE_VGA) {
549 dev_err(dev, "only VGA mode supported, currently\n");
550 return -EINVAL;
551 }
552
553 if (tve->mode == TVE_MODE_VGA) {
554 ret = of_property_read_u32(np, "fsl,hsync-pin",
555 &tve->di_hsync_pin);
556
557 if (ret < 0) {
558 dev_err(dev, "failed to get hsync pin\n");
559 return ret;
560 }
561
562 ret = of_property_read_u32(np, "fsl,vsync-pin",
563 &tve->di_vsync_pin);
564
565 if (ret < 0) {
566 dev_err(dev, "failed to get vsync pin\n");
567 return ret;
568 }
569 }
570
571 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
572 base = devm_ioremap_resource(dev, res);
573 if (IS_ERR(base))
574 return PTR_ERR(base);
575
576 tve_regmap_config.lock_arg = tve;
577 tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
578 &tve_regmap_config);
579 if (IS_ERR(tve->regmap)) {
580 dev_err(dev, "failed to init regmap: %ld\n",
581 PTR_ERR(tve->regmap));
582 return PTR_ERR(tve->regmap);
583 }
584
585 irq = platform_get_irq(pdev, 0);
586 if (irq < 0)
587 return irq;
588
589 ret = devm_request_threaded_irq(dev, irq, NULL,
590 imx_tve_irq_handler, IRQF_ONESHOT,
591 "imx-tve", tve);
592 if (ret < 0) {
593 dev_err(dev, "failed to request irq: %d\n", ret);
594 return ret;
595 }
596
597 tve->dac_reg = devm_regulator_get(dev, "dac");
598 if (!IS_ERR(tve->dac_reg)) {
599 if (regulator_get_voltage(tve->dac_reg) != IMX_TVE_DAC_VOLTAGE)
600 dev_warn(dev, "dac voltage is not %d uV\n", IMX_TVE_DAC_VOLTAGE);
601 ret = regulator_enable(tve->dac_reg);
602 if (ret)
603 return ret;
604 ret = devm_add_action_or_reset(dev, imx_tve_disable_regulator, tve);
605 if (ret)
606 return ret;
607 }
608
609 tve->clk = devm_clk_get(dev, "tve");
610 if (IS_ERR(tve->clk)) {
611 dev_err(dev, "failed to get high speed tve clock: %ld\n",
612 PTR_ERR(tve->clk));
613 return PTR_ERR(tve->clk);
614 }
615
616 /* this is the IPU DI clock input selector, can be parented to tve_di */
617 tve->di_sel_clk = devm_clk_get(dev, "di_sel");
618 if (IS_ERR(tve->di_sel_clk)) {
619 dev_err(dev, "failed to get ipu di mux clock: %ld\n",
620 PTR_ERR(tve->di_sel_clk));
621 return PTR_ERR(tve->di_sel_clk);
622 }
623
624 ret = tve_clk_init(tve, base);
625 if (ret < 0)
626 return ret;
627
628 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
629 if (ret < 0) {
630 dev_err(dev, "failed to read configuration register: %d\n",
631 ret);
632 return ret;
633 }
634 if (val != 0x00100000) {
635 dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
636 return -ENODEV;
637 }
638
639 /* disable cable detection for VGA mode */
640 ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
641 if (ret)
642 return ret;
643
644 platform_set_drvdata(pdev, tve);
645
646 return component_add(dev, &imx_tve_ops);
647 }
648
imx_tve_remove(struct platform_device * pdev)649 static int imx_tve_remove(struct platform_device *pdev)
650 {
651 component_del(&pdev->dev, &imx_tve_ops);
652 return 0;
653 }
654
655 static const struct of_device_id imx_tve_dt_ids[] = {
656 { .compatible = "fsl,imx53-tve", },
657 { /* sentinel */ }
658 };
659 MODULE_DEVICE_TABLE(of, imx_tve_dt_ids);
660
661 static struct platform_driver imx_tve_driver = {
662 .probe = imx_tve_probe,
663 .remove = imx_tve_remove,
664 .driver = {
665 .of_match_table = imx_tve_dt_ids,
666 .name = "imx-tve",
667 },
668 };
669
670 module_platform_driver(imx_tve_driver);
671
672 MODULE_DESCRIPTION("i.MX Television Encoder driver");
673 MODULE_AUTHOR("Philipp Zabel, Pengutronix");
674 MODULE_LICENSE("GPL");
675 MODULE_ALIAS("platform:imx-tve");
676