1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2016 Broadcom
4 */
5
6 /**
7 * DOC: VC4 SDTV module
8 *
9 * The VEC encoder generates PAL or NTSC composite video output.
10 *
11 * TV mode selection is done by an atomic property on the encoder,
12 * because a drm_mode_modeinfo is insufficient to distinguish between
13 * PAL and PAL-M or NTSC and NTSC-J.
14 */
15
16 #include <drm/drm_atomic_helper.h>
17 #include <drm/drm_edid.h>
18 #include <drm/drm_panel.h>
19 #include <drm/drm_probe_helper.h>
20 #include <drm/drm_simple_kms_helper.h>
21 #include <linux/clk.h>
22 #include <linux/component.h>
23 #include <linux/of_graph.h>
24 #include <linux/of_platform.h>
25 #include <linux/pm_runtime.h>
26
27 #include "vc4_drv.h"
28 #include "vc4_regs.h"
29
30 /* WSE Registers */
31 #define VEC_WSE_RESET 0xc0
32
33 #define VEC_WSE_CONTROL 0xc4
34 #define VEC_WSE_WSS_ENABLE BIT(7)
35
36 #define VEC_WSE_WSS_DATA 0xc8
37 #define VEC_WSE_VPS_DATA1 0xcc
38 #define VEC_WSE_VPS_CONTROL 0xd0
39
40 /* VEC Registers */
41 #define VEC_REVID 0x100
42
43 #define VEC_CONFIG0 0x104
44 #define VEC_CONFIG0_YDEL_MASK GENMASK(28, 26)
45 #define VEC_CONFIG0_YDEL(x) ((x) << 26)
46 #define VEC_CONFIG0_CDEL_MASK GENMASK(25, 24)
47 #define VEC_CONFIG0_CDEL(x) ((x) << 24)
48 #define VEC_CONFIG0_PBPR_FIL BIT(18)
49 #define VEC_CONFIG0_CHROMA_GAIN_MASK GENMASK(17, 16)
50 #define VEC_CONFIG0_CHROMA_GAIN_UNITY (0 << 16)
51 #define VEC_CONFIG0_CHROMA_GAIN_1_32 (1 << 16)
52 #define VEC_CONFIG0_CHROMA_GAIN_1_16 (2 << 16)
53 #define VEC_CONFIG0_CHROMA_GAIN_1_8 (3 << 16)
54 #define VEC_CONFIG0_CBURST_GAIN_MASK GENMASK(14, 13)
55 #define VEC_CONFIG0_CBURST_GAIN_UNITY (0 << 13)
56 #define VEC_CONFIG0_CBURST_GAIN_1_128 (1 << 13)
57 #define VEC_CONFIG0_CBURST_GAIN_1_64 (2 << 13)
58 #define VEC_CONFIG0_CBURST_GAIN_1_32 (3 << 13)
59 #define VEC_CONFIG0_CHRBW1 BIT(11)
60 #define VEC_CONFIG0_CHRBW0 BIT(10)
61 #define VEC_CONFIG0_SYNCDIS BIT(9)
62 #define VEC_CONFIG0_BURDIS BIT(8)
63 #define VEC_CONFIG0_CHRDIS BIT(7)
64 #define VEC_CONFIG0_PDEN BIT(6)
65 #define VEC_CONFIG0_YCDELAY BIT(4)
66 #define VEC_CONFIG0_RAMPEN BIT(2)
67 #define VEC_CONFIG0_YCDIS BIT(2)
68 #define VEC_CONFIG0_STD_MASK GENMASK(1, 0)
69 #define VEC_CONFIG0_NTSC_STD 0
70 #define VEC_CONFIG0_PAL_BDGHI_STD 1
71 #define VEC_CONFIG0_PAL_N_STD 3
72
73 #define VEC_SCHPH 0x108
74 #define VEC_SOFT_RESET 0x10c
75 #define VEC_CLMP0_START 0x144
76 #define VEC_CLMP0_END 0x148
77 #define VEC_FREQ3_2 0x180
78 #define VEC_FREQ1_0 0x184
79
80 #define VEC_CONFIG1 0x188
81 #define VEC_CONFIG_VEC_RESYNC_OFF BIT(18)
82 #define VEC_CONFIG_RGB219 BIT(17)
83 #define VEC_CONFIG_CBAR_EN BIT(16)
84 #define VEC_CONFIG_TC_OBB BIT(15)
85 #define VEC_CONFIG1_OUTPUT_MODE_MASK GENMASK(12, 10)
86 #define VEC_CONFIG1_C_Y_CVBS (0 << 10)
87 #define VEC_CONFIG1_CVBS_Y_C (1 << 10)
88 #define VEC_CONFIG1_PR_Y_PB (2 << 10)
89 #define VEC_CONFIG1_RGB (4 << 10)
90 #define VEC_CONFIG1_Y_C_CVBS (5 << 10)
91 #define VEC_CONFIG1_C_CVBS_Y (6 << 10)
92 #define VEC_CONFIG1_C_CVBS_CVBS (7 << 10)
93 #define VEC_CONFIG1_DIS_CHR BIT(9)
94 #define VEC_CONFIG1_DIS_LUMA BIT(8)
95 #define VEC_CONFIG1_YCBCR_IN BIT(6)
96 #define VEC_CONFIG1_DITHER_TYPE_LFSR 0
97 #define VEC_CONFIG1_DITHER_TYPE_COUNTER BIT(5)
98 #define VEC_CONFIG1_DITHER_EN BIT(4)
99 #define VEC_CONFIG1_CYDELAY BIT(3)
100 #define VEC_CONFIG1_LUMADIS BIT(2)
101 #define VEC_CONFIG1_COMPDIS BIT(1)
102 #define VEC_CONFIG1_CUSTOM_FREQ BIT(0)
103
104 #define VEC_CONFIG2 0x18c
105 #define VEC_CONFIG2_PROG_SCAN BIT(15)
106 #define VEC_CONFIG2_SYNC_ADJ_MASK GENMASK(14, 12)
107 #define VEC_CONFIG2_SYNC_ADJ(x) (((x) / 2) << 12)
108 #define VEC_CONFIG2_PBPR_EN BIT(10)
109 #define VEC_CONFIG2_UV_DIG_DIS BIT(6)
110 #define VEC_CONFIG2_RGB_DIG_DIS BIT(5)
111 #define VEC_CONFIG2_TMUX_MASK GENMASK(3, 2)
112 #define VEC_CONFIG2_TMUX_DRIVE0 (0 << 2)
113 #define VEC_CONFIG2_TMUX_RG_COMP (1 << 2)
114 #define VEC_CONFIG2_TMUX_UV_YC (2 << 2)
115 #define VEC_CONFIG2_TMUX_SYNC_YC (3 << 2)
116
117 #define VEC_INTERRUPT_CONTROL 0x190
118 #define VEC_INTERRUPT_STATUS 0x194
119 #define VEC_FCW_SECAM_B 0x198
120 #define VEC_SECAM_GAIN_VAL 0x19c
121
122 #define VEC_CONFIG3 0x1a0
123 #define VEC_CONFIG3_HORIZ_LEN_STD (0 << 0)
124 #define VEC_CONFIG3_HORIZ_LEN_MPEG1_SIF (1 << 0)
125 #define VEC_CONFIG3_SHAPE_NON_LINEAR BIT(1)
126
127 #define VEC_STATUS0 0x200
128 #define VEC_MASK0 0x204
129
130 #define VEC_CFG 0x208
131 #define VEC_CFG_SG_MODE_MASK GENMASK(6, 5)
132 #define VEC_CFG_SG_MODE(x) ((x) << 5)
133 #define VEC_CFG_SG_EN BIT(4)
134 #define VEC_CFG_VEC_EN BIT(3)
135 #define VEC_CFG_MB_EN BIT(2)
136 #define VEC_CFG_ENABLE BIT(1)
137 #define VEC_CFG_TB_EN BIT(0)
138
139 #define VEC_DAC_TEST 0x20c
140
141 #define VEC_DAC_CONFIG 0x210
142 #define VEC_DAC_CONFIG_LDO_BIAS_CTRL(x) ((x) << 24)
143 #define VEC_DAC_CONFIG_DRIVER_CTRL(x) ((x) << 16)
144 #define VEC_DAC_CONFIG_DAC_CTRL(x) (x)
145
146 #define VEC_DAC_MISC 0x214
147 #define VEC_DAC_MISC_VCD_CTRL_MASK GENMASK(31, 16)
148 #define VEC_DAC_MISC_VCD_CTRL(x) ((x) << 16)
149 #define VEC_DAC_MISC_VID_ACT BIT(8)
150 #define VEC_DAC_MISC_VCD_PWRDN BIT(6)
151 #define VEC_DAC_MISC_BIAS_PWRDN BIT(5)
152 #define VEC_DAC_MISC_DAC_PWRDN BIT(2)
153 #define VEC_DAC_MISC_LDO_PWRDN BIT(1)
154 #define VEC_DAC_MISC_DAC_RST_N BIT(0)
155
156
157 /* General VEC hardware state. */
158 struct vc4_vec {
159 struct platform_device *pdev;
160
161 struct drm_encoder *encoder;
162 struct drm_connector *connector;
163
164 void __iomem *regs;
165
166 struct clk *clock;
167
168 const struct vc4_vec_tv_mode *tv_mode;
169
170 struct debugfs_regset32 regset;
171 };
172
173 #define VEC_READ(offset) readl(vec->regs + (offset))
174 #define VEC_WRITE(offset, val) writel(val, vec->regs + (offset))
175
176 /* VC4 VEC encoder KMS struct */
177 struct vc4_vec_encoder {
178 struct vc4_encoder base;
179 struct vc4_vec *vec;
180 };
181
182 static inline struct vc4_vec_encoder *
to_vc4_vec_encoder(struct drm_encoder * encoder)183 to_vc4_vec_encoder(struct drm_encoder *encoder)
184 {
185 return container_of(encoder, struct vc4_vec_encoder, base.base);
186 }
187
188 /* VC4 VEC connector KMS struct */
189 struct vc4_vec_connector {
190 struct drm_connector base;
191 struct vc4_vec *vec;
192
193 /* Since the connector is attached to just the one encoder,
194 * this is the reference to it so we can do the best_encoder()
195 * hook.
196 */
197 struct drm_encoder *encoder;
198 };
199
200 enum vc4_vec_tv_mode_id {
201 VC4_VEC_TV_MODE_NTSC,
202 VC4_VEC_TV_MODE_NTSC_J,
203 VC4_VEC_TV_MODE_PAL,
204 VC4_VEC_TV_MODE_PAL_M,
205 };
206
207 struct vc4_vec_tv_mode {
208 const struct drm_display_mode *mode;
209 void (*mode_set)(struct vc4_vec *vec);
210 };
211
212 static const struct debugfs_reg32 vec_regs[] = {
213 VC4_REG32(VEC_WSE_CONTROL),
214 VC4_REG32(VEC_WSE_WSS_DATA),
215 VC4_REG32(VEC_WSE_VPS_DATA1),
216 VC4_REG32(VEC_WSE_VPS_CONTROL),
217 VC4_REG32(VEC_REVID),
218 VC4_REG32(VEC_CONFIG0),
219 VC4_REG32(VEC_SCHPH),
220 VC4_REG32(VEC_CLMP0_START),
221 VC4_REG32(VEC_CLMP0_END),
222 VC4_REG32(VEC_FREQ3_2),
223 VC4_REG32(VEC_FREQ1_0),
224 VC4_REG32(VEC_CONFIG1),
225 VC4_REG32(VEC_CONFIG2),
226 VC4_REG32(VEC_INTERRUPT_CONTROL),
227 VC4_REG32(VEC_INTERRUPT_STATUS),
228 VC4_REG32(VEC_FCW_SECAM_B),
229 VC4_REG32(VEC_SECAM_GAIN_VAL),
230 VC4_REG32(VEC_CONFIG3),
231 VC4_REG32(VEC_STATUS0),
232 VC4_REG32(VEC_MASK0),
233 VC4_REG32(VEC_CFG),
234 VC4_REG32(VEC_DAC_TEST),
235 VC4_REG32(VEC_DAC_CONFIG),
236 VC4_REG32(VEC_DAC_MISC),
237 };
238
vc4_vec_ntsc_mode_set(struct vc4_vec * vec)239 static void vc4_vec_ntsc_mode_set(struct vc4_vec *vec)
240 {
241 VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN);
242 VEC_WRITE(VEC_CONFIG1, VEC_CONFIG1_C_CVBS_CVBS);
243 }
244
vc4_vec_ntsc_j_mode_set(struct vc4_vec * vec)245 static void vc4_vec_ntsc_j_mode_set(struct vc4_vec *vec)
246 {
247 VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_NTSC_STD);
248 VEC_WRITE(VEC_CONFIG1, VEC_CONFIG1_C_CVBS_CVBS);
249 }
250
251 static const struct drm_display_mode ntsc_mode = {
252 DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 13500,
253 720, 720 + 14, 720 + 14 + 64, 720 + 14 + 64 + 60, 0,
254 480, 480 + 3, 480 + 3 + 3, 480 + 3 + 3 + 16, 0,
255 DRM_MODE_FLAG_INTERLACE)
256 };
257
vc4_vec_pal_mode_set(struct vc4_vec * vec)258 static void vc4_vec_pal_mode_set(struct vc4_vec *vec)
259 {
260 VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_PAL_BDGHI_STD);
261 VEC_WRITE(VEC_CONFIG1, VEC_CONFIG1_C_CVBS_CVBS);
262 }
263
vc4_vec_pal_m_mode_set(struct vc4_vec * vec)264 static void vc4_vec_pal_m_mode_set(struct vc4_vec *vec)
265 {
266 VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_PAL_BDGHI_STD);
267 VEC_WRITE(VEC_CONFIG1,
268 VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ);
269 VEC_WRITE(VEC_FREQ3_2, 0x223b);
270 VEC_WRITE(VEC_FREQ1_0, 0x61d1);
271 }
272
273 static const struct drm_display_mode pal_mode = {
274 DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 13500,
275 720, 720 + 20, 720 + 20 + 64, 720 + 20 + 64 + 60, 0,
276 576, 576 + 2, 576 + 2 + 3, 576 + 2 + 3 + 20, 0,
277 DRM_MODE_FLAG_INTERLACE)
278 };
279
280 static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = {
281 [VC4_VEC_TV_MODE_NTSC] = {
282 .mode = &ntsc_mode,
283 .mode_set = vc4_vec_ntsc_mode_set,
284 },
285 [VC4_VEC_TV_MODE_NTSC_J] = {
286 .mode = &ntsc_mode,
287 .mode_set = vc4_vec_ntsc_j_mode_set,
288 },
289 [VC4_VEC_TV_MODE_PAL] = {
290 .mode = &pal_mode,
291 .mode_set = vc4_vec_pal_mode_set,
292 },
293 [VC4_VEC_TV_MODE_PAL_M] = {
294 .mode = &pal_mode,
295 .mode_set = vc4_vec_pal_m_mode_set,
296 },
297 };
298
299 static enum drm_connector_status
vc4_vec_connector_detect(struct drm_connector * connector,bool force)300 vc4_vec_connector_detect(struct drm_connector *connector, bool force)
301 {
302 return connector_status_unknown;
303 }
304
vc4_vec_connector_destroy(struct drm_connector * connector)305 static void vc4_vec_connector_destroy(struct drm_connector *connector)
306 {
307 drm_connector_unregister(connector);
308 drm_connector_cleanup(connector);
309 }
310
vc4_vec_connector_get_modes(struct drm_connector * connector)311 static int vc4_vec_connector_get_modes(struct drm_connector *connector)
312 {
313 struct drm_connector_state *state = connector->state;
314 struct drm_display_mode *mode;
315
316 mode = drm_mode_duplicate(connector->dev,
317 vc4_vec_tv_modes[state->tv.mode].mode);
318 if (!mode) {
319 DRM_ERROR("Failed to create a new display mode\n");
320 return -ENOMEM;
321 }
322
323 drm_mode_probed_add(connector, mode);
324
325 return 1;
326 }
327
328 static const struct drm_connector_funcs vc4_vec_connector_funcs = {
329 .detect = vc4_vec_connector_detect,
330 .fill_modes = drm_helper_probe_single_connector_modes,
331 .destroy = vc4_vec_connector_destroy,
332 .reset = drm_atomic_helper_connector_reset,
333 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
334 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
335 };
336
337 static const struct drm_connector_helper_funcs vc4_vec_connector_helper_funcs = {
338 .get_modes = vc4_vec_connector_get_modes,
339 };
340
vc4_vec_connector_init(struct drm_device * dev,struct vc4_vec * vec)341 static struct drm_connector *vc4_vec_connector_init(struct drm_device *dev,
342 struct vc4_vec *vec)
343 {
344 struct drm_connector *connector = NULL;
345 struct vc4_vec_connector *vec_connector;
346
347 vec_connector = devm_kzalloc(dev->dev, sizeof(*vec_connector),
348 GFP_KERNEL);
349 if (!vec_connector)
350 return ERR_PTR(-ENOMEM);
351
352 connector = &vec_connector->base;
353 connector->interlace_allowed = true;
354
355 vec_connector->encoder = vec->encoder;
356 vec_connector->vec = vec;
357
358 drm_connector_init(dev, connector, &vc4_vec_connector_funcs,
359 DRM_MODE_CONNECTOR_Composite);
360 drm_connector_helper_add(connector, &vc4_vec_connector_helper_funcs);
361
362 drm_object_attach_property(&connector->base,
363 dev->mode_config.tv_mode_property,
364 VC4_VEC_TV_MODE_NTSC);
365 vec->tv_mode = &vc4_vec_tv_modes[VC4_VEC_TV_MODE_NTSC];
366
367 drm_connector_attach_encoder(connector, vec->encoder);
368
369 return connector;
370 }
371
vc4_vec_encoder_disable(struct drm_encoder * encoder)372 static void vc4_vec_encoder_disable(struct drm_encoder *encoder)
373 {
374 struct vc4_vec_encoder *vc4_vec_encoder = to_vc4_vec_encoder(encoder);
375 struct vc4_vec *vec = vc4_vec_encoder->vec;
376 int ret;
377
378 VEC_WRITE(VEC_CFG, 0);
379 VEC_WRITE(VEC_DAC_MISC,
380 VEC_DAC_MISC_VCD_PWRDN |
381 VEC_DAC_MISC_BIAS_PWRDN |
382 VEC_DAC_MISC_DAC_PWRDN |
383 VEC_DAC_MISC_LDO_PWRDN);
384
385 clk_disable_unprepare(vec->clock);
386
387 ret = pm_runtime_put(&vec->pdev->dev);
388 if (ret < 0) {
389 DRM_ERROR("Failed to release power domain: %d\n", ret);
390 return;
391 }
392 }
393
vc4_vec_encoder_enable(struct drm_encoder * encoder)394 static void vc4_vec_encoder_enable(struct drm_encoder *encoder)
395 {
396 struct vc4_vec_encoder *vc4_vec_encoder = to_vc4_vec_encoder(encoder);
397 struct vc4_vec *vec = vc4_vec_encoder->vec;
398 int ret;
399
400 ret = pm_runtime_get_sync(&vec->pdev->dev);
401 if (ret < 0) {
402 DRM_ERROR("Failed to retain power domain: %d\n", ret);
403 return;
404 }
405
406 /*
407 * We need to set the clock rate each time we enable the encoder
408 * because there's a chance we share the same parent with the HDMI
409 * clock, and both drivers are requesting different rates.
410 * The good news is, these 2 encoders cannot be enabled at the same
411 * time, thus preventing incompatible rate requests.
412 */
413 ret = clk_set_rate(vec->clock, 108000000);
414 if (ret) {
415 DRM_ERROR("Failed to set clock rate: %d\n", ret);
416 return;
417 }
418
419 ret = clk_prepare_enable(vec->clock);
420 if (ret) {
421 DRM_ERROR("Failed to turn on core clock: %d\n", ret);
422 return;
423 }
424
425 /* Reset the different blocks */
426 VEC_WRITE(VEC_WSE_RESET, 1);
427 VEC_WRITE(VEC_SOFT_RESET, 1);
428
429 /* Disable the CGSM-A and WSE blocks */
430 VEC_WRITE(VEC_WSE_CONTROL, 0);
431
432 /* Write config common to all modes. */
433
434 /*
435 * Color subcarrier phase: phase = 360 * SCHPH / 256.
436 * 0x28 <=> 39.375 deg.
437 */
438 VEC_WRITE(VEC_SCHPH, 0x28);
439
440 /*
441 * Reset to default values.
442 */
443 VEC_WRITE(VEC_CLMP0_START, 0xac);
444 VEC_WRITE(VEC_CLMP0_END, 0xec);
445 VEC_WRITE(VEC_CONFIG2,
446 VEC_CONFIG2_UV_DIG_DIS | VEC_CONFIG2_RGB_DIG_DIS);
447 VEC_WRITE(VEC_CONFIG3, VEC_CONFIG3_HORIZ_LEN_STD);
448 VEC_WRITE(VEC_DAC_CONFIG,
449 VEC_DAC_CONFIG_DAC_CTRL(0xc) |
450 VEC_DAC_CONFIG_DRIVER_CTRL(0xc) |
451 VEC_DAC_CONFIG_LDO_BIAS_CTRL(0x46));
452
453 /* Mask all interrupts. */
454 VEC_WRITE(VEC_MASK0, 0);
455
456 vec->tv_mode->mode_set(vec);
457
458 VEC_WRITE(VEC_DAC_MISC,
459 VEC_DAC_MISC_VID_ACT | VEC_DAC_MISC_DAC_RST_N);
460 VEC_WRITE(VEC_CFG, VEC_CFG_VEC_EN);
461 }
462
463
vc4_vec_encoder_mode_fixup(struct drm_encoder * encoder,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)464 static bool vc4_vec_encoder_mode_fixup(struct drm_encoder *encoder,
465 const struct drm_display_mode *mode,
466 struct drm_display_mode *adjusted_mode)
467 {
468 return true;
469 }
470
vc4_vec_encoder_atomic_mode_set(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)471 static void vc4_vec_encoder_atomic_mode_set(struct drm_encoder *encoder,
472 struct drm_crtc_state *crtc_state,
473 struct drm_connector_state *conn_state)
474 {
475 struct vc4_vec_encoder *vc4_vec_encoder = to_vc4_vec_encoder(encoder);
476 struct vc4_vec *vec = vc4_vec_encoder->vec;
477
478 vec->tv_mode = &vc4_vec_tv_modes[conn_state->tv.mode];
479 }
480
vc4_vec_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)481 static int vc4_vec_encoder_atomic_check(struct drm_encoder *encoder,
482 struct drm_crtc_state *crtc_state,
483 struct drm_connector_state *conn_state)
484 {
485 const struct vc4_vec_tv_mode *vec_mode;
486
487 vec_mode = &vc4_vec_tv_modes[conn_state->tv.mode];
488
489 if (conn_state->crtc &&
490 !drm_mode_equal(vec_mode->mode, &crtc_state->adjusted_mode))
491 return -EINVAL;
492
493 return 0;
494 }
495
496 static const struct drm_encoder_helper_funcs vc4_vec_encoder_helper_funcs = {
497 .disable = vc4_vec_encoder_disable,
498 .enable = vc4_vec_encoder_enable,
499 .mode_fixup = vc4_vec_encoder_mode_fixup,
500 .atomic_check = vc4_vec_encoder_atomic_check,
501 .atomic_mode_set = vc4_vec_encoder_atomic_mode_set,
502 };
503
504 static const struct of_device_id vc4_vec_dt_match[] = {
505 { .compatible = "brcm,bcm2835-vec", .data = NULL },
506 { /* sentinel */ },
507 };
508
509 static const char * const tv_mode_names[] = {
510 [VC4_VEC_TV_MODE_NTSC] = "NTSC",
511 [VC4_VEC_TV_MODE_NTSC_J] = "NTSC-J",
512 [VC4_VEC_TV_MODE_PAL] = "PAL",
513 [VC4_VEC_TV_MODE_PAL_M] = "PAL-M",
514 };
515
vc4_vec_bind(struct device * dev,struct device * master,void * data)516 static int vc4_vec_bind(struct device *dev, struct device *master, void *data)
517 {
518 struct platform_device *pdev = to_platform_device(dev);
519 struct drm_device *drm = dev_get_drvdata(master);
520 struct vc4_dev *vc4 = to_vc4_dev(drm);
521 struct vc4_vec *vec;
522 struct vc4_vec_encoder *vc4_vec_encoder;
523 int ret;
524
525 ret = drm_mode_create_tv_properties(drm, ARRAY_SIZE(tv_mode_names),
526 tv_mode_names);
527 if (ret)
528 return ret;
529
530 vec = devm_kzalloc(dev, sizeof(*vec), GFP_KERNEL);
531 if (!vec)
532 return -ENOMEM;
533
534 vc4_vec_encoder = devm_kzalloc(dev, sizeof(*vc4_vec_encoder),
535 GFP_KERNEL);
536 if (!vc4_vec_encoder)
537 return -ENOMEM;
538 vc4_vec_encoder->base.type = VC4_ENCODER_TYPE_VEC;
539 vc4_vec_encoder->vec = vec;
540 vec->encoder = &vc4_vec_encoder->base.base;
541
542 vec->pdev = pdev;
543 vec->regs = vc4_ioremap_regs(pdev, 0);
544 if (IS_ERR(vec->regs))
545 return PTR_ERR(vec->regs);
546 vec->regset.base = vec->regs;
547 vec->regset.regs = vec_regs;
548 vec->regset.nregs = ARRAY_SIZE(vec_regs);
549
550 vec->clock = devm_clk_get(dev, NULL);
551 if (IS_ERR(vec->clock)) {
552 ret = PTR_ERR(vec->clock);
553 if (ret != -EPROBE_DEFER)
554 DRM_ERROR("Failed to get clock: %d\n", ret);
555 return ret;
556 }
557
558 pm_runtime_enable(dev);
559
560 drm_simple_encoder_init(drm, vec->encoder, DRM_MODE_ENCODER_TVDAC);
561 drm_encoder_helper_add(vec->encoder, &vc4_vec_encoder_helper_funcs);
562
563 vec->connector = vc4_vec_connector_init(drm, vec);
564 if (IS_ERR(vec->connector)) {
565 ret = PTR_ERR(vec->connector);
566 goto err_destroy_encoder;
567 }
568
569 dev_set_drvdata(dev, vec);
570
571 vc4->vec = vec;
572
573 vc4_debugfs_add_regset32(drm, "vec_regs", &vec->regset);
574
575 return 0;
576
577 err_destroy_encoder:
578 drm_encoder_cleanup(vec->encoder);
579 pm_runtime_disable(dev);
580
581 return ret;
582 }
583
vc4_vec_unbind(struct device * dev,struct device * master,void * data)584 static void vc4_vec_unbind(struct device *dev, struct device *master,
585 void *data)
586 {
587 struct drm_device *drm = dev_get_drvdata(master);
588 struct vc4_dev *vc4 = to_vc4_dev(drm);
589 struct vc4_vec *vec = dev_get_drvdata(dev);
590
591 vc4_vec_connector_destroy(vec->connector);
592 drm_encoder_cleanup(vec->encoder);
593 pm_runtime_disable(dev);
594
595 vc4->vec = NULL;
596 }
597
598 static const struct component_ops vc4_vec_ops = {
599 .bind = vc4_vec_bind,
600 .unbind = vc4_vec_unbind,
601 };
602
vc4_vec_dev_probe(struct platform_device * pdev)603 static int vc4_vec_dev_probe(struct platform_device *pdev)
604 {
605 return component_add(&pdev->dev, &vc4_vec_ops);
606 }
607
vc4_vec_dev_remove(struct platform_device * pdev)608 static int vc4_vec_dev_remove(struct platform_device *pdev)
609 {
610 component_del(&pdev->dev, &vc4_vec_ops);
611 return 0;
612 }
613
614 struct platform_driver vc4_vec_driver = {
615 .probe = vc4_vec_dev_probe,
616 .remove = vc4_vec_dev_remove,
617 .driver = {
618 .name = "vc4_vec",
619 .of_match_table = vc4_vec_dt_match,
620 },
621 };
622