1 /******************************************************************************* 2 * 3 * Copyright (c) 2015-2016 Intel Corporation. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenFabrics.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 * 33 *******************************************************************************/ 34 35 #ifndef I40IW_D_H 36 #define I40IW_D_H 37 38 #define I40IW_FIRST_USER_QP_ID 2 39 40 #define I40IW_DB_ADDR_OFFSET (4 * 1024 * 1024 - 64 * 1024) 41 #define I40IW_VF_DB_ADDR_OFFSET (64 * 1024) 42 43 #define I40IW_PE_DB_SIZE_4M 1 44 #define I40IW_PE_DB_SIZE_8M 2 45 46 #define I40IW_DDP_VER 1 47 #define I40IW_RDMAP_VER 1 48 49 #define I40IW_RDMA_MODE_RDMAC 0 50 #define I40IW_RDMA_MODE_IETF 1 51 52 #define I40IW_QP_STATE_INVALID 0 53 #define I40IW_QP_STATE_IDLE 1 54 #define I40IW_QP_STATE_RTS 2 55 #define I40IW_QP_STATE_CLOSING 3 56 #define I40IW_QP_STATE_RESERVED 4 57 #define I40IW_QP_STATE_TERMINATE 5 58 #define I40IW_QP_STATE_ERROR 6 59 60 #define I40IW_STAG_STATE_INVALID 0 61 #define I40IW_STAG_STATE_VALID 1 62 63 #define I40IW_STAG_TYPE_SHARED 0 64 #define I40IW_STAG_TYPE_NONSHARED 1 65 66 #define I40IW_MAX_USER_PRIORITY 8 67 #define I40IW_MAX_STATS_COUNT 16 68 #define I40IW_FIRST_NON_PF_STAT 4 69 70 71 #define I40IW_MTU_TO_MSS_IPV4 40 72 #define I40IW_MTU_TO_MSS_IPV6 60 73 #define I40IW_DEFAULT_MTU 1500 74 75 #define LS_64_1(val, bits) ((u64)(uintptr_t)val << bits) 76 #define RS_64_1(val, bits) ((u64)(uintptr_t)val >> bits) 77 #define LS_32_1(val, bits) (u32)(val << bits) 78 #define RS_32_1(val, bits) (u32)(val >> bits) 79 #define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF)) 80 81 #define QS_HANDLE_UNKNOWN 0xffff 82 83 #define LS_64(val, field) (((u64)val << field ## _SHIFT) & (field ## _MASK)) 84 85 #define RS_64(val, field) ((u64)(val & field ## _MASK) >> field ## _SHIFT) 86 #define LS_32(val, field) ((val << field ## _SHIFT) & (field ## _MASK)) 87 #define RS_32(val, field) ((val & field ## _MASK) >> field ## _SHIFT) 88 89 #define TERM_DDP_LEN_TAGGED 14 90 #define TERM_DDP_LEN_UNTAGGED 18 91 #define TERM_RDMA_LEN 28 92 #define RDMA_OPCODE_MASK 0x0f 93 #define RDMA_READ_REQ_OPCODE 1 94 #define Q2_BAD_FRAME_OFFSET 72 95 #define Q2_FPSN_OFFSET 64 96 #define CQE_MAJOR_DRV 0x8000 97 98 #define I40IW_TERM_SENT 0x01 99 #define I40IW_TERM_RCVD 0x02 100 #define I40IW_TERM_DONE 0x04 101 #define I40IW_MAC_HLEN 14 102 103 #define I40IW_INVALID_WQE_INDEX 0xffffffff 104 105 #define I40IW_CQP_WAIT_POLL_REGS 1 106 #define I40IW_CQP_WAIT_POLL_CQ 2 107 #define I40IW_CQP_WAIT_EVENT 3 108 109 #define I40IW_CQP_INIT_WQE(wqe) memset(wqe, 0, 64) 110 111 #define I40IW_GET_CURRENT_CQ_ELEMENT(_cq) \ 112 ( \ 113 &((_cq)->cq_base[I40IW_RING_GETCURRENT_HEAD((_cq)->cq_ring)]) \ 114 ) 115 #define I40IW_GET_CURRENT_EXTENDED_CQ_ELEMENT(_cq) \ 116 ( \ 117 &(((struct i40iw_extended_cqe *) \ 118 ((_cq)->cq_base))[I40IW_RING_GETCURRENT_HEAD((_cq)->cq_ring)]) \ 119 ) 120 121 #define I40IW_GET_CURRENT_AEQ_ELEMENT(_aeq) \ 122 ( \ 123 &_aeq->aeqe_base[I40IW_RING_GETCURRENT_TAIL(_aeq->aeq_ring)] \ 124 ) 125 126 #define I40IW_GET_CURRENT_CEQ_ELEMENT(_ceq) \ 127 ( \ 128 &_ceq->ceqe_base[I40IW_RING_GETCURRENT_TAIL(_ceq->ceq_ring)] \ 129 ) 130 131 #define I40IW_AE_SOURCE_RSVD 0x0 132 #define I40IW_AE_SOURCE_RQ 0x1 133 #define I40IW_AE_SOURCE_RQ_0011 0x3 134 135 #define I40IW_AE_SOURCE_CQ 0x2 136 #define I40IW_AE_SOURCE_CQ_0110 0x6 137 #define I40IW_AE_SOURCE_CQ_1010 0xA 138 #define I40IW_AE_SOURCE_CQ_1110 0xE 139 140 #define I40IW_AE_SOURCE_SQ 0x5 141 #define I40IW_AE_SOURCE_SQ_0111 0x7 142 143 #define I40IW_AE_SOURCE_IN_RR_WR 0x9 144 #define I40IW_AE_SOURCE_IN_RR_WR_1011 0xB 145 #define I40IW_AE_SOURCE_OUT_RR 0xD 146 #define I40IW_AE_SOURCE_OUT_RR_1111 0xF 147 148 #define I40IW_TCP_STATE_NON_EXISTENT 0 149 #define I40IW_TCP_STATE_CLOSED 1 150 #define I40IW_TCP_STATE_LISTEN 2 151 #define I40IW_STATE_SYN_SEND 3 152 #define I40IW_TCP_STATE_SYN_RECEIVED 4 153 #define I40IW_TCP_STATE_ESTABLISHED 5 154 #define I40IW_TCP_STATE_CLOSE_WAIT 6 155 #define I40IW_TCP_STATE_FIN_WAIT_1 7 156 #define I40IW_TCP_STATE_CLOSING 8 157 #define I40IW_TCP_STATE_LAST_ACK 9 158 #define I40IW_TCP_STATE_FIN_WAIT_2 10 159 #define I40IW_TCP_STATE_TIME_WAIT 11 160 #define I40IW_TCP_STATE_RESERVED_1 12 161 #define I40IW_TCP_STATE_RESERVED_2 13 162 #define I40IW_TCP_STATE_RESERVED_3 14 163 #define I40IW_TCP_STATE_RESERVED_4 15 164 165 /* ILQ CQP hash table fields */ 166 #define I40IW_CQPSQ_QHASH_VLANID_SHIFT 32 167 #define I40IW_CQPSQ_QHASH_VLANID_MASK \ 168 ((u64)0xfff << I40IW_CQPSQ_QHASH_VLANID_SHIFT) 169 170 #define I40IW_CQPSQ_QHASH_QPN_SHIFT 32 171 #define I40IW_CQPSQ_QHASH_QPN_MASK \ 172 ((u64)0x3ffff << I40IW_CQPSQ_QHASH_QPN_SHIFT) 173 174 #define I40IW_CQPSQ_QHASH_QS_HANDLE_SHIFT 0 175 #define I40IW_CQPSQ_QHASH_QS_HANDLE_MASK ((u64)0x3ff << I40IW_CQPSQ_QHASH_QS_HANDLE_SHIFT) 176 177 #define I40IW_CQPSQ_QHASH_SRC_PORT_SHIFT 16 178 #define I40IW_CQPSQ_QHASH_SRC_PORT_MASK \ 179 ((u64)0xffff << I40IW_CQPSQ_QHASH_SRC_PORT_SHIFT) 180 181 #define I40IW_CQPSQ_QHASH_DEST_PORT_SHIFT 0 182 #define I40IW_CQPSQ_QHASH_DEST_PORT_MASK \ 183 ((u64)0xffff << I40IW_CQPSQ_QHASH_DEST_PORT_SHIFT) 184 185 #define I40IW_CQPSQ_QHASH_ADDR0_SHIFT 32 186 #define I40IW_CQPSQ_QHASH_ADDR0_MASK \ 187 ((u64)0xffffffff << I40IW_CQPSQ_QHASH_ADDR0_SHIFT) 188 189 #define I40IW_CQPSQ_QHASH_ADDR1_SHIFT 0 190 #define I40IW_CQPSQ_QHASH_ADDR1_MASK \ 191 ((u64)0xffffffff << I40IW_CQPSQ_QHASH_ADDR1_SHIFT) 192 193 #define I40IW_CQPSQ_QHASH_ADDR2_SHIFT 32 194 #define I40IW_CQPSQ_QHASH_ADDR2_MASK \ 195 ((u64)0xffffffff << I40IW_CQPSQ_QHASH_ADDR2_SHIFT) 196 197 #define I40IW_CQPSQ_QHASH_ADDR3_SHIFT 0 198 #define I40IW_CQPSQ_QHASH_ADDR3_MASK \ 199 ((u64)0xffffffff << I40IW_CQPSQ_QHASH_ADDR3_SHIFT) 200 201 #define I40IW_CQPSQ_QHASH_WQEVALID_SHIFT 63 202 #define I40IW_CQPSQ_QHASH_WQEVALID_MASK \ 203 ((u64)0x1 << I40IW_CQPSQ_QHASH_WQEVALID_SHIFT) 204 #define I40IW_CQPSQ_QHASH_OPCODE_SHIFT 32 205 #define I40IW_CQPSQ_QHASH_OPCODE_MASK \ 206 ((u64)0x3f << I40IW_CQPSQ_QHASH_OPCODE_SHIFT) 207 208 #define I40IW_CQPSQ_QHASH_MANAGE_SHIFT 61 209 #define I40IW_CQPSQ_QHASH_MANAGE_MASK \ 210 ((u64)0x3 << I40IW_CQPSQ_QHASH_MANAGE_SHIFT) 211 212 #define I40IW_CQPSQ_QHASH_IPV4VALID_SHIFT 60 213 #define I40IW_CQPSQ_QHASH_IPV4VALID_MASK \ 214 ((u64)0x1 << I40IW_CQPSQ_QHASH_IPV4VALID_SHIFT) 215 216 #define I40IW_CQPSQ_QHASH_VLANVALID_SHIFT 59 217 #define I40IW_CQPSQ_QHASH_VLANVALID_MASK \ 218 ((u64)0x1 << I40IW_CQPSQ_QHASH_VLANVALID_SHIFT) 219 220 #define I40IW_CQPSQ_QHASH_ENTRYTYPE_SHIFT 42 221 #define I40IW_CQPSQ_QHASH_ENTRYTYPE_MASK \ 222 ((u64)0x7 << I40IW_CQPSQ_QHASH_ENTRYTYPE_SHIFT) 223 /* CQP Host Context */ 224 #define I40IW_CQPHC_EN_DC_TCP_SHIFT 0 225 #define I40IW_CQPHC_EN_DC_TCP_MASK (1UL << I40IW_CQPHC_EN_DC_TCP_SHIFT) 226 227 #define I40IW_CQPHC_SQSIZE_SHIFT 8 228 #define I40IW_CQPHC_SQSIZE_MASK (0xfUL << I40IW_CQPHC_SQSIZE_SHIFT) 229 230 #define I40IW_CQPHC_DISABLE_PFPDUS_SHIFT 1 231 #define I40IW_CQPHC_DISABLE_PFPDUS_MASK (0x1UL << I40IW_CQPHC_DISABLE_PFPDUS_SHIFT) 232 233 #define I40IW_CQPHC_ENABLED_VFS_SHIFT 32 234 #define I40IW_CQPHC_ENABLED_VFS_MASK (0x3fULL << I40IW_CQPHC_ENABLED_VFS_SHIFT) 235 236 #define I40IW_CQPHC_HMC_PROFILE_SHIFT 0 237 #define I40IW_CQPHC_HMC_PROFILE_MASK (0x7ULL << I40IW_CQPHC_HMC_PROFILE_SHIFT) 238 239 #define I40IW_CQPHC_SVER_SHIFT 24 240 #define I40IW_CQPHC_SVER_MASK (0xffUL << I40IW_CQPHC_SVER_SHIFT) 241 242 #define I40IW_CQPHC_SQBASE_SHIFT 9 243 #define I40IW_CQPHC_SQBASE_MASK \ 244 (0xfffffffffffffeULL << I40IW_CQPHC_SQBASE_SHIFT) 245 246 #define I40IW_CQPHC_QPCTX_SHIFT 0 247 #define I40IW_CQPHC_QPCTX_MASK \ 248 (0xffffffffffffffffULL << I40IW_CQPHC_QPCTX_SHIFT) 249 #define I40IW_CQPHC_SVER 1 250 251 #define I40IW_CQP_SW_SQSIZE_4 4 252 #define I40IW_CQP_SW_SQSIZE_2048 2048 253 254 /* iWARP QP Doorbell shadow area */ 255 #define I40IW_QP_DBSA_HW_SQ_TAIL_SHIFT 0 256 #define I40IW_QP_DBSA_HW_SQ_TAIL_MASK \ 257 (0x3fffUL << I40IW_QP_DBSA_HW_SQ_TAIL_SHIFT) 258 259 /* Completion Queue Doorbell shadow area */ 260 #define I40IW_CQ_DBSA_CQEIDX_SHIFT 0 261 #define I40IW_CQ_DBSA_CQEIDX_MASK (0xfffffUL << I40IW_CQ_DBSA_CQEIDX_SHIFT) 262 263 #define I40IW_CQ_DBSA_SW_CQ_SELECT_SHIFT 0 264 #define I40IW_CQ_DBSA_SW_CQ_SELECT_MASK \ 265 (0x3fffUL << I40IW_CQ_DBSA_SW_CQ_SELECT_SHIFT) 266 267 #define I40IW_CQ_DBSA_ARM_NEXT_SHIFT 14 268 #define I40IW_CQ_DBSA_ARM_NEXT_MASK (1UL << I40IW_CQ_DBSA_ARM_NEXT_SHIFT) 269 270 #define I40IW_CQ_DBSA_ARM_NEXT_SE_SHIFT 15 271 #define I40IW_CQ_DBSA_ARM_NEXT_SE_MASK (1UL << I40IW_CQ_DBSA_ARM_NEXT_SE_SHIFT) 272 273 #define I40IW_CQ_DBSA_ARM_SEQ_NUM_SHIFT 16 274 #define I40IW_CQ_DBSA_ARM_SEQ_NUM_MASK \ 275 (0x3UL << I40IW_CQ_DBSA_ARM_SEQ_NUM_SHIFT) 276 277 /* CQP and iWARP Completion Queue */ 278 #define I40IW_CQ_QPCTX_SHIFT I40IW_CQPHC_QPCTX_SHIFT 279 #define I40IW_CQ_QPCTX_MASK I40IW_CQPHC_QPCTX_MASK 280 281 #define I40IW_CCQ_OPRETVAL_SHIFT 0 282 #define I40IW_CCQ_OPRETVAL_MASK (0xffffffffUL << I40IW_CCQ_OPRETVAL_SHIFT) 283 284 #define I40IW_CQ_MINERR_SHIFT 0 285 #define I40IW_CQ_MINERR_MASK (0xffffUL << I40IW_CQ_MINERR_SHIFT) 286 287 #define I40IW_CQ_MAJERR_SHIFT 16 288 #define I40IW_CQ_MAJERR_MASK (0xffffUL << I40IW_CQ_MAJERR_SHIFT) 289 290 #define I40IW_CQ_WQEIDX_SHIFT 32 291 #define I40IW_CQ_WQEIDX_MASK (0x3fffULL << I40IW_CQ_WQEIDX_SHIFT) 292 293 #define I40IW_CQ_ERROR_SHIFT 55 294 #define I40IW_CQ_ERROR_MASK (1ULL << I40IW_CQ_ERROR_SHIFT) 295 296 #define I40IW_CQ_SQ_SHIFT 62 297 #define I40IW_CQ_SQ_MASK (1ULL << I40IW_CQ_SQ_SHIFT) 298 299 #define I40IW_CQ_VALID_SHIFT 63 300 #define I40IW_CQ_VALID_MASK (1ULL << I40IW_CQ_VALID_SHIFT) 301 302 #define I40IWCQ_PAYLDLEN_SHIFT 0 303 #define I40IWCQ_PAYLDLEN_MASK (0xffffffffUL << I40IWCQ_PAYLDLEN_SHIFT) 304 305 #define I40IWCQ_TCPSEQNUM_SHIFT 32 306 #define I40IWCQ_TCPSEQNUM_MASK (0xffffffffULL << I40IWCQ_TCPSEQNUM_SHIFT) 307 308 #define I40IWCQ_INVSTAG_SHIFT 0 309 #define I40IWCQ_INVSTAG_MASK (0xffffffffUL << I40IWCQ_INVSTAG_SHIFT) 310 311 #define I40IWCQ_QPID_SHIFT 32 312 #define I40IWCQ_QPID_MASK (0x3ffffULL << I40IWCQ_QPID_SHIFT) 313 314 #define I40IWCQ_PSHDROP_SHIFT 51 315 #define I40IWCQ_PSHDROP_MASK (1ULL << I40IWCQ_PSHDROP_SHIFT) 316 317 #define I40IWCQ_SRQ_SHIFT 52 318 #define I40IWCQ_SRQ_MASK (1ULL << I40IWCQ_SRQ_SHIFT) 319 320 #define I40IWCQ_STAG_SHIFT 53 321 #define I40IWCQ_STAG_MASK (1ULL << I40IWCQ_STAG_SHIFT) 322 323 #define I40IWCQ_SOEVENT_SHIFT 54 324 #define I40IWCQ_SOEVENT_MASK (1ULL << I40IWCQ_SOEVENT_SHIFT) 325 326 #define I40IWCQ_OP_SHIFT 56 327 #define I40IWCQ_OP_MASK (0x3fULL << I40IWCQ_OP_SHIFT) 328 329 /* CEQE format */ 330 #define I40IW_CEQE_CQCTX_SHIFT 0 331 #define I40IW_CEQE_CQCTX_MASK \ 332 (0x7fffffffffffffffULL << I40IW_CEQE_CQCTX_SHIFT) 333 334 #define I40IW_CEQE_VALID_SHIFT 63 335 #define I40IW_CEQE_VALID_MASK (1ULL << I40IW_CEQE_VALID_SHIFT) 336 337 /* AEQE format */ 338 #define I40IW_AEQE_COMPCTX_SHIFT I40IW_CQPHC_QPCTX_SHIFT 339 #define I40IW_AEQE_COMPCTX_MASK I40IW_CQPHC_QPCTX_MASK 340 341 #define I40IW_AEQE_QPCQID_SHIFT 0 342 #define I40IW_AEQE_QPCQID_MASK (0x3ffffUL << I40IW_AEQE_QPCQID_SHIFT) 343 344 #define I40IW_AEQE_WQDESCIDX_SHIFT 18 345 #define I40IW_AEQE_WQDESCIDX_MASK (0x3fffULL << I40IW_AEQE_WQDESCIDX_SHIFT) 346 347 #define I40IW_AEQE_OVERFLOW_SHIFT 33 348 #define I40IW_AEQE_OVERFLOW_MASK (1ULL << I40IW_AEQE_OVERFLOW_SHIFT) 349 350 #define I40IW_AEQE_AECODE_SHIFT 34 351 #define I40IW_AEQE_AECODE_MASK (0xffffULL << I40IW_AEQE_AECODE_SHIFT) 352 353 #define I40IW_AEQE_AESRC_SHIFT 50 354 #define I40IW_AEQE_AESRC_MASK (0xfULL << I40IW_AEQE_AESRC_SHIFT) 355 356 #define I40IW_AEQE_IWSTATE_SHIFT 54 357 #define I40IW_AEQE_IWSTATE_MASK (0x7ULL << I40IW_AEQE_IWSTATE_SHIFT) 358 359 #define I40IW_AEQE_TCPSTATE_SHIFT 57 360 #define I40IW_AEQE_TCPSTATE_MASK (0xfULL << I40IW_AEQE_TCPSTATE_SHIFT) 361 362 #define I40IW_AEQE_Q2DATA_SHIFT 61 363 #define I40IW_AEQE_Q2DATA_MASK (0x3ULL << I40IW_AEQE_Q2DATA_SHIFT) 364 365 #define I40IW_AEQE_VALID_SHIFT 63 366 #define I40IW_AEQE_VALID_MASK (1ULL << I40IW_AEQE_VALID_SHIFT) 367 368 /* CQP SQ WQES */ 369 #define I40IW_QP_TYPE_IWARP 1 370 #define I40IW_QP_TYPE_UDA 2 371 #define I40IW_QP_TYPE_CQP 4 372 373 #define I40IW_CQ_TYPE_IWARP 1 374 #define I40IW_CQ_TYPE_ILQ 2 375 #define I40IW_CQ_TYPE_IEQ 3 376 #define I40IW_CQ_TYPE_CQP 4 377 378 #define I40IWQP_TERM_SEND_TERM_AND_FIN 0 379 #define I40IWQP_TERM_SEND_TERM_ONLY 1 380 #define I40IWQP_TERM_SEND_FIN_ONLY 2 381 #define I40IWQP_TERM_DONOT_SEND_TERM_OR_FIN 3 382 383 #define I40IW_CQP_OP_CREATE_QP 0 384 #define I40IW_CQP_OP_MODIFY_QP 0x1 385 #define I40IW_CQP_OP_DESTROY_QP 0x02 386 #define I40IW_CQP_OP_CREATE_CQ 0x03 387 #define I40IW_CQP_OP_MODIFY_CQ 0x04 388 #define I40IW_CQP_OP_DESTROY_CQ 0x05 389 #define I40IW_CQP_OP_CREATE_SRQ 0x06 390 #define I40IW_CQP_OP_MODIFY_SRQ 0x07 391 #define I40IW_CQP_OP_DESTROY_SRQ 0x08 392 #define I40IW_CQP_OP_ALLOC_STAG 0x09 393 #define I40IW_CQP_OP_REG_MR 0x0a 394 #define I40IW_CQP_OP_QUERY_STAG 0x0b 395 #define I40IW_CQP_OP_REG_SMR 0x0c 396 #define I40IW_CQP_OP_DEALLOC_STAG 0x0d 397 #define I40IW_CQP_OP_MANAGE_LOC_MAC_IP_TABLE 0x0e 398 #define I40IW_CQP_OP_MANAGE_ARP 0x0f 399 #define I40IW_CQP_OP_MANAGE_VF_PBLE_BP 0x10 400 #define I40IW_CQP_OP_QUERY_RDMA_FEATURES 0x12 401 #define I40IW_CQP_OP_UPLOAD_CONTEXT 0x13 402 #define I40IW_CQP_OP_ALLOCATE_LOC_MAC_IP_TABLE_ENTRY 0x14 403 #define I40IW_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE 0x15 404 #define I40IW_CQP_OP_CREATE_CEQ 0x16 405 #define I40IW_CQP_OP_DESTROY_CEQ 0x18 406 #define I40IW_CQP_OP_CREATE_AEQ 0x19 407 #define I40IW_CQP_OP_DESTROY_AEQ 0x1b 408 #define I40IW_CQP_OP_CREATE_ADDR_VECT 0x1c 409 #define I40IW_CQP_OP_MODIFY_ADDR_VECT 0x1d 410 #define I40IW_CQP_OP_DESTROY_ADDR_VECT 0x1e 411 #define I40IW_CQP_OP_UPDATE_PE_SDS 0x1f 412 #define I40IW_CQP_OP_QUERY_FPM_VALUES 0x20 413 #define I40IW_CQP_OP_COMMIT_FPM_VALUES 0x21 414 #define I40IW_CQP_OP_FLUSH_WQES 0x22 415 /* I40IW_CQP_OP_GEN_AE is the same value as I40IW_CQP_OP_FLUSH_WQES */ 416 #define I40IW_CQP_OP_GEN_AE 0x22 417 #define I40IW_CQP_OP_MANAGE_APBVT 0x23 418 #define I40IW_CQP_OP_NOP 0x24 419 #define I40IW_CQP_OP_MANAGE_QUAD_HASH_TABLE_ENTRY 0x25 420 #define I40IW_CQP_OP_CREATE_UDA_MCAST_GROUP 0x26 421 #define I40IW_CQP_OP_MODIFY_UDA_MCAST_GROUP 0x27 422 #define I40IW_CQP_OP_DESTROY_UDA_MCAST_GROUP 0x28 423 #define I40IW_CQP_OP_SUSPEND_QP 0x29 424 #define I40IW_CQP_OP_RESUME_QP 0x2a 425 #define I40IW_CQP_OP_SHMC_PAGES_ALLOCATED 0x2b 426 #define I40IW_CQP_OP_SET_HMC_RESOURCE_PROFILE 0x2d 427 428 #define I40IW_FEATURE_BUF_SIZE (8 * I40IW_MAX_FEATURES) 429 430 #define I40IW_FW_VER_MINOR_SHIFT 0 431 #define I40IW_FW_VER_MINOR_MASK \ 432 (0xffffULL << I40IW_FW_VER_MINOR_SHIFT) 433 434 #define I40IW_FW_VER_MAJOR_SHIFT 16 435 #define I40IW_FW_VER_MAJOR_MASK \ 436 (0xffffULL << I40IW_FW_VER_MAJOR_SHIFT) 437 438 #define I40IW_FEATURE_INFO_SHIFT 0 439 #define I40IW_FEATURE_INFO_MASK \ 440 (0xffffULL << I40IW_FEATURE_INFO_SHIFT) 441 442 #define I40IW_FEATURE_CNT_SHIFT 32 443 #define I40IW_FEATURE_CNT_MASK \ 444 (0xffffULL << I40IW_FEATURE_CNT_SHIFT) 445 446 #define I40IW_UDA_QPSQ_NEXT_HEADER_SHIFT 16 447 #define I40IW_UDA_QPSQ_NEXT_HEADER_MASK ((u64)0xff << I40IW_UDA_QPSQ_NEXT_HEADER_SHIFT) 448 449 #define I40IW_UDA_QPSQ_OPCODE_SHIFT 32 450 #define I40IW_UDA_QPSQ_OPCODE_MASK ((u64)0x3f << I40IW_UDA_QPSQ_OPCODE_SHIFT) 451 452 #define I40IW_UDA_QPSQ_MACLEN_SHIFT 56 453 #define I40IW_UDA_QPSQ_MACLEN_MASK \ 454 ((u64)0x7f << I40IW_UDA_QPSQ_MACLEN_SHIFT) 455 456 #define I40IW_UDA_QPSQ_IPLEN_SHIFT 48 457 #define I40IW_UDA_QPSQ_IPLEN_MASK \ 458 ((u64)0x7f << I40IW_UDA_QPSQ_IPLEN_SHIFT) 459 460 #define I40IW_UDA_QPSQ_L4T_SHIFT 30 461 #define I40IW_UDA_QPSQ_L4T_MASK \ 462 ((u64)0x3 << I40IW_UDA_QPSQ_L4T_SHIFT) 463 464 #define I40IW_UDA_QPSQ_IIPT_SHIFT 28 465 #define I40IW_UDA_QPSQ_IIPT_MASK \ 466 ((u64)0x3 << I40IW_UDA_QPSQ_IIPT_SHIFT) 467 468 #define I40IW_UDA_QPSQ_L4LEN_SHIFT 24 469 #define I40IW_UDA_QPSQ_L4LEN_MASK ((u64)0xf << I40IW_UDA_QPSQ_L4LEN_SHIFT) 470 471 #define I40IW_UDA_QPSQ_AVIDX_SHIFT 0 472 #define I40IW_UDA_QPSQ_AVIDX_MASK ((u64)0xffff << I40IW_UDA_QPSQ_AVIDX_SHIFT) 473 474 #define I40IW_UDA_QPSQ_VALID_SHIFT 63 475 #define I40IW_UDA_QPSQ_VALID_MASK \ 476 ((u64)0x1 << I40IW_UDA_QPSQ_VALID_SHIFT) 477 478 #define I40IW_UDA_QPSQ_SIGCOMPL_SHIFT 62 479 #define I40IW_UDA_QPSQ_SIGCOMPL_MASK ((u64)0x1 << I40IW_UDA_QPSQ_SIGCOMPL_SHIFT) 480 481 #define I40IW_UDA_PAYLOADLEN_SHIFT 0 482 #define I40IW_UDA_PAYLOADLEN_MASK ((u64)0x3fff << I40IW_UDA_PAYLOADLEN_SHIFT) 483 484 #define I40IW_UDA_HDRLEN_SHIFT 16 485 #define I40IW_UDA_HDRLEN_MASK ((u64)0x1ff << I40IW_UDA_HDRLEN_SHIFT) 486 487 #define I40IW_VLAN_TAG_VALID_SHIFT 50 488 #define I40IW_VLAN_TAG_VALID_MASK ((u64)0x1 << I40IW_VLAN_TAG_VALID_SHIFT) 489 490 #define I40IW_UDA_L3PROTO_SHIFT 0 491 #define I40IW_UDA_L3PROTO_MASK ((u64)0x3 << I40IW_UDA_L3PROTO_SHIFT) 492 493 #define I40IW_UDA_L4PROTO_SHIFT 16 494 #define I40IW_UDA_L4PROTO_MASK ((u64)0x3 << I40IW_UDA_L4PROTO_SHIFT) 495 496 #define I40IW_UDA_QPSQ_DOLOOPBACK_SHIFT 44 497 #define I40IW_UDA_QPSQ_DOLOOPBACK_MASK \ 498 ((u64)0x1 << I40IW_UDA_QPSQ_DOLOOPBACK_SHIFT) 499 500 /* CQP SQ WQE common fields */ 501 #define I40IW_CQPSQ_OPCODE_SHIFT 32 502 #define I40IW_CQPSQ_OPCODE_MASK (0x3fULL << I40IW_CQPSQ_OPCODE_SHIFT) 503 504 #define I40IW_CQPSQ_WQEVALID_SHIFT 63 505 #define I40IW_CQPSQ_WQEVALID_MASK (1ULL << I40IW_CQPSQ_WQEVALID_SHIFT) 506 507 #define I40IW_CQPSQ_TPHVAL_SHIFT 0 508 #define I40IW_CQPSQ_TPHVAL_MASK (0xffUL << I40IW_CQPSQ_TPHVAL_SHIFT) 509 510 #define I40IW_CQPSQ_TPHEN_SHIFT 60 511 #define I40IW_CQPSQ_TPHEN_MASK (1ULL << I40IW_CQPSQ_TPHEN_SHIFT) 512 513 #define I40IW_CQPSQ_PBUFADDR_SHIFT I40IW_CQPHC_QPCTX_SHIFT 514 #define I40IW_CQPSQ_PBUFADDR_MASK I40IW_CQPHC_QPCTX_MASK 515 516 /* Create/Modify/Destroy QP */ 517 518 #define I40IW_CQPSQ_QP_NEWMSS_SHIFT 32 519 #define I40IW_CQPSQ_QP_NEWMSS_MASK (0x3fffULL << I40IW_CQPSQ_QP_NEWMSS_SHIFT) 520 521 #define I40IW_CQPSQ_QP_TERMLEN_SHIFT 48 522 #define I40IW_CQPSQ_QP_TERMLEN_MASK (0xfULL << I40IW_CQPSQ_QP_TERMLEN_SHIFT) 523 524 #define I40IW_CQPSQ_QP_QPCTX_SHIFT I40IW_CQPHC_QPCTX_SHIFT 525 #define I40IW_CQPSQ_QP_QPCTX_MASK I40IW_CQPHC_QPCTX_MASK 526 527 #define I40IW_CQPSQ_QP_QPID_SHIFT 0 528 #define I40IW_CQPSQ_QP_QPID_MASK (0x3FFFFUL) 529 /* I40IWCQ_QPID_MASK */ 530 531 #define I40IW_CQPSQ_QP_OP_SHIFT 32 532 #define I40IW_CQPSQ_QP_OP_MASK I40IWCQ_OP_MASK 533 534 #define I40IW_CQPSQ_QP_ORDVALID_SHIFT 42 535 #define I40IW_CQPSQ_QP_ORDVALID_MASK (1ULL << I40IW_CQPSQ_QP_ORDVALID_SHIFT) 536 537 #define I40IW_CQPSQ_QP_TOECTXVALID_SHIFT 43 538 #define I40IW_CQPSQ_QP_TOECTXVALID_MASK \ 539 (1ULL << I40IW_CQPSQ_QP_TOECTXVALID_SHIFT) 540 541 #define I40IW_CQPSQ_QP_CACHEDVARVALID_SHIFT 44 542 #define I40IW_CQPSQ_QP_CACHEDVARVALID_MASK \ 543 (1ULL << I40IW_CQPSQ_QP_CACHEDVARVALID_SHIFT) 544 545 #define I40IW_CQPSQ_QP_VQ_SHIFT 45 546 #define I40IW_CQPSQ_QP_VQ_MASK (1ULL << I40IW_CQPSQ_QP_VQ_SHIFT) 547 548 #define I40IW_CQPSQ_QP_FORCELOOPBACK_SHIFT 46 549 #define I40IW_CQPSQ_QP_FORCELOOPBACK_MASK \ 550 (1ULL << I40IW_CQPSQ_QP_FORCELOOPBACK_SHIFT) 551 552 #define I40IW_CQPSQ_QP_CQNUMVALID_SHIFT 47 553 #define I40IW_CQPSQ_QP_CQNUMVALID_MASK \ 554 (1ULL << I40IW_CQPSQ_QP_CQNUMVALID_SHIFT) 555 556 #define I40IW_CQPSQ_QP_QPTYPE_SHIFT 48 557 #define I40IW_CQPSQ_QP_QPTYPE_MASK (0x3ULL << I40IW_CQPSQ_QP_QPTYPE_SHIFT) 558 559 #define I40IW_CQPSQ_QP_MSSCHANGE_SHIFT 52 560 #define I40IW_CQPSQ_QP_MSSCHANGE_MASK (1ULL << I40IW_CQPSQ_QP_MSSCHANGE_SHIFT) 561 562 #define I40IW_CQPSQ_QP_IGNOREMWBOUND_SHIFT 54 563 #define I40IW_CQPSQ_QP_IGNOREMWBOUND_MASK \ 564 (1ULL << I40IW_CQPSQ_QP_IGNOREMWBOUND_SHIFT) 565 566 #define I40IW_CQPSQ_QP_REMOVEHASHENTRY_SHIFT 55 567 #define I40IW_CQPSQ_QP_REMOVEHASHENTRY_MASK \ 568 (1ULL << I40IW_CQPSQ_QP_REMOVEHASHENTRY_SHIFT) 569 570 #define I40IW_CQPSQ_QP_TERMACT_SHIFT 56 571 #define I40IW_CQPSQ_QP_TERMACT_MASK (0x3ULL << I40IW_CQPSQ_QP_TERMACT_SHIFT) 572 573 #define I40IW_CQPSQ_QP_RESETCON_SHIFT 58 574 #define I40IW_CQPSQ_QP_RESETCON_MASK (1ULL << I40IW_CQPSQ_QP_RESETCON_SHIFT) 575 576 #define I40IW_CQPSQ_QP_ARPTABIDXVALID_SHIFT 59 577 #define I40IW_CQPSQ_QP_ARPTABIDXVALID_MASK \ 578 (1ULL << I40IW_CQPSQ_QP_ARPTABIDXVALID_SHIFT) 579 580 #define I40IW_CQPSQ_QP_NEXTIWSTATE_SHIFT 60 581 #define I40IW_CQPSQ_QP_NEXTIWSTATE_MASK \ 582 (0x7ULL << I40IW_CQPSQ_QP_NEXTIWSTATE_SHIFT) 583 584 #define I40IW_CQPSQ_QP_DBSHADOWADDR_SHIFT I40IW_CQPHC_QPCTX_SHIFT 585 #define I40IW_CQPSQ_QP_DBSHADOWADDR_MASK I40IW_CQPHC_QPCTX_MASK 586 587 /* Create/Modify/Destroy CQ */ 588 #define I40IW_CQPSQ_CQ_CQSIZE_SHIFT 0 589 #define I40IW_CQPSQ_CQ_CQSIZE_MASK (0x3ffffUL << I40IW_CQPSQ_CQ_CQSIZE_SHIFT) 590 591 #define I40IW_CQPSQ_CQ_CQCTX_SHIFT 0 592 #define I40IW_CQPSQ_CQ_CQCTX_MASK \ 593 (0x7fffffffffffffffULL << I40IW_CQPSQ_CQ_CQCTX_SHIFT) 594 595 #define I40IW_CQPSQ_CQ_CQCTX_SHIFT 0 596 #define I40IW_CQPSQ_CQ_CQCTX_MASK \ 597 (0x7fffffffffffffffULL << I40IW_CQPSQ_CQ_CQCTX_SHIFT) 598 599 #define I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD_SHIFT 0 600 #define I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD_MASK \ 601 (0x3ffff << I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD_SHIFT) 602 603 #define I40IW_CQPSQ_CQ_CEQID_SHIFT 24 604 #define I40IW_CQPSQ_CQ_CEQID_MASK (0x7fUL << I40IW_CQPSQ_CQ_CEQID_SHIFT) 605 606 #define I40IW_CQPSQ_CQ_OP_SHIFT 32 607 #define I40IW_CQPSQ_CQ_OP_MASK (0x3fULL << I40IW_CQPSQ_CQ_OP_SHIFT) 608 609 #define I40IW_CQPSQ_CQ_CQRESIZE_SHIFT 43 610 #define I40IW_CQPSQ_CQ_CQRESIZE_MASK (1ULL << I40IW_CQPSQ_CQ_CQRESIZE_SHIFT) 611 612 #define I40IW_CQPSQ_CQ_LPBLSIZE_SHIFT 44 613 #define I40IW_CQPSQ_CQ_LPBLSIZE_MASK (3ULL << I40IW_CQPSQ_CQ_LPBLSIZE_SHIFT) 614 615 #define I40IW_CQPSQ_CQ_CHKOVERFLOW_SHIFT 46 616 #define I40IW_CQPSQ_CQ_CHKOVERFLOW_MASK \ 617 (1ULL << I40IW_CQPSQ_CQ_CHKOVERFLOW_SHIFT) 618 619 #define I40IW_CQPSQ_CQ_VIRTMAP_SHIFT 47 620 #define I40IW_CQPSQ_CQ_VIRTMAP_MASK (1ULL << I40IW_CQPSQ_CQ_VIRTMAP_SHIFT) 621 622 #define I40IW_CQPSQ_CQ_ENCEQEMASK_SHIFT 48 623 #define I40IW_CQPSQ_CQ_ENCEQEMASK_MASK \ 624 (1ULL << I40IW_CQPSQ_CQ_ENCEQEMASK_SHIFT) 625 626 #define I40IW_CQPSQ_CQ_CEQIDVALID_SHIFT 49 627 #define I40IW_CQPSQ_CQ_CEQIDVALID_MASK \ 628 (1ULL << I40IW_CQPSQ_CQ_CEQIDVALID_SHIFT) 629 630 #define I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT_SHIFT 61 631 #define I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT_MASK \ 632 (1ULL << I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT_SHIFT) 633 634 /* Create/Modify/Destroy Shared Receive Queue */ 635 636 #define I40IW_CQPSQ_SRQ_RQSIZE_SHIFT 0 637 #define I40IW_CQPSQ_SRQ_RQSIZE_MASK (0xfUL << I40IW_CQPSQ_SRQ_RQSIZE_SHIFT) 638 639 #define I40IW_CQPSQ_SRQ_RQWQESIZE_SHIFT 4 640 #define I40IW_CQPSQ_SRQ_RQWQESIZE_MASK \ 641 (0x7UL << I40IW_CQPSQ_SRQ_RQWQESIZE_SHIFT) 642 643 #define I40IW_CQPSQ_SRQ_SRQLIMIT_SHIFT 32 644 #define I40IW_CQPSQ_SRQ_SRQLIMIT_MASK \ 645 (0xfffULL << I40IW_CQPSQ_SRQ_SRQLIMIT_SHIFT) 646 647 #define I40IW_CQPSQ_SRQ_SRQCTX_SHIFT I40IW_CQPHC_QPCTX_SHIFT 648 #define I40IW_CQPSQ_SRQ_SRQCTX_MASK I40IW_CQPHC_QPCTX_MASK 649 650 #define I40IW_CQPSQ_SRQ_PDID_SHIFT 16 651 #define I40IW_CQPSQ_SRQ_PDID_MASK \ 652 (0x7fffULL << I40IW_CQPSQ_SRQ_PDID_SHIFT) 653 654 #define I40IW_CQPSQ_SRQ_SRQID_SHIFT 0 655 #define I40IW_CQPSQ_SRQ_SRQID_MASK (0x7fffUL << I40IW_CQPSQ_SRQ_SRQID_SHIFT) 656 657 #define I40IW_CQPSQ_SRQ_LPBLSIZE_SHIFT I40IW_CQPSQ_CQ_LPBLSIZE_SHIFT 658 #define I40IW_CQPSQ_SRQ_LPBLSIZE_MASK I40IW_CQPSQ_CQ_LPBLSIZE_MASK 659 660 #define I40IW_CQPSQ_SRQ_VIRTMAP_SHIFT I40IW_CQPSQ_CQ_VIRTMAP_SHIFT 661 #define I40IW_CQPSQ_SRQ_VIRTMAP_MASK I40IW_CQPSQ_CQ_VIRTMAP_MASK 662 663 #define I40IW_CQPSQ_SRQ_TPHEN_SHIFT I40IW_CQPSQ_TPHEN_SHIFT 664 #define I40IW_CQPSQ_SRQ_TPHEN_MASK I40IW_CQPSQ_TPHEN_MASK 665 666 #define I40IW_CQPSQ_SRQ_ARMLIMITEVENT_SHIFT 61 667 #define I40IW_CQPSQ_SRQ_ARMLIMITEVENT_MASK \ 668 (1ULL << I40IW_CQPSQ_SRQ_ARMLIMITEVENT_SHIFT) 669 670 #define I40IW_CQPSQ_SRQ_DBSHADOWAREA_SHIFT 6 671 #define I40IW_CQPSQ_SRQ_DBSHADOWAREA_MASK \ 672 (0x3ffffffffffffffULL << I40IW_CQPSQ_SRQ_DBSHADOWAREA_SHIFT) 673 674 #define I40IW_CQPSQ_SRQ_FIRSTPMPBLIDX_SHIFT 0 675 #define I40IW_CQPSQ_SRQ_FIRSTPMPBLIDX_MASK \ 676 (0xfffffffUL << I40IW_CQPSQ_SRQ_FIRSTPMPBLIDX_SHIFT) 677 678 /* Allocate/Register/Register Shared/Deallocate Stag */ 679 #define I40IW_CQPSQ_STAG_VA_FBO_SHIFT I40IW_CQPHC_QPCTX_SHIFT 680 #define I40IW_CQPSQ_STAG_VA_FBO_MASK I40IW_CQPHC_QPCTX_MASK 681 682 #define I40IW_CQPSQ_STAG_STAGLEN_SHIFT 0 683 #define I40IW_CQPSQ_STAG_STAGLEN_MASK \ 684 (0x3fffffffffffULL << I40IW_CQPSQ_STAG_STAGLEN_SHIFT) 685 686 #define I40IW_CQPSQ_STAG_PDID_SHIFT 48 687 #define I40IW_CQPSQ_STAG_PDID_MASK (0x7fffULL << I40IW_CQPSQ_STAG_PDID_SHIFT) 688 689 #define I40IW_CQPSQ_STAG_KEY_SHIFT 0 690 #define I40IW_CQPSQ_STAG_KEY_MASK (0xffUL << I40IW_CQPSQ_STAG_KEY_SHIFT) 691 692 #define I40IW_CQPSQ_STAG_IDX_SHIFT 8 693 #define I40IW_CQPSQ_STAG_IDX_MASK (0xffffffUL << I40IW_CQPSQ_STAG_IDX_SHIFT) 694 695 #define I40IW_CQPSQ_STAG_PARENTSTAGIDX_SHIFT 32 696 #define I40IW_CQPSQ_STAG_PARENTSTAGIDX_MASK \ 697 (0xffffffULL << I40IW_CQPSQ_STAG_PARENTSTAGIDX_SHIFT) 698 699 #define I40IW_CQPSQ_STAG_MR_SHIFT 43 700 #define I40IW_CQPSQ_STAG_MR_MASK (1ULL << I40IW_CQPSQ_STAG_MR_SHIFT) 701 702 #define I40IW_CQPSQ_STAG_LPBLSIZE_SHIFT I40IW_CQPSQ_CQ_LPBLSIZE_SHIFT 703 #define I40IW_CQPSQ_STAG_LPBLSIZE_MASK I40IW_CQPSQ_CQ_LPBLSIZE_MASK 704 705 #define I40IW_CQPSQ_STAG_HPAGESIZE_SHIFT 46 706 #define I40IW_CQPSQ_STAG_HPAGESIZE_MASK \ 707 (1ULL << I40IW_CQPSQ_STAG_HPAGESIZE_SHIFT) 708 709 #define I40IW_CQPSQ_STAG_ARIGHTS_SHIFT 48 710 #define I40IW_CQPSQ_STAG_ARIGHTS_MASK \ 711 (0x1fULL << I40IW_CQPSQ_STAG_ARIGHTS_SHIFT) 712 713 #define I40IW_CQPSQ_STAG_REMACCENABLED_SHIFT 53 714 #define I40IW_CQPSQ_STAG_REMACCENABLED_MASK \ 715 (1ULL << I40IW_CQPSQ_STAG_REMACCENABLED_SHIFT) 716 717 #define I40IW_CQPSQ_STAG_VABASEDTO_SHIFT 59 718 #define I40IW_CQPSQ_STAG_VABASEDTO_MASK \ 719 (1ULL << I40IW_CQPSQ_STAG_VABASEDTO_SHIFT) 720 721 #define I40IW_CQPSQ_STAG_USEHMCFNIDX_SHIFT 60 722 #define I40IW_CQPSQ_STAG_USEHMCFNIDX_MASK \ 723 (1ULL << I40IW_CQPSQ_STAG_USEHMCFNIDX_SHIFT) 724 725 #define I40IW_CQPSQ_STAG_USEPFRID_SHIFT 61 726 #define I40IW_CQPSQ_STAG_USEPFRID_MASK \ 727 (1ULL << I40IW_CQPSQ_STAG_USEPFRID_SHIFT) 728 729 #define I40IW_CQPSQ_STAG_PBA_SHIFT I40IW_CQPHC_QPCTX_SHIFT 730 #define I40IW_CQPSQ_STAG_PBA_MASK I40IW_CQPHC_QPCTX_MASK 731 732 #define I40IW_CQPSQ_STAG_HMCFNIDX_SHIFT 0 733 #define I40IW_CQPSQ_STAG_HMCFNIDX_MASK \ 734 (0x3fUL << I40IW_CQPSQ_STAG_HMCFNIDX_SHIFT) 735 736 #define I40IW_CQPSQ_STAG_FIRSTPMPBLIDX_SHIFT 0 737 #define I40IW_CQPSQ_STAG_FIRSTPMPBLIDX_MASK \ 738 (0xfffffffUL << I40IW_CQPSQ_STAG_FIRSTPMPBLIDX_SHIFT) 739 740 /* Query stag */ 741 #define I40IW_CQPSQ_QUERYSTAG_IDX_SHIFT I40IW_CQPSQ_STAG_IDX_SHIFT 742 #define I40IW_CQPSQ_QUERYSTAG_IDX_MASK I40IW_CQPSQ_STAG_IDX_MASK 743 744 /* Allocate Local IP Address Entry */ 745 746 /* Manage Local IP Address Table - MLIPA */ 747 #define I40IW_CQPSQ_MLIPA_IPV6LO_SHIFT I40IW_CQPHC_QPCTX_SHIFT 748 #define I40IW_CQPSQ_MLIPA_IPV6LO_MASK I40IW_CQPHC_QPCTX_MASK 749 750 #define I40IW_CQPSQ_MLIPA_IPV6HI_SHIFT I40IW_CQPHC_QPCTX_SHIFT 751 #define I40IW_CQPSQ_MLIPA_IPV6HI_MASK I40IW_CQPHC_QPCTX_MASK 752 753 #define I40IW_CQPSQ_MLIPA_IPV4_SHIFT 0 754 #define I40IW_CQPSQ_MLIPA_IPV4_MASK \ 755 (0xffffffffUL << I40IW_CQPSQ_MLIPA_IPV4_SHIFT) 756 757 #define I40IW_CQPSQ_MLIPA_IPTABLEIDX_SHIFT 0 758 #define I40IW_CQPSQ_MLIPA_IPTABLEIDX_MASK \ 759 (0x3fUL << I40IW_CQPSQ_MLIPA_IPTABLEIDX_SHIFT) 760 761 #define I40IW_CQPSQ_MLIPA_IPV4VALID_SHIFT 42 762 #define I40IW_CQPSQ_MLIPA_IPV4VALID_MASK \ 763 (1ULL << I40IW_CQPSQ_MLIPA_IPV4VALID_SHIFT) 764 765 #define I40IW_CQPSQ_MLIPA_IPV6VALID_SHIFT 43 766 #define I40IW_CQPSQ_MLIPA_IPV6VALID_MASK \ 767 (1ULL << I40IW_CQPSQ_MLIPA_IPV6VALID_SHIFT) 768 769 #define I40IW_CQPSQ_MLIPA_FREEENTRY_SHIFT 62 770 #define I40IW_CQPSQ_MLIPA_FREEENTRY_MASK \ 771 (1ULL << I40IW_CQPSQ_MLIPA_FREEENTRY_SHIFT) 772 773 #define I40IW_CQPSQ_MLIPA_IGNORE_REF_CNT_SHIFT 61 774 #define I40IW_CQPSQ_MLIPA_IGNORE_REF_CNT_MASK \ 775 (1ULL << I40IW_CQPSQ_MLIPA_IGNORE_REF_CNT_SHIFT) 776 777 #define I40IW_CQPSQ_MLIPA_MAC0_SHIFT 0 778 #define I40IW_CQPSQ_MLIPA_MAC0_MASK (0xffUL << I40IW_CQPSQ_MLIPA_MAC0_SHIFT) 779 780 #define I40IW_CQPSQ_MLIPA_MAC1_SHIFT 8 781 #define I40IW_CQPSQ_MLIPA_MAC1_MASK (0xffUL << I40IW_CQPSQ_MLIPA_MAC1_SHIFT) 782 783 #define I40IW_CQPSQ_MLIPA_MAC2_SHIFT 16 784 #define I40IW_CQPSQ_MLIPA_MAC2_MASK (0xffUL << I40IW_CQPSQ_MLIPA_MAC2_SHIFT) 785 786 #define I40IW_CQPSQ_MLIPA_MAC3_SHIFT 24 787 #define I40IW_CQPSQ_MLIPA_MAC3_MASK (0xffUL << I40IW_CQPSQ_MLIPA_MAC3_SHIFT) 788 789 #define I40IW_CQPSQ_MLIPA_MAC4_SHIFT 32 790 #define I40IW_CQPSQ_MLIPA_MAC4_MASK (0xffULL << I40IW_CQPSQ_MLIPA_MAC4_SHIFT) 791 792 #define I40IW_CQPSQ_MLIPA_MAC5_SHIFT 40 793 #define I40IW_CQPSQ_MLIPA_MAC5_MASK (0xffULL << I40IW_CQPSQ_MLIPA_MAC5_SHIFT) 794 795 /* Manage ARP Table - MAT */ 796 #define I40IW_CQPSQ_MAT_REACHMAX_SHIFT 0 797 #define I40IW_CQPSQ_MAT_REACHMAX_MASK \ 798 (0xffffffffUL << I40IW_CQPSQ_MAT_REACHMAX_SHIFT) 799 800 #define I40IW_CQPSQ_MAT_MACADDR_SHIFT 0 801 #define I40IW_CQPSQ_MAT_MACADDR_MASK \ 802 (0xffffffffffffULL << I40IW_CQPSQ_MAT_MACADDR_SHIFT) 803 804 #define I40IW_CQPSQ_MAT_ARPENTRYIDX_SHIFT 0 805 #define I40IW_CQPSQ_MAT_ARPENTRYIDX_MASK \ 806 (0xfffUL << I40IW_CQPSQ_MAT_ARPENTRYIDX_SHIFT) 807 808 #define I40IW_CQPSQ_MAT_ENTRYVALID_SHIFT 42 809 #define I40IW_CQPSQ_MAT_ENTRYVALID_MASK \ 810 (1ULL << I40IW_CQPSQ_MAT_ENTRYVALID_SHIFT) 811 812 #define I40IW_CQPSQ_MAT_PERMANENT_SHIFT 43 813 #define I40IW_CQPSQ_MAT_PERMANENT_MASK \ 814 (1ULL << I40IW_CQPSQ_MAT_PERMANENT_SHIFT) 815 816 #define I40IW_CQPSQ_MAT_QUERY_SHIFT 44 817 #define I40IW_CQPSQ_MAT_QUERY_MASK (1ULL << I40IW_CQPSQ_MAT_QUERY_SHIFT) 818 819 /* Manage VF PBLE Backing Pages - MVPBP*/ 820 #define I40IW_CQPSQ_MVPBP_PD_ENTRY_CNT_SHIFT 0 821 #define I40IW_CQPSQ_MVPBP_PD_ENTRY_CNT_MASK \ 822 (0x3ffULL << I40IW_CQPSQ_MVPBP_PD_ENTRY_CNT_SHIFT) 823 824 #define I40IW_CQPSQ_MVPBP_FIRST_PD_INX_SHIFT 16 825 #define I40IW_CQPSQ_MVPBP_FIRST_PD_INX_MASK \ 826 (0x1ffULL << I40IW_CQPSQ_MVPBP_FIRST_PD_INX_SHIFT) 827 828 #define I40IW_CQPSQ_MVPBP_SD_INX_SHIFT 32 829 #define I40IW_CQPSQ_MVPBP_SD_INX_MASK \ 830 (0xfffULL << I40IW_CQPSQ_MVPBP_SD_INX_SHIFT) 831 832 #define I40IW_CQPSQ_MVPBP_INV_PD_ENT_SHIFT 62 833 #define I40IW_CQPSQ_MVPBP_INV_PD_ENT_MASK \ 834 (0x1ULL << I40IW_CQPSQ_MVPBP_INV_PD_ENT_SHIFT) 835 836 #define I40IW_CQPSQ_MVPBP_PD_PLPBA_SHIFT 3 837 #define I40IW_CQPSQ_MVPBP_PD_PLPBA_MASK \ 838 (0x1fffffffffffffffULL << I40IW_CQPSQ_MVPBP_PD_PLPBA_SHIFT) 839 840 #define I40IW_INVALID_PUSH_PAGE_INDEX 0xffff 841 842 #define I40IW_CQPSQ_MPP_QS_HANDLE_SHIFT 0 843 #define I40IW_CQPSQ_MPP_QS_HANDLE_MASK (0xffffUL << \ 844 I40IW_CQPSQ_MPP_QS_HANDLE_SHIFT) 845 846 #define I40IW_CQPSQ_MPP_PPIDX_SHIFT 0 847 #define I40IW_CQPSQ_MPP_PPIDX_MASK (0x3ffUL << I40IW_CQPSQ_MPP_PPIDX_SHIFT) 848 849 #define I40IW_CQPSQ_MPP_FREE_PAGE_SHIFT 62 850 #define I40IW_CQPSQ_MPP_FREE_PAGE_MASK (1ULL << I40IW_CQPSQ_MPP_FREE_PAGE_SHIFT) 851 852 /* Upload Context - UCTX */ 853 #define I40IW_CQPSQ_UCTX_QPCTXADDR_SHIFT I40IW_CQPHC_QPCTX_SHIFT 854 #define I40IW_CQPSQ_UCTX_QPCTXADDR_MASK I40IW_CQPHC_QPCTX_MASK 855 856 #define I40IW_CQPSQ_UCTX_QPID_SHIFT 0 857 #define I40IW_CQPSQ_UCTX_QPID_MASK (0x3ffffUL << I40IW_CQPSQ_UCTX_QPID_SHIFT) 858 859 #define I40IW_CQPSQ_UCTX_QPTYPE_SHIFT 48 860 #define I40IW_CQPSQ_UCTX_QPTYPE_MASK (0xfULL << I40IW_CQPSQ_UCTX_QPTYPE_SHIFT) 861 862 #define I40IW_CQPSQ_UCTX_RAWFORMAT_SHIFT 61 863 #define I40IW_CQPSQ_UCTX_RAWFORMAT_MASK \ 864 (1ULL << I40IW_CQPSQ_UCTX_RAWFORMAT_SHIFT) 865 866 #define I40IW_CQPSQ_UCTX_FREEZEQP_SHIFT 62 867 #define I40IW_CQPSQ_UCTX_FREEZEQP_MASK \ 868 (1ULL << I40IW_CQPSQ_UCTX_FREEZEQP_SHIFT) 869 870 /* Manage HMC PM Function Table - MHMC */ 871 #define I40IW_CQPSQ_MHMC_VFIDX_SHIFT 0 872 #define I40IW_CQPSQ_MHMC_VFIDX_MASK (0x7fUL << I40IW_CQPSQ_MHMC_VFIDX_SHIFT) 873 874 #define I40IW_CQPSQ_MHMC_FREEPMFN_SHIFT 62 875 #define I40IW_CQPSQ_MHMC_FREEPMFN_MASK \ 876 (1ULL << I40IW_CQPSQ_MHMC_FREEPMFN_SHIFT) 877 878 /* Set HMC Resource Profile - SHMCRP */ 879 #define I40IW_CQPSQ_SHMCRP_HMC_PROFILE_SHIFT 0 880 #define I40IW_CQPSQ_SHMCRP_HMC_PROFILE_MASK \ 881 (0x7ULL << I40IW_CQPSQ_SHMCRP_HMC_PROFILE_SHIFT) 882 #define I40IW_CQPSQ_SHMCRP_VFNUM_SHIFT 32 883 #define I40IW_CQPSQ_SHMCRP_VFNUM_MASK (0x3fULL << I40IW_CQPSQ_SHMCRP_VFNUM_SHIFT) 884 885 /* Create/Destroy CEQ */ 886 #define I40IW_CQPSQ_CEQ_CEQSIZE_SHIFT 0 887 #define I40IW_CQPSQ_CEQ_CEQSIZE_MASK \ 888 (0x1ffffUL << I40IW_CQPSQ_CEQ_CEQSIZE_SHIFT) 889 890 #define I40IW_CQPSQ_CEQ_CEQID_SHIFT 0 891 #define I40IW_CQPSQ_CEQ_CEQID_MASK (0x7fUL << I40IW_CQPSQ_CEQ_CEQID_SHIFT) 892 893 #define I40IW_CQPSQ_CEQ_LPBLSIZE_SHIFT I40IW_CQPSQ_CQ_LPBLSIZE_SHIFT 894 #define I40IW_CQPSQ_CEQ_LPBLSIZE_MASK I40IW_CQPSQ_CQ_LPBLSIZE_MASK 895 896 #define I40IW_CQPSQ_CEQ_VMAP_SHIFT 47 897 #define I40IW_CQPSQ_CEQ_VMAP_MASK (1ULL << I40IW_CQPSQ_CEQ_VMAP_SHIFT) 898 899 #define I40IW_CQPSQ_CEQ_FIRSTPMPBLIDX_SHIFT 0 900 #define I40IW_CQPSQ_CEQ_FIRSTPMPBLIDX_MASK \ 901 (0xfffffffUL << I40IW_CQPSQ_CEQ_FIRSTPMPBLIDX_SHIFT) 902 903 /* Create/Destroy AEQ */ 904 #define I40IW_CQPSQ_AEQ_AEQECNT_SHIFT 0 905 #define I40IW_CQPSQ_AEQ_AEQECNT_MASK \ 906 (0x7ffffUL << I40IW_CQPSQ_AEQ_AEQECNT_SHIFT) 907 908 #define I40IW_CQPSQ_AEQ_LPBLSIZE_SHIFT I40IW_CQPSQ_CQ_LPBLSIZE_SHIFT 909 #define I40IW_CQPSQ_AEQ_LPBLSIZE_MASK I40IW_CQPSQ_CQ_LPBLSIZE_MASK 910 911 #define I40IW_CQPSQ_AEQ_VMAP_SHIFT 47 912 #define I40IW_CQPSQ_AEQ_VMAP_MASK (1ULL << I40IW_CQPSQ_AEQ_VMAP_SHIFT) 913 914 #define I40IW_CQPSQ_AEQ_FIRSTPMPBLIDX_SHIFT 0 915 #define I40IW_CQPSQ_AEQ_FIRSTPMPBLIDX_MASK \ 916 (0xfffffffUL << I40IW_CQPSQ_AEQ_FIRSTPMPBLIDX_SHIFT) 917 918 /* Commit FPM Values - CFPM */ 919 #define I40IW_CQPSQ_CFPM_HMCFNID_SHIFT 0 920 #define I40IW_CQPSQ_CFPM_HMCFNID_MASK (0x3fUL << I40IW_CQPSQ_CFPM_HMCFNID_SHIFT) 921 922 /* Flush WQEs - FWQE */ 923 #define I40IW_CQPSQ_FWQE_AECODE_SHIFT 0 924 #define I40IW_CQPSQ_FWQE_AECODE_MASK (0xffffUL << I40IW_CQPSQ_FWQE_AECODE_SHIFT) 925 926 #define I40IW_CQPSQ_FWQE_AESOURCE_SHIFT 16 927 #define I40IW_CQPSQ_FWQE_AESOURCE_MASK \ 928 (0xfUL << I40IW_CQPSQ_FWQE_AESOURCE_SHIFT) 929 930 #define I40IW_CQPSQ_FWQE_RQMNERR_SHIFT 0 931 #define I40IW_CQPSQ_FWQE_RQMNERR_MASK \ 932 (0xffffUL << I40IW_CQPSQ_FWQE_RQMNERR_SHIFT) 933 934 #define I40IW_CQPSQ_FWQE_RQMJERR_SHIFT 16 935 #define I40IW_CQPSQ_FWQE_RQMJERR_MASK \ 936 (0xffffUL << I40IW_CQPSQ_FWQE_RQMJERR_SHIFT) 937 938 #define I40IW_CQPSQ_FWQE_SQMNERR_SHIFT 32 939 #define I40IW_CQPSQ_FWQE_SQMNERR_MASK \ 940 (0xffffULL << I40IW_CQPSQ_FWQE_SQMNERR_SHIFT) 941 942 #define I40IW_CQPSQ_FWQE_SQMJERR_SHIFT 48 943 #define I40IW_CQPSQ_FWQE_SQMJERR_MASK \ 944 (0xffffULL << I40IW_CQPSQ_FWQE_SQMJERR_SHIFT) 945 946 #define I40IW_CQPSQ_FWQE_QPID_SHIFT 0 947 #define I40IW_CQPSQ_FWQE_QPID_MASK (0x3ffffULL << I40IW_CQPSQ_FWQE_QPID_SHIFT) 948 949 #define I40IW_CQPSQ_FWQE_GENERATE_AE_SHIFT 59 950 #define I40IW_CQPSQ_FWQE_GENERATE_AE_MASK (1ULL << \ 951 I40IW_CQPSQ_FWQE_GENERATE_AE_SHIFT) 952 953 #define I40IW_CQPSQ_FWQE_USERFLCODE_SHIFT 60 954 #define I40IW_CQPSQ_FWQE_USERFLCODE_MASK \ 955 (1ULL << I40IW_CQPSQ_FWQE_USERFLCODE_SHIFT) 956 957 #define I40IW_CQPSQ_FWQE_FLUSHSQ_SHIFT 61 958 #define I40IW_CQPSQ_FWQE_FLUSHSQ_MASK (1ULL << I40IW_CQPSQ_FWQE_FLUSHSQ_SHIFT) 959 960 #define I40IW_CQPSQ_FWQE_FLUSHRQ_SHIFT 62 961 #define I40IW_CQPSQ_FWQE_FLUSHRQ_MASK (1ULL << I40IW_CQPSQ_FWQE_FLUSHRQ_SHIFT) 962 963 /* Manage Accelerated Port Table - MAPT */ 964 #define I40IW_CQPSQ_MAPT_PORT_SHIFT 0 965 #define I40IW_CQPSQ_MAPT_PORT_MASK (0xffffUL << I40IW_CQPSQ_MAPT_PORT_SHIFT) 966 967 #define I40IW_CQPSQ_MAPT_ADDPORT_SHIFT 62 968 #define I40IW_CQPSQ_MAPT_ADDPORT_MASK (1ULL << I40IW_CQPSQ_MAPT_ADDPORT_SHIFT) 969 970 /* Update Protocol Engine SDs */ 971 #define I40IW_CQPSQ_UPESD_SDCMD_SHIFT 0 972 #define I40IW_CQPSQ_UPESD_SDCMD_MASK (0xffffffffUL << I40IW_CQPSQ_UPESD_SDCMD_SHIFT) 973 974 #define I40IW_CQPSQ_UPESD_SDDATALOW_SHIFT 0 975 #define I40IW_CQPSQ_UPESD_SDDATALOW_MASK \ 976 (0xffffffffUL << I40IW_CQPSQ_UPESD_SDDATALOW_SHIFT) 977 978 #define I40IW_CQPSQ_UPESD_SDDATAHI_SHIFT 32 979 #define I40IW_CQPSQ_UPESD_SDDATAHI_MASK \ 980 (0xffffffffULL << I40IW_CQPSQ_UPESD_SDDATAHI_SHIFT) 981 #define I40IW_CQPSQ_UPESD_HMCFNID_SHIFT 0 982 #define I40IW_CQPSQ_UPESD_HMCFNID_MASK \ 983 (0x3fUL << I40IW_CQPSQ_UPESD_HMCFNID_SHIFT) 984 985 #define I40IW_CQPSQ_UPESD_ENTRY_VALID_SHIFT 63 986 #define I40IW_CQPSQ_UPESD_ENTRY_VALID_MASK \ 987 ((u64)1 << I40IW_CQPSQ_UPESD_ENTRY_VALID_SHIFT) 988 989 #define I40IW_CQPSQ_UPESD_ENTRY_COUNT_SHIFT 0 990 #define I40IW_CQPSQ_UPESD_ENTRY_COUNT_MASK \ 991 (0xfUL << I40IW_CQPSQ_UPESD_ENTRY_COUNT_SHIFT) 992 993 #define I40IW_CQPSQ_UPESD_SKIP_ENTRY_SHIFT 7 994 #define I40IW_CQPSQ_UPESD_SKIP_ENTRY_MASK \ 995 (0x1UL << I40IW_CQPSQ_UPESD_SKIP_ENTRY_SHIFT) 996 997 /* Suspend QP */ 998 #define I40IW_CQPSQ_SUSPENDQP_QPID_SHIFT 0 999 #define I40IW_CQPSQ_SUSPENDQP_QPID_MASK (0x3FFFFUL) 1000 /* I40IWCQ_QPID_MASK */ 1001 1002 /* Resume QP */ 1003 #define I40IW_CQPSQ_RESUMEQP_QSHANDLE_SHIFT 0 1004 #define I40IW_CQPSQ_RESUMEQP_QSHANDLE_MASK \ 1005 (0xffffffffUL << I40IW_CQPSQ_RESUMEQP_QSHANDLE_SHIFT) 1006 1007 #define I40IW_CQPSQ_RESUMEQP_QPID_SHIFT 0 1008 #define I40IW_CQPSQ_RESUMEQP_QPID_MASK (0x3FFFFUL) 1009 /* I40IWCQ_QPID_MASK */ 1010 1011 /* IW QP Context */ 1012 #define I40IWQPC_DDP_VER_SHIFT 0 1013 #define I40IWQPC_DDP_VER_MASK (3UL << I40IWQPC_DDP_VER_SHIFT) 1014 1015 #define I40IWQPC_SNAP_SHIFT 2 1016 #define I40IWQPC_SNAP_MASK (1UL << I40IWQPC_SNAP_SHIFT) 1017 1018 #define I40IWQPC_IPV4_SHIFT 3 1019 #define I40IWQPC_IPV4_MASK (1UL << I40IWQPC_IPV4_SHIFT) 1020 1021 #define I40IWQPC_NONAGLE_SHIFT 4 1022 #define I40IWQPC_NONAGLE_MASK (1UL << I40IWQPC_NONAGLE_SHIFT) 1023 1024 #define I40IWQPC_INSERTVLANTAG_SHIFT 5 1025 #define I40IWQPC_INSERTVLANTAG_MASK (1 << I40IWQPC_INSERTVLANTAG_SHIFT) 1026 1027 #define I40IWQPC_USESRQ_SHIFT 6 1028 #define I40IWQPC_USESRQ_MASK (1UL << I40IWQPC_USESRQ_SHIFT) 1029 1030 #define I40IWQPC_TIMESTAMP_SHIFT 7 1031 #define I40IWQPC_TIMESTAMP_MASK (1UL << I40IWQPC_TIMESTAMP_SHIFT) 1032 1033 #define I40IWQPC_RQWQESIZE_SHIFT 8 1034 #define I40IWQPC_RQWQESIZE_MASK (3UL << I40IWQPC_RQWQESIZE_SHIFT) 1035 1036 #define I40IWQPC_INSERTL2TAG2_SHIFT 11 1037 #define I40IWQPC_INSERTL2TAG2_MASK (1UL << I40IWQPC_INSERTL2TAG2_SHIFT) 1038 1039 #define I40IWQPC_LIMIT_SHIFT 12 1040 #define I40IWQPC_LIMIT_MASK (3UL << I40IWQPC_LIMIT_SHIFT) 1041 1042 #define I40IWQPC_DROPOOOSEG_SHIFT 15 1043 #define I40IWQPC_DROPOOOSEG_MASK (1UL << I40IWQPC_DROPOOOSEG_SHIFT) 1044 1045 #define I40IWQPC_DUPACK_THRESH_SHIFT 16 1046 #define I40IWQPC_DUPACK_THRESH_MASK (7UL << I40IWQPC_DUPACK_THRESH_SHIFT) 1047 1048 #define I40IWQPC_ERR_RQ_IDX_VALID_SHIFT 19 1049 #define I40IWQPC_ERR_RQ_IDX_VALID_MASK (1UL << I40IWQPC_ERR_RQ_IDX_VALID_SHIFT) 1050 1051 #define I40IWQPC_DIS_VLAN_CHECKS_SHIFT 19 1052 #define I40IWQPC_DIS_VLAN_CHECKS_MASK (7UL << I40IWQPC_DIS_VLAN_CHECKS_SHIFT) 1053 1054 #define I40IWQPC_RCVTPHEN_SHIFT 28 1055 #define I40IWQPC_RCVTPHEN_MASK (1UL << I40IWQPC_RCVTPHEN_SHIFT) 1056 1057 #define I40IWQPC_XMITTPHEN_SHIFT 29 1058 #define I40IWQPC_XMITTPHEN_MASK (1ULL << I40IWQPC_XMITTPHEN_SHIFT) 1059 1060 #define I40IWQPC_RQTPHEN_SHIFT 30 1061 #define I40IWQPC_RQTPHEN_MASK (1UL << I40IWQPC_RQTPHEN_SHIFT) 1062 1063 #define I40IWQPC_SQTPHEN_SHIFT 31 1064 #define I40IWQPC_SQTPHEN_MASK (1ULL << I40IWQPC_SQTPHEN_SHIFT) 1065 1066 #define I40IWQPC_PPIDX_SHIFT 32 1067 #define I40IWQPC_PPIDX_MASK (0x3ffULL << I40IWQPC_PPIDX_SHIFT) 1068 1069 #define I40IWQPC_PMENA_SHIFT 47 1070 #define I40IWQPC_PMENA_MASK (1ULL << I40IWQPC_PMENA_SHIFT) 1071 1072 #define I40IWQPC_RDMAP_VER_SHIFT 62 1073 #define I40IWQPC_RDMAP_VER_MASK (3ULL << I40IWQPC_RDMAP_VER_SHIFT) 1074 1075 #define I40IWQPC_SQADDR_SHIFT I40IW_CQPHC_QPCTX_SHIFT 1076 #define I40IWQPC_SQADDR_MASK I40IW_CQPHC_QPCTX_MASK 1077 1078 #define I40IWQPC_RQADDR_SHIFT I40IW_CQPHC_QPCTX_SHIFT 1079 #define I40IWQPC_RQADDR_MASK I40IW_CQPHC_QPCTX_MASK 1080 1081 #define I40IWQPC_TTL_SHIFT 0 1082 #define I40IWQPC_TTL_MASK (0xffUL << I40IWQPC_TTL_SHIFT) 1083 1084 #define I40IWQPC_RQSIZE_SHIFT 8 1085 #define I40IWQPC_RQSIZE_MASK (0xfUL << I40IWQPC_RQSIZE_SHIFT) 1086 1087 #define I40IWQPC_SQSIZE_SHIFT 12 1088 #define I40IWQPC_SQSIZE_MASK (0xfUL << I40IWQPC_SQSIZE_SHIFT) 1089 1090 #define I40IWQPC_SRCMACADDRIDX_SHIFT 16 1091 #define I40IWQPC_SRCMACADDRIDX_MASK (0x3fUL << I40IWQPC_SRCMACADDRIDX_SHIFT) 1092 1093 #define I40IWQPC_AVOIDSTRETCHACK_SHIFT 23 1094 #define I40IWQPC_AVOIDSTRETCHACK_MASK (1UL << I40IWQPC_AVOIDSTRETCHACK_SHIFT) 1095 1096 #define I40IWQPC_TOS_SHIFT 24 1097 #define I40IWQPC_TOS_MASK (0xffUL << I40IWQPC_TOS_SHIFT) 1098 1099 #define I40IWQPC_SRCPORTNUM_SHIFT 32 1100 #define I40IWQPC_SRCPORTNUM_MASK (0xffffULL << I40IWQPC_SRCPORTNUM_SHIFT) 1101 1102 #define I40IWQPC_DESTPORTNUM_SHIFT 48 1103 #define I40IWQPC_DESTPORTNUM_MASK (0xffffULL << I40IWQPC_DESTPORTNUM_SHIFT) 1104 1105 #define I40IWQPC_DESTIPADDR0_SHIFT 32 1106 #define I40IWQPC_DESTIPADDR0_MASK \ 1107 (0xffffffffULL << I40IWQPC_DESTIPADDR0_SHIFT) 1108 1109 #define I40IWQPC_DESTIPADDR1_SHIFT 0 1110 #define I40IWQPC_DESTIPADDR1_MASK \ 1111 (0xffffffffULL << I40IWQPC_DESTIPADDR1_SHIFT) 1112 1113 #define I40IWQPC_DESTIPADDR2_SHIFT 32 1114 #define I40IWQPC_DESTIPADDR2_MASK \ 1115 (0xffffffffULL << I40IWQPC_DESTIPADDR2_SHIFT) 1116 1117 #define I40IWQPC_DESTIPADDR3_SHIFT 0 1118 #define I40IWQPC_DESTIPADDR3_MASK \ 1119 (0xffffffffULL << I40IWQPC_DESTIPADDR3_SHIFT) 1120 1121 #define I40IWQPC_SNDMSS_SHIFT 16 1122 #define I40IWQPC_SNDMSS_MASK (0x3fffUL << I40IWQPC_SNDMSS_SHIFT) 1123 1124 #define I40IW_UDA_QPC_MAXFRAMESIZE_SHIFT 16 1125 #define I40IW_UDA_QPC_MAXFRAMESIZE_MASK (0x3fffUL << I40IW_UDA_QPC_MAXFRAMESIZE_SHIFT) 1126 1127 #define I40IWQPC_VLANTAG_SHIFT 32 1128 #define I40IWQPC_VLANTAG_MASK (0xffffULL << I40IWQPC_VLANTAG_SHIFT) 1129 1130 #define I40IWQPC_ARPIDX_SHIFT 48 1131 #define I40IWQPC_ARPIDX_MASK (0xffffULL << I40IWQPC_ARPIDX_SHIFT) 1132 1133 #define I40IWQPC_FLOWLABEL_SHIFT 0 1134 #define I40IWQPC_FLOWLABEL_MASK (0xfffffUL << I40IWQPC_FLOWLABEL_SHIFT) 1135 1136 #define I40IWQPC_WSCALE_SHIFT 20 1137 #define I40IWQPC_WSCALE_MASK (1UL << I40IWQPC_WSCALE_SHIFT) 1138 1139 #define I40IWQPC_KEEPALIVE_SHIFT 21 1140 #define I40IWQPC_KEEPALIVE_MASK (1UL << I40IWQPC_KEEPALIVE_SHIFT) 1141 1142 #define I40IWQPC_IGNORE_TCP_OPT_SHIFT 22 1143 #define I40IWQPC_IGNORE_TCP_OPT_MASK (1UL << I40IWQPC_IGNORE_TCP_OPT_SHIFT) 1144 1145 #define I40IWQPC_IGNORE_TCP_UNS_OPT_SHIFT 23 1146 #define I40IWQPC_IGNORE_TCP_UNS_OPT_MASK \ 1147 (1UL << I40IWQPC_IGNORE_TCP_UNS_OPT_SHIFT) 1148 1149 #define I40IWQPC_TCPSTATE_SHIFT 28 1150 #define I40IWQPC_TCPSTATE_MASK (0xfUL << I40IWQPC_TCPSTATE_SHIFT) 1151 1152 #define I40IWQPC_RCVSCALE_SHIFT 32 1153 #define I40IWQPC_RCVSCALE_MASK (0xfULL << I40IWQPC_RCVSCALE_SHIFT) 1154 1155 #define I40IWQPC_SNDSCALE_SHIFT 40 1156 #define I40IWQPC_SNDSCALE_MASK (0xfULL << I40IWQPC_SNDSCALE_SHIFT) 1157 1158 #define I40IWQPC_PDIDX_SHIFT 48 1159 #define I40IWQPC_PDIDX_MASK (0x7fffULL << I40IWQPC_PDIDX_SHIFT) 1160 1161 #define I40IWQPC_KALIVE_TIMER_MAX_PROBES_SHIFT 16 1162 #define I40IWQPC_KALIVE_TIMER_MAX_PROBES_MASK \ 1163 (0xffUL << I40IWQPC_KALIVE_TIMER_MAX_PROBES_SHIFT) 1164 1165 #define I40IWQPC_KEEPALIVE_INTERVAL_SHIFT 24 1166 #define I40IWQPC_KEEPALIVE_INTERVAL_MASK \ 1167 (0xffUL << I40IWQPC_KEEPALIVE_INTERVAL_SHIFT) 1168 1169 #define I40IWQPC_TIMESTAMP_RECENT_SHIFT 0 1170 #define I40IWQPC_TIMESTAMP_RECENT_MASK \ 1171 (0xffffffffUL << I40IWQPC_TIMESTAMP_RECENT_SHIFT) 1172 1173 #define I40IWQPC_TIMESTAMP_AGE_SHIFT 32 1174 #define I40IWQPC_TIMESTAMP_AGE_MASK \ 1175 (0xffffffffULL << I40IWQPC_TIMESTAMP_AGE_SHIFT) 1176 1177 #define I40IWQPC_SNDNXT_SHIFT 0 1178 #define I40IWQPC_SNDNXT_MASK (0xffffffffUL << I40IWQPC_SNDNXT_SHIFT) 1179 1180 #define I40IWQPC_SNDWND_SHIFT 32 1181 #define I40IWQPC_SNDWND_MASK (0xffffffffULL << I40IWQPC_SNDWND_SHIFT) 1182 1183 #define I40IWQPC_RCVNXT_SHIFT 0 1184 #define I40IWQPC_RCVNXT_MASK (0xffffffffUL << I40IWQPC_RCVNXT_SHIFT) 1185 1186 #define I40IWQPC_RCVWND_SHIFT 32 1187 #define I40IWQPC_RCVWND_MASK (0xffffffffULL << I40IWQPC_RCVWND_SHIFT) 1188 1189 #define I40IWQPC_SNDMAX_SHIFT 0 1190 #define I40IWQPC_SNDMAX_MASK (0xffffffffUL << I40IWQPC_SNDMAX_SHIFT) 1191 1192 #define I40IWQPC_SNDUNA_SHIFT 32 1193 #define I40IWQPC_SNDUNA_MASK (0xffffffffULL << I40IWQPC_SNDUNA_SHIFT) 1194 1195 #define I40IWQPC_SRTT_SHIFT 0 1196 #define I40IWQPC_SRTT_MASK (0xffffffffUL << I40IWQPC_SRTT_SHIFT) 1197 1198 #define I40IWQPC_RTTVAR_SHIFT 32 1199 #define I40IWQPC_RTTVAR_MASK (0xffffffffULL << I40IWQPC_RTTVAR_SHIFT) 1200 1201 #define I40IWQPC_SSTHRESH_SHIFT 0 1202 #define I40IWQPC_SSTHRESH_MASK (0xffffffffUL << I40IWQPC_SSTHRESH_SHIFT) 1203 1204 #define I40IWQPC_CWND_SHIFT 32 1205 #define I40IWQPC_CWND_MASK (0xffffffffULL << I40IWQPC_CWND_SHIFT) 1206 1207 #define I40IWQPC_SNDWL1_SHIFT 0 1208 #define I40IWQPC_SNDWL1_MASK (0xffffffffUL << I40IWQPC_SNDWL1_SHIFT) 1209 1210 #define I40IWQPC_SNDWL2_SHIFT 32 1211 #define I40IWQPC_SNDWL2_MASK (0xffffffffULL << I40IWQPC_SNDWL2_SHIFT) 1212 1213 #define I40IWQPC_ERR_RQ_IDX_SHIFT 32 1214 #define I40IWQPC_ERR_RQ_IDX_MASK (0x3fffULL << I40IWQPC_ERR_RQ_IDX_SHIFT) 1215 1216 #define I40IWQPC_MAXSNDWND_SHIFT 0 1217 #define I40IWQPC_MAXSNDWND_MASK (0xffffffffUL << I40IWQPC_MAXSNDWND_SHIFT) 1218 1219 #define I40IWQPC_REXMIT_THRESH_SHIFT 48 1220 #define I40IWQPC_REXMIT_THRESH_MASK (0x3fULL << I40IWQPC_REXMIT_THRESH_SHIFT) 1221 1222 #define I40IWQPC_TXCQNUM_SHIFT 0 1223 #define I40IWQPC_TXCQNUM_MASK (0x1ffffUL << I40IWQPC_TXCQNUM_SHIFT) 1224 1225 #define I40IWQPC_RXCQNUM_SHIFT 32 1226 #define I40IWQPC_RXCQNUM_MASK (0x1ffffULL << I40IWQPC_RXCQNUM_SHIFT) 1227 1228 #define I40IWQPC_STAT_INDEX_SHIFT 0 1229 #define I40IWQPC_STAT_INDEX_MASK (0x1fULL << I40IWQPC_STAT_INDEX_SHIFT) 1230 1231 #define I40IWQPC_Q2ADDR_SHIFT 0 1232 #define I40IWQPC_Q2ADDR_MASK (0xffffffffffffff00ULL << I40IWQPC_Q2ADDR_SHIFT) 1233 1234 #define I40IWQPC_LASTBYTESENT_SHIFT 0 1235 #define I40IWQPC_LASTBYTESENT_MASK (0xffUL << I40IWQPC_LASTBYTESENT_SHIFT) 1236 1237 #define I40IWQPC_SRQID_SHIFT 32 1238 #define I40IWQPC_SRQID_MASK (0xffULL << I40IWQPC_SRQID_SHIFT) 1239 1240 #define I40IWQPC_ORDSIZE_SHIFT 0 1241 #define I40IWQPC_ORDSIZE_MASK (0x7fUL << I40IWQPC_ORDSIZE_SHIFT) 1242 1243 #define I40IWQPC_IRDSIZE_SHIFT 16 1244 #define I40IWQPC_IRDSIZE_MASK (0x3UL << I40IWQPC_IRDSIZE_SHIFT) 1245 1246 #define I40IWQPC_WRRDRSPOK_SHIFT 20 1247 #define I40IWQPC_WRRDRSPOK_MASK (1UL << I40IWQPC_WRRDRSPOK_SHIFT) 1248 1249 #define I40IWQPC_RDOK_SHIFT 21 1250 #define I40IWQPC_RDOK_MASK (1UL << I40IWQPC_RDOK_SHIFT) 1251 1252 #define I40IWQPC_SNDMARKERS_SHIFT 22 1253 #define I40IWQPC_SNDMARKERS_MASK (1UL << I40IWQPC_SNDMARKERS_SHIFT) 1254 1255 #define I40IWQPC_BINDEN_SHIFT 23 1256 #define I40IWQPC_BINDEN_MASK (1UL << I40IWQPC_BINDEN_SHIFT) 1257 1258 #define I40IWQPC_FASTREGEN_SHIFT 24 1259 #define I40IWQPC_FASTREGEN_MASK (1UL << I40IWQPC_FASTREGEN_SHIFT) 1260 1261 #define I40IWQPC_PRIVEN_SHIFT 25 1262 #define I40IWQPC_PRIVEN_MASK (1UL << I40IWQPC_PRIVEN_SHIFT) 1263 1264 #define I40IWQPC_USESTATSINSTANCE_SHIFT 26 1265 #define I40IWQPC_USESTATSINSTANCE_MASK (1UL << I40IWQPC_USESTATSINSTANCE_SHIFT) 1266 1267 #define I40IWQPC_IWARPMODE_SHIFT 28 1268 #define I40IWQPC_IWARPMODE_MASK (1UL << I40IWQPC_IWARPMODE_SHIFT) 1269 1270 #define I40IWQPC_RCVMARKERS_SHIFT 29 1271 #define I40IWQPC_RCVMARKERS_MASK (1UL << I40IWQPC_RCVMARKERS_SHIFT) 1272 1273 #define I40IWQPC_ALIGNHDRS_SHIFT 30 1274 #define I40IWQPC_ALIGNHDRS_MASK (1UL << I40IWQPC_ALIGNHDRS_SHIFT) 1275 1276 #define I40IWQPC_RCVNOMPACRC_SHIFT 31 1277 #define I40IWQPC_RCVNOMPACRC_MASK (1UL << I40IWQPC_RCVNOMPACRC_SHIFT) 1278 1279 #define I40IWQPC_RCVMARKOFFSET_SHIFT 33 1280 #define I40IWQPC_RCVMARKOFFSET_MASK (0x1ffULL << I40IWQPC_RCVMARKOFFSET_SHIFT) 1281 1282 #define I40IWQPC_SNDMARKOFFSET_SHIFT 48 1283 #define I40IWQPC_SNDMARKOFFSET_MASK (0x1ffULL << I40IWQPC_SNDMARKOFFSET_SHIFT) 1284 1285 #define I40IWQPC_QPCOMPCTX_SHIFT I40IW_CQPHC_QPCTX_SHIFT 1286 #define I40IWQPC_QPCOMPCTX_MASK I40IW_CQPHC_QPCTX_MASK 1287 1288 #define I40IWQPC_SQTPHVAL_SHIFT 0 1289 #define I40IWQPC_SQTPHVAL_MASK (0xffUL << I40IWQPC_SQTPHVAL_SHIFT) 1290 1291 #define I40IWQPC_RQTPHVAL_SHIFT 8 1292 #define I40IWQPC_RQTPHVAL_MASK (0xffUL << I40IWQPC_RQTPHVAL_SHIFT) 1293 1294 #define I40IWQPC_QSHANDLE_SHIFT 16 1295 #define I40IWQPC_QSHANDLE_MASK (0x3ffUL << I40IWQPC_QSHANDLE_SHIFT) 1296 1297 #define I40IWQPC_EXCEPTION_LAN_QUEUE_SHIFT 32 1298 #define I40IWQPC_EXCEPTION_LAN_QUEUE_MASK (0xfffULL << \ 1299 I40IWQPC_EXCEPTION_LAN_QUEUE_SHIFT) 1300 1301 #define I40IWQPC_LOCAL_IPADDR3_SHIFT 0 1302 #define I40IWQPC_LOCAL_IPADDR3_MASK \ 1303 (0xffffffffUL << I40IWQPC_LOCAL_IPADDR3_SHIFT) 1304 1305 #define I40IWQPC_LOCAL_IPADDR2_SHIFT 32 1306 #define I40IWQPC_LOCAL_IPADDR2_MASK \ 1307 (0xffffffffULL << I40IWQPC_LOCAL_IPADDR2_SHIFT) 1308 1309 #define I40IWQPC_LOCAL_IPADDR1_SHIFT 0 1310 #define I40IWQPC_LOCAL_IPADDR1_MASK \ 1311 (0xffffffffUL << I40IWQPC_LOCAL_IPADDR1_SHIFT) 1312 1313 #define I40IWQPC_LOCAL_IPADDR0_SHIFT 32 1314 #define I40IWQPC_LOCAL_IPADDR0_MASK \ 1315 (0xffffffffULL << I40IWQPC_LOCAL_IPADDR0_SHIFT) 1316 1317 /* wqe size considering 32 bytes per wqe*/ 1318 #define I40IW_QP_SW_MIN_WQSIZE 4 /*in WRs*/ 1319 #define I40IW_SQ_RSVD 2 1320 #define I40IW_RQ_RSVD 1 1321 #define I40IW_MAX_QUANTAS_PER_WR 2 1322 #define I40IW_QP_SW_MAX_SQ_QUANTAS 2048 1323 #define I40IW_QP_SW_MAX_RQ_QUANTAS 16384 1324 #define I40IW_MAX_QP_WRS ((I40IW_QP_SW_MAX_SQ_QUANTAS / I40IW_MAX_QUANTAS_PER_WR) - 1) 1325 1326 #define I40IWQP_OP_RDMA_WRITE 0 1327 #define I40IWQP_OP_RDMA_READ 1 1328 #define I40IWQP_OP_RDMA_SEND 3 1329 #define I40IWQP_OP_RDMA_SEND_INV 4 1330 #define I40IWQP_OP_RDMA_SEND_SOL_EVENT 5 1331 #define I40IWQP_OP_RDMA_SEND_SOL_EVENT_INV 6 1332 #define I40IWQP_OP_BIND_MW 8 1333 #define I40IWQP_OP_FAST_REGISTER 9 1334 #define I40IWQP_OP_LOCAL_INVALIDATE 10 1335 #define I40IWQP_OP_RDMA_READ_LOC_INV 11 1336 #define I40IWQP_OP_NOP 12 1337 1338 #define I40IW_RSVD_SHIFT 41 1339 #define I40IW_RSVD_MASK (0x7fffULL << I40IW_RSVD_SHIFT) 1340 1341 /* iwarp QP SQ WQE common fields */ 1342 #define I40IWQPSQ_OPCODE_SHIFT 32 1343 #define I40IWQPSQ_OPCODE_MASK (0x3fULL << I40IWQPSQ_OPCODE_SHIFT) 1344 1345 #define I40IWQPSQ_ADDFRAGCNT_SHIFT 38 1346 #define I40IWQPSQ_ADDFRAGCNT_MASK (0x7ULL << I40IWQPSQ_ADDFRAGCNT_SHIFT) 1347 1348 #define I40IWQPSQ_STREAMMODE_SHIFT 58 1349 #define I40IWQPSQ_STREAMMODE_MASK (1ULL << I40IWQPSQ_STREAMMODE_SHIFT) 1350 1351 #define I40IWQPSQ_WAITFORRCVPDU_SHIFT 59 1352 #define I40IWQPSQ_WAITFORRCVPDU_MASK (1ULL << I40IWQPSQ_WAITFORRCVPDU_SHIFT) 1353 1354 #define I40IWQPSQ_READFENCE_SHIFT 60 1355 #define I40IWQPSQ_READFENCE_MASK (1ULL << I40IWQPSQ_READFENCE_SHIFT) 1356 1357 #define I40IWQPSQ_LOCALFENCE_SHIFT 61 1358 #define I40IWQPSQ_LOCALFENCE_MASK (1ULL << I40IWQPSQ_LOCALFENCE_SHIFT) 1359 1360 #define I40IWQPSQ_SIGCOMPL_SHIFT 62 1361 #define I40IWQPSQ_SIGCOMPL_MASK (1ULL << I40IWQPSQ_SIGCOMPL_SHIFT) 1362 1363 #define I40IWQPSQ_VALID_SHIFT 63 1364 #define I40IWQPSQ_VALID_MASK (1ULL << I40IWQPSQ_VALID_SHIFT) 1365 1366 #define I40IWQPSQ_FRAG_TO_SHIFT I40IW_CQPHC_QPCTX_SHIFT 1367 #define I40IWQPSQ_FRAG_TO_MASK I40IW_CQPHC_QPCTX_MASK 1368 1369 #define I40IWQPSQ_FRAG_LEN_SHIFT 0 1370 #define I40IWQPSQ_FRAG_LEN_MASK (0xffffffffUL << I40IWQPSQ_FRAG_LEN_SHIFT) 1371 1372 #define I40IWQPSQ_FRAG_STAG_SHIFT 32 1373 #define I40IWQPSQ_FRAG_STAG_MASK (0xffffffffULL << I40IWQPSQ_FRAG_STAG_SHIFT) 1374 1375 #define I40IWQPSQ_REMSTAGINV_SHIFT 0 1376 #define I40IWQPSQ_REMSTAGINV_MASK (0xffffffffUL << I40IWQPSQ_REMSTAGINV_SHIFT) 1377 1378 #define I40IWQPSQ_INLINEDATAFLAG_SHIFT 57 1379 #define I40IWQPSQ_INLINEDATAFLAG_MASK (1ULL << I40IWQPSQ_INLINEDATAFLAG_SHIFT) 1380 1381 #define I40IWQPSQ_INLINEDATALEN_SHIFT 48 1382 #define I40IWQPSQ_INLINEDATALEN_MASK \ 1383 (0x7fULL << I40IWQPSQ_INLINEDATALEN_SHIFT) 1384 1385 /* iwarp send with push mode */ 1386 #define I40IWQPSQ_WQDESCIDX_SHIFT 0 1387 #define I40IWQPSQ_WQDESCIDX_MASK (0x3fffUL << I40IWQPSQ_WQDESCIDX_SHIFT) 1388 1389 /* rdma write */ 1390 #define I40IWQPSQ_REMSTAG_SHIFT 0 1391 #define I40IWQPSQ_REMSTAG_MASK (0xffffffffUL << I40IWQPSQ_REMSTAG_SHIFT) 1392 1393 #define I40IWQPSQ_REMTO_SHIFT I40IW_CQPHC_QPCTX_SHIFT 1394 #define I40IWQPSQ_REMTO_MASK I40IW_CQPHC_QPCTX_MASK 1395 1396 /* memory window */ 1397 #define I40IWQPSQ_STAGRIGHTS_SHIFT 48 1398 #define I40IWQPSQ_STAGRIGHTS_MASK (0x1fULL << I40IWQPSQ_STAGRIGHTS_SHIFT) 1399 1400 #define I40IWQPSQ_VABASEDTO_SHIFT 53 1401 #define I40IWQPSQ_VABASEDTO_MASK (1ULL << I40IWQPSQ_VABASEDTO_SHIFT) 1402 1403 #define I40IWQPSQ_MWLEN_SHIFT I40IW_CQPHC_QPCTX_SHIFT 1404 #define I40IWQPSQ_MWLEN_MASK I40IW_CQPHC_QPCTX_MASK 1405 1406 #define I40IWQPSQ_PARENTMRSTAG_SHIFT 0 1407 #define I40IWQPSQ_PARENTMRSTAG_MASK \ 1408 (0xffffffffUL << I40IWQPSQ_PARENTMRSTAG_SHIFT) 1409 1410 #define I40IWQPSQ_MWSTAG_SHIFT 32 1411 #define I40IWQPSQ_MWSTAG_MASK (0xffffffffULL << I40IWQPSQ_MWSTAG_SHIFT) 1412 1413 #define I40IWQPSQ_BASEVA_TO_FBO_SHIFT I40IW_CQPHC_QPCTX_SHIFT 1414 #define I40IWQPSQ_BASEVA_TO_FBO_MASK I40IW_CQPHC_QPCTX_MASK 1415 1416 /* Local Invalidate */ 1417 #define I40IWQPSQ_LOCSTAG_SHIFT 32 1418 #define I40IWQPSQ_LOCSTAG_MASK (0xffffffffULL << I40IWQPSQ_LOCSTAG_SHIFT) 1419 1420 /* Fast Register */ 1421 #define I40IWQPSQ_STAGKEY_SHIFT 0 1422 #define I40IWQPSQ_STAGKEY_MASK (0xffUL << I40IWQPSQ_STAGKEY_SHIFT) 1423 1424 #define I40IWQPSQ_STAGINDEX_SHIFT 8 1425 #define I40IWQPSQ_STAGINDEX_MASK (0xffffffUL << I40IWQPSQ_STAGINDEX_SHIFT) 1426 1427 #define I40IWQPSQ_COPYHOSTPBLS_SHIFT 43 1428 #define I40IWQPSQ_COPYHOSTPBLS_MASK (1ULL << I40IWQPSQ_COPYHOSTPBLS_SHIFT) 1429 1430 #define I40IWQPSQ_LPBLSIZE_SHIFT 44 1431 #define I40IWQPSQ_LPBLSIZE_MASK (3ULL << I40IWQPSQ_LPBLSIZE_SHIFT) 1432 1433 #define I40IWQPSQ_HPAGESIZE_SHIFT 46 1434 #define I40IWQPSQ_HPAGESIZE_MASK (3ULL << I40IWQPSQ_HPAGESIZE_SHIFT) 1435 1436 #define I40IWQPSQ_STAGLEN_SHIFT 0 1437 #define I40IWQPSQ_STAGLEN_MASK (0x1ffffffffffULL << I40IWQPSQ_STAGLEN_SHIFT) 1438 1439 #define I40IWQPSQ_FIRSTPMPBLIDXLO_SHIFT 48 1440 #define I40IWQPSQ_FIRSTPMPBLIDXLO_MASK \ 1441 (0xffffULL << I40IWQPSQ_FIRSTPMPBLIDXLO_SHIFT) 1442 1443 #define I40IWQPSQ_FIRSTPMPBLIDXHI_SHIFT 0 1444 #define I40IWQPSQ_FIRSTPMPBLIDXHI_MASK \ 1445 (0xfffUL << I40IWQPSQ_FIRSTPMPBLIDXHI_SHIFT) 1446 1447 #define I40IWQPSQ_PBLADDR_SHIFT 12 1448 #define I40IWQPSQ_PBLADDR_MASK (0xfffffffffffffULL << I40IWQPSQ_PBLADDR_SHIFT) 1449 1450 /* iwarp QP RQ WQE common fields */ 1451 #define I40IWQPRQ_ADDFRAGCNT_SHIFT I40IWQPSQ_ADDFRAGCNT_SHIFT 1452 #define I40IWQPRQ_ADDFRAGCNT_MASK I40IWQPSQ_ADDFRAGCNT_MASK 1453 1454 #define I40IWQPRQ_VALID_SHIFT I40IWQPSQ_VALID_SHIFT 1455 #define I40IWQPRQ_VALID_MASK I40IWQPSQ_VALID_MASK 1456 1457 #define I40IWQPRQ_COMPLCTX_SHIFT I40IW_CQPHC_QPCTX_SHIFT 1458 #define I40IWQPRQ_COMPLCTX_MASK I40IW_CQPHC_QPCTX_MASK 1459 1460 #define I40IWQPRQ_FRAG_LEN_SHIFT I40IWQPSQ_FRAG_LEN_SHIFT 1461 #define I40IWQPRQ_FRAG_LEN_MASK I40IWQPSQ_FRAG_LEN_MASK 1462 1463 #define I40IWQPRQ_STAG_SHIFT I40IWQPSQ_FRAG_STAG_SHIFT 1464 #define I40IWQPRQ_STAG_MASK I40IWQPSQ_FRAG_STAG_MASK 1465 1466 #define I40IWQPRQ_TO_SHIFT I40IWQPSQ_FRAG_TO_SHIFT 1467 #define I40IWQPRQ_TO_MASK I40IWQPSQ_FRAG_TO_MASK 1468 1469 /* Query FPM CQP buf */ 1470 #define I40IW_QUERY_FPM_MAX_QPS_SHIFT 0 1471 #define I40IW_QUERY_FPM_MAX_QPS_MASK \ 1472 (0x7ffffUL << I40IW_QUERY_FPM_MAX_QPS_SHIFT) 1473 1474 #define I40IW_QUERY_FPM_MAX_CQS_SHIFT 0 1475 #define I40IW_QUERY_FPM_MAX_CQS_MASK \ 1476 (0x3ffffUL << I40IW_QUERY_FPM_MAX_CQS_SHIFT) 1477 1478 #define I40IW_QUERY_FPM_FIRST_PE_SD_INDEX_SHIFT 0 1479 #define I40IW_QUERY_FPM_FIRST_PE_SD_INDEX_MASK \ 1480 (0x3fffUL << I40IW_QUERY_FPM_FIRST_PE_SD_INDEX_SHIFT) 1481 1482 #define I40IW_QUERY_FPM_MAX_PE_SDS_SHIFT 32 1483 #define I40IW_QUERY_FPM_MAX_PE_SDS_MASK \ 1484 (0x3fffULL << I40IW_QUERY_FPM_MAX_PE_SDS_SHIFT) 1485 1486 #define I40IW_QUERY_FPM_MAX_QPS_SHIFT 0 1487 #define I40IW_QUERY_FPM_MAX_QPS_MASK \ 1488 (0x7ffffUL << I40IW_QUERY_FPM_MAX_QPS_SHIFT) 1489 1490 #define I40IW_QUERY_FPM_MAX_CQS_SHIFT 0 1491 #define I40IW_QUERY_FPM_MAX_CQS_MASK \ 1492 (0x3ffffUL << I40IW_QUERY_FPM_MAX_CQS_SHIFT) 1493 1494 #define I40IW_QUERY_FPM_MAX_CEQS_SHIFT 0 1495 #define I40IW_QUERY_FPM_MAX_CEQS_MASK \ 1496 (0xffUL << I40IW_QUERY_FPM_MAX_CEQS_SHIFT) 1497 1498 #define I40IW_QUERY_FPM_XFBLOCKSIZE_SHIFT 32 1499 #define I40IW_QUERY_FPM_XFBLOCKSIZE_MASK \ 1500 (0xffffffffULL << I40IW_QUERY_FPM_XFBLOCKSIZE_SHIFT) 1501 1502 #define I40IW_QUERY_FPM_Q1BLOCKSIZE_SHIFT 32 1503 #define I40IW_QUERY_FPM_Q1BLOCKSIZE_MASK \ 1504 (0xffffffffULL << I40IW_QUERY_FPM_Q1BLOCKSIZE_SHIFT) 1505 1506 #define I40IW_QUERY_FPM_HTMULTIPLIER_SHIFT 16 1507 #define I40IW_QUERY_FPM_HTMULTIPLIER_MASK \ 1508 (0xfUL << I40IW_QUERY_FPM_HTMULTIPLIER_SHIFT) 1509 1510 #define I40IW_QUERY_FPM_TIMERBUCKET_SHIFT 32 1511 #define I40IW_QUERY_FPM_TIMERBUCKET_MASK \ 1512 (0xffFFULL << I40IW_QUERY_FPM_TIMERBUCKET_SHIFT) 1513 1514 /* Static HMC pages allocated buf */ 1515 #define I40IW_SHMC_PAGE_ALLOCATED_HMC_FN_ID_SHIFT 0 1516 #define I40IW_SHMC_PAGE_ALLOCATED_HMC_FN_ID_MASK \ 1517 (0x3fUL << I40IW_SHMC_PAGE_ALLOCATED_HMC_FN_ID_SHIFT) 1518 1519 #define I40IW_HW_PAGE_SIZE 4096 1520 #define I40IW_DONE_COUNT 1000 1521 #define I40IW_SLEEP_COUNT 10 1522 1523 enum { 1524 I40IW_QUEUES_ALIGNMENT_MASK = (128 - 1), 1525 I40IW_AEQ_ALIGNMENT_MASK = (256 - 1), 1526 I40IW_Q2_ALIGNMENT_MASK = (256 - 1), 1527 I40IW_CEQ_ALIGNMENT_MASK = (256 - 1), 1528 I40IW_CQ0_ALIGNMENT_MASK = (256 - 1), 1529 I40IW_HOST_CTX_ALIGNMENT_MASK = (4 - 1), 1530 I40IW_SHADOWAREA_MASK = (128 - 1), 1531 I40IW_FPM_QUERY_BUF_ALIGNMENT_MASK = (4 - 1), 1532 I40IW_FPM_COMMIT_BUF_ALIGNMENT_MASK = (4 - 1) 1533 }; 1534 1535 enum i40iw_alignment { 1536 I40IW_CQP_ALIGNMENT = 0x200, 1537 I40IW_AEQ_ALIGNMENT = 0x100, 1538 I40IW_CEQ_ALIGNMENT = 0x100, 1539 I40IW_CQ0_ALIGNMENT = 0x100, 1540 I40IW_SD_BUF_ALIGNMENT = 0x80, 1541 I40IW_FEATURE_BUF_ALIGNMENT = 0x8 1542 }; 1543 1544 #define I40IW_WQE_SIZE_64 64 1545 1546 #define I40IW_QP_WQE_MIN_SIZE 32 1547 #define I40IW_QP_WQE_MAX_SIZE 128 1548 1549 #define I40IW_UPDATE_SD_BUF_SIZE 128 1550 1551 #define I40IW_CQE_QTYPE_RQ 0 1552 #define I40IW_CQE_QTYPE_SQ 1 1553 1554 #define I40IW_RING_INIT(_ring, _size) \ 1555 { \ 1556 (_ring).head = 0; \ 1557 (_ring).tail = 0; \ 1558 (_ring).size = (_size); \ 1559 } 1560 #define I40IW_RING_GETSIZE(_ring) ((_ring).size) 1561 #define I40IW_RING_GETCURRENT_HEAD(_ring) ((_ring).head) 1562 #define I40IW_RING_GETCURRENT_TAIL(_ring) ((_ring).tail) 1563 1564 #define I40IW_RING_MOVE_HEAD(_ring, _retcode) \ 1565 { \ 1566 register u32 size; \ 1567 size = (_ring).size; \ 1568 if (!I40IW_RING_FULL_ERR(_ring)) { \ 1569 (_ring).head = ((_ring).head + 1) % size; \ 1570 (_retcode) = 0; \ 1571 } else { \ 1572 (_retcode) = I40IW_ERR_RING_FULL; \ 1573 } \ 1574 } 1575 1576 #define I40IW_RING_MOVE_HEAD_BY_COUNT(_ring, _count, _retcode) \ 1577 { \ 1578 register u32 size; \ 1579 size = (_ring).size; \ 1580 if ((I40IW_RING_WORK_AVAILABLE(_ring) + (_count)) < size) { \ 1581 (_ring).head = ((_ring).head + (_count)) % size; \ 1582 (_retcode) = 0; \ 1583 } else { \ 1584 (_retcode) = I40IW_ERR_RING_FULL; \ 1585 } \ 1586 } 1587 1588 #define I40IW_RING_MOVE_TAIL(_ring) \ 1589 (_ring).tail = ((_ring).tail + 1) % (_ring).size 1590 1591 #define I40IW_RING_MOVE_HEAD_NOCHECK(_ring) \ 1592 (_ring).head = ((_ring).head + 1) % (_ring).size 1593 1594 #define I40IW_RING_MOVE_TAIL_BY_COUNT(_ring, _count) \ 1595 (_ring).tail = ((_ring).tail + (_count)) % (_ring).size 1596 1597 #define I40IW_RING_SET_TAIL(_ring, _pos) \ 1598 (_ring).tail = (_pos) % (_ring).size 1599 1600 #define I40IW_RING_FULL_ERR(_ring) \ 1601 ( \ 1602 (I40IW_RING_WORK_AVAILABLE(_ring) == ((_ring).size - 1)) \ 1603 ) 1604 1605 #define I40IW_ERR_RING_FULL2(_ring) \ 1606 ( \ 1607 (I40IW_RING_WORK_AVAILABLE(_ring) == ((_ring).size - 2)) \ 1608 ) 1609 1610 #define I40IW_ERR_RING_FULL3(_ring) \ 1611 ( \ 1612 (I40IW_RING_WORK_AVAILABLE(_ring) == ((_ring).size - 3)) \ 1613 ) 1614 1615 #define I40IW_RING_MORE_WORK(_ring) \ 1616 ( \ 1617 (I40IW_RING_WORK_AVAILABLE(_ring) != 0) \ 1618 ) 1619 1620 #define I40IW_RING_WORK_AVAILABLE(_ring) \ 1621 ( \ 1622 (((_ring).head + (_ring).size - (_ring).tail) % (_ring).size) \ 1623 ) 1624 1625 #define I40IW_RING_GET_WQES_AVAILABLE(_ring) \ 1626 ( \ 1627 ((_ring).size - I40IW_RING_WORK_AVAILABLE(_ring) - 1) \ 1628 ) 1629 1630 #define I40IW_ATOMIC_RING_MOVE_HEAD(_ring, index, _retcode) \ 1631 { \ 1632 index = I40IW_RING_GETCURRENT_HEAD(_ring); \ 1633 I40IW_RING_MOVE_HEAD(_ring, _retcode); \ 1634 } 1635 1636 /* Async Events codes */ 1637 #define I40IW_AE_AMP_UNALLOCATED_STAG 0x0102 1638 #define I40IW_AE_AMP_INVALID_STAG 0x0103 1639 #define I40IW_AE_AMP_BAD_QP 0x0104 1640 #define I40IW_AE_AMP_BAD_PD 0x0105 1641 #define I40IW_AE_AMP_BAD_STAG_KEY 0x0106 1642 #define I40IW_AE_AMP_BAD_STAG_INDEX 0x0107 1643 #define I40IW_AE_AMP_BOUNDS_VIOLATION 0x0108 1644 #define I40IW_AE_AMP_RIGHTS_VIOLATION 0x0109 1645 #define I40IW_AE_AMP_TO_WRAP 0x010a 1646 #define I40IW_AE_AMP_FASTREG_SHARED 0x010b 1647 #define I40IW_AE_AMP_FASTREG_VALID_STAG 0x010c 1648 #define I40IW_AE_AMP_FASTREG_MW_STAG 0x010d 1649 #define I40IW_AE_AMP_FASTREG_INVALID_RIGHTS 0x010e 1650 #define I40IW_AE_AMP_FASTREG_PBL_TABLE_OVERFLOW 0x010f 1651 #define I40IW_AE_AMP_FASTREG_INVALID_LENGTH 0x0110 1652 #define I40IW_AE_AMP_INVALIDATE_SHARED 0x0111 1653 #define I40IW_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS 0x0112 1654 #define I40IW_AE_AMP_INVALIDATE_MR_WITH_BOUND_WINDOWS 0x0113 1655 #define I40IW_AE_AMP_MWBIND_VALID_STAG 0x0114 1656 #define I40IW_AE_AMP_MWBIND_OF_MR_STAG 0x0115 1657 #define I40IW_AE_AMP_MWBIND_TO_ZERO_BASED_STAG 0x0116 1658 #define I40IW_AE_AMP_MWBIND_TO_MW_STAG 0x0117 1659 #define I40IW_AE_AMP_MWBIND_INVALID_RIGHTS 0x0118 1660 #define I40IW_AE_AMP_MWBIND_INVALID_BOUNDS 0x0119 1661 #define I40IW_AE_AMP_MWBIND_TO_INVALID_PARENT 0x011a 1662 #define I40IW_AE_AMP_MWBIND_BIND_DISABLED 0x011b 1663 #define I40IW_AE_UDA_XMIT_DGRAM_TOO_LONG 0x0132 1664 #define I40IW_AE_UDA_XMIT_DGRAM_TOO_SHORT 0x0134 1665 #define I40IW_AE_BAD_CLOSE 0x0201 1666 #define I40IW_AE_RDMAP_ROE_BAD_LLP_CLOSE 0x0202 1667 #define I40IW_AE_CQ_OPERATION_ERROR 0x0203 1668 #define I40IW_AE_PRIV_OPERATION_DENIED 0x011c 1669 #define I40IW_AE_RDMA_READ_WHILE_ORD_ZERO 0x0205 1670 #define I40IW_AE_STAG_ZERO_INVALID 0x0206 1671 #define I40IW_AE_IB_RREQ_AND_Q1_FULL 0x0207 1672 #define I40IW_AE_WQE_UNEXPECTED_OPCODE 0x020a 1673 #define I40IW_AE_WQE_INVALID_PARAMETER 0x020b 1674 #define I40IW_AE_WQE_LSMM_TOO_LONG 0x0220 1675 #define I40IW_AE_DDP_INVALID_MSN_GAP_IN_MSN 0x0301 1676 #define I40IW_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER 0x0303 1677 #define I40IW_AE_DDP_UBE_INVALID_DDP_VERSION 0x0304 1678 #define I40IW_AE_DDP_UBE_INVALID_MO 0x0305 1679 #define I40IW_AE_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE 0x0306 1680 #define I40IW_AE_DDP_UBE_INVALID_QN 0x0307 1681 #define I40IW_AE_DDP_NO_L_BIT 0x0308 1682 #define I40IW_AE_RDMAP_ROE_INVALID_RDMAP_VERSION 0x0311 1683 #define I40IW_AE_RDMAP_ROE_UNEXPECTED_OPCODE 0x0312 1684 #define I40IW_AE_ROE_INVALID_RDMA_READ_REQUEST 0x0313 1685 #define I40IW_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP 0x0314 1686 #define I40IW_AE_INVALID_ARP_ENTRY 0x0401 1687 #define I40IW_AE_INVALID_TCP_OPTION_RCVD 0x0402 1688 #define I40IW_AE_STALE_ARP_ENTRY 0x0403 1689 #define I40IW_AE_INVALID_MAC_ENTRY 0x0405 1690 #define I40IW_AE_LLP_CLOSE_COMPLETE 0x0501 1691 #define I40IW_AE_LLP_CONNECTION_RESET 0x0502 1692 #define I40IW_AE_LLP_FIN_RECEIVED 0x0503 1693 #define I40IW_AE_LLP_RECEIVED_MPA_CRC_ERROR 0x0505 1694 #define I40IW_AE_LLP_SEGMENT_TOO_LARGE 0x0506 1695 #define I40IW_AE_LLP_SEGMENT_TOO_SMALL 0x0507 1696 #define I40IW_AE_LLP_SYN_RECEIVED 0x0508 1697 #define I40IW_AE_LLP_TERMINATE_RECEIVED 0x0509 1698 #define I40IW_AE_LLP_TOO_MANY_RETRIES 0x050a 1699 #define I40IW_AE_LLP_TOO_MANY_KEEPALIVE_RETRIES 0x050b 1700 #define I40IW_AE_LLP_DOUBT_REACHABILITY 0x050c 1701 #define I40IW_AE_LLP_RX_VLAN_MISMATCH 0x050d 1702 #define I40IW_AE_RESOURCE_EXHAUSTION 0x0520 1703 #define I40IW_AE_RESET_SENT 0x0601 1704 #define I40IW_AE_TERMINATE_SENT 0x0602 1705 #define I40IW_AE_RESET_NOT_SENT 0x0603 1706 #define I40IW_AE_LCE_QP_CATASTROPHIC 0x0700 1707 #define I40IW_AE_LCE_FUNCTION_CATASTROPHIC 0x0701 1708 #define I40IW_AE_LCE_CQ_CATASTROPHIC 0x0702 1709 #define I40IW_AE_QP_SUSPEND_COMPLETE 0x0900 1710 1711 #define OP_DELETE_LOCAL_MAC_IPADDR_ENTRY 1 1712 #define OP_CEQ_DESTROY 2 1713 #define OP_AEQ_DESTROY 3 1714 #define OP_DELETE_ARP_CACHE_ENTRY 4 1715 #define OP_MANAGE_APBVT_ENTRY 5 1716 #define OP_CEQ_CREATE 6 1717 #define OP_AEQ_CREATE 7 1718 #define OP_ALLOC_LOCAL_MAC_IPADDR_ENTRY 8 1719 #define OP_ADD_LOCAL_MAC_IPADDR_ENTRY 9 1720 #define OP_MANAGE_QHASH_TABLE_ENTRY 10 1721 #define OP_QP_MODIFY 11 1722 #define OP_QP_UPLOAD_CONTEXT 12 1723 #define OP_CQ_CREATE 13 1724 #define OP_CQ_DESTROY 14 1725 #define OP_QP_CREATE 15 1726 #define OP_QP_DESTROY 16 1727 #define OP_ALLOC_STAG 17 1728 #define OP_MR_REG_NON_SHARED 18 1729 #define OP_DEALLOC_STAG 19 1730 #define OP_MW_ALLOC 20 1731 #define OP_QP_FLUSH_WQES 21 1732 #define OP_ADD_ARP_CACHE_ENTRY 22 1733 #define OP_UPDATE_PE_SDS 23 1734 #define OP_MANAGE_HMC_PM_FUNC_TABLE 24 1735 #define OP_SUSPEND 25 1736 #define OP_RESUME 26 1737 #define OP_MANAGE_VF_PBLE_BP 27 1738 #define OP_QUERY_FPM_VALUES 28 1739 #define OP_COMMIT_FPM_VALUES 29 1740 #define OP_REQUESTED_COMMANDS 30 1741 #define OP_COMPLETED_COMMANDS 31 1742 #define OP_GEN_AE 32 1743 #define OP_QUERY_RDMA_FEATURES 33 1744 #define OP_SIZE_CQP_STAT_ARRAY 34 1745 1746 #endif 1747