1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /*
3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved.
4 * Copyright (c) 2020, Intel Corporation. All rights reserved.
5 */
6
7 #ifndef MLX5_IB_H
8 #define MLX5_IB_H
9
10 #include <linux/kernel.h>
11 #include <linux/sched.h>
12 #include <rdma/ib_verbs.h>
13 #include <rdma/ib_umem.h>
14 #include <rdma/ib_smi.h>
15 #include <linux/mlx5/driver.h>
16 #include <linux/mlx5/cq.h>
17 #include <linux/mlx5/fs.h>
18 #include <linux/mlx5/qp.h>
19 #include <linux/types.h>
20 #include <linux/mlx5/transobj.h>
21 #include <rdma/ib_user_verbs.h>
22 #include <rdma/mlx5-abi.h>
23 #include <rdma/uverbs_ioctl.h>
24 #include <rdma/mlx5_user_ioctl_cmds.h>
25 #include <rdma/mlx5_user_ioctl_verbs.h>
26
27 #include "srq.h"
28
29 #define mlx5_ib_dbg(_dev, format, arg...) \
30 dev_dbg(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \
31 __LINE__, current->pid, ##arg)
32
33 #define mlx5_ib_err(_dev, format, arg...) \
34 dev_err(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \
35 __LINE__, current->pid, ##arg)
36
37 #define mlx5_ib_warn(_dev, format, arg...) \
38 dev_warn(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \
39 __LINE__, current->pid, ##arg)
40
41 #define MLX5_IB_DEFAULT_UIDX 0xffffff
42 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index)
43
44 static __always_inline unsigned long
__mlx5_log_page_size_to_bitmap(unsigned int log_pgsz_bits,unsigned int pgsz_shift)45 __mlx5_log_page_size_to_bitmap(unsigned int log_pgsz_bits,
46 unsigned int pgsz_shift)
47 {
48 unsigned int largest_pg_shift =
49 min_t(unsigned long, (1ULL << log_pgsz_bits) - 1 + pgsz_shift,
50 BITS_PER_LONG - 1);
51
52 /*
53 * Despite a command allowing it, the device does not support lower than
54 * 4k page size.
55 */
56 pgsz_shift = max_t(unsigned int, MLX5_ADAPTER_PAGE_SHIFT, pgsz_shift);
57 return GENMASK(largest_pg_shift, pgsz_shift);
58 }
59
60 /*
61 * For mkc users, instead of a page_offset the command has a start_iova which
62 * specifies both the page_offset and the on-the-wire IOVA
63 */
64 #define mlx5_umem_find_best_pgsz(umem, typ, log_pgsz_fld, pgsz_shift, iova) \
65 ib_umem_find_best_pgsz(umem, \
66 __mlx5_log_page_size_to_bitmap( \
67 __mlx5_bit_sz(typ, log_pgsz_fld), \
68 pgsz_shift), \
69 iova)
70
71 static __always_inline unsigned long
__mlx5_page_offset_to_bitmask(unsigned int page_offset_bits,unsigned int offset_shift)72 __mlx5_page_offset_to_bitmask(unsigned int page_offset_bits,
73 unsigned int offset_shift)
74 {
75 unsigned int largest_offset_shift =
76 min_t(unsigned long, page_offset_bits - 1 + offset_shift,
77 BITS_PER_LONG - 1);
78
79 return GENMASK(largest_offset_shift, offset_shift);
80 }
81
82 /*
83 * QP/CQ/WQ/etc type commands take a page offset that satisifies:
84 * page_offset_quantized * (page_size/scale) = page_offset
85 * Which restricts allowed page sizes to ones that satisify the above.
86 */
87 unsigned long __mlx5_umem_find_best_quantized_pgoff(
88 struct ib_umem *umem, unsigned long pgsz_bitmap,
89 unsigned int page_offset_bits, u64 pgoff_bitmask, unsigned int scale,
90 unsigned int *page_offset_quantized);
91 #define mlx5_umem_find_best_quantized_pgoff(umem, typ, log_pgsz_fld, \
92 pgsz_shift, page_offset_fld, \
93 scale, page_offset_quantized) \
94 __mlx5_umem_find_best_quantized_pgoff( \
95 umem, \
96 __mlx5_log_page_size_to_bitmap( \
97 __mlx5_bit_sz(typ, log_pgsz_fld), pgsz_shift), \
98 __mlx5_bit_sz(typ, page_offset_fld), \
99 GENMASK(31, order_base_2(scale)), scale, \
100 page_offset_quantized)
101
102 #define mlx5_umem_find_best_cq_quantized_pgoff(umem, typ, log_pgsz_fld, \
103 pgsz_shift, page_offset_fld, \
104 scale, page_offset_quantized) \
105 __mlx5_umem_find_best_quantized_pgoff( \
106 umem, \
107 __mlx5_log_page_size_to_bitmap( \
108 __mlx5_bit_sz(typ, log_pgsz_fld), pgsz_shift), \
109 __mlx5_bit_sz(typ, page_offset_fld), 0, scale, \
110 page_offset_quantized)
111
112 enum {
113 MLX5_IB_MMAP_OFFSET_START = 9,
114 MLX5_IB_MMAP_OFFSET_END = 255,
115 };
116
117 enum {
118 MLX5_IB_MMAP_CMD_SHIFT = 8,
119 MLX5_IB_MMAP_CMD_MASK = 0xff,
120 };
121
122 enum {
123 MLX5_RES_SCAT_DATA32_CQE = 0x1,
124 MLX5_RES_SCAT_DATA64_CQE = 0x2,
125 MLX5_REQ_SCAT_DATA32_CQE = 0x11,
126 MLX5_REQ_SCAT_DATA64_CQE = 0x22,
127 };
128
129 enum mlx5_ib_mad_ifc_flags {
130 MLX5_MAD_IFC_IGNORE_MKEY = 1,
131 MLX5_MAD_IFC_IGNORE_BKEY = 2,
132 MLX5_MAD_IFC_NET_VIEW = 4,
133 };
134
135 enum {
136 MLX5_CROSS_CHANNEL_BFREG = 0,
137 };
138
139 enum {
140 MLX5_CQE_VERSION_V0,
141 MLX5_CQE_VERSION_V1,
142 };
143
144 enum {
145 MLX5_TM_MAX_RNDV_MSG_SIZE = 64,
146 MLX5_TM_MAX_SGE = 1,
147 };
148
149 enum {
150 MLX5_IB_INVALID_UAR_INDEX = BIT(31),
151 MLX5_IB_INVALID_BFREG = BIT(31),
152 };
153
154 enum {
155 MLX5_MAX_MEMIC_PAGES = 0x100,
156 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f,
157 };
158
159 enum {
160 MLX5_MEMIC_BASE_ALIGN = 6,
161 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN,
162 };
163
164 enum mlx5_ib_mmap_type {
165 MLX5_IB_MMAP_TYPE_MEMIC = 1,
166 MLX5_IB_MMAP_TYPE_VAR = 2,
167 MLX5_IB_MMAP_TYPE_UAR_WC = 3,
168 MLX5_IB_MMAP_TYPE_UAR_NC = 4,
169 MLX5_IB_MMAP_TYPE_MEMIC_OP = 5,
170 };
171
172 struct mlx5_bfreg_info {
173 u32 *sys_pages;
174 int num_low_latency_bfregs;
175 unsigned int *count;
176
177 /*
178 * protect bfreg allocation data structs
179 */
180 struct mutex lock;
181 u32 ver;
182 u8 lib_uar_4k : 1;
183 u8 lib_uar_dyn : 1;
184 u32 num_sys_pages;
185 u32 num_static_sys_pages;
186 u32 total_num_bfregs;
187 u32 num_dyn_bfregs;
188 };
189
190 struct mlx5_ib_ucontext {
191 struct ib_ucontext ibucontext;
192 struct list_head db_page_list;
193
194 /* protect doorbell record alloc/free
195 */
196 struct mutex db_page_mutex;
197 struct mlx5_bfreg_info bfregi;
198 u8 cqe_version;
199 /* Transport Domain number */
200 u32 tdn;
201
202 u64 lib_caps;
203 u16 devx_uid;
204 /* For RoCE LAG TX affinity */
205 atomic_t tx_port_affinity;
206 };
207
to_mucontext(struct ib_ucontext * ibucontext)208 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
209 {
210 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext);
211 }
212
213 struct mlx5_ib_pd {
214 struct ib_pd ibpd;
215 u32 pdn;
216 u16 uid;
217 };
218
219 enum {
220 MLX5_IB_FLOW_ACTION_MODIFY_HEADER,
221 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT,
222 MLX5_IB_FLOW_ACTION_DECAP,
223 };
224
225 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1)
226 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1)
227 #if (MLX5_IB_FLOW_LAST_PRIO <= 0)
228 #error "Invalid number of bypass priorities"
229 #endif
230 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1)
231
232 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1)
233 #define MLX5_IB_NUM_SNIFFER_FTS 2
234 #define MLX5_IB_NUM_EGRESS_FTS 1
235 struct mlx5_ib_flow_prio {
236 struct mlx5_flow_table *flow_table;
237 unsigned int refcount;
238 };
239
240 struct mlx5_ib_flow_handler {
241 struct list_head list;
242 struct ib_flow ibflow;
243 struct mlx5_ib_flow_prio *prio;
244 struct mlx5_flow_handle *rule;
245 struct ib_counters *ibcounters;
246 struct mlx5_ib_dev *dev;
247 struct mlx5_ib_flow_matcher *flow_matcher;
248 };
249
250 struct mlx5_ib_flow_matcher {
251 struct mlx5_ib_match_params matcher_mask;
252 int mask_len;
253 enum mlx5_ib_flow_type flow_type;
254 enum mlx5_flow_namespace_type ns_type;
255 u16 priority;
256 struct mlx5_core_dev *mdev;
257 atomic_t usecnt;
258 u8 match_criteria_enable;
259 };
260
261 struct mlx5_ib_pp {
262 u16 index;
263 struct mlx5_core_dev *mdev;
264 };
265
266 struct mlx5_ib_flow_db {
267 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT];
268 struct mlx5_ib_flow_prio egress_prios[MLX5_IB_NUM_FLOW_FT];
269 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS];
270 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS];
271 struct mlx5_ib_flow_prio fdb;
272 struct mlx5_ib_flow_prio rdma_rx[MLX5_IB_NUM_FLOW_FT];
273 struct mlx5_ib_flow_prio rdma_tx[MLX5_IB_NUM_FLOW_FT];
274 struct mlx5_flow_table *lag_demux_ft;
275 /* Protect flow steering bypass flow tables
276 * when add/del flow rules.
277 * only single add/removal of flow steering rule could be done
278 * simultaneously.
279 */
280 struct mutex lock;
281 };
282
283 /* Use macros here so that don't have to duplicate
284 * enum ib_send_flags and enum ib_qp_type for low-level driver
285 */
286
287 #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0)
288 #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1)
289 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2)
290 #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3)
291 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4)
292 #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END
293
294 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1
295 /*
296 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI
297 * creates the actual hardware QP.
298 */
299 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2
300 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3
301 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4
302 #define MLX5_IB_WR_UMR IB_WR_RESERVED1
303
304 #define MLX5_IB_UMR_OCTOWORD 16
305 #define MLX5_IB_UMR_XLT_ALIGNMENT 64
306
307 #define MLX5_IB_UPD_XLT_ZAP BIT(0)
308 #define MLX5_IB_UPD_XLT_ENABLE BIT(1)
309 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2)
310 #define MLX5_IB_UPD_XLT_ADDR BIT(3)
311 #define MLX5_IB_UPD_XLT_PD BIT(4)
312 #define MLX5_IB_UPD_XLT_ACCESS BIT(5)
313 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6)
314
315 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags.
316 *
317 * These flags are intended for internal use by the mlx5_ib driver, and they
318 * rely on the range reserved for that use in the ib_qp_create_flags enum.
319 */
320 #define MLX5_IB_QP_CREATE_SQPN_QP1 IB_QP_CREATE_RESERVED_START
321 #define MLX5_IB_QP_CREATE_WC_TEST (IB_QP_CREATE_RESERVED_START << 1)
322
323 struct wr_list {
324 u16 opcode;
325 u16 next;
326 };
327
328 enum mlx5_ib_rq_flags {
329 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0,
330 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1,
331 };
332
333 struct mlx5_ib_wq {
334 struct mlx5_frag_buf_ctrl fbc;
335 u64 *wrid;
336 u32 *wr_data;
337 struct wr_list *w_list;
338 unsigned *wqe_head;
339 u16 unsig_count;
340
341 /* serialize post to the work queue
342 */
343 spinlock_t lock;
344 int wqe_cnt;
345 int max_post;
346 int max_gs;
347 int offset;
348 int wqe_shift;
349 unsigned head;
350 unsigned tail;
351 u16 cur_post;
352 u16 last_poll;
353 void *cur_edge;
354 };
355
356 enum mlx5_ib_wq_flags {
357 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1,
358 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2,
359 };
360
361 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
362 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16
363 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
364 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13
365 #define MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES 3
366
367 struct mlx5_ib_rwq {
368 struct ib_wq ibwq;
369 struct mlx5_core_qp core_qp;
370 u32 rq_num_pas;
371 u32 log_rq_stride;
372 u32 log_rq_size;
373 u32 rq_page_offset;
374 u32 log_page_size;
375 u32 log_num_strides;
376 u32 two_byte_shift_en;
377 u32 single_stride_log_num_of_bytes;
378 struct ib_umem *umem;
379 size_t buf_size;
380 unsigned int page_shift;
381 struct mlx5_db db;
382 u32 user_index;
383 u32 wqe_count;
384 u32 wqe_shift;
385 int wq_sig;
386 u32 create_flags; /* Use enum mlx5_ib_wq_flags */
387 };
388
389 struct mlx5_ib_rwq_ind_table {
390 struct ib_rwq_ind_table ib_rwq_ind_tbl;
391 u32 rqtn;
392 u16 uid;
393 };
394
395 struct mlx5_ib_ubuffer {
396 struct ib_umem *umem;
397 int buf_size;
398 u64 buf_addr;
399 };
400
401 struct mlx5_ib_qp_base {
402 struct mlx5_ib_qp *container_mibqp;
403 struct mlx5_core_qp mqp;
404 struct mlx5_ib_ubuffer ubuffer;
405 };
406
407 struct mlx5_ib_qp_trans {
408 struct mlx5_ib_qp_base base;
409 u16 xrcdn;
410 u32 alt_port;
411 u8 atomic_rd_en;
412 u8 resp_depth;
413 };
414
415 struct mlx5_ib_rss_qp {
416 u32 tirn;
417 };
418
419 struct mlx5_ib_rq {
420 struct mlx5_ib_qp_base base;
421 struct mlx5_ib_wq *rq;
422 struct mlx5_ib_ubuffer ubuffer;
423 struct mlx5_db *doorbell;
424 u32 tirn;
425 u8 state;
426 u32 flags;
427 };
428
429 struct mlx5_ib_sq {
430 struct mlx5_ib_qp_base base;
431 struct mlx5_ib_wq *sq;
432 struct mlx5_ib_ubuffer ubuffer;
433 struct mlx5_db *doorbell;
434 struct mlx5_flow_handle *flow_rule;
435 u32 tisn;
436 u8 state;
437 };
438
439 struct mlx5_ib_raw_packet_qp {
440 struct mlx5_ib_sq sq;
441 struct mlx5_ib_rq rq;
442 };
443
444 struct mlx5_bf {
445 int buf_size;
446 unsigned long offset;
447 struct mlx5_sq_bfreg *bfreg;
448 };
449
450 struct mlx5_ib_dct {
451 struct mlx5_core_dct mdct;
452 u32 *in;
453 };
454
455 struct mlx5_ib_gsi_qp {
456 struct ib_qp *rx_qp;
457 u32 port_num;
458 struct ib_qp_cap cap;
459 struct ib_cq *cq;
460 struct mlx5_ib_gsi_wr *outstanding_wrs;
461 u32 outstanding_pi, outstanding_ci;
462 int num_qps;
463 /* Protects access to the tx_qps. Post send operations synchronize
464 * with tx_qp creation in setup_qp(). Also protects the
465 * outstanding_wrs array and indices.
466 */
467 spinlock_t lock;
468 struct ib_qp **tx_qps;
469 };
470
471 struct mlx5_ib_qp {
472 struct ib_qp ibqp;
473 union {
474 struct mlx5_ib_qp_trans trans_qp;
475 struct mlx5_ib_raw_packet_qp raw_packet_qp;
476 struct mlx5_ib_rss_qp rss_qp;
477 struct mlx5_ib_dct dct;
478 struct mlx5_ib_gsi_qp gsi;
479 };
480 struct mlx5_frag_buf buf;
481
482 struct mlx5_db db;
483 struct mlx5_ib_wq rq;
484
485 u8 sq_signal_bits;
486 u8 next_fence;
487 struct mlx5_ib_wq sq;
488
489 /* serialize qp state modifications
490 */
491 struct mutex mutex;
492 /* cached variant of create_flags from struct ib_qp_init_attr */
493 u32 flags;
494 u32 port;
495 u8 state;
496 int max_inline_data;
497 struct mlx5_bf bf;
498 u8 has_rq:1;
499 u8 is_rss:1;
500
501 /* only for user space QPs. For kernel
502 * we have it from the bf object
503 */
504 int bfregn;
505
506 struct list_head qps_list;
507 struct list_head cq_recv_list;
508 struct list_head cq_send_list;
509 struct mlx5_rate_limit rl;
510 u32 underlay_qpn;
511 u32 flags_en;
512 /*
513 * IB/core doesn't store low-level QP types, so
514 * store both MLX and IBTA types in the field below.
515 * IB_QPT_DRIVER will be break to DCI/DCT subtypes.
516 */
517 enum ib_qp_type type;
518 /* A flag to indicate if there's a new counter is configured
519 * but not take effective
520 */
521 u32 counter_pending;
522 u16 gsi_lag_port;
523 };
524
525 struct mlx5_ib_cq_buf {
526 struct mlx5_frag_buf_ctrl fbc;
527 struct mlx5_frag_buf frag_buf;
528 struct ib_umem *umem;
529 int cqe_size;
530 int nent;
531 };
532
533 struct mlx5_umr_wr {
534 struct ib_send_wr wr;
535 u64 virt_addr;
536 u64 offset;
537 struct ib_pd *pd;
538 unsigned int page_shift;
539 unsigned int xlt_size;
540 u64 length;
541 int access_flags;
542 u32 mkey;
543 u8 ignore_free_state:1;
544 };
545
umr_wr(const struct ib_send_wr * wr)546 static inline const struct mlx5_umr_wr *umr_wr(const struct ib_send_wr *wr)
547 {
548 return container_of(wr, struct mlx5_umr_wr, wr);
549 }
550
551 enum mlx5_ib_cq_pr_flags {
552 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0,
553 };
554
555 struct mlx5_ib_cq {
556 struct ib_cq ibcq;
557 struct mlx5_core_cq mcq;
558 struct mlx5_ib_cq_buf buf;
559 struct mlx5_db db;
560
561 /* serialize access to the CQ
562 */
563 spinlock_t lock;
564
565 /* protect resize cq
566 */
567 struct mutex resize_mutex;
568 struct mlx5_ib_cq_buf *resize_buf;
569 struct ib_umem *resize_umem;
570 int cqe_size;
571 struct list_head list_send_qp;
572 struct list_head list_recv_qp;
573 u32 create_flags;
574 struct list_head wc_list;
575 enum ib_cq_notify_flags notify_flags;
576 struct work_struct notify_work;
577 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */
578 };
579
580 struct mlx5_ib_wc {
581 struct ib_wc wc;
582 struct list_head list;
583 };
584
585 struct mlx5_ib_srq {
586 struct ib_srq ibsrq;
587 struct mlx5_core_srq msrq;
588 struct mlx5_frag_buf buf;
589 struct mlx5_db db;
590 struct mlx5_frag_buf_ctrl fbc;
591 u64 *wrid;
592 /* protect SRQ hanlding
593 */
594 spinlock_t lock;
595 int head;
596 int tail;
597 u16 wqe_ctr;
598 struct ib_umem *umem;
599 /* serialize arming a SRQ
600 */
601 struct mutex mutex;
602 int wq_sig;
603 };
604
605 struct mlx5_ib_xrcd {
606 struct ib_xrcd ibxrcd;
607 u32 xrcdn;
608 };
609
610 enum mlx5_ib_mtt_access_flags {
611 MLX5_IB_MTT_READ = (1 << 0),
612 MLX5_IB_MTT_WRITE = (1 << 1),
613 };
614
615 struct mlx5_user_mmap_entry {
616 struct rdma_user_mmap_entry rdma_entry;
617 u8 mmap_flag;
618 u64 address;
619 u32 page_idx;
620 };
621
622 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE)
623
624 #define MLX5_IB_DM_MEMIC_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\
625 IB_ACCESS_REMOTE_WRITE |\
626 IB_ACCESS_REMOTE_READ |\
627 IB_ACCESS_REMOTE_ATOMIC |\
628 IB_ZERO_BASED)
629
630 #define MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\
631 IB_ACCESS_REMOTE_WRITE |\
632 IB_ACCESS_REMOTE_READ |\
633 IB_ZERO_BASED)
634
635 #define mlx5_update_odp_stats(mr, counter_name, value) \
636 atomic64_add(value, &((mr)->odp_stats.counter_name))
637
638 struct mlx5_ib_mr {
639 struct ib_mr ibmr;
640 struct mlx5_core_mkey mmkey;
641
642 /* User MR data */
643 struct mlx5_cache_ent *cache_ent;
644 struct ib_umem *umem;
645
646 /* This is zero'd when the MR is allocated */
647 union {
648 /* Used only while the MR is in the cache */
649 struct {
650 u32 out[MLX5_ST_SZ_DW(create_mkey_out)];
651 struct mlx5_async_work cb_work;
652 /* Cache list element */
653 struct list_head list;
654 };
655
656 /* Used only by kernel MRs (umem == NULL) */
657 struct {
658 void *descs;
659 void *descs_alloc;
660 dma_addr_t desc_map;
661 int max_descs;
662 int ndescs;
663 int desc_size;
664 int access_mode;
665
666 /* For Kernel IB_MR_TYPE_INTEGRITY */
667 struct mlx5_core_sig_ctx *sig;
668 struct mlx5_ib_mr *pi_mr;
669 struct mlx5_ib_mr *klm_mr;
670 struct mlx5_ib_mr *mtt_mr;
671 u64 data_iova;
672 u64 pi_iova;
673 int meta_ndescs;
674 int meta_length;
675 int data_length;
676 };
677
678 /* Used only by User MRs (umem != NULL) */
679 struct {
680 unsigned int page_shift;
681 /* Current access_flags */
682 int access_flags;
683
684 /* For User ODP */
685 struct mlx5_ib_mr *parent;
686 struct xarray implicit_children;
687 union {
688 struct work_struct work;
689 } odp_destroy;
690 struct ib_odp_counters odp_stats;
691 bool is_odp_implicit;
692 };
693 };
694 };
695
696 /* Zero the fields in the mr that are variant depending on usage */
mlx5_clear_mr(struct mlx5_ib_mr * mr)697 static inline void mlx5_clear_mr(struct mlx5_ib_mr *mr)
698 {
699 memset(mr->out, 0, sizeof(*mr) - offsetof(struct mlx5_ib_mr, out));
700 }
701
is_odp_mr(struct mlx5_ib_mr * mr)702 static inline bool is_odp_mr(struct mlx5_ib_mr *mr)
703 {
704 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem &&
705 mr->umem->is_odp;
706 }
707
is_dmabuf_mr(struct mlx5_ib_mr * mr)708 static inline bool is_dmabuf_mr(struct mlx5_ib_mr *mr)
709 {
710 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem &&
711 mr->umem->is_dmabuf;
712 }
713
714 struct mlx5_ib_mw {
715 struct ib_mw ibmw;
716 struct mlx5_core_mkey mmkey;
717 int ndescs;
718 };
719
720 struct mlx5_ib_devx_mr {
721 struct mlx5_core_mkey mmkey;
722 int ndescs;
723 };
724
725 struct mlx5_ib_umr_context {
726 struct ib_cqe cqe;
727 enum ib_wc_status status;
728 struct completion done;
729 };
730
731 struct umr_common {
732 struct ib_pd *pd;
733 struct ib_cq *cq;
734 struct ib_qp *qp;
735 /* control access to UMR QP
736 */
737 struct semaphore sem;
738 };
739
740 struct mlx5_cache_ent {
741 struct list_head head;
742 /* sync access to the cahce entry
743 */
744 spinlock_t lock;
745
746
747 char name[4];
748 u32 order;
749 u32 xlt;
750 u32 access_mode;
751 u32 page;
752
753 u8 disabled:1;
754 u8 fill_to_high_water:1;
755
756 /*
757 * - available_mrs is the length of list head, ie the number of MRs
758 * available for immediate allocation.
759 * - total_mrs is available_mrs plus all in use MRs that could be
760 * returned to the cache.
761 * - limit is the low water mark for available_mrs, 2* limit is the
762 * upper water mark.
763 * - pending is the number of MRs currently being created
764 */
765 u32 total_mrs;
766 u32 available_mrs;
767 u32 limit;
768 u32 pending;
769
770 /* Statistics */
771 u32 miss;
772
773 struct mlx5_ib_dev *dev;
774 struct work_struct work;
775 struct delayed_work dwork;
776 };
777
778 struct mlx5_mr_cache {
779 struct workqueue_struct *wq;
780 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES];
781 struct dentry *root;
782 unsigned long last_add;
783 };
784
785 struct mlx5_ib_port_resources {
786 struct mlx5_ib_gsi_qp *gsi;
787 struct work_struct pkey_change_work;
788 };
789
790 struct mlx5_ib_resources {
791 struct ib_cq *c0;
792 u32 xrcdn0;
793 u32 xrcdn1;
794 struct ib_pd *p0;
795 struct ib_srq *s0;
796 struct ib_srq *s1;
797 struct mlx5_ib_port_resources ports[2];
798 /* Protects changes to the port resources */
799 struct mutex mutex;
800 };
801
802 struct mlx5_ib_counters {
803 const char **names;
804 size_t *offsets;
805 u32 num_q_counters;
806 u32 num_cong_counters;
807 u32 num_ext_ppcnt_counters;
808 u16 set_id;
809 };
810
811 struct mlx5_ib_multiport_info;
812
813 struct mlx5_ib_multiport {
814 struct mlx5_ib_multiport_info *mpi;
815 /* To be held when accessing the multiport info */
816 spinlock_t mpi_lock;
817 };
818
819 struct mlx5_roce {
820 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL
821 * netdev pointer
822 */
823 rwlock_t netdev_lock;
824 struct net_device *netdev;
825 struct notifier_block nb;
826 atomic_t tx_port_affinity;
827 enum ib_port_state last_port_state;
828 struct mlx5_ib_dev *dev;
829 u32 native_port_num;
830 };
831
832 struct mlx5_ib_port {
833 struct mlx5_ib_counters cnts;
834 struct mlx5_ib_multiport mp;
835 struct mlx5_ib_dbg_cc_params *dbg_cc_params;
836 struct mlx5_roce roce;
837 struct mlx5_eswitch_rep *rep;
838 };
839
840 struct mlx5_ib_dbg_param {
841 int offset;
842 struct mlx5_ib_dev *dev;
843 struct dentry *dentry;
844 u32 port_num;
845 };
846
847 enum mlx5_ib_dbg_cc_types {
848 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE,
849 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI,
850 MLX5_IB_DBG_CC_RP_TIME_RESET,
851 MLX5_IB_DBG_CC_RP_BYTE_RESET,
852 MLX5_IB_DBG_CC_RP_THRESHOLD,
853 MLX5_IB_DBG_CC_RP_AI_RATE,
854 MLX5_IB_DBG_CC_RP_MAX_RATE,
855 MLX5_IB_DBG_CC_RP_HAI_RATE,
856 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC,
857 MLX5_IB_DBG_CC_RP_MIN_RATE,
858 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP,
859 MLX5_IB_DBG_CC_RP_DCE_TCP_G,
860 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT,
861 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD,
862 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE,
863 MLX5_IB_DBG_CC_RP_GD,
864 MLX5_IB_DBG_CC_NP_MIN_TIME_BETWEEN_CNPS,
865 MLX5_IB_DBG_CC_NP_CNP_DSCP,
866 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE,
867 MLX5_IB_DBG_CC_NP_CNP_PRIO,
868 MLX5_IB_DBG_CC_MAX,
869 };
870
871 struct mlx5_ib_dbg_cc_params {
872 struct dentry *root;
873 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX];
874 };
875
876 enum {
877 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100,
878 };
879
880 struct mlx5_ib_delay_drop {
881 struct mlx5_ib_dev *dev;
882 struct work_struct delay_drop_work;
883 /* serialize setting of delay drop */
884 struct mutex lock;
885 u32 timeout;
886 bool activate;
887 atomic_t events_cnt;
888 atomic_t rqs_cnt;
889 struct dentry *dir_debugfs;
890 };
891
892 enum mlx5_ib_stages {
893 MLX5_IB_STAGE_INIT,
894 MLX5_IB_STAGE_FS,
895 MLX5_IB_STAGE_CAPS,
896 MLX5_IB_STAGE_NON_DEFAULT_CB,
897 MLX5_IB_STAGE_ROCE,
898 MLX5_IB_STAGE_QP,
899 MLX5_IB_STAGE_SRQ,
900 MLX5_IB_STAGE_DEVICE_RESOURCES,
901 MLX5_IB_STAGE_DEVICE_NOTIFIER,
902 MLX5_IB_STAGE_ODP,
903 MLX5_IB_STAGE_COUNTERS,
904 MLX5_IB_STAGE_CONG_DEBUGFS,
905 MLX5_IB_STAGE_UAR,
906 MLX5_IB_STAGE_BFREG,
907 MLX5_IB_STAGE_PRE_IB_REG_UMR,
908 MLX5_IB_STAGE_WHITELIST_UID,
909 MLX5_IB_STAGE_IB_REG,
910 MLX5_IB_STAGE_POST_IB_REG_UMR,
911 MLX5_IB_STAGE_DELAY_DROP,
912 MLX5_IB_STAGE_RESTRACK,
913 MLX5_IB_STAGE_MAX,
914 };
915
916 struct mlx5_ib_stage {
917 int (*init)(struct mlx5_ib_dev *dev);
918 void (*cleanup)(struct mlx5_ib_dev *dev);
919 };
920
921 #define STAGE_CREATE(_stage, _init, _cleanup) \
922 .stage[_stage] = {.init = _init, .cleanup = _cleanup}
923
924 struct mlx5_ib_profile {
925 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX];
926 };
927
928 struct mlx5_ib_multiport_info {
929 struct list_head list;
930 struct mlx5_ib_dev *ibdev;
931 struct mlx5_core_dev *mdev;
932 struct notifier_block mdev_events;
933 struct completion unref_comp;
934 u64 sys_image_guid;
935 u32 mdev_refcnt;
936 bool is_master;
937 bool unaffiliate;
938 };
939
940 struct mlx5_ib_flow_action {
941 struct ib_flow_action ib_action;
942 union {
943 struct {
944 u64 ib_flags;
945 struct mlx5_accel_esp_xfrm *ctx;
946 } esp_aes_gcm;
947 struct {
948 struct mlx5_ib_dev *dev;
949 u32 sub_type;
950 union {
951 struct mlx5_modify_hdr *modify_hdr;
952 struct mlx5_pkt_reformat *pkt_reformat;
953 };
954 } flow_action_raw;
955 };
956 };
957
958 struct mlx5_dm {
959 struct mlx5_core_dev *dev;
960 /* This lock is used to protect the access to the shared
961 * allocation map when concurrent requests by different
962 * processes are handled.
963 */
964 spinlock_t lock;
965 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES);
966 };
967
968 struct mlx5_read_counters_attr {
969 struct mlx5_fc *hw_cntrs_hndl;
970 u64 *out;
971 u32 flags;
972 };
973
974 enum mlx5_ib_counters_type {
975 MLX5_IB_COUNTERS_FLOW,
976 };
977
978 struct mlx5_ib_mcounters {
979 struct ib_counters ibcntrs;
980 enum mlx5_ib_counters_type type;
981 /* number of counters supported for this counters type */
982 u32 counters_num;
983 struct mlx5_fc *hw_cntrs_hndl;
984 /* read function for this counters type */
985 int (*read_counters)(struct ib_device *ibdev,
986 struct mlx5_read_counters_attr *read_attr);
987 /* max index set as part of create_flow */
988 u32 cntrs_max_index;
989 /* number of counters data entries (<description,index> pair) */
990 u32 ncounters;
991 /* counters data array for descriptions and indexes */
992 struct mlx5_ib_flow_counters_desc *counters_data;
993 /* protects access to mcounters internal data */
994 struct mutex mcntrs_mutex;
995 };
996
997 static inline struct mlx5_ib_mcounters *
to_mcounters(struct ib_counters * ibcntrs)998 to_mcounters(struct ib_counters *ibcntrs)
999 {
1000 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs);
1001 }
1002
1003 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
1004 bool is_egress,
1005 struct mlx5_flow_act *action);
1006 struct mlx5_ib_lb_state {
1007 /* protect the user_td */
1008 struct mutex mutex;
1009 u32 user_td;
1010 int qps;
1011 bool enabled;
1012 };
1013
1014 struct mlx5_ib_pf_eq {
1015 struct notifier_block irq_nb;
1016 struct mlx5_ib_dev *dev;
1017 struct mlx5_eq *core;
1018 struct work_struct work;
1019 spinlock_t lock; /* Pagefaults spinlock */
1020 struct workqueue_struct *wq;
1021 mempool_t *pool;
1022 };
1023
1024 struct mlx5_devx_event_table {
1025 struct mlx5_nb devx_nb;
1026 /* serialize updating the event_xa */
1027 struct mutex event_xa_lock;
1028 struct xarray event_xa;
1029 };
1030
1031 struct mlx5_var_table {
1032 /* serialize updating the bitmap */
1033 struct mutex bitmap_lock;
1034 unsigned long *bitmap;
1035 u64 hw_start_addr;
1036 u32 stride_size;
1037 u64 num_var_hw_entries;
1038 };
1039
1040 struct mlx5_port_caps {
1041 bool has_smi;
1042 u8 ext_port_cap;
1043 };
1044
1045 struct mlx5_ib_dev {
1046 struct ib_device ib_dev;
1047 struct mlx5_core_dev *mdev;
1048 struct notifier_block mdev_events;
1049 int num_ports;
1050 /* serialize update of capability mask
1051 */
1052 struct mutex cap_mask_mutex;
1053 u8 ib_active:1;
1054 u8 is_rep:1;
1055 u8 lag_active:1;
1056 u8 wc_support:1;
1057 u8 fill_delay;
1058 struct umr_common umrc;
1059 /* sync used page count stats
1060 */
1061 struct mlx5_ib_resources devr;
1062
1063 atomic_t mkey_var;
1064 struct mlx5_mr_cache cache;
1065 struct timer_list delay_timer;
1066 /* Prevents soft lock on massive reg MRs */
1067 struct mutex slow_path_mutex;
1068 struct ib_odp_caps odp_caps;
1069 u64 odp_max_size;
1070 struct mutex odp_eq_mutex;
1071 struct mlx5_ib_pf_eq odp_pf_eq;
1072
1073 struct xarray odp_mkeys;
1074
1075 u32 null_mkey;
1076 struct mlx5_ib_flow_db *flow_db;
1077 /* protect resources needed as part of reset flow */
1078 spinlock_t reset_flow_resource_lock;
1079 struct list_head qp_list;
1080 /* Array with num_ports elements */
1081 struct mlx5_ib_port *port;
1082 struct mlx5_sq_bfreg bfreg;
1083 struct mlx5_sq_bfreg wc_bfreg;
1084 struct mlx5_sq_bfreg fp_bfreg;
1085 struct mlx5_ib_delay_drop delay_drop;
1086 const struct mlx5_ib_profile *profile;
1087
1088 struct mlx5_ib_lb_state lb;
1089 u8 umr_fence;
1090 struct list_head ib_dev_list;
1091 u64 sys_image_guid;
1092 struct mlx5_dm dm;
1093 u16 devx_whitelist_uid;
1094 struct mlx5_srq_table srq_table;
1095 struct mlx5_qp_table qp_table;
1096 struct mlx5_async_ctx async_ctx;
1097 struct mlx5_devx_event_table devx_event_table;
1098 struct mlx5_var_table var_table;
1099
1100 struct xarray sig_mrs;
1101 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
1102 u16 pkey_table_len;
1103 };
1104
to_mibcq(struct mlx5_core_cq * mcq)1105 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq)
1106 {
1107 return container_of(mcq, struct mlx5_ib_cq, mcq);
1108 }
1109
to_mxrcd(struct ib_xrcd * ibxrcd)1110 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd)
1111 {
1112 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd);
1113 }
1114
to_mdev(struct ib_device * ibdev)1115 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev)
1116 {
1117 return container_of(ibdev, struct mlx5_ib_dev, ib_dev);
1118 }
1119
mr_to_mdev(struct mlx5_ib_mr * mr)1120 static inline struct mlx5_ib_dev *mr_to_mdev(struct mlx5_ib_mr *mr)
1121 {
1122 return to_mdev(mr->ibmr.device);
1123 }
1124
mlx5_udata_to_mdev(struct ib_udata * udata)1125 static inline struct mlx5_ib_dev *mlx5_udata_to_mdev(struct ib_udata *udata)
1126 {
1127 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
1128 udata, struct mlx5_ib_ucontext, ibucontext);
1129
1130 return to_mdev(context->ibucontext.device);
1131 }
1132
to_mcq(struct ib_cq * ibcq)1133 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq)
1134 {
1135 return container_of(ibcq, struct mlx5_ib_cq, ibcq);
1136 }
1137
to_mibqp(struct mlx5_core_qp * mqp)1138 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp)
1139 {
1140 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp;
1141 }
1142
to_mibrwq(struct mlx5_core_qp * core_qp)1143 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp)
1144 {
1145 return container_of(core_qp, struct mlx5_ib_rwq, core_qp);
1146 }
1147
to_mpd(struct ib_pd * ibpd)1148 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd)
1149 {
1150 return container_of(ibpd, struct mlx5_ib_pd, ibpd);
1151 }
1152
to_msrq(struct ib_srq * ibsrq)1153 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq)
1154 {
1155 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq);
1156 }
1157
to_mqp(struct ib_qp * ibqp)1158 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp)
1159 {
1160 return container_of(ibqp, struct mlx5_ib_qp, ibqp);
1161 }
1162
to_mrwq(struct ib_wq * ibwq)1163 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq)
1164 {
1165 return container_of(ibwq, struct mlx5_ib_rwq, ibwq);
1166 }
1167
to_mrwq_ind_table(struct ib_rwq_ind_table * ib_rwq_ind_tbl)1168 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
1169 {
1170 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl);
1171 }
1172
to_mibsrq(struct mlx5_core_srq * msrq)1173 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq)
1174 {
1175 return container_of(msrq, struct mlx5_ib_srq, msrq);
1176 }
1177
to_mmr(struct ib_mr * ibmr)1178 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr)
1179 {
1180 return container_of(ibmr, struct mlx5_ib_mr, ibmr);
1181 }
1182
to_mmw(struct ib_mw * ibmw)1183 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw)
1184 {
1185 return container_of(ibmw, struct mlx5_ib_mw, ibmw);
1186 }
1187
1188 static inline struct mlx5_ib_flow_action *
to_mflow_act(struct ib_flow_action * ibact)1189 to_mflow_act(struct ib_flow_action *ibact)
1190 {
1191 return container_of(ibact, struct mlx5_ib_flow_action, ib_action);
1192 }
1193
1194 static inline struct mlx5_user_mmap_entry *
to_mmmap(struct rdma_user_mmap_entry * rdma_entry)1195 to_mmmap(struct rdma_user_mmap_entry *rdma_entry)
1196 {
1197 return container_of(rdma_entry,
1198 struct mlx5_user_mmap_entry, rdma_entry);
1199 }
1200
1201 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context,
1202 struct ib_udata *udata, unsigned long virt,
1203 struct mlx5_db *db);
1204 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db);
1205 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
1206 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
1207 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index);
1208 int mlx5_ib_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr,
1209 struct ib_udata *udata);
1210 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
mlx5_ib_destroy_ah(struct ib_ah * ah,u32 flags)1211 static inline int mlx5_ib_destroy_ah(struct ib_ah *ah, u32 flags)
1212 {
1213 return 0;
1214 }
1215 int mlx5_ib_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr,
1216 struct ib_udata *udata);
1217 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
1218 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
1219 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr);
1220 int mlx5_ib_destroy_srq(struct ib_srq *srq, struct ib_udata *udata);
1221 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr,
1222 const struct ib_recv_wr **bad_wr);
1223 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp);
1224 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp);
1225 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1226 struct ib_qp_init_attr *init_attr,
1227 struct ib_udata *udata);
1228 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1229 int attr_mask, struct ib_udata *udata);
1230 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
1231 struct ib_qp_init_attr *qp_init_attr);
1232 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata);
1233 void mlx5_ib_drain_sq(struct ib_qp *qp);
1234 void mlx5_ib_drain_rq(struct ib_qp *qp);
1235 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
1236 size_t buflen, size_t *bc);
1237 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
1238 size_t buflen, size_t *bc);
1239 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer,
1240 size_t buflen, size_t *bc);
1241 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
1242 struct ib_udata *udata);
1243 int mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata);
1244 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
1245 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
1246 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period);
1247 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata);
1248 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc);
1249 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1250 u64 virt_addr, int access_flags,
1251 struct ib_udata *udata);
1252 struct ib_mr *mlx5_ib_reg_user_mr_dmabuf(struct ib_pd *pd, u64 start,
1253 u64 length, u64 virt_addr,
1254 int fd, int access_flags,
1255 struct ib_udata *udata);
1256 int mlx5_ib_advise_mr(struct ib_pd *pd,
1257 enum ib_uverbs_advise_mr_advice advice,
1258 u32 flags,
1259 struct ib_sge *sg_list,
1260 u32 num_sge,
1261 struct uverbs_attr_bundle *attrs);
1262 int mlx5_ib_alloc_mw(struct ib_mw *mw, struct ib_udata *udata);
1263 int mlx5_ib_dealloc_mw(struct ib_mw *mw);
1264 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages,
1265 int page_shift, int flags);
1266 int mlx5_ib_update_mr_pas(struct mlx5_ib_mr *mr, unsigned int flags);
1267 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd,
1268 struct ib_udata *udata,
1269 int access_flags);
1270 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr);
1271 void mlx5_ib_free_odp_mr(struct mlx5_ib_mr *mr);
1272 struct ib_mr *mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start,
1273 u64 length, u64 virt_addr, int access_flags,
1274 struct ib_pd *pd, struct ib_udata *udata);
1275 int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1276 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1277 u32 max_num_sg);
1278 struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd,
1279 u32 max_num_sg,
1280 u32 max_num_meta_sg);
1281 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1282 unsigned int *sg_offset);
1283 int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg,
1284 int data_sg_nents, unsigned int *data_sg_offset,
1285 struct scatterlist *meta_sg, int meta_sg_nents,
1286 unsigned int *meta_sg_offset);
1287 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u32 port_num,
1288 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
1289 const struct ib_mad *in, struct ib_mad *out,
1290 size_t *out_mad_size, u16 *out_mad_pkey_index);
1291 int mlx5_ib_alloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata);
1292 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata);
1293 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, unsigned int port);
1294 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev,
1295 __be64 *sys_image_guid);
1296 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev,
1297 u16 *max_pkeys);
1298 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev,
1299 u32 *vendor_id);
1300 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc);
1301 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid);
1302 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u32 port, u16 index,
1303 u16 *pkey);
1304 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u32 port, int index,
1305 union ib_gid *gid);
1306 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u32 port,
1307 struct ib_port_attr *props);
1308 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port,
1309 struct ib_port_attr *props);
1310 void mlx5_ib_populate_pas(struct ib_umem *umem, size_t page_size, __be64 *pas,
1311 u64 access_flags);
1312 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num);
1313 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq);
1314 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev);
1315 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev);
1316
1317 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev,
1318 unsigned int entry, int access_flags);
1319
1320 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask,
1321 struct ib_mr_status *mr_status);
1322 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
1323 struct ib_wq_init_attr *init_attr,
1324 struct ib_udata *udata);
1325 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata);
1326 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
1327 u32 wq_attr_mask, struct ib_udata *udata);
1328 int mlx5_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_table,
1329 struct ib_rwq_ind_table_init_attr *init_attr,
1330 struct ib_udata *udata);
1331 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table);
1332 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm,
1333 struct ib_dm_mr_attr *attr,
1334 struct uverbs_attr_bundle *attrs);
1335
1336 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1337 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev);
1338 int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev, struct mlx5_ib_pf_eq *eq);
1339 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev);
1340 int __init mlx5_ib_odp_init(void);
1341 void mlx5_ib_odp_cleanup(void);
1342 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent);
1343 void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries,
1344 struct mlx5_ib_mr *mr, int flags);
1345
1346 int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd,
1347 enum ib_uverbs_advise_mr_advice advice,
1348 u32 flags, struct ib_sge *sg_list, u32 num_sge);
1349 int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr);
1350 int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr);
1351 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
mlx5_ib_odp_init_one(struct mlx5_ib_dev * ibdev)1352 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; }
mlx5r_odp_create_eq(struct mlx5_ib_dev * dev,struct mlx5_ib_pf_eq * eq)1353 static inline int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev,
1354 struct mlx5_ib_pf_eq *eq)
1355 {
1356 return 0;
1357 }
mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev * ibdev)1358 static inline void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev) {}
mlx5_ib_odp_init(void)1359 static inline int mlx5_ib_odp_init(void) { return 0; }
mlx5_ib_odp_cleanup(void)1360 static inline void mlx5_ib_odp_cleanup(void) {}
mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent * ent)1361 static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) {}
mlx5_odp_populate_xlt(void * xlt,size_t idx,size_t nentries,struct mlx5_ib_mr * mr,int flags)1362 static inline void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries,
1363 struct mlx5_ib_mr *mr, int flags) {}
1364
1365 static inline int
mlx5_ib_advise_mr_prefetch(struct ib_pd * pd,enum ib_uverbs_advise_mr_advice advice,u32 flags,struct ib_sge * sg_list,u32 num_sge)1366 mlx5_ib_advise_mr_prefetch(struct ib_pd *pd,
1367 enum ib_uverbs_advise_mr_advice advice, u32 flags,
1368 struct ib_sge *sg_list, u32 num_sge)
1369 {
1370 return -EOPNOTSUPP;
1371 }
mlx5_ib_init_odp_mr(struct mlx5_ib_mr * mr)1372 static inline int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr)
1373 {
1374 return -EOPNOTSUPP;
1375 }
mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr * mr)1376 static inline int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr)
1377 {
1378 return -EOPNOTSUPP;
1379 }
1380 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
1381
1382 extern const struct mmu_interval_notifier_ops mlx5_mn_ops;
1383
1384 /* Needed for rep profile */
1385 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
1386 const struct mlx5_ib_profile *profile,
1387 int stage);
1388 int __mlx5_ib_add(struct mlx5_ib_dev *dev,
1389 const struct mlx5_ib_profile *profile);
1390
1391 int mlx5_ib_get_vf_config(struct ib_device *device, int vf,
1392 u32 port, struct ifla_vf_info *info);
1393 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf,
1394 u32 port, int state);
1395 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf,
1396 u32 port, struct ifla_vf_stats *stats);
1397 int mlx5_ib_get_vf_guid(struct ib_device *device, int vf, u32 port,
1398 struct ifla_vf_guid *node_guid,
1399 struct ifla_vf_guid *port_guid);
1400 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u32 port,
1401 u64 guid, int type);
1402
1403 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev,
1404 const struct ib_gid_attr *attr);
1405
1406 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num);
1407 void mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num);
1408
1409 /* GSI QP helper functions */
1410 int mlx5_ib_create_gsi(struct ib_pd *pd, struct mlx5_ib_qp *mqp,
1411 struct ib_qp_init_attr *attr);
1412 int mlx5_ib_destroy_gsi(struct mlx5_ib_qp *mqp);
1413 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr,
1414 int attr_mask);
1415 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr,
1416 int qp_attr_mask,
1417 struct ib_qp_init_attr *qp_init_attr);
1418 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr,
1419 const struct ib_send_wr **bad_wr);
1420 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr,
1421 const struct ib_recv_wr **bad_wr);
1422 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi);
1423
1424 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc);
1425
1426 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi,
1427 int bfregn);
1428 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi);
1429 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev,
1430 u32 ib_port_num,
1431 u32 *native_port_num);
1432 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev,
1433 u32 port_num);
1434
1435 extern const struct uapi_definition mlx5_ib_devx_defs[];
1436 extern const struct uapi_definition mlx5_ib_flow_defs[];
1437 extern const struct uapi_definition mlx5_ib_qos_defs[];
1438 extern const struct uapi_definition mlx5_ib_std_types_defs[];
1439
init_query_mad(struct ib_smp * mad)1440 static inline void init_query_mad(struct ib_smp *mad)
1441 {
1442 mad->base_version = 1;
1443 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
1444 mad->class_version = 1;
1445 mad->method = IB_MGMT_METHOD_GET;
1446 }
1447
is_qp1(enum ib_qp_type qp_type)1448 static inline int is_qp1(enum ib_qp_type qp_type)
1449 {
1450 return qp_type == MLX5_IB_QPT_HW_GSI || qp_type == IB_QPT_GSI;
1451 }
1452
1453 #define MLX5_MAX_UMR_SHIFT 16
1454 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT)
1455
check_cq_create_flags(u32 flags)1456 static inline u32 check_cq_create_flags(u32 flags)
1457 {
1458 /*
1459 * It returns non-zero value for unsupported CQ
1460 * create flags, otherwise it returns zero.
1461 */
1462 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN |
1463 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION));
1464 }
1465
verify_assign_uidx(u8 cqe_version,u32 cmd_uidx,u32 * user_index)1466 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx,
1467 u32 *user_index)
1468 {
1469 if (cqe_version) {
1470 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) ||
1471 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK))
1472 return -EINVAL;
1473 *user_index = cmd_uidx;
1474 } else {
1475 *user_index = MLX5_IB_DEFAULT_UIDX;
1476 }
1477
1478 return 0;
1479 }
1480
get_qp_user_index(struct mlx5_ib_ucontext * ucontext,struct mlx5_ib_create_qp * ucmd,int inlen,u32 * user_index)1481 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext,
1482 struct mlx5_ib_create_qp *ucmd,
1483 int inlen,
1484 u32 *user_index)
1485 {
1486 u8 cqe_version = ucontext->cqe_version;
1487
1488 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version &&
1489 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1490 return 0;
1491
1492 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version)
1493 return -EINVAL;
1494
1495 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1496 }
1497
get_srq_user_index(struct mlx5_ib_ucontext * ucontext,struct mlx5_ib_create_srq * ucmd,int inlen,u32 * user_index)1498 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext,
1499 struct mlx5_ib_create_srq *ucmd,
1500 int inlen,
1501 u32 *user_index)
1502 {
1503 u8 cqe_version = ucontext->cqe_version;
1504
1505 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version &&
1506 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1507 return 0;
1508
1509 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version)
1510 return -EINVAL;
1511
1512 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1513 }
1514
get_uars_per_sys_page(struct mlx5_ib_dev * dev,bool lib_support)1515 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support)
1516 {
1517 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1518 MLX5_UARS_IN_PAGE : 1;
1519 }
1520
get_num_static_uars(struct mlx5_ib_dev * dev,struct mlx5_bfreg_info * bfregi)1521 static inline int get_num_static_uars(struct mlx5_ib_dev *dev,
1522 struct mlx5_bfreg_info *bfregi)
1523 {
1524 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages;
1525 }
1526
1527 extern void *xlt_emergency_page;
1528
1529 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
1530 struct mlx5_bfreg_info *bfregi, u32 bfregn,
1531 bool dyn_bfreg);
1532
mlx5_ib_can_load_pas_with_umr(struct mlx5_ib_dev * dev,size_t length)1533 static inline bool mlx5_ib_can_load_pas_with_umr(struct mlx5_ib_dev *dev,
1534 size_t length)
1535 {
1536 /*
1537 * umr_check_mkey_mask() rejects MLX5_MKEY_MASK_PAGE_SIZE which is
1538 * always set if MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (aka
1539 * MLX5_IB_UPD_XLT_ADDR and MLX5_IB_UPD_XLT_ENABLE) is set. Thus, a mkey
1540 * can never be enabled without this capability. Simplify this weird
1541 * quirky hardware by just saying it can't use PAS lists with UMR at
1542 * all.
1543 */
1544 if (MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled))
1545 return false;
1546
1547 /*
1548 * length is the size of the MR in bytes when mlx5_ib_update_xlt() is
1549 * used.
1550 */
1551 if (!MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset) &&
1552 length >= MLX5_MAX_UMR_PAGES * PAGE_SIZE)
1553 return false;
1554 return true;
1555 }
1556
1557 /*
1558 * true if an existing MR can be reconfigured to new access_flags using UMR.
1559 * Older HW cannot use UMR to update certain elements of the MKC. See
1560 * umr_check_mkey_mask(), get_umr_update_access_mask() and umr_check_mkey_mask()
1561 */
mlx5_ib_can_reconfig_with_umr(struct mlx5_ib_dev * dev,unsigned int current_access_flags,unsigned int target_access_flags)1562 static inline bool mlx5_ib_can_reconfig_with_umr(struct mlx5_ib_dev *dev,
1563 unsigned int current_access_flags,
1564 unsigned int target_access_flags)
1565 {
1566 unsigned int diffs = current_access_flags ^ target_access_flags;
1567
1568 if ((diffs & IB_ACCESS_REMOTE_ATOMIC) &&
1569 MLX5_CAP_GEN(dev->mdev, atomic) &&
1570 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled))
1571 return false;
1572
1573 if ((diffs & IB_ACCESS_RELAXED_ORDERING) &&
1574 MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write) &&
1575 !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write_umr))
1576 return false;
1577
1578 if ((diffs & IB_ACCESS_RELAXED_ORDERING) &&
1579 MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read) &&
1580 !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_umr))
1581 return false;
1582
1583 return true;
1584 }
1585
mlx5r_store_odp_mkey(struct mlx5_ib_dev * dev,struct mlx5_core_mkey * mmkey)1586 static inline int mlx5r_store_odp_mkey(struct mlx5_ib_dev *dev,
1587 struct mlx5_core_mkey *mmkey)
1588 {
1589 refcount_set(&mmkey->usecount, 1);
1590
1591 return xa_err(xa_store(&dev->odp_mkeys, mlx5_base_mkey(mmkey->key),
1592 mmkey, GFP_KERNEL));
1593 }
1594
1595 /* deref an mkey that can participate in ODP flow */
mlx5r_deref_odp_mkey(struct mlx5_core_mkey * mmkey)1596 static inline void mlx5r_deref_odp_mkey(struct mlx5_core_mkey *mmkey)
1597 {
1598 if (refcount_dec_and_test(&mmkey->usecount))
1599 wake_up(&mmkey->wait);
1600 }
1601
1602 /* deref an mkey that can participate in ODP flow and wait for relese */
mlx5r_deref_wait_odp_mkey(struct mlx5_core_mkey * mmkey)1603 static inline void mlx5r_deref_wait_odp_mkey(struct mlx5_core_mkey *mmkey)
1604 {
1605 mlx5r_deref_odp_mkey(mmkey);
1606 wait_event(mmkey->wait, refcount_read(&mmkey->usecount) == 0);
1607 }
1608
1609 int mlx5_ib_test_wc(struct mlx5_ib_dev *dev);
1610
mlx5_ib_lag_should_assign_affinity(struct mlx5_ib_dev * dev)1611 static inline bool mlx5_ib_lag_should_assign_affinity(struct mlx5_ib_dev *dev)
1612 {
1613 return dev->lag_active ||
1614 (MLX5_CAP_GEN(dev->mdev, num_lag_ports) > 1 &&
1615 MLX5_CAP_GEN(dev->mdev, lag_tx_port_affinity));
1616 }
1617 #endif /* MLX5_IB_H */
1618