1 /*
2  *  Amiga Linux/m68k Ariadne Ethernet Driver
3  *
4  *  © Copyright 1995 by Geert Uytterhoeven (geert@linux-m68k.org)
5  *			Peter De Schrijver
6  *		       (Peter.DeSchrijver@linux.cc.kuleuven.ac.be)
7  *
8  *  ----------------------------------------------------------------------------------
9  *
10  *  This program is based on
11  *
12  *	lance.c:	An AMD LANCE ethernet driver for linux.
13  *			Written 1993-94 by Donald Becker.
14  *
15  *	Am79C960:	PCnet(tm)-ISA Single-Chip Ethernet Controller
16  *			Advanced Micro Devices
17  *			Publication #16907, Rev. B, Amendment/0, May 1994
18  *
19  *	MC68230:	Parallel Interface/Timer (PI/T)
20  *			Motorola Semiconductors, December, 1983
21  *
22  *  ----------------------------------------------------------------------------------
23  *
24  *  This file is subject to the terms and conditions of the GNU General Public
25  *  License.  See the file COPYING in the main directory of the Linux
26  *  distribution for more details.
27  *
28  *  ----------------------------------------------------------------------------------
29  *
30  *  The Ariadne is a Zorro-II board made by Village Tronic. It contains:
31  *
32  *	- an Am79C960 PCnet-ISA Single-Chip Ethernet Controller with both
33  *	  10BASE-2 (thin coax) and 10BASE-T (UTP) connectors
34  *
35  *	- an MC68230 Parallel Interface/Timer configured as 2 parallel ports
36  */
37 
38 
39     /*
40      *	Am79C960 PCnet-ISA
41      */
42 
43 struct Am79C960 {
44     volatile u_short AddressPROM[8];
45 				/* IEEE Address PROM (Unused in the Ariadne) */
46     volatile u_short RDP;	/* Register Data Port */
47     volatile u_short RAP;	/* Register Address Port */
48     volatile u_short Reset;	/* Reset Chip on Read Access */
49     volatile u_short IDP;	/* ISACSR Data Port */
50 };
51 
52 
53     /*
54      *	Am79C960 Control and Status Registers
55      *
56      *	These values are already swap()ed!!
57      *
58      *	Only registers marked with a `-' are intended for network software
59      *	access
60      */
61 
62 #define CSR0		0x0000	/* - PCnet-ISA Controller Status */
63 #define CSR1		0x0100	/* - IADR[15:0] */
64 #define CSR2		0x0200	/* - IADR[23:16] */
65 #define CSR3		0x0300	/* - Interrupt Masks and Deferral Control */
66 #define CSR4		0x0400	/* - Test and Features Control */
67 #define CSR6		0x0600	/*   RCV/XMT Descriptor Table Length */
68 #define CSR8		0x0800	/* - Logical Address Filter, LADRF[15:0] */
69 #define CSR9		0x0900	/* - Logical Address Filter, LADRF[31:16] */
70 #define CSR10		0x0a00	/* - Logical Address Filter, LADRF[47:32] */
71 #define CSR11		0x0b00	/* - Logical Address Filter, LADRF[63:48] */
72 #define CSR12		0x0c00	/* - Physical Address Register, PADR[15:0] */
73 #define CSR13		0x0d00	/* - Physical Address Register, PADR[31:16] */
74 #define CSR14		0x0e00	/* - Physical Address Register, PADR[47:32] */
75 #define CSR15		0x0f00	/* - Mode Register */
76 #define CSR16		0x1000	/*   Initialization Block Address Lower */
77 #define CSR17		0x1100	/*   Initialization Block Address Upper */
78 #define CSR18		0x1200	/*   Current Receive Buffer Address */
79 #define CSR19		0x1300	/*   Current Receive Buffer Address */
80 #define CSR20		0x1400	/*   Current Transmit Buffer Address */
81 #define CSR21		0x1500	/*   Current Transmit Buffer Address */
82 #define CSR22		0x1600	/*   Next Receive Buffer Address */
83 #define CSR23		0x1700	/*   Next Receive Buffer Address */
84 #define CSR24		0x1800	/* - Base Address of Receive Ring */
85 #define CSR25		0x1900	/* - Base Address of Receive Ring */
86 #define CSR26		0x1a00	/*   Next Receive Descriptor Address */
87 #define CSR27		0x1b00	/*   Next Receive Descriptor Address */
88 #define CSR28		0x1c00	/*   Current Receive Descriptor Address */
89 #define CSR29		0x1d00	/*   Current Receive Descriptor Address */
90 #define CSR30		0x1e00	/* - Base Address of Transmit Ring */
91 #define CSR31		0x1f00	/* - Base Address of transmit Ring */
92 #define CSR32		0x2000	/*   Next Transmit Descriptor Address */
93 #define CSR33		0x2100	/*   Next Transmit Descriptor Address */
94 #define CSR34		0x2200	/*   Current Transmit Descriptor Address */
95 #define CSR35		0x2300	/*   Current Transmit Descriptor Address */
96 #define CSR36		0x2400	/*   Next Next Receive Descriptor Address */
97 #define CSR37		0x2500	/*   Next Next Receive Descriptor Address */
98 #define CSR38		0x2600	/*   Next Next Transmit Descriptor Address */
99 #define CSR39		0x2700	/*   Next Next Transmit Descriptor Address */
100 #define CSR40		0x2800	/*   Current Receive Status and Byte Count */
101 #define CSR41		0x2900	/*   Current Receive Status and Byte Count */
102 #define CSR42		0x2a00	/*   Current Transmit Status and Byte Count */
103 #define CSR43		0x2b00	/*   Current Transmit Status and Byte Count */
104 #define CSR44		0x2c00	/*   Next Receive Status and Byte Count */
105 #define CSR45		0x2d00	/*   Next Receive Status and Byte Count */
106 #define CSR46		0x2e00	/*   Poll Time Counter */
107 #define CSR47		0x2f00	/*   Polling Interval */
108 #define CSR48		0x3000	/*   Temporary Storage */
109 #define CSR49		0x3100	/*   Temporary Storage */
110 #define CSR50		0x3200	/*   Temporary Storage */
111 #define CSR51		0x3300	/*   Temporary Storage */
112 #define CSR52		0x3400	/*   Temporary Storage */
113 #define CSR53		0x3500	/*   Temporary Storage */
114 #define CSR54		0x3600	/*   Temporary Storage */
115 #define CSR55		0x3700	/*   Temporary Storage */
116 #define CSR56		0x3800	/*   Temporary Storage */
117 #define CSR57		0x3900	/*   Temporary Storage */
118 #define CSR58		0x3a00	/*   Temporary Storage */
119 #define CSR59		0x3b00	/*   Temporary Storage */
120 #define CSR60		0x3c00	/*   Previous Transmit Descriptor Address */
121 #define CSR61		0x3d00	/*   Previous Transmit Descriptor Address */
122 #define CSR62		0x3e00	/*   Previous Transmit Status and Byte Count */
123 #define CSR63		0x3f00	/*   Previous Transmit Status and Byte Count */
124 #define CSR64		0x4000	/*   Next Transmit Buffer Address */
125 #define CSR65		0x4100	/*   Next Transmit Buffer Address */
126 #define CSR66		0x4200	/*   Next Transmit Status and Byte Count */
127 #define CSR67		0x4300	/*   Next Transmit Status and Byte Count */
128 #define CSR68		0x4400	/*   Transmit Status Temporary Storage */
129 #define CSR69		0x4500	/*   Transmit Status Temporary Storage */
130 #define CSR70		0x4600	/*   Temporary Storage */
131 #define CSR71		0x4700	/*   Temporary Storage */
132 #define CSR72		0x4800	/*   Receive Ring Counter */
133 #define CSR74		0x4a00	/*   Transmit Ring Counter */
134 #define CSR76		0x4c00	/* - Receive Ring Length */
135 #define CSR78		0x4e00	/* - Transmit Ring Length */
136 #define CSR80		0x5000	/* - Burst and FIFO Threshold Control */
137 #define CSR82		0x5200	/* - Bus Activity Timer */
138 #define CSR84		0x5400	/*   DMA Address */
139 #define CSR85		0x5500	/*   DMA Address */
140 #define CSR86		0x5600	/*   Buffer Byte Counter */
141 #define CSR88		0x5800	/* - Chip ID */
142 #define CSR89		0x5900	/* - Chip ID */
143 #define CSR92		0x5c00	/*   Ring Length Conversion */
144 #define CSR94		0x5e00	/*   Transmit Time Domain Reflectometry Count */
145 #define CSR96		0x6000	/*   Bus Interface Scratch Register 0 */
146 #define CSR97		0x6100	/*   Bus Interface Scratch Register 0 */
147 #define CSR98		0x6200	/*   Bus Interface Scratch Register 1 */
148 #define CSR99		0x6300	/*   Bus Interface Scratch Register 1 */
149 #define CSR104		0x6800	/*   SWAP */
150 #define CSR105		0x6900	/*   SWAP */
151 #define CSR108		0x6c00	/*   Buffer Management Scratch */
152 #define CSR109		0x6d00	/*   Buffer Management Scratch */
153 #define CSR112		0x7000	/* - Missed Frame Count */
154 #define CSR114		0x7200	/* - Receive Collision Count */
155 #define CSR124		0x7c00	/* - Buffer Management Unit Test */
156 
157 
158     /*
159      *	Am79C960 ISA Control and Status Registers
160      *
161      *	These values are already swap()ed!!
162      */
163 
164 #define ISACSR0		0x0000	/* Master Mode Read Active */
165 #define ISACSR1		0x0100	/* Master Mode Write Active */
166 #define ISACSR2		0x0200	/* Miscellaneous Configuration */
167 #define ISACSR4		0x0400	/* LED0 Status (Link Integrity) */
168 #define ISACSR5		0x0500	/* LED1 Status */
169 #define ISACSR6		0x0600	/* LED2 Status */
170 #define ISACSR7		0x0700	/* LED3 Status */
171 
172 
173     /*
174      *	Bit definitions for CSR0 (PCnet-ISA Controller Status)
175      *
176      *	These values are already swap()ed!!
177      */
178 
179 #define ERR		0x0080	/* Error */
180 #define BABL		0x0040	/* Babble: Transmitted too many bits */
181 #define CERR		0x0020	/* No Heartbeat (10BASE-T) */
182 #define MISS		0x0010	/* Missed Frame */
183 #define MERR		0x0008	/* Memory Error */
184 #define RINT		0x0004	/* Receive Interrupt */
185 #define TINT		0x0002	/* Transmit Interrupt */
186 #define IDON		0x0001	/* Initialization Done */
187 #define INTR		0x8000	/* Interrupt Flag */
188 #define INEA		0x4000	/* Interrupt Enable */
189 #define RXON		0x2000	/* Receive On */
190 #define TXON		0x1000	/* Transmit On */
191 #define TDMD		0x0800	/* Transmit Demand */
192 #define STOP		0x0400	/* Stop */
193 #define STRT		0x0200	/* Start */
194 #define INIT		0x0100	/* Initialize */
195 
196 
197     /*
198      *	Bit definitions for CSR3 (Interrupt Masks and Deferral Control)
199      *
200      *	These values are already swap()ed!!
201      */
202 
203 #define BABLM		0x0040	/* Babble Mask */
204 #define MISSM		0x0010	/* Missed Frame Mask */
205 #define MERRM		0x0008	/* Memory Error Mask */
206 #define RINTM		0x0004	/* Receive Interrupt Mask */
207 #define TINTM		0x0002	/* Transmit Interrupt Mask */
208 #define IDONM		0x0001	/* Initialization Done Mask */
209 #define DXMT2PD		0x1000	/* Disable Transmit Two Part Deferral */
210 #define EMBA		0x0800	/* Enable Modified Back-off Algorithm */
211 
212 
213     /*
214      *	Bit definitions for CSR4 (Test and Features Control)
215      *
216      *	These values are already swap()ed!!
217      */
218 
219 #define ENTST		0x0080	/* Enable Test Mode */
220 #define DMAPLUS		0x0040	/* Disable Burst Transaction Counter */
221 #define TIMER		0x0020	/* Timer Enable Register */
222 #define DPOLL		0x0010	/* Disable Transmit Polling */
223 #define APAD_XMT	0x0008	/* Auto Pad Transmit */
224 #define ASTRP_RCV	0x0004	/* Auto Pad Stripping */
225 #define MFCO		0x0002	/* Missed Frame Counter Overflow Interrupt */
226 #define MFCOM		0x0001	/* Missed Frame Counter Overflow Mask */
227 #define RCVCCO		0x2000	/* Receive Collision Counter Overflow Interrupt */
228 #define RCVCCOM		0x1000	/* Receive Collision Counter Overflow Mask */
229 #define TXSTRT		0x0800	/* Transmit Start Status */
230 #define TXSTRTM		0x0400	/* Transmit Start Mask */
231 #define JAB		0x0200	/* Jabber Error */
232 #define JABM		0x0100	/* Jabber Error Mask */
233 
234 
235     /*
236      *	Bit definitions for CSR15 (Mode Register)
237      *
238      *	These values are already swap()ed!!
239      */
240 
241 #define PROM		0x0080	/* Promiscuous Mode */
242 #define DRCVBC		0x0040	/* Disable Receive Broadcast */
243 #define DRCVPA		0x0020	/* Disable Receive Physical Address */
244 #define DLNKTST		0x0010	/* Disable Link Status */
245 #define DAPC		0x0008	/* Disable Automatic Polarity Correction */
246 #define MENDECL		0x0004	/* MENDEC Loopback Mode */
247 #define LRTTSEL		0x0002	/* Low Receive Threshold/Transmit Mode Select */
248 #define PORTSEL1	0x0001	/* Port Select Bits */
249 #define PORTSEL2	0x8000	/* Port Select Bits */
250 #define INTL		0x4000	/* Internal Loopback */
251 #define DRTY		0x2000	/* Disable Retry */
252 #define FCOLL		0x1000	/* Force Collision */
253 #define DXMTFCS		0x0800	/* Disable Transmit CRC */
254 #define LOOP		0x0400	/* Loopback Enable */
255 #define DTX		0x0200	/* Disable Transmitter */
256 #define DRX		0x0100	/* Disable Receiver */
257 
258 
259     /*
260      *	Bit definitions for ISACSR2 (Miscellaneous Configuration)
261      *
262      *	These values are already swap()ed!!
263      */
264 
265 #define ASEL		0x0200	/* Media Interface Port Auto Select */
266 
267 
268     /*
269      *	Bit definitions for ISACSR5-7 (LED1-3 Status)
270      *
271      *	These values are already swap()ed!!
272      */
273 
274 #define LEDOUT		0x0080	/* Current LED Status */
275 #define PSE		0x8000	/* Pulse Stretcher Enable */
276 #define XMTE		0x1000	/* Enable Transmit Status Signal */
277 #define RVPOLE		0x0800	/* Enable Receive Polarity Signal */
278 #define RCVE		0x0400	/* Enable Receive Status Signal */
279 #define JABE		0x0200	/* Enable Jabber Signal */
280 #define COLE		0x0100	/* Enable Collision Signal */
281 
282 
283     /*
284      *	Receive Descriptor Ring Entry
285      */
286 
287 struct RDRE {
288     volatile u_short RMD0;	/* LADR[15:0] */
289     volatile u_short RMD1;	/* HADR[23:16] | Receive Flags */
290     volatile u_short RMD2;	/* Buffer Byte Count (two's complement) */
291     volatile u_short RMD3;	/* Message Byte Count */
292 };
293 
294 
295     /*
296      *	Transmit Descriptor Ring Entry
297      */
298 
299 struct TDRE {
300     volatile u_short TMD0;	/* LADR[15:0] */
301     volatile u_short TMD1;	/* HADR[23:16] | Transmit Flags */
302     volatile u_short TMD2;	/* Buffer Byte Count (two's complement) */
303     volatile u_short TMD3;	/* Error Flags */
304 };
305 
306 
307     /*
308      *	Receive Flags
309      */
310 
311 #define RF_OWN		0x0080	/* PCnet-ISA controller owns the descriptor */
312 #define RF_ERR		0x0040	/* Error */
313 #define RF_FRAM		0x0020	/* Framing Error */
314 #define RF_OFLO		0x0010	/* Overflow Error */
315 #define RF_CRC		0x0008	/* CRC Error */
316 #define RF_BUFF		0x0004	/* Buffer Error */
317 #define RF_STP		0x0002	/* Start of Packet */
318 #define RF_ENP		0x0001	/* End of Packet */
319 
320 
321     /*
322      *	Transmit Flags
323      */
324 
325 #define TF_OWN		0x0080	/* PCnet-ISA controller owns the descriptor */
326 #define TF_ERR		0x0040	/* Error */
327 #define TF_ADD_FCS	0x0020	/* Controls FCS Generation */
328 #define TF_MORE		0x0010	/* More than one retry needed */
329 #define TF_ONE		0x0008	/* One retry needed */
330 #define TF_DEF		0x0004	/* Deferred */
331 #define TF_STP		0x0002	/* Start of Packet */
332 #define TF_ENP		0x0001	/* End of Packet */
333 
334 
335     /*
336      *	Error Flags
337      */
338 
339 #define EF_BUFF		0x0080	/* Buffer Error */
340 #define EF_UFLO		0x0040	/* Underflow Error */
341 #define EF_LCOL		0x0010	/* Late Collision */
342 #define EF_LCAR		0x0008	/* Loss of Carrier */
343 #define EF_RTRY		0x0004	/* Retry Error */
344 #define EF_TDR		0xff03	/* Time Domain Reflectometry */
345 
346 
347 
348     /*
349      *	MC68230 Parallel Interface/Timer
350      */
351 
352 struct MC68230 {
353     volatile u_char PGCR;	/* Port General Control Register */
354     u_char Pad1[1];
355     volatile u_char PSRR;	/* Port Service Request Register */
356     u_char Pad2[1];
357     volatile u_char PADDR;	/* Port A Data Direction Register */
358     u_char Pad3[1];
359     volatile u_char PBDDR;	/* Port B Data Direction Register */
360     u_char Pad4[1];
361     volatile u_char PCDDR;	/* Port C Data Direction Register */
362     u_char Pad5[1];
363     volatile u_char PIVR;	/* Port Interrupt Vector Register */
364     u_char Pad6[1];
365     volatile u_char PACR;	/* Port A Control Register */
366     u_char Pad7[1];
367     volatile u_char PBCR;	/* Port B Control Register */
368     u_char Pad8[1];
369     volatile u_char PADR;	/* Port A Data Register */
370     u_char Pad9[1];
371     volatile u_char PBDR;	/* Port B Data Register */
372     u_char Pad10[1];
373     volatile u_char PAAR;	/* Port A Alternate Register */
374     u_char Pad11[1];
375     volatile u_char PBAR;	/* Port B Alternate Register */
376     u_char Pad12[1];
377     volatile u_char PCDR;	/* Port C Data Register */
378     u_char Pad13[1];
379     volatile u_char PSR;	/* Port Status Register */
380     u_char Pad14[5];
381     volatile u_char TCR;	/* Timer Control Register */
382     u_char Pad15[1];
383     volatile u_char TIVR;	/* Timer Interrupt Vector Register */
384     u_char Pad16[3];
385     volatile u_char CPRH;	/* Counter Preload Register (High) */
386     u_char Pad17[1];
387     volatile u_char CPRM;	/* Counter Preload Register (Mid) */
388     u_char Pad18[1];
389     volatile u_char CPRL;	/* Counter Preload Register (Low) */
390     u_char Pad19[3];
391     volatile u_char CNTRH;	/* Count Register (High) */
392     u_char Pad20[1];
393     volatile u_char CNTRM;	/* Count Register (Mid) */
394     u_char Pad21[1];
395     volatile u_char CNTRL;	/* Count Register (Low) */
396     u_char Pad22[1];
397     volatile u_char TSR;	/* Timer Status Register */
398     u_char Pad23[11];
399 };
400 
401 
402     /*
403      *	Ariadne Expansion Board Structure
404      */
405 
406 #define ARIADNE_LANCE		0x360
407 
408 #define ARIADNE_PIT		0x1000
409 
410 #define ARIADNE_BOOTPROM	0x4000	/* I guess it's here :-) */
411 #define ARIADNE_BOOTPROM_SIZE	0x4000
412 
413 #define ARIADNE_RAM		0x8000	/* Always access WORDs!! */
414 #define ARIADNE_RAM_SIZE	0x8000
415 
416