1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell OcteonTx2 RVU Ethernet driver
3 *
4 * Copyright (C) 2020 Marvell International Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/etherdevice.h>
12 #include <net/ip.h>
13 #include <net/tso.h>
14
15 #include "otx2_reg.h"
16 #include "otx2_common.h"
17 #include "otx2_struct.h"
18 #include "otx2_txrx.h"
19 #include "otx2_ptp.h"
20 #include "cn10k.h"
21
22 #define CQE_ADDR(CQ, idx) ((CQ)->cqe_base + ((CQ)->cqe_size * (idx)))
23
otx2_get_next_cqe(struct otx2_cq_queue * cq)24 static struct nix_cqe_hdr_s *otx2_get_next_cqe(struct otx2_cq_queue *cq)
25 {
26 struct nix_cqe_hdr_s *cqe_hdr;
27
28 cqe_hdr = (struct nix_cqe_hdr_s *)CQE_ADDR(cq, cq->cq_head);
29 if (cqe_hdr->cqe_type == NIX_XQE_TYPE_INVALID)
30 return NULL;
31
32 cq->cq_head++;
33 cq->cq_head &= (cq->cqe_cnt - 1);
34
35 return cqe_hdr;
36 }
37
frag_num(unsigned int i)38 static unsigned int frag_num(unsigned int i)
39 {
40 #ifdef __BIG_ENDIAN
41 return (i & ~3) + 3 - (i & 3);
42 #else
43 return i;
44 #endif
45 }
46
otx2_dma_map_skb_frag(struct otx2_nic * pfvf,struct sk_buff * skb,int seg,int * len)47 static dma_addr_t otx2_dma_map_skb_frag(struct otx2_nic *pfvf,
48 struct sk_buff *skb, int seg, int *len)
49 {
50 const skb_frag_t *frag;
51 struct page *page;
52 int offset;
53
54 /* First segment is always skb->data */
55 if (!seg) {
56 page = virt_to_page(skb->data);
57 offset = offset_in_page(skb->data);
58 *len = skb_headlen(skb);
59 } else {
60 frag = &skb_shinfo(skb)->frags[seg - 1];
61 page = skb_frag_page(frag);
62 offset = skb_frag_off(frag);
63 *len = skb_frag_size(frag);
64 }
65 return otx2_dma_map_page(pfvf, page, offset, *len, DMA_TO_DEVICE);
66 }
67
otx2_dma_unmap_skb_frags(struct otx2_nic * pfvf,struct sg_list * sg)68 static void otx2_dma_unmap_skb_frags(struct otx2_nic *pfvf, struct sg_list *sg)
69 {
70 int seg;
71
72 for (seg = 0; seg < sg->num_segs; seg++) {
73 otx2_dma_unmap_page(pfvf, sg->dma_addr[seg],
74 sg->size[seg], DMA_TO_DEVICE);
75 }
76 sg->num_segs = 0;
77 }
78
otx2_snd_pkt_handler(struct otx2_nic * pfvf,struct otx2_cq_queue * cq,struct otx2_snd_queue * sq,struct nix_cqe_tx_s * cqe,int budget,int * tx_pkts,int * tx_bytes)79 static void otx2_snd_pkt_handler(struct otx2_nic *pfvf,
80 struct otx2_cq_queue *cq,
81 struct otx2_snd_queue *sq,
82 struct nix_cqe_tx_s *cqe,
83 int budget, int *tx_pkts, int *tx_bytes)
84 {
85 struct nix_send_comp_s *snd_comp = &cqe->comp;
86 struct skb_shared_hwtstamps ts;
87 struct sk_buff *skb = NULL;
88 u64 timestamp, tsns;
89 struct sg_list *sg;
90 int err;
91
92 if (unlikely(snd_comp->status) && netif_msg_tx_err(pfvf))
93 net_err_ratelimited("%s: TX%d: Error in send CQ status:%x\n",
94 pfvf->netdev->name, cq->cint_idx,
95 snd_comp->status);
96
97 sg = &sq->sg[snd_comp->sqe_id];
98 skb = (struct sk_buff *)sg->skb;
99 if (unlikely(!skb))
100 return;
101
102 if (skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) {
103 timestamp = ((u64 *)sq->timestamps->base)[snd_comp->sqe_id];
104 if (timestamp != 1) {
105 err = otx2_ptp_tstamp2time(pfvf, timestamp, &tsns);
106 if (!err) {
107 memset(&ts, 0, sizeof(ts));
108 ts.hwtstamp = ns_to_ktime(tsns);
109 skb_tstamp_tx(skb, &ts);
110 }
111 }
112 }
113
114 *tx_bytes += skb->len;
115 (*tx_pkts)++;
116 otx2_dma_unmap_skb_frags(pfvf, sg);
117 napi_consume_skb(skb, budget);
118 sg->skb = (u64)NULL;
119 }
120
otx2_set_rxtstamp(struct otx2_nic * pfvf,struct sk_buff * skb,void * data)121 static void otx2_set_rxtstamp(struct otx2_nic *pfvf,
122 struct sk_buff *skb, void *data)
123 {
124 u64 tsns;
125 int err;
126
127 if (!(pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED))
128 return;
129
130 /* The first 8 bytes is the timestamp */
131 err = otx2_ptp_tstamp2time(pfvf, be64_to_cpu(*(__be64 *)data), &tsns);
132 if (err)
133 return;
134
135 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(tsns);
136 }
137
otx2_skb_add_frag(struct otx2_nic * pfvf,struct sk_buff * skb,u64 iova,int len,struct nix_rx_parse_s * parse)138 static void otx2_skb_add_frag(struct otx2_nic *pfvf, struct sk_buff *skb,
139 u64 iova, int len, struct nix_rx_parse_s *parse)
140 {
141 struct page *page;
142 int off = 0;
143 void *va;
144
145 va = phys_to_virt(otx2_iova_to_phys(pfvf->iommu_domain, iova));
146
147 if (likely(!skb_shinfo(skb)->nr_frags)) {
148 /* Check if data starts at some nonzero offset
149 * from the start of the buffer. For now the
150 * only possible offset is 8 bytes in the case
151 * where packet is prepended by a timestamp.
152 */
153 if (parse->laptr) {
154 otx2_set_rxtstamp(pfvf, skb, va);
155 off = OTX2_HW_TIMESTAMP_LEN;
156 }
157 }
158
159 page = virt_to_page(va);
160 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
161 va - page_address(page) + off, len - off, pfvf->rbsize);
162
163 otx2_dma_unmap_page(pfvf, iova - OTX2_HEAD_ROOM,
164 pfvf->rbsize, DMA_FROM_DEVICE);
165 }
166
otx2_set_rxhash(struct otx2_nic * pfvf,struct nix_cqe_rx_s * cqe,struct sk_buff * skb)167 static void otx2_set_rxhash(struct otx2_nic *pfvf,
168 struct nix_cqe_rx_s *cqe, struct sk_buff *skb)
169 {
170 enum pkt_hash_types hash_type = PKT_HASH_TYPE_NONE;
171 struct otx2_rss_info *rss;
172 u32 hash = 0;
173
174 if (!(pfvf->netdev->features & NETIF_F_RXHASH))
175 return;
176
177 rss = &pfvf->hw.rss_info;
178 if (rss->flowkey_cfg) {
179 if (rss->flowkey_cfg &
180 ~(NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6))
181 hash_type = PKT_HASH_TYPE_L4;
182 else
183 hash_type = PKT_HASH_TYPE_L3;
184 hash = cqe->hdr.flow_tag;
185 }
186 skb_set_hash(skb, hash, hash_type);
187 }
188
otx2_free_rcv_seg(struct otx2_nic * pfvf,struct nix_cqe_rx_s * cqe,int qidx)189 static void otx2_free_rcv_seg(struct otx2_nic *pfvf, struct nix_cqe_rx_s *cqe,
190 int qidx)
191 {
192 struct nix_rx_sg_s *sg = &cqe->sg;
193 void *end, *start;
194 u64 *seg_addr;
195 int seg;
196
197 start = (void *)sg;
198 end = start + ((cqe->parse.desc_sizem1 + 1) * 16);
199 while (start < end) {
200 sg = (struct nix_rx_sg_s *)start;
201 seg_addr = &sg->seg_addr;
202 for (seg = 0; seg < sg->segs; seg++, seg_addr++)
203 pfvf->hw_ops->aura_freeptr(pfvf, qidx,
204 *seg_addr & ~0x07ULL);
205 start += sizeof(*sg);
206 }
207 }
208
otx2_check_rcv_errors(struct otx2_nic * pfvf,struct nix_cqe_rx_s * cqe,int qidx)209 static bool otx2_check_rcv_errors(struct otx2_nic *pfvf,
210 struct nix_cqe_rx_s *cqe, int qidx)
211 {
212 struct otx2_drv_stats *stats = &pfvf->hw.drv_stats;
213 struct nix_rx_parse_s *parse = &cqe->parse;
214
215 if (netif_msg_rx_err(pfvf))
216 netdev_err(pfvf->netdev,
217 "RQ%d: Error pkt with errlev:0x%x errcode:0x%x\n",
218 qidx, parse->errlev, parse->errcode);
219
220 if (parse->errlev == NPC_ERRLVL_RE) {
221 switch (parse->errcode) {
222 case ERRCODE_FCS:
223 case ERRCODE_FCS_RCV:
224 atomic_inc(&stats->rx_fcs_errs);
225 break;
226 case ERRCODE_UNDERSIZE:
227 atomic_inc(&stats->rx_undersize_errs);
228 break;
229 case ERRCODE_OVERSIZE:
230 atomic_inc(&stats->rx_oversize_errs);
231 break;
232 case ERRCODE_OL2_LEN_MISMATCH:
233 atomic_inc(&stats->rx_len_errs);
234 break;
235 default:
236 atomic_inc(&stats->rx_other_errs);
237 break;
238 }
239 } else if (parse->errlev == NPC_ERRLVL_NIX) {
240 switch (parse->errcode) {
241 case ERRCODE_OL3_LEN:
242 case ERRCODE_OL4_LEN:
243 case ERRCODE_IL3_LEN:
244 case ERRCODE_IL4_LEN:
245 atomic_inc(&stats->rx_len_errs);
246 break;
247 case ERRCODE_OL4_CSUM:
248 case ERRCODE_IL4_CSUM:
249 atomic_inc(&stats->rx_csum_errs);
250 break;
251 default:
252 atomic_inc(&stats->rx_other_errs);
253 break;
254 }
255 } else {
256 atomic_inc(&stats->rx_other_errs);
257 /* For now ignore all the NPC parser errors and
258 * pass the packets to stack.
259 */
260 return false;
261 }
262
263 /* If RXALL is enabled pass on packets to stack. */
264 if (pfvf->netdev->features & NETIF_F_RXALL)
265 return false;
266
267 /* Free buffer back to pool */
268 if (cqe->sg.segs)
269 otx2_free_rcv_seg(pfvf, cqe, qidx);
270 return true;
271 }
272
otx2_rcv_pkt_handler(struct otx2_nic * pfvf,struct napi_struct * napi,struct otx2_cq_queue * cq,struct nix_cqe_rx_s * cqe)273 static void otx2_rcv_pkt_handler(struct otx2_nic *pfvf,
274 struct napi_struct *napi,
275 struct otx2_cq_queue *cq,
276 struct nix_cqe_rx_s *cqe)
277 {
278 struct nix_rx_parse_s *parse = &cqe->parse;
279 struct nix_rx_sg_s *sg = &cqe->sg;
280 struct sk_buff *skb = NULL;
281 void *end, *start;
282 u64 *seg_addr;
283 u16 *seg_size;
284 int seg;
285
286 if (unlikely(parse->errlev || parse->errcode)) {
287 if (otx2_check_rcv_errors(pfvf, cqe, cq->cq_idx))
288 return;
289 }
290
291 skb = napi_get_frags(napi);
292 if (unlikely(!skb))
293 return;
294
295 start = (void *)sg;
296 end = start + ((cqe->parse.desc_sizem1 + 1) * 16);
297 while (start < end) {
298 sg = (struct nix_rx_sg_s *)start;
299 seg_addr = &sg->seg_addr;
300 seg_size = (void *)sg;
301 for (seg = 0; seg < sg->segs; seg++, seg_addr++) {
302 otx2_skb_add_frag(pfvf, skb, *seg_addr, seg_size[seg],
303 parse);
304 cq->pool_ptrs++;
305 }
306 start += sizeof(*sg);
307 }
308 otx2_set_rxhash(pfvf, cqe, skb);
309
310 skb_record_rx_queue(skb, cq->cq_idx);
311 if (pfvf->netdev->features & NETIF_F_RXCSUM)
312 skb->ip_summed = CHECKSUM_UNNECESSARY;
313
314 napi_gro_frags(napi);
315 }
316
otx2_rx_napi_handler(struct otx2_nic * pfvf,struct napi_struct * napi,struct otx2_cq_queue * cq,int budget)317 static int otx2_rx_napi_handler(struct otx2_nic *pfvf,
318 struct napi_struct *napi,
319 struct otx2_cq_queue *cq, int budget)
320 {
321 struct nix_cqe_rx_s *cqe;
322 int processed_cqe = 0;
323
324 while (likely(processed_cqe < budget)) {
325 cqe = (struct nix_cqe_rx_s *)CQE_ADDR(cq, cq->cq_head);
326 if (cqe->hdr.cqe_type == NIX_XQE_TYPE_INVALID ||
327 !cqe->sg.seg_addr) {
328 if (!processed_cqe)
329 return 0;
330 break;
331 }
332 cq->cq_head++;
333 cq->cq_head &= (cq->cqe_cnt - 1);
334
335 otx2_rcv_pkt_handler(pfvf, napi, cq, cqe);
336
337 cqe->hdr.cqe_type = NIX_XQE_TYPE_INVALID;
338 cqe->sg.seg_addr = 0x00;
339 processed_cqe++;
340 }
341
342 /* Free CQEs to HW */
343 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR,
344 ((u64)cq->cq_idx << 32) | processed_cqe);
345
346 if (unlikely(!cq->pool_ptrs))
347 return 0;
348 /* Refill pool with new buffers */
349 pfvf->hw_ops->refill_pool_ptrs(pfvf, cq);
350
351 return processed_cqe;
352 }
353
otx2_refill_pool_ptrs(void * dev,struct otx2_cq_queue * cq)354 void otx2_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq)
355 {
356 struct otx2_nic *pfvf = dev;
357 dma_addr_t bufptr;
358
359 while (cq->pool_ptrs) {
360 if (otx2_alloc_buffer(pfvf, cq, &bufptr))
361 break;
362 otx2_aura_freeptr(pfvf, cq->cq_idx, bufptr + OTX2_HEAD_ROOM);
363 cq->pool_ptrs--;
364 }
365 }
366
otx2_tx_napi_handler(struct otx2_nic * pfvf,struct otx2_cq_queue * cq,int budget)367 static int otx2_tx_napi_handler(struct otx2_nic *pfvf,
368 struct otx2_cq_queue *cq, int budget)
369 {
370 int tx_pkts = 0, tx_bytes = 0;
371 struct nix_cqe_tx_s *cqe;
372 int processed_cqe = 0;
373
374 while (likely(processed_cqe < budget)) {
375 cqe = (struct nix_cqe_tx_s *)otx2_get_next_cqe(cq);
376 if (unlikely(!cqe)) {
377 if (!processed_cqe)
378 return 0;
379 break;
380 }
381 otx2_snd_pkt_handler(pfvf, cq, &pfvf->qset.sq[cq->cint_idx],
382 cqe, budget, &tx_pkts, &tx_bytes);
383
384 cqe->hdr.cqe_type = NIX_XQE_TYPE_INVALID;
385 processed_cqe++;
386 }
387
388 /* Free CQEs to HW */
389 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR,
390 ((u64)cq->cq_idx << 32) | processed_cqe);
391
392 if (likely(tx_pkts)) {
393 struct netdev_queue *txq;
394
395 txq = netdev_get_tx_queue(pfvf->netdev, cq->cint_idx);
396 netdev_tx_completed_queue(txq, tx_pkts, tx_bytes);
397 /* Check if queue was stopped earlier due to ring full */
398 smp_mb();
399 if (netif_tx_queue_stopped(txq) &&
400 netif_carrier_ok(pfvf->netdev))
401 netif_tx_wake_queue(txq);
402 }
403 return 0;
404 }
405
otx2_napi_handler(struct napi_struct * napi,int budget)406 int otx2_napi_handler(struct napi_struct *napi, int budget)
407 {
408 struct otx2_cq_poll *cq_poll;
409 int workdone = 0, cq_idx, i;
410 struct otx2_cq_queue *cq;
411 struct otx2_qset *qset;
412 struct otx2_nic *pfvf;
413
414 cq_poll = container_of(napi, struct otx2_cq_poll, napi);
415 pfvf = (struct otx2_nic *)cq_poll->dev;
416 qset = &pfvf->qset;
417
418 for (i = CQS_PER_CINT - 1; i >= 0; i--) {
419 cq_idx = cq_poll->cq_ids[i];
420 if (unlikely(cq_idx == CINT_INVALID_CQ))
421 continue;
422 cq = &qset->cq[cq_idx];
423 if (cq->cq_type == CQ_RX) {
424 /* If the RQ refill WQ task is running, skip napi
425 * scheduler for this queue.
426 */
427 if (cq->refill_task_sched)
428 continue;
429 workdone += otx2_rx_napi_handler(pfvf, napi,
430 cq, budget);
431 } else {
432 workdone += otx2_tx_napi_handler(pfvf, cq, budget);
433 }
434 }
435
436 /* Clear the IRQ */
437 otx2_write64(pfvf, NIX_LF_CINTX_INT(cq_poll->cint_idx), BIT_ULL(0));
438
439 if (workdone < budget && napi_complete_done(napi, workdone)) {
440 /* If interface is going down, don't re-enable IRQ */
441 if (pfvf->flags & OTX2_FLAG_INTF_DOWN)
442 return workdone;
443
444 /* Re-enable interrupts */
445 otx2_write64(pfvf, NIX_LF_CINTX_ENA_W1S(cq_poll->cint_idx),
446 BIT_ULL(0));
447 }
448 return workdone;
449 }
450
otx2_sqe_flush(void * dev,struct otx2_snd_queue * sq,int size,int qidx)451 void otx2_sqe_flush(void *dev, struct otx2_snd_queue *sq,
452 int size, int qidx)
453 {
454 u64 status;
455
456 /* Packet data stores should finish before SQE is flushed to HW */
457 dma_wmb();
458
459 do {
460 memcpy(sq->lmt_addr, sq->sqe_base, size);
461 status = otx2_lmt_flush(sq->io_addr);
462 } while (status == 0);
463
464 sq->head++;
465 sq->head &= (sq->sqe_cnt - 1);
466 }
467
468 #define MAX_SEGS_PER_SG 3
469 /* Add SQE scatter/gather subdescriptor structure */
otx2_sqe_add_sg(struct otx2_nic * pfvf,struct otx2_snd_queue * sq,struct sk_buff * skb,int num_segs,int * offset)470 static bool otx2_sqe_add_sg(struct otx2_nic *pfvf, struct otx2_snd_queue *sq,
471 struct sk_buff *skb, int num_segs, int *offset)
472 {
473 struct nix_sqe_sg_s *sg = NULL;
474 u64 dma_addr, *iova = NULL;
475 u16 *sg_lens = NULL;
476 int seg, len;
477
478 sq->sg[sq->head].num_segs = 0;
479
480 for (seg = 0; seg < num_segs; seg++) {
481 if ((seg % MAX_SEGS_PER_SG) == 0) {
482 sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset);
483 sg->ld_type = NIX_SEND_LDTYPE_LDD;
484 sg->subdc = NIX_SUBDC_SG;
485 sg->segs = 0;
486 sg_lens = (void *)sg;
487 iova = (void *)sg + sizeof(*sg);
488 /* Next subdc always starts at a 16byte boundary.
489 * So if sg->segs is whether 2 or 3, offset += 16bytes.
490 */
491 if ((num_segs - seg) >= (MAX_SEGS_PER_SG - 1))
492 *offset += sizeof(*sg) + (3 * sizeof(u64));
493 else
494 *offset += sizeof(*sg) + sizeof(u64);
495 }
496 dma_addr = otx2_dma_map_skb_frag(pfvf, skb, seg, &len);
497 if (dma_mapping_error(pfvf->dev, dma_addr))
498 return false;
499
500 sg_lens[frag_num(seg % MAX_SEGS_PER_SG)] = len;
501 sg->segs++;
502 *iova++ = dma_addr;
503
504 /* Save DMA mapping info for later unmapping */
505 sq->sg[sq->head].dma_addr[seg] = dma_addr;
506 sq->sg[sq->head].size[seg] = len;
507 sq->sg[sq->head].num_segs++;
508 }
509
510 sq->sg[sq->head].skb = (u64)skb;
511 return true;
512 }
513
514 /* Add SQE extended header subdescriptor */
otx2_sqe_add_ext(struct otx2_nic * pfvf,struct otx2_snd_queue * sq,struct sk_buff * skb,int * offset)515 static void otx2_sqe_add_ext(struct otx2_nic *pfvf, struct otx2_snd_queue *sq,
516 struct sk_buff *skb, int *offset)
517 {
518 struct nix_sqe_ext_s *ext;
519
520 ext = (struct nix_sqe_ext_s *)(sq->sqe_base + *offset);
521 ext->subdc = NIX_SUBDC_EXT;
522 if (skb_shinfo(skb)->gso_size) {
523 ext->lso = 1;
524 ext->lso_sb = skb_transport_offset(skb) + tcp_hdrlen(skb);
525 ext->lso_mps = skb_shinfo(skb)->gso_size;
526
527 /* Only TSOv4 and TSOv6 GSO offloads are supported */
528 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4) {
529 ext->lso_format = pfvf->hw.lso_tsov4_idx;
530
531 /* HW adds payload size to 'ip_hdr->tot_len' while
532 * sending TSO segment, hence set payload length
533 * in IP header of the packet to just header length.
534 */
535 ip_hdr(skb)->tot_len =
536 htons(ext->lso_sb - skb_network_offset(skb));
537 } else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
538 ext->lso_format = pfvf->hw.lso_tsov6_idx;
539
540 ipv6_hdr(skb)->payload_len =
541 htons(ext->lso_sb - skb_network_offset(skb));
542 } else if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
543 __be16 l3_proto = vlan_get_protocol(skb);
544 struct udphdr *udph = udp_hdr(skb);
545 u16 iplen;
546
547 ext->lso_sb = skb_transport_offset(skb) +
548 sizeof(struct udphdr);
549
550 /* HW adds payload size to length fields in IP and
551 * UDP headers while segmentation, hence adjust the
552 * lengths to just header sizes.
553 */
554 iplen = htons(ext->lso_sb - skb_network_offset(skb));
555 if (l3_proto == htons(ETH_P_IP)) {
556 ip_hdr(skb)->tot_len = iplen;
557 ext->lso_format = pfvf->hw.lso_udpv4_idx;
558 } else {
559 ipv6_hdr(skb)->payload_len = iplen;
560 ext->lso_format = pfvf->hw.lso_udpv6_idx;
561 }
562
563 udph->len = htons(sizeof(struct udphdr));
564 }
565 } else if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
566 ext->tstmp = 1;
567 }
568
569 #define OTX2_VLAN_PTR_OFFSET (ETH_HLEN - ETH_TLEN)
570 if (skb_vlan_tag_present(skb)) {
571 if (skb->vlan_proto == htons(ETH_P_8021Q)) {
572 ext->vlan1_ins_ena = 1;
573 ext->vlan1_ins_ptr = OTX2_VLAN_PTR_OFFSET;
574 ext->vlan1_ins_tci = skb_vlan_tag_get(skb);
575 } else if (skb->vlan_proto == htons(ETH_P_8021AD)) {
576 ext->vlan0_ins_ena = 1;
577 ext->vlan0_ins_ptr = OTX2_VLAN_PTR_OFFSET;
578 ext->vlan0_ins_tci = skb_vlan_tag_get(skb);
579 }
580 }
581
582 *offset += sizeof(*ext);
583 }
584
otx2_sqe_add_mem(struct otx2_snd_queue * sq,int * offset,int alg,u64 iova)585 static void otx2_sqe_add_mem(struct otx2_snd_queue *sq, int *offset,
586 int alg, u64 iova)
587 {
588 struct nix_sqe_mem_s *mem;
589
590 mem = (struct nix_sqe_mem_s *)(sq->sqe_base + *offset);
591 mem->subdc = NIX_SUBDC_MEM;
592 mem->alg = alg;
593 mem->wmem = 1; /* wait for the memory operation */
594 mem->addr = iova;
595
596 *offset += sizeof(*mem);
597 }
598
599 /* Add SQE header subdescriptor structure */
otx2_sqe_add_hdr(struct otx2_nic * pfvf,struct otx2_snd_queue * sq,struct nix_sqe_hdr_s * sqe_hdr,struct sk_buff * skb,u16 qidx)600 static void otx2_sqe_add_hdr(struct otx2_nic *pfvf, struct otx2_snd_queue *sq,
601 struct nix_sqe_hdr_s *sqe_hdr,
602 struct sk_buff *skb, u16 qidx)
603 {
604 int proto = 0;
605
606 /* Check if SQE was framed before, if yes then no need to
607 * set these constants again and again.
608 */
609 if (!sqe_hdr->total) {
610 /* Don't free Tx buffers to Aura */
611 sqe_hdr->df = 1;
612 sqe_hdr->aura = sq->aura_id;
613 /* Post a CQE Tx after pkt transmission */
614 sqe_hdr->pnc = 1;
615 sqe_hdr->sq = qidx;
616 }
617 sqe_hdr->total = skb->len;
618 /* Set SQE identifier which will be used later for freeing SKB */
619 sqe_hdr->sqe_id = sq->head;
620
621 /* Offload TCP/UDP checksum to HW */
622 if (skb->ip_summed == CHECKSUM_PARTIAL) {
623 sqe_hdr->ol3ptr = skb_network_offset(skb);
624 sqe_hdr->ol4ptr = skb_transport_offset(skb);
625 /* get vlan protocol Ethertype */
626 if (eth_type_vlan(skb->protocol))
627 skb->protocol = vlan_get_protocol(skb);
628
629 if (skb->protocol == htons(ETH_P_IP)) {
630 proto = ip_hdr(skb)->protocol;
631 /* In case of TSO, HW needs this to be explicitly set.
632 * So set this always, instead of adding a check.
633 */
634 sqe_hdr->ol3type = NIX_SENDL3TYPE_IP4_CKSUM;
635 } else if (skb->protocol == htons(ETH_P_IPV6)) {
636 proto = ipv6_hdr(skb)->nexthdr;
637 sqe_hdr->ol3type = NIX_SENDL3TYPE_IP6;
638 }
639
640 if (proto == IPPROTO_TCP)
641 sqe_hdr->ol4type = NIX_SENDL4TYPE_TCP_CKSUM;
642 else if (proto == IPPROTO_UDP)
643 sqe_hdr->ol4type = NIX_SENDL4TYPE_UDP_CKSUM;
644 }
645 }
646
otx2_dma_map_tso_skb(struct otx2_nic * pfvf,struct otx2_snd_queue * sq,struct sk_buff * skb,int sqe,int hdr_len)647 static int otx2_dma_map_tso_skb(struct otx2_nic *pfvf,
648 struct otx2_snd_queue *sq,
649 struct sk_buff *skb, int sqe, int hdr_len)
650 {
651 int num_segs = skb_shinfo(skb)->nr_frags + 1;
652 struct sg_list *sg = &sq->sg[sqe];
653 u64 dma_addr;
654 int seg, len;
655
656 sg->num_segs = 0;
657
658 /* Get payload length at skb->data */
659 len = skb_headlen(skb) - hdr_len;
660
661 for (seg = 0; seg < num_segs; seg++) {
662 /* Skip skb->data, if there is no payload */
663 if (!seg && !len)
664 continue;
665 dma_addr = otx2_dma_map_skb_frag(pfvf, skb, seg, &len);
666 if (dma_mapping_error(pfvf->dev, dma_addr))
667 goto unmap;
668
669 /* Save DMA mapping info for later unmapping */
670 sg->dma_addr[sg->num_segs] = dma_addr;
671 sg->size[sg->num_segs] = len;
672 sg->num_segs++;
673 }
674 return 0;
675 unmap:
676 otx2_dma_unmap_skb_frags(pfvf, sg);
677 return -EINVAL;
678 }
679
otx2_tso_frag_dma_addr(struct otx2_snd_queue * sq,struct sk_buff * skb,int seg,u64 seg_addr,int hdr_len,int sqe)680 static u64 otx2_tso_frag_dma_addr(struct otx2_snd_queue *sq,
681 struct sk_buff *skb, int seg,
682 u64 seg_addr, int hdr_len, int sqe)
683 {
684 struct sg_list *sg = &sq->sg[sqe];
685 const skb_frag_t *frag;
686 int offset;
687
688 if (seg < 0)
689 return sg->dma_addr[0] + (seg_addr - (u64)skb->data);
690
691 frag = &skb_shinfo(skb)->frags[seg];
692 offset = seg_addr - (u64)skb_frag_address(frag);
693 if (skb_headlen(skb) - hdr_len)
694 seg++;
695 return sg->dma_addr[seg] + offset;
696 }
697
otx2_sqe_tso_add_sg(struct otx2_snd_queue * sq,struct sg_list * list,int * offset)698 static void otx2_sqe_tso_add_sg(struct otx2_snd_queue *sq,
699 struct sg_list *list, int *offset)
700 {
701 struct nix_sqe_sg_s *sg = NULL;
702 u16 *sg_lens = NULL;
703 u64 *iova = NULL;
704 int seg;
705
706 /* Add SG descriptors with buffer addresses */
707 for (seg = 0; seg < list->num_segs; seg++) {
708 if ((seg % MAX_SEGS_PER_SG) == 0) {
709 sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset);
710 sg->ld_type = NIX_SEND_LDTYPE_LDD;
711 sg->subdc = NIX_SUBDC_SG;
712 sg->segs = 0;
713 sg_lens = (void *)sg;
714 iova = (void *)sg + sizeof(*sg);
715 /* Next subdc always starts at a 16byte boundary.
716 * So if sg->segs is whether 2 or 3, offset += 16bytes.
717 */
718 if ((list->num_segs - seg) >= (MAX_SEGS_PER_SG - 1))
719 *offset += sizeof(*sg) + (3 * sizeof(u64));
720 else
721 *offset += sizeof(*sg) + sizeof(u64);
722 }
723 sg_lens[frag_num(seg % MAX_SEGS_PER_SG)] = list->size[seg];
724 *iova++ = list->dma_addr[seg];
725 sg->segs++;
726 }
727 }
728
otx2_sq_append_tso(struct otx2_nic * pfvf,struct otx2_snd_queue * sq,struct sk_buff * skb,u16 qidx)729 static void otx2_sq_append_tso(struct otx2_nic *pfvf, struct otx2_snd_queue *sq,
730 struct sk_buff *skb, u16 qidx)
731 {
732 struct netdev_queue *txq = netdev_get_tx_queue(pfvf->netdev, qidx);
733 int hdr_len, tcp_data, seg_len, pkt_len, offset;
734 struct nix_sqe_hdr_s *sqe_hdr;
735 int first_sqe = sq->head;
736 struct sg_list list;
737 struct tso_t tso;
738
739 hdr_len = tso_start(skb, &tso);
740
741 /* Map SKB's fragments to DMA.
742 * It's done here to avoid mapping for every TSO segment's packet.
743 */
744 if (otx2_dma_map_tso_skb(pfvf, sq, skb, first_sqe, hdr_len)) {
745 dev_kfree_skb_any(skb);
746 return;
747 }
748
749 netdev_tx_sent_queue(txq, skb->len);
750
751 tcp_data = skb->len - hdr_len;
752 while (tcp_data > 0) {
753 char *hdr;
754
755 seg_len = min_t(int, skb_shinfo(skb)->gso_size, tcp_data);
756 tcp_data -= seg_len;
757
758 /* Set SQE's SEND_HDR */
759 memset(sq->sqe_base, 0, sq->sqe_size);
760 sqe_hdr = (struct nix_sqe_hdr_s *)(sq->sqe_base);
761 otx2_sqe_add_hdr(pfvf, sq, sqe_hdr, skb, qidx);
762 offset = sizeof(*sqe_hdr);
763
764 /* Add TSO segment's pkt header */
765 hdr = sq->tso_hdrs->base + (sq->head * TSO_HEADER_SIZE);
766 tso_build_hdr(skb, hdr, &tso, seg_len, tcp_data == 0);
767 list.dma_addr[0] =
768 sq->tso_hdrs->iova + (sq->head * TSO_HEADER_SIZE);
769 list.size[0] = hdr_len;
770 list.num_segs = 1;
771
772 /* Add TSO segment's payload data fragments */
773 pkt_len = hdr_len;
774 while (seg_len > 0) {
775 int size;
776
777 size = min_t(int, tso.size, seg_len);
778
779 list.size[list.num_segs] = size;
780 list.dma_addr[list.num_segs] =
781 otx2_tso_frag_dma_addr(sq, skb,
782 tso.next_frag_idx - 1,
783 (u64)tso.data, hdr_len,
784 first_sqe);
785 list.num_segs++;
786 pkt_len += size;
787 seg_len -= size;
788 tso_build_data(skb, &tso, size);
789 }
790 sqe_hdr->total = pkt_len;
791 otx2_sqe_tso_add_sg(sq, &list, &offset);
792
793 /* DMA mappings and skb needs to be freed only after last
794 * TSO segment is transmitted out. So set 'PNC' only for
795 * last segment. Also point last segment's sqe_id to first
796 * segment's SQE index where skb address and DMA mappings
797 * are saved.
798 */
799 if (!tcp_data) {
800 sqe_hdr->pnc = 1;
801 sqe_hdr->sqe_id = first_sqe;
802 sq->sg[first_sqe].skb = (u64)skb;
803 } else {
804 sqe_hdr->pnc = 0;
805 }
806
807 sqe_hdr->sizem1 = (offset / 16) - 1;
808
809 /* Flush SQE to HW */
810 pfvf->hw_ops->sqe_flush(pfvf, sq, offset, qidx);
811 }
812 }
813
is_hw_tso_supported(struct otx2_nic * pfvf,struct sk_buff * skb)814 static bool is_hw_tso_supported(struct otx2_nic *pfvf,
815 struct sk_buff *skb)
816 {
817 int payload_len, last_seg_size;
818
819 if (test_bit(HW_TSO, &pfvf->hw.cap_flag))
820 return true;
821
822 /* On 96xx A0, HW TSO not supported */
823 if (!is_96xx_B0(pfvf->pdev))
824 return false;
825
826 /* HW has an issue due to which when the payload of the last LSO
827 * segment is shorter than 16 bytes, some header fields may not
828 * be correctly modified, hence don't offload such TSO segments.
829 */
830
831 payload_len = skb->len - (skb_transport_offset(skb) + tcp_hdrlen(skb));
832 last_seg_size = payload_len % skb_shinfo(skb)->gso_size;
833 if (last_seg_size && last_seg_size < 16)
834 return false;
835
836 return true;
837 }
838
otx2_get_sqe_count(struct otx2_nic * pfvf,struct sk_buff * skb)839 static int otx2_get_sqe_count(struct otx2_nic *pfvf, struct sk_buff *skb)
840 {
841 if (!skb_shinfo(skb)->gso_size)
842 return 1;
843
844 /* HW TSO */
845 if (is_hw_tso_supported(pfvf, skb))
846 return 1;
847
848 /* SW TSO */
849 return skb_shinfo(skb)->gso_segs;
850 }
851
otx2_set_txtstamp(struct otx2_nic * pfvf,struct sk_buff * skb,struct otx2_snd_queue * sq,int * offset)852 static void otx2_set_txtstamp(struct otx2_nic *pfvf, struct sk_buff *skb,
853 struct otx2_snd_queue *sq, int *offset)
854 {
855 u64 iova;
856
857 if (!skb_shinfo(skb)->gso_size &&
858 skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
859 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
860 iova = sq->timestamps->iova + (sq->head * sizeof(u64));
861 otx2_sqe_add_mem(sq, offset, NIX_SENDMEMALG_E_SETTSTMP, iova);
862 } else {
863 skb_tx_timestamp(skb);
864 }
865 }
866
otx2_sq_append_skb(struct net_device * netdev,struct otx2_snd_queue * sq,struct sk_buff * skb,u16 qidx)867 bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *sq,
868 struct sk_buff *skb, u16 qidx)
869 {
870 struct netdev_queue *txq = netdev_get_tx_queue(netdev, qidx);
871 struct otx2_nic *pfvf = netdev_priv(netdev);
872 int offset, num_segs, free_sqe;
873 struct nix_sqe_hdr_s *sqe_hdr;
874
875 /* Check if there is room for new SQE.
876 * 'Num of SQBs freed to SQ's pool - SQ's Aura count'
877 * will give free SQE count.
878 */
879 free_sqe = (sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb;
880
881 if (free_sqe < sq->sqe_thresh ||
882 free_sqe < otx2_get_sqe_count(pfvf, skb))
883 return false;
884
885 num_segs = skb_shinfo(skb)->nr_frags + 1;
886
887 /* If SKB doesn't fit in a single SQE, linearize it.
888 * TODO: Consider adding JUMP descriptor instead.
889 */
890 if (unlikely(num_segs > OTX2_MAX_FRAGS_IN_SQE)) {
891 if (__skb_linearize(skb)) {
892 dev_kfree_skb_any(skb);
893 return true;
894 }
895 num_segs = skb_shinfo(skb)->nr_frags + 1;
896 }
897
898 if (skb_shinfo(skb)->gso_size && !is_hw_tso_supported(pfvf, skb)) {
899 /* Insert vlan tag before giving pkt to tso */
900 if (skb_vlan_tag_present(skb))
901 skb = __vlan_hwaccel_push_inside(skb);
902 otx2_sq_append_tso(pfvf, sq, skb, qidx);
903 return true;
904 }
905
906 /* Set SQE's SEND_HDR.
907 * Do not clear the first 64bit as it contains constant info.
908 */
909 memset(sq->sqe_base + 8, 0, sq->sqe_size - 8);
910 sqe_hdr = (struct nix_sqe_hdr_s *)(sq->sqe_base);
911 otx2_sqe_add_hdr(pfvf, sq, sqe_hdr, skb, qidx);
912 offset = sizeof(*sqe_hdr);
913
914 /* Add extended header if needed */
915 otx2_sqe_add_ext(pfvf, sq, skb, &offset);
916
917 /* Add SG subdesc with data frags */
918 if (!otx2_sqe_add_sg(pfvf, sq, skb, num_segs, &offset)) {
919 otx2_dma_unmap_skb_frags(pfvf, &sq->sg[sq->head]);
920 return false;
921 }
922
923 otx2_set_txtstamp(pfvf, skb, sq, &offset);
924
925 sqe_hdr->sizem1 = (offset / 16) - 1;
926
927 netdev_tx_sent_queue(txq, skb->len);
928
929 /* Flush SQE to HW */
930 pfvf->hw_ops->sqe_flush(pfvf, sq, offset, qidx);
931
932 return true;
933 }
934 EXPORT_SYMBOL(otx2_sq_append_skb);
935
otx2_cleanup_rx_cqes(struct otx2_nic * pfvf,struct otx2_cq_queue * cq)936 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq)
937 {
938 struct nix_cqe_rx_s *cqe;
939 int processed_cqe = 0;
940 u64 iova, pa;
941
942 while ((cqe = (struct nix_cqe_rx_s *)otx2_get_next_cqe(cq))) {
943 if (!cqe->sg.subdc)
944 continue;
945 processed_cqe++;
946 if (cqe->sg.segs > 1) {
947 otx2_free_rcv_seg(pfvf, cqe, cq->cq_idx);
948 continue;
949 }
950 iova = cqe->sg.seg_addr - OTX2_HEAD_ROOM;
951 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova);
952 otx2_dma_unmap_page(pfvf, iova, pfvf->rbsize, DMA_FROM_DEVICE);
953 put_page(virt_to_page(phys_to_virt(pa)));
954 }
955
956 /* Free CQEs to HW */
957 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR,
958 ((u64)cq->cq_idx << 32) | processed_cqe);
959 }
960
otx2_cleanup_tx_cqes(struct otx2_nic * pfvf,struct otx2_cq_queue * cq)961 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq)
962 {
963 struct sk_buff *skb = NULL;
964 struct otx2_snd_queue *sq;
965 struct nix_cqe_tx_s *cqe;
966 int processed_cqe = 0;
967 struct sg_list *sg;
968
969 sq = &pfvf->qset.sq[cq->cint_idx];
970
971 while ((cqe = (struct nix_cqe_tx_s *)otx2_get_next_cqe(cq))) {
972 sg = &sq->sg[cqe->comp.sqe_id];
973 skb = (struct sk_buff *)sg->skb;
974 if (skb) {
975 otx2_dma_unmap_skb_frags(pfvf, sg);
976 dev_kfree_skb_any(skb);
977 sg->skb = (u64)NULL;
978 }
979 processed_cqe++;
980 }
981
982 /* Free CQEs to HW */
983 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR,
984 ((u64)cq->cq_idx << 32) | processed_cqe);
985 }
986
otx2_rxtx_enable(struct otx2_nic * pfvf,bool enable)987 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable)
988 {
989 struct msg_req *msg;
990 int err;
991
992 mutex_lock(&pfvf->mbox.lock);
993 if (enable)
994 msg = otx2_mbox_alloc_msg_nix_lf_start_rx(&pfvf->mbox);
995 else
996 msg = otx2_mbox_alloc_msg_nix_lf_stop_rx(&pfvf->mbox);
997
998 if (!msg) {
999 mutex_unlock(&pfvf->mbox.lock);
1000 return -ENOMEM;
1001 }
1002
1003 err = otx2_sync_mbox_msg(&pfvf->mbox);
1004 mutex_unlock(&pfvf->mbox.lock);
1005 return err;
1006 }
1007