1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
4  *
5  * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
6  *
7  * This driver has been based on the spi-gpio.c:
8  *	Copyright (C) 2006,2008 David Brownell
9  */
10 
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/spinlock.h>
15 #include <linux/platform_device.h>
16 #include <linux/io.h>
17 #include <linux/spi/spi.h>
18 #include <linux/spi/spi_bitbang.h>
19 #include <linux/bitops.h>
20 #include <linux/clk.h>
21 #include <linux/err.h>
22 #include <linux/platform_data/spi-ath79.h>
23 
24 #define DRV_NAME	"ath79-spi"
25 
26 #define ATH79_SPI_RRW_DELAY_FACTOR	12000
27 #define MHZ				(1000 * 1000)
28 
29 #define AR71XX_SPI_REG_FS		0x00	/* Function Select */
30 #define AR71XX_SPI_REG_CTRL		0x04	/* SPI Control */
31 #define AR71XX_SPI_REG_IOC		0x08	/* SPI I/O Control */
32 #define AR71XX_SPI_REG_RDS		0x0c	/* Read Data Shift */
33 
34 #define AR71XX_SPI_FS_GPIO		BIT(0)	/* Enable GPIO mode */
35 
36 #define AR71XX_SPI_IOC_DO		BIT(0)	/* Data Out pin */
37 #define AR71XX_SPI_IOC_CLK		BIT(8)	/* CLK pin */
38 #define AR71XX_SPI_IOC_CS(n)		BIT(16 + (n))
39 
40 struct ath79_spi {
41 	struct spi_bitbang	bitbang;
42 	u32			ioc_base;
43 	u32			reg_ctrl;
44 	void __iomem		*base;
45 	struct clk		*clk;
46 	unsigned int		rrw_delay;
47 };
48 
ath79_spi_rr(struct ath79_spi * sp,unsigned int reg)49 static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned int reg)
50 {
51 	return ioread32(sp->base + reg);
52 }
53 
ath79_spi_wr(struct ath79_spi * sp,unsigned int reg,u32 val)54 static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned int reg, u32 val)
55 {
56 	iowrite32(val, sp->base + reg);
57 }
58 
ath79_spidev_to_sp(struct spi_device * spi)59 static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)
60 {
61 	return spi_master_get_devdata(spi->master);
62 }
63 
ath79_spi_delay(struct ath79_spi * sp,unsigned int nsecs)64 static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned int nsecs)
65 {
66 	if (nsecs > sp->rrw_delay)
67 		ndelay(nsecs - sp->rrw_delay);
68 }
69 
ath79_spi_chipselect(struct spi_device * spi,int is_active)70 static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
71 {
72 	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
73 	int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
74 	u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);
75 
76 	if (cs_high)
77 		sp->ioc_base |= cs_bit;
78 	else
79 		sp->ioc_base &= ~cs_bit;
80 
81 	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
82 }
83 
ath79_spi_enable(struct ath79_spi * sp)84 static void ath79_spi_enable(struct ath79_spi *sp)
85 {
86 	/* enable GPIO mode */
87 	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
88 
89 	/* save CTRL register */
90 	sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
91 	sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
92 
93 	/* clear clk and mosi in the base state */
94 	sp->ioc_base &= ~(AR71XX_SPI_IOC_DO | AR71XX_SPI_IOC_CLK);
95 
96 	/* TODO: setup speed? */
97 	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
98 }
99 
ath79_spi_disable(struct ath79_spi * sp)100 static void ath79_spi_disable(struct ath79_spi *sp)
101 {
102 	/* restore CTRL register */
103 	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
104 	/* disable GPIO mode */
105 	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
106 }
107 
ath79_spi_txrx_mode0(struct spi_device * spi,unsigned int nsecs,u32 word,u8 bits,unsigned flags)108 static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned int nsecs,
109 			       u32 word, u8 bits, unsigned flags)
110 {
111 	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
112 	u32 ioc = sp->ioc_base;
113 
114 	/* clock starts at inactive polarity */
115 	for (word <<= (32 - bits); likely(bits); bits--) {
116 		u32 out;
117 
118 		if (word & (1 << 31))
119 			out = ioc | AR71XX_SPI_IOC_DO;
120 		else
121 			out = ioc & ~AR71XX_SPI_IOC_DO;
122 
123 		/* setup MSB (to slave) on trailing edge */
124 		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
125 		ath79_spi_delay(sp, nsecs);
126 		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
127 		ath79_spi_delay(sp, nsecs);
128 		if (bits == 1)
129 			ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
130 
131 		word <<= 1;
132 	}
133 
134 	return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
135 }
136 
ath79_spi_probe(struct platform_device * pdev)137 static int ath79_spi_probe(struct platform_device *pdev)
138 {
139 	struct spi_master *master;
140 	struct ath79_spi *sp;
141 	struct ath79_spi_platform_data *pdata;
142 	unsigned long rate;
143 	int ret;
144 
145 	master = spi_alloc_master(&pdev->dev, sizeof(*sp));
146 	if (master == NULL) {
147 		dev_err(&pdev->dev, "failed to allocate spi master\n");
148 		return -ENOMEM;
149 	}
150 
151 	sp = spi_master_get_devdata(master);
152 	master->dev.of_node = pdev->dev.of_node;
153 	platform_set_drvdata(pdev, sp);
154 
155 	pdata = dev_get_platdata(&pdev->dev);
156 
157 	master->use_gpio_descriptors = true;
158 	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
159 	master->flags = SPI_MASTER_GPIO_SS;
160 	if (pdata) {
161 		master->bus_num = pdata->bus_num;
162 		master->num_chipselect = pdata->num_chipselect;
163 	}
164 
165 	sp->bitbang.master = master;
166 	sp->bitbang.chipselect = ath79_spi_chipselect;
167 	sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
168 	sp->bitbang.flags = SPI_CS_HIGH;
169 
170 	sp->base = devm_platform_ioremap_resource(pdev, 0);
171 	if (IS_ERR(sp->base)) {
172 		ret = PTR_ERR(sp->base);
173 		goto err_put_master;
174 	}
175 
176 	sp->clk = devm_clk_get(&pdev->dev, "ahb");
177 	if (IS_ERR(sp->clk)) {
178 		ret = PTR_ERR(sp->clk);
179 		goto err_put_master;
180 	}
181 
182 	ret = clk_prepare_enable(sp->clk);
183 	if (ret)
184 		goto err_put_master;
185 
186 	rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
187 	if (!rate) {
188 		ret = -EINVAL;
189 		goto err_clk_disable;
190 	}
191 
192 	sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
193 	dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
194 		sp->rrw_delay);
195 
196 	ath79_spi_enable(sp);
197 	ret = spi_bitbang_start(&sp->bitbang);
198 	if (ret)
199 		goto err_disable;
200 
201 	return 0;
202 
203 err_disable:
204 	ath79_spi_disable(sp);
205 err_clk_disable:
206 	clk_disable_unprepare(sp->clk);
207 err_put_master:
208 	spi_master_put(sp->bitbang.master);
209 
210 	return ret;
211 }
212 
ath79_spi_remove(struct platform_device * pdev)213 static int ath79_spi_remove(struct platform_device *pdev)
214 {
215 	struct ath79_spi *sp = platform_get_drvdata(pdev);
216 
217 	spi_bitbang_stop(&sp->bitbang);
218 	ath79_spi_disable(sp);
219 	clk_disable_unprepare(sp->clk);
220 	spi_master_put(sp->bitbang.master);
221 
222 	return 0;
223 }
224 
ath79_spi_shutdown(struct platform_device * pdev)225 static void ath79_spi_shutdown(struct platform_device *pdev)
226 {
227 	ath79_spi_remove(pdev);
228 }
229 
230 static const struct of_device_id ath79_spi_of_match[] = {
231 	{ .compatible = "qca,ar7100-spi", },
232 	{ },
233 };
234 MODULE_DEVICE_TABLE(of, ath79_spi_of_match);
235 
236 static struct platform_driver ath79_spi_driver = {
237 	.probe		= ath79_spi_probe,
238 	.remove		= ath79_spi_remove,
239 	.shutdown	= ath79_spi_shutdown,
240 	.driver		= {
241 		.name	= DRV_NAME,
242 		.of_match_table = ath79_spi_of_match,
243 	},
244 };
245 module_platform_driver(ath79_spi_driver);
246 
247 MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
248 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
249 MODULE_LICENSE("GPL v2");
250 MODULE_ALIAS("platform:" DRV_NAME);
251