1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Driver for Atmel AT32 and AT91 SPI Controllers
4 *
5 * Copyright (C) 2006 Atmel Corporation
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/clk.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/delay.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/dmaengine.h>
15 #include <linux/err.h>
16 #include <linux/interrupt.h>
17 #include <linux/spi/spi.h>
18 #include <linux/slab.h>
19 #include <linux/of.h>
20
21 #include <linux/io.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/pm_runtime.h>
25 #include <trace/events/spi.h>
26
27 /* SPI register offsets */
28 #define SPI_CR 0x0000
29 #define SPI_MR 0x0004
30 #define SPI_RDR 0x0008
31 #define SPI_TDR 0x000c
32 #define SPI_SR 0x0010
33 #define SPI_IER 0x0014
34 #define SPI_IDR 0x0018
35 #define SPI_IMR 0x001c
36 #define SPI_CSR0 0x0030
37 #define SPI_CSR1 0x0034
38 #define SPI_CSR2 0x0038
39 #define SPI_CSR3 0x003c
40 #define SPI_FMR 0x0040
41 #define SPI_FLR 0x0044
42 #define SPI_VERSION 0x00fc
43 #define SPI_RPR 0x0100
44 #define SPI_RCR 0x0104
45 #define SPI_TPR 0x0108
46 #define SPI_TCR 0x010c
47 #define SPI_RNPR 0x0110
48 #define SPI_RNCR 0x0114
49 #define SPI_TNPR 0x0118
50 #define SPI_TNCR 0x011c
51 #define SPI_PTCR 0x0120
52 #define SPI_PTSR 0x0124
53
54 /* Bitfields in CR */
55 #define SPI_SPIEN_OFFSET 0
56 #define SPI_SPIEN_SIZE 1
57 #define SPI_SPIDIS_OFFSET 1
58 #define SPI_SPIDIS_SIZE 1
59 #define SPI_SWRST_OFFSET 7
60 #define SPI_SWRST_SIZE 1
61 #define SPI_LASTXFER_OFFSET 24
62 #define SPI_LASTXFER_SIZE 1
63 #define SPI_TXFCLR_OFFSET 16
64 #define SPI_TXFCLR_SIZE 1
65 #define SPI_RXFCLR_OFFSET 17
66 #define SPI_RXFCLR_SIZE 1
67 #define SPI_FIFOEN_OFFSET 30
68 #define SPI_FIFOEN_SIZE 1
69 #define SPI_FIFODIS_OFFSET 31
70 #define SPI_FIFODIS_SIZE 1
71
72 /* Bitfields in MR */
73 #define SPI_MSTR_OFFSET 0
74 #define SPI_MSTR_SIZE 1
75 #define SPI_PS_OFFSET 1
76 #define SPI_PS_SIZE 1
77 #define SPI_PCSDEC_OFFSET 2
78 #define SPI_PCSDEC_SIZE 1
79 #define SPI_FDIV_OFFSET 3
80 #define SPI_FDIV_SIZE 1
81 #define SPI_MODFDIS_OFFSET 4
82 #define SPI_MODFDIS_SIZE 1
83 #define SPI_WDRBT_OFFSET 5
84 #define SPI_WDRBT_SIZE 1
85 #define SPI_LLB_OFFSET 7
86 #define SPI_LLB_SIZE 1
87 #define SPI_PCS_OFFSET 16
88 #define SPI_PCS_SIZE 4
89 #define SPI_DLYBCS_OFFSET 24
90 #define SPI_DLYBCS_SIZE 8
91
92 /* Bitfields in RDR */
93 #define SPI_RD_OFFSET 0
94 #define SPI_RD_SIZE 16
95
96 /* Bitfields in TDR */
97 #define SPI_TD_OFFSET 0
98 #define SPI_TD_SIZE 16
99
100 /* Bitfields in SR */
101 #define SPI_RDRF_OFFSET 0
102 #define SPI_RDRF_SIZE 1
103 #define SPI_TDRE_OFFSET 1
104 #define SPI_TDRE_SIZE 1
105 #define SPI_MODF_OFFSET 2
106 #define SPI_MODF_SIZE 1
107 #define SPI_OVRES_OFFSET 3
108 #define SPI_OVRES_SIZE 1
109 #define SPI_ENDRX_OFFSET 4
110 #define SPI_ENDRX_SIZE 1
111 #define SPI_ENDTX_OFFSET 5
112 #define SPI_ENDTX_SIZE 1
113 #define SPI_RXBUFF_OFFSET 6
114 #define SPI_RXBUFF_SIZE 1
115 #define SPI_TXBUFE_OFFSET 7
116 #define SPI_TXBUFE_SIZE 1
117 #define SPI_NSSR_OFFSET 8
118 #define SPI_NSSR_SIZE 1
119 #define SPI_TXEMPTY_OFFSET 9
120 #define SPI_TXEMPTY_SIZE 1
121 #define SPI_SPIENS_OFFSET 16
122 #define SPI_SPIENS_SIZE 1
123 #define SPI_TXFEF_OFFSET 24
124 #define SPI_TXFEF_SIZE 1
125 #define SPI_TXFFF_OFFSET 25
126 #define SPI_TXFFF_SIZE 1
127 #define SPI_TXFTHF_OFFSET 26
128 #define SPI_TXFTHF_SIZE 1
129 #define SPI_RXFEF_OFFSET 27
130 #define SPI_RXFEF_SIZE 1
131 #define SPI_RXFFF_OFFSET 28
132 #define SPI_RXFFF_SIZE 1
133 #define SPI_RXFTHF_OFFSET 29
134 #define SPI_RXFTHF_SIZE 1
135 #define SPI_TXFPTEF_OFFSET 30
136 #define SPI_TXFPTEF_SIZE 1
137 #define SPI_RXFPTEF_OFFSET 31
138 #define SPI_RXFPTEF_SIZE 1
139
140 /* Bitfields in CSR0 */
141 #define SPI_CPOL_OFFSET 0
142 #define SPI_CPOL_SIZE 1
143 #define SPI_NCPHA_OFFSET 1
144 #define SPI_NCPHA_SIZE 1
145 #define SPI_CSAAT_OFFSET 3
146 #define SPI_CSAAT_SIZE 1
147 #define SPI_BITS_OFFSET 4
148 #define SPI_BITS_SIZE 4
149 #define SPI_SCBR_OFFSET 8
150 #define SPI_SCBR_SIZE 8
151 #define SPI_DLYBS_OFFSET 16
152 #define SPI_DLYBS_SIZE 8
153 #define SPI_DLYBCT_OFFSET 24
154 #define SPI_DLYBCT_SIZE 8
155
156 /* Bitfields in RCR */
157 #define SPI_RXCTR_OFFSET 0
158 #define SPI_RXCTR_SIZE 16
159
160 /* Bitfields in TCR */
161 #define SPI_TXCTR_OFFSET 0
162 #define SPI_TXCTR_SIZE 16
163
164 /* Bitfields in RNCR */
165 #define SPI_RXNCR_OFFSET 0
166 #define SPI_RXNCR_SIZE 16
167
168 /* Bitfields in TNCR */
169 #define SPI_TXNCR_OFFSET 0
170 #define SPI_TXNCR_SIZE 16
171
172 /* Bitfields in PTCR */
173 #define SPI_RXTEN_OFFSET 0
174 #define SPI_RXTEN_SIZE 1
175 #define SPI_RXTDIS_OFFSET 1
176 #define SPI_RXTDIS_SIZE 1
177 #define SPI_TXTEN_OFFSET 8
178 #define SPI_TXTEN_SIZE 1
179 #define SPI_TXTDIS_OFFSET 9
180 #define SPI_TXTDIS_SIZE 1
181
182 /* Bitfields in FMR */
183 #define SPI_TXRDYM_OFFSET 0
184 #define SPI_TXRDYM_SIZE 2
185 #define SPI_RXRDYM_OFFSET 4
186 #define SPI_RXRDYM_SIZE 2
187 #define SPI_TXFTHRES_OFFSET 16
188 #define SPI_TXFTHRES_SIZE 6
189 #define SPI_RXFTHRES_OFFSET 24
190 #define SPI_RXFTHRES_SIZE 6
191
192 /* Bitfields in FLR */
193 #define SPI_TXFL_OFFSET 0
194 #define SPI_TXFL_SIZE 6
195 #define SPI_RXFL_OFFSET 16
196 #define SPI_RXFL_SIZE 6
197
198 /* Constants for BITS */
199 #define SPI_BITS_8_BPT 0
200 #define SPI_BITS_9_BPT 1
201 #define SPI_BITS_10_BPT 2
202 #define SPI_BITS_11_BPT 3
203 #define SPI_BITS_12_BPT 4
204 #define SPI_BITS_13_BPT 5
205 #define SPI_BITS_14_BPT 6
206 #define SPI_BITS_15_BPT 7
207 #define SPI_BITS_16_BPT 8
208 #define SPI_ONE_DATA 0
209 #define SPI_TWO_DATA 1
210 #define SPI_FOUR_DATA 2
211
212 /* Bit manipulation macros */
213 #define SPI_BIT(name) \
214 (1 << SPI_##name##_OFFSET)
215 #define SPI_BF(name, value) \
216 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
217 #define SPI_BFEXT(name, value) \
218 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
219 #define SPI_BFINS(name, value, old) \
220 (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
221 | SPI_BF(name, value))
222
223 /* Register access macros */
224 #define spi_readl(port, reg) \
225 readl_relaxed((port)->regs + SPI_##reg)
226 #define spi_writel(port, reg, value) \
227 writel_relaxed((value), (port)->regs + SPI_##reg)
228 #define spi_writew(port, reg, value) \
229 writew_relaxed((value), (port)->regs + SPI_##reg)
230
231 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
232 * cache operations; better heuristics consider wordsize and bitrate.
233 */
234 #define DMA_MIN_BYTES 16
235
236 #define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
237
238 #define AUTOSUSPEND_TIMEOUT 2000
239
240 struct atmel_spi_caps {
241 bool is_spi2;
242 bool has_wdrbt;
243 bool has_dma_support;
244 bool has_pdc_support;
245 };
246
247 /*
248 * The core SPI transfer engine just talks to a register bank to set up
249 * DMA transfers; transfer queue progress is driven by IRQs. The clock
250 * framework provides the base clock, subdivided for each spi_device.
251 */
252 struct atmel_spi {
253 spinlock_t lock;
254 unsigned long flags;
255
256 phys_addr_t phybase;
257 void __iomem *regs;
258 int irq;
259 struct clk *clk;
260 struct platform_device *pdev;
261 unsigned long spi_clk;
262
263 struct spi_transfer *current_transfer;
264 int current_remaining_bytes;
265 int done_status;
266 dma_addr_t dma_addr_rx_bbuf;
267 dma_addr_t dma_addr_tx_bbuf;
268 void *addr_rx_bbuf;
269 void *addr_tx_bbuf;
270
271 struct completion xfer_completion;
272
273 struct atmel_spi_caps caps;
274
275 bool use_dma;
276 bool use_pdc;
277
278 bool keep_cs;
279
280 u32 fifo_size;
281 u8 native_cs_free;
282 u8 native_cs_for_gpio;
283 };
284
285 /* Controller-specific per-slave state */
286 struct atmel_spi_device {
287 u32 csr;
288 };
289
290 #define SPI_MAX_DMA_XFER 65535 /* true for both PDC and DMA */
291 #define INVALID_DMA_ADDRESS 0xffffffff
292
293 /*
294 * Version 2 of the SPI controller has
295 * - CR.LASTXFER
296 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
297 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
298 * - SPI_CSRx.CSAAT
299 * - SPI_CSRx.SBCR allows faster clocking
300 */
atmel_spi_is_v2(struct atmel_spi * as)301 static bool atmel_spi_is_v2(struct atmel_spi *as)
302 {
303 return as->caps.is_spi2;
304 }
305
306 /*
307 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
308 * they assume that spi slave device state will not change on deselect, so
309 * that automagic deselection is OK. ("NPCSx rises if no data is to be
310 * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
311 * controllers have CSAAT and friends.
312 *
313 * Even controller newer than ar91rm9200, using GPIOs can make sens as
314 * it lets us support active-high chipselects despite the controller's
315 * belief that only active-low devices/systems exists.
316 *
317 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
318 * right when driven with GPIO. ("Mode Fault does not allow more than one
319 * Master on Chip Select 0.") No workaround exists for that ... so for
320 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
321 * and (c) will trigger that first erratum in some cases.
322 */
323
cs_activate(struct atmel_spi * as,struct spi_device * spi)324 static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
325 {
326 struct atmel_spi_device *asd = spi->controller_state;
327 int chip_select;
328 u32 mr;
329
330 if (spi->cs_gpiod)
331 chip_select = as->native_cs_for_gpio;
332 else
333 chip_select = spi->chip_select;
334
335 if (atmel_spi_is_v2(as)) {
336 spi_writel(as, CSR0 + 4 * chip_select, asd->csr);
337 /* For the low SPI version, there is a issue that PDC transfer
338 * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
339 */
340 spi_writel(as, CSR0, asd->csr);
341 if (as->caps.has_wdrbt) {
342 spi_writel(as, MR,
343 SPI_BF(PCS, ~(0x01 << chip_select))
344 | SPI_BIT(WDRBT)
345 | SPI_BIT(MODFDIS)
346 | SPI_BIT(MSTR));
347 } else {
348 spi_writel(as, MR,
349 SPI_BF(PCS, ~(0x01 << chip_select))
350 | SPI_BIT(MODFDIS)
351 | SPI_BIT(MSTR));
352 }
353
354 mr = spi_readl(as, MR);
355 if (spi->cs_gpiod)
356 gpiod_set_value(spi->cs_gpiod, 1);
357 } else {
358 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
359 int i;
360 u32 csr;
361
362 /* Make sure clock polarity is correct */
363 for (i = 0; i < spi->master->num_chipselect; i++) {
364 csr = spi_readl(as, CSR0 + 4 * i);
365 if ((csr ^ cpol) & SPI_BIT(CPOL))
366 spi_writel(as, CSR0 + 4 * i,
367 csr ^ SPI_BIT(CPOL));
368 }
369
370 mr = spi_readl(as, MR);
371 mr = SPI_BFINS(PCS, ~(1 << chip_select), mr);
372 if (spi->cs_gpiod)
373 gpiod_set_value(spi->cs_gpiod, 1);
374 spi_writel(as, MR, mr);
375 }
376
377 dev_dbg(&spi->dev, "activate NPCS, mr %08x\n", mr);
378 }
379
cs_deactivate(struct atmel_spi * as,struct spi_device * spi)380 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
381 {
382 int chip_select;
383 u32 mr;
384
385 if (spi->cs_gpiod)
386 chip_select = as->native_cs_for_gpio;
387 else
388 chip_select = spi->chip_select;
389
390 /* only deactivate *this* device; sometimes transfers to
391 * another device may be active when this routine is called.
392 */
393 mr = spi_readl(as, MR);
394 if (~SPI_BFEXT(PCS, mr) & (1 << chip_select)) {
395 mr = SPI_BFINS(PCS, 0xf, mr);
396 spi_writel(as, MR, mr);
397 }
398
399 dev_dbg(&spi->dev, "DEactivate NPCS, mr %08x\n", mr);
400
401 if (!spi->cs_gpiod)
402 spi_writel(as, CR, SPI_BIT(LASTXFER));
403 else
404 gpiod_set_value(spi->cs_gpiod, 0);
405 }
406
atmel_spi_lock(struct atmel_spi * as)407 static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
408 {
409 spin_lock_irqsave(&as->lock, as->flags);
410 }
411
atmel_spi_unlock(struct atmel_spi * as)412 static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock)
413 {
414 spin_unlock_irqrestore(&as->lock, as->flags);
415 }
416
atmel_spi_is_vmalloc_xfer(struct spi_transfer * xfer)417 static inline bool atmel_spi_is_vmalloc_xfer(struct spi_transfer *xfer)
418 {
419 return is_vmalloc_addr(xfer->tx_buf) || is_vmalloc_addr(xfer->rx_buf);
420 }
421
atmel_spi_use_dma(struct atmel_spi * as,struct spi_transfer * xfer)422 static inline bool atmel_spi_use_dma(struct atmel_spi *as,
423 struct spi_transfer *xfer)
424 {
425 return as->use_dma && xfer->len >= DMA_MIN_BYTES;
426 }
427
atmel_spi_can_dma(struct spi_master * master,struct spi_device * spi,struct spi_transfer * xfer)428 static bool atmel_spi_can_dma(struct spi_master *master,
429 struct spi_device *spi,
430 struct spi_transfer *xfer)
431 {
432 struct atmel_spi *as = spi_master_get_devdata(master);
433
434 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5))
435 return atmel_spi_use_dma(as, xfer) &&
436 !atmel_spi_is_vmalloc_xfer(xfer);
437 else
438 return atmel_spi_use_dma(as, xfer);
439
440 }
441
atmel_spi_dma_slave_config(struct atmel_spi * as,struct dma_slave_config * slave_config,u8 bits_per_word)442 static int atmel_spi_dma_slave_config(struct atmel_spi *as,
443 struct dma_slave_config *slave_config,
444 u8 bits_per_word)
445 {
446 struct spi_master *master = platform_get_drvdata(as->pdev);
447 int err = 0;
448
449 if (bits_per_word > 8) {
450 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
451 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
452 } else {
453 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
454 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
455 }
456
457 slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
458 slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR;
459 slave_config->src_maxburst = 1;
460 slave_config->dst_maxburst = 1;
461 slave_config->device_fc = false;
462
463 /*
464 * This driver uses fixed peripheral select mode (PS bit set to '0' in
465 * the Mode Register).
466 * So according to the datasheet, when FIFOs are available (and
467 * enabled), the Transmit FIFO operates in Multiple Data Mode.
468 * In this mode, up to 2 data, not 4, can be written into the Transmit
469 * Data Register in a single access.
470 * However, the first data has to be written into the lowest 16 bits and
471 * the second data into the highest 16 bits of the Transmit
472 * Data Register. For 8bit data (the most frequent case), it would
473 * require to rework tx_buf so each data would actualy fit 16 bits.
474 * So we'd rather write only one data at the time. Hence the transmit
475 * path works the same whether FIFOs are available (and enabled) or not.
476 */
477 slave_config->direction = DMA_MEM_TO_DEV;
478 if (dmaengine_slave_config(master->dma_tx, slave_config)) {
479 dev_err(&as->pdev->dev,
480 "failed to configure tx dma channel\n");
481 err = -EINVAL;
482 }
483
484 /*
485 * This driver configures the spi controller for master mode (MSTR bit
486 * set to '1' in the Mode Register).
487 * So according to the datasheet, when FIFOs are available (and
488 * enabled), the Receive FIFO operates in Single Data Mode.
489 * So the receive path works the same whether FIFOs are available (and
490 * enabled) or not.
491 */
492 slave_config->direction = DMA_DEV_TO_MEM;
493 if (dmaengine_slave_config(master->dma_rx, slave_config)) {
494 dev_err(&as->pdev->dev,
495 "failed to configure rx dma channel\n");
496 err = -EINVAL;
497 }
498
499 return err;
500 }
501
atmel_spi_configure_dma(struct spi_master * master,struct atmel_spi * as)502 static int atmel_spi_configure_dma(struct spi_master *master,
503 struct atmel_spi *as)
504 {
505 struct dma_slave_config slave_config;
506 struct device *dev = &as->pdev->dev;
507 int err;
508
509 master->dma_tx = dma_request_chan(dev, "tx");
510 if (IS_ERR(master->dma_tx)) {
511 err = PTR_ERR(master->dma_tx);
512 dev_dbg(dev, "No TX DMA channel, DMA is disabled\n");
513 goto error_clear;
514 }
515
516 master->dma_rx = dma_request_chan(dev, "rx");
517 if (IS_ERR(master->dma_rx)) {
518 err = PTR_ERR(master->dma_rx);
519 /*
520 * No reason to check EPROBE_DEFER here since we have already
521 * requested tx channel.
522 */
523 dev_dbg(dev, "No RX DMA channel, DMA is disabled\n");
524 goto error;
525 }
526
527 err = atmel_spi_dma_slave_config(as, &slave_config, 8);
528 if (err)
529 goto error;
530
531 dev_info(&as->pdev->dev,
532 "Using %s (tx) and %s (rx) for DMA transfers\n",
533 dma_chan_name(master->dma_tx),
534 dma_chan_name(master->dma_rx));
535
536 return 0;
537 error:
538 if (!IS_ERR(master->dma_rx))
539 dma_release_channel(master->dma_rx);
540 if (!IS_ERR(master->dma_tx))
541 dma_release_channel(master->dma_tx);
542 error_clear:
543 master->dma_tx = master->dma_rx = NULL;
544 return err;
545 }
546
atmel_spi_stop_dma(struct spi_master * master)547 static void atmel_spi_stop_dma(struct spi_master *master)
548 {
549 if (master->dma_rx)
550 dmaengine_terminate_all(master->dma_rx);
551 if (master->dma_tx)
552 dmaengine_terminate_all(master->dma_tx);
553 }
554
atmel_spi_release_dma(struct spi_master * master)555 static void atmel_spi_release_dma(struct spi_master *master)
556 {
557 if (master->dma_rx) {
558 dma_release_channel(master->dma_rx);
559 master->dma_rx = NULL;
560 }
561 if (master->dma_tx) {
562 dma_release_channel(master->dma_tx);
563 master->dma_tx = NULL;
564 }
565 }
566
567 /* This function is called by the DMA driver from tasklet context */
dma_callback(void * data)568 static void dma_callback(void *data)
569 {
570 struct spi_master *master = data;
571 struct atmel_spi *as = spi_master_get_devdata(master);
572
573 if (is_vmalloc_addr(as->current_transfer->rx_buf) &&
574 IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
575 memcpy(as->current_transfer->rx_buf, as->addr_rx_bbuf,
576 as->current_transfer->len);
577 }
578 complete(&as->xfer_completion);
579 }
580
581 /*
582 * Next transfer using PIO without FIFO.
583 */
atmel_spi_next_xfer_single(struct spi_master * master,struct spi_transfer * xfer)584 static void atmel_spi_next_xfer_single(struct spi_master *master,
585 struct spi_transfer *xfer)
586 {
587 struct atmel_spi *as = spi_master_get_devdata(master);
588 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
589
590 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
591
592 /* Make sure data is not remaining in RDR */
593 spi_readl(as, RDR);
594 while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
595 spi_readl(as, RDR);
596 cpu_relax();
597 }
598
599 if (xfer->bits_per_word > 8)
600 spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos));
601 else
602 spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
603
604 dev_dbg(master->dev.parent,
605 " start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
606 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
607 xfer->bits_per_word);
608
609 /* Enable relevant interrupts */
610 spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
611 }
612
613 /*
614 * Next transfer using PIO with FIFO.
615 */
atmel_spi_next_xfer_fifo(struct spi_master * master,struct spi_transfer * xfer)616 static void atmel_spi_next_xfer_fifo(struct spi_master *master,
617 struct spi_transfer *xfer)
618 {
619 struct atmel_spi *as = spi_master_get_devdata(master);
620 u32 current_remaining_data, num_data;
621 u32 offset = xfer->len - as->current_remaining_bytes;
622 const u16 *words = (const u16 *)((u8 *)xfer->tx_buf + offset);
623 const u8 *bytes = (const u8 *)((u8 *)xfer->tx_buf + offset);
624 u16 td0, td1;
625 u32 fifomr;
626
627 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_fifo\n");
628
629 /* Compute the number of data to transfer in the current iteration */
630 current_remaining_data = ((xfer->bits_per_word > 8) ?
631 ((u32)as->current_remaining_bytes >> 1) :
632 (u32)as->current_remaining_bytes);
633 num_data = min(current_remaining_data, as->fifo_size);
634
635 /* Flush RX and TX FIFOs */
636 spi_writel(as, CR, SPI_BIT(RXFCLR) | SPI_BIT(TXFCLR));
637 while (spi_readl(as, FLR))
638 cpu_relax();
639
640 /* Set RX FIFO Threshold to the number of data to transfer */
641 fifomr = spi_readl(as, FMR);
642 spi_writel(as, FMR, SPI_BFINS(RXFTHRES, num_data, fifomr));
643
644 /* Clear FIFO flags in the Status Register, especially RXFTHF */
645 (void)spi_readl(as, SR);
646
647 /* Fill TX FIFO */
648 while (num_data >= 2) {
649 if (xfer->bits_per_word > 8) {
650 td0 = *words++;
651 td1 = *words++;
652 } else {
653 td0 = *bytes++;
654 td1 = *bytes++;
655 }
656
657 spi_writel(as, TDR, (td1 << 16) | td0);
658 num_data -= 2;
659 }
660
661 if (num_data) {
662 if (xfer->bits_per_word > 8)
663 td0 = *words++;
664 else
665 td0 = *bytes++;
666
667 spi_writew(as, TDR, td0);
668 num_data--;
669 }
670
671 dev_dbg(master->dev.parent,
672 " start fifo xfer %p: len %u tx %p rx %p bitpw %d\n",
673 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
674 xfer->bits_per_word);
675
676 /*
677 * Enable RX FIFO Threshold Flag interrupt to be notified about
678 * transfer completion.
679 */
680 spi_writel(as, IER, SPI_BIT(RXFTHF) | SPI_BIT(OVRES));
681 }
682
683 /*
684 * Next transfer using PIO.
685 */
atmel_spi_next_xfer_pio(struct spi_master * master,struct spi_transfer * xfer)686 static void atmel_spi_next_xfer_pio(struct spi_master *master,
687 struct spi_transfer *xfer)
688 {
689 struct atmel_spi *as = spi_master_get_devdata(master);
690
691 if (as->fifo_size)
692 atmel_spi_next_xfer_fifo(master, xfer);
693 else
694 atmel_spi_next_xfer_single(master, xfer);
695 }
696
697 /*
698 * Submit next transfer for DMA.
699 */
atmel_spi_next_xfer_dma_submit(struct spi_master * master,struct spi_transfer * xfer,u32 * plen)700 static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
701 struct spi_transfer *xfer,
702 u32 *plen)
703 __must_hold(&as->lock)
704 {
705 struct atmel_spi *as = spi_master_get_devdata(master);
706 struct dma_chan *rxchan = master->dma_rx;
707 struct dma_chan *txchan = master->dma_tx;
708 struct dma_async_tx_descriptor *rxdesc;
709 struct dma_async_tx_descriptor *txdesc;
710 struct dma_slave_config slave_config;
711 dma_cookie_t cookie;
712
713 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
714
715 /* Check that the channels are available */
716 if (!rxchan || !txchan)
717 return -ENODEV;
718
719 /* release lock for DMA operations */
720 atmel_spi_unlock(as);
721
722 *plen = xfer->len;
723
724 if (atmel_spi_dma_slave_config(as, &slave_config,
725 xfer->bits_per_word))
726 goto err_exit;
727
728 /* Send both scatterlists */
729 if (atmel_spi_is_vmalloc_xfer(xfer) &&
730 IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
731 rxdesc = dmaengine_prep_slave_single(rxchan,
732 as->dma_addr_rx_bbuf,
733 xfer->len,
734 DMA_DEV_TO_MEM,
735 DMA_PREP_INTERRUPT |
736 DMA_CTRL_ACK);
737 } else {
738 rxdesc = dmaengine_prep_slave_sg(rxchan,
739 xfer->rx_sg.sgl,
740 xfer->rx_sg.nents,
741 DMA_DEV_TO_MEM,
742 DMA_PREP_INTERRUPT |
743 DMA_CTRL_ACK);
744 }
745 if (!rxdesc)
746 goto err_dma;
747
748 if (atmel_spi_is_vmalloc_xfer(xfer) &&
749 IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
750 memcpy(as->addr_tx_bbuf, xfer->tx_buf, xfer->len);
751 txdesc = dmaengine_prep_slave_single(txchan,
752 as->dma_addr_tx_bbuf,
753 xfer->len, DMA_MEM_TO_DEV,
754 DMA_PREP_INTERRUPT |
755 DMA_CTRL_ACK);
756 } else {
757 txdesc = dmaengine_prep_slave_sg(txchan,
758 xfer->tx_sg.sgl,
759 xfer->tx_sg.nents,
760 DMA_MEM_TO_DEV,
761 DMA_PREP_INTERRUPT |
762 DMA_CTRL_ACK);
763 }
764 if (!txdesc)
765 goto err_dma;
766
767 dev_dbg(master->dev.parent,
768 " start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
769 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma,
770 xfer->rx_buf, (unsigned long long)xfer->rx_dma);
771
772 /* Enable relevant interrupts */
773 spi_writel(as, IER, SPI_BIT(OVRES));
774
775 /* Put the callback on the RX transfer only, that should finish last */
776 rxdesc->callback = dma_callback;
777 rxdesc->callback_param = master;
778
779 /* Submit and fire RX and TX with TX last so we're ready to read! */
780 cookie = rxdesc->tx_submit(rxdesc);
781 if (dma_submit_error(cookie))
782 goto err_dma;
783 cookie = txdesc->tx_submit(txdesc);
784 if (dma_submit_error(cookie))
785 goto err_dma;
786 rxchan->device->device_issue_pending(rxchan);
787 txchan->device->device_issue_pending(txchan);
788
789 /* take back lock */
790 atmel_spi_lock(as);
791 return 0;
792
793 err_dma:
794 spi_writel(as, IDR, SPI_BIT(OVRES));
795 atmel_spi_stop_dma(master);
796 err_exit:
797 atmel_spi_lock(as);
798 return -ENOMEM;
799 }
800
atmel_spi_next_xfer_data(struct spi_master * master,struct spi_transfer * xfer,dma_addr_t * tx_dma,dma_addr_t * rx_dma,u32 * plen)801 static void atmel_spi_next_xfer_data(struct spi_master *master,
802 struct spi_transfer *xfer,
803 dma_addr_t *tx_dma,
804 dma_addr_t *rx_dma,
805 u32 *plen)
806 {
807 *rx_dma = xfer->rx_dma + xfer->len - *plen;
808 *tx_dma = xfer->tx_dma + xfer->len - *plen;
809 if (*plen > master->max_dma_len)
810 *plen = master->max_dma_len;
811 }
812
atmel_spi_set_xfer_speed(struct atmel_spi * as,struct spi_device * spi,struct spi_transfer * xfer)813 static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
814 struct spi_device *spi,
815 struct spi_transfer *xfer)
816 {
817 u32 scbr, csr;
818 unsigned long bus_hz;
819 int chip_select;
820
821 if (spi->cs_gpiod)
822 chip_select = as->native_cs_for_gpio;
823 else
824 chip_select = spi->chip_select;
825
826 /* v1 chips start out at half the peripheral bus speed. */
827 bus_hz = as->spi_clk;
828 if (!atmel_spi_is_v2(as))
829 bus_hz /= 2;
830
831 /*
832 * Calculate the lowest divider that satisfies the
833 * constraint, assuming div32/fdiv/mbz == 0.
834 */
835 scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz);
836
837 /*
838 * If the resulting divider doesn't fit into the
839 * register bitfield, we can't satisfy the constraint.
840 */
841 if (scbr >= (1 << SPI_SCBR_SIZE)) {
842 dev_err(&spi->dev,
843 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
844 xfer->speed_hz, scbr, bus_hz/255);
845 return -EINVAL;
846 }
847 if (scbr == 0) {
848 dev_err(&spi->dev,
849 "setup: %d Hz too high, scbr %u; max %ld Hz\n",
850 xfer->speed_hz, scbr, bus_hz);
851 return -EINVAL;
852 }
853 csr = spi_readl(as, CSR0 + 4 * chip_select);
854 csr = SPI_BFINS(SCBR, scbr, csr);
855 spi_writel(as, CSR0 + 4 * chip_select, csr);
856 xfer->effective_speed_hz = bus_hz / scbr;
857
858 return 0;
859 }
860
861 /*
862 * Submit next transfer for PDC.
863 * lock is held, spi irq is blocked
864 */
atmel_spi_pdc_next_xfer(struct spi_master * master,struct spi_message * msg,struct spi_transfer * xfer)865 static void atmel_spi_pdc_next_xfer(struct spi_master *master,
866 struct spi_message *msg,
867 struct spi_transfer *xfer)
868 {
869 struct atmel_spi *as = spi_master_get_devdata(master);
870 u32 len;
871 dma_addr_t tx_dma, rx_dma;
872
873 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
874
875 len = as->current_remaining_bytes;
876 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
877 as->current_remaining_bytes -= len;
878
879 spi_writel(as, RPR, rx_dma);
880 spi_writel(as, TPR, tx_dma);
881
882 if (msg->spi->bits_per_word > 8)
883 len >>= 1;
884 spi_writel(as, RCR, len);
885 spi_writel(as, TCR, len);
886
887 dev_dbg(&msg->spi->dev,
888 " start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
889 xfer, xfer->len, xfer->tx_buf,
890 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
891 (unsigned long long)xfer->rx_dma);
892
893 if (as->current_remaining_bytes) {
894 len = as->current_remaining_bytes;
895 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
896 as->current_remaining_bytes -= len;
897
898 spi_writel(as, RNPR, rx_dma);
899 spi_writel(as, TNPR, tx_dma);
900
901 if (msg->spi->bits_per_word > 8)
902 len >>= 1;
903 spi_writel(as, RNCR, len);
904 spi_writel(as, TNCR, len);
905
906 dev_dbg(&msg->spi->dev,
907 " next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
908 xfer, xfer->len, xfer->tx_buf,
909 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
910 (unsigned long long)xfer->rx_dma);
911 }
912
913 /* REVISIT: We're waiting for RXBUFF before we start the next
914 * transfer because we need to handle some difficult timing
915 * issues otherwise. If we wait for TXBUFE in one transfer and
916 * then starts waiting for RXBUFF in the next, it's difficult
917 * to tell the difference between the RXBUFF interrupt we're
918 * actually waiting for and the RXBUFF interrupt of the
919 * previous transfer.
920 *
921 * It should be doable, though. Just not now...
922 */
923 spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES));
924 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
925 }
926
927 /*
928 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
929 * - The buffer is either valid for CPU access, else NULL
930 * - If the buffer is valid, so is its DMA address
931 *
932 * This driver manages the dma address unless message->is_dma_mapped.
933 */
934 static int
atmel_spi_dma_map_xfer(struct atmel_spi * as,struct spi_transfer * xfer)935 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
936 {
937 struct device *dev = &as->pdev->dev;
938
939 xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
940 if (xfer->tx_buf) {
941 /* tx_buf is a const void* where we need a void * for the dma
942 * mapping */
943 void *nonconst_tx = (void *)xfer->tx_buf;
944
945 xfer->tx_dma = dma_map_single(dev,
946 nonconst_tx, xfer->len,
947 DMA_TO_DEVICE);
948 if (dma_mapping_error(dev, xfer->tx_dma))
949 return -ENOMEM;
950 }
951 if (xfer->rx_buf) {
952 xfer->rx_dma = dma_map_single(dev,
953 xfer->rx_buf, xfer->len,
954 DMA_FROM_DEVICE);
955 if (dma_mapping_error(dev, xfer->rx_dma)) {
956 if (xfer->tx_buf)
957 dma_unmap_single(dev,
958 xfer->tx_dma, xfer->len,
959 DMA_TO_DEVICE);
960 return -ENOMEM;
961 }
962 }
963 return 0;
964 }
965
atmel_spi_dma_unmap_xfer(struct spi_master * master,struct spi_transfer * xfer)966 static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
967 struct spi_transfer *xfer)
968 {
969 if (xfer->tx_dma != INVALID_DMA_ADDRESS)
970 dma_unmap_single(master->dev.parent, xfer->tx_dma,
971 xfer->len, DMA_TO_DEVICE);
972 if (xfer->rx_dma != INVALID_DMA_ADDRESS)
973 dma_unmap_single(master->dev.parent, xfer->rx_dma,
974 xfer->len, DMA_FROM_DEVICE);
975 }
976
atmel_spi_disable_pdc_transfer(struct atmel_spi * as)977 static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
978 {
979 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
980 }
981
982 static void
atmel_spi_pump_single_data(struct atmel_spi * as,struct spi_transfer * xfer)983 atmel_spi_pump_single_data(struct atmel_spi *as, struct spi_transfer *xfer)
984 {
985 u8 *rxp;
986 u16 *rxp16;
987 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
988
989 if (xfer->bits_per_word > 8) {
990 rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
991 *rxp16 = spi_readl(as, RDR);
992 } else {
993 rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
994 *rxp = spi_readl(as, RDR);
995 }
996 if (xfer->bits_per_word > 8) {
997 if (as->current_remaining_bytes > 2)
998 as->current_remaining_bytes -= 2;
999 else
1000 as->current_remaining_bytes = 0;
1001 } else {
1002 as->current_remaining_bytes--;
1003 }
1004 }
1005
1006 static void
atmel_spi_pump_fifo_data(struct atmel_spi * as,struct spi_transfer * xfer)1007 atmel_spi_pump_fifo_data(struct atmel_spi *as, struct spi_transfer *xfer)
1008 {
1009 u32 fifolr = spi_readl(as, FLR);
1010 u32 num_bytes, num_data = SPI_BFEXT(RXFL, fifolr);
1011 u32 offset = xfer->len - as->current_remaining_bytes;
1012 u16 *words = (u16 *)((u8 *)xfer->rx_buf + offset);
1013 u8 *bytes = (u8 *)((u8 *)xfer->rx_buf + offset);
1014 u16 rd; /* RD field is the lowest 16 bits of RDR */
1015
1016 /* Update the number of remaining bytes to transfer */
1017 num_bytes = ((xfer->bits_per_word > 8) ?
1018 (num_data << 1) :
1019 num_data);
1020
1021 if (as->current_remaining_bytes > num_bytes)
1022 as->current_remaining_bytes -= num_bytes;
1023 else
1024 as->current_remaining_bytes = 0;
1025
1026 /* Handle odd number of bytes when data are more than 8bit width */
1027 if (xfer->bits_per_word > 8)
1028 as->current_remaining_bytes &= ~0x1;
1029
1030 /* Read data */
1031 while (num_data) {
1032 rd = spi_readl(as, RDR);
1033 if (xfer->bits_per_word > 8)
1034 *words++ = rd;
1035 else
1036 *bytes++ = rd;
1037 num_data--;
1038 }
1039 }
1040
1041 /* Called from IRQ
1042 *
1043 * Must update "current_remaining_bytes" to keep track of data
1044 * to transfer.
1045 */
1046 static void
atmel_spi_pump_pio_data(struct atmel_spi * as,struct spi_transfer * xfer)1047 atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
1048 {
1049 if (as->fifo_size)
1050 atmel_spi_pump_fifo_data(as, xfer);
1051 else
1052 atmel_spi_pump_single_data(as, xfer);
1053 }
1054
1055 /* Interrupt
1056 *
1057 * No need for locking in this Interrupt handler: done_status is the
1058 * only information modified.
1059 */
1060 static irqreturn_t
atmel_spi_pio_interrupt(int irq,void * dev_id)1061 atmel_spi_pio_interrupt(int irq, void *dev_id)
1062 {
1063 struct spi_master *master = dev_id;
1064 struct atmel_spi *as = spi_master_get_devdata(master);
1065 u32 status, pending, imr;
1066 struct spi_transfer *xfer;
1067 int ret = IRQ_NONE;
1068
1069 imr = spi_readl(as, IMR);
1070 status = spi_readl(as, SR);
1071 pending = status & imr;
1072
1073 if (pending & SPI_BIT(OVRES)) {
1074 ret = IRQ_HANDLED;
1075 spi_writel(as, IDR, SPI_BIT(OVRES));
1076 dev_warn(master->dev.parent, "overrun\n");
1077
1078 /*
1079 * When we get an overrun, we disregard the current
1080 * transfer. Data will not be copied back from any
1081 * bounce buffer and msg->actual_len will not be
1082 * updated with the last xfer.
1083 *
1084 * We will also not process any remaning transfers in
1085 * the message.
1086 */
1087 as->done_status = -EIO;
1088 smp_wmb();
1089
1090 /* Clear any overrun happening while cleaning up */
1091 spi_readl(as, SR);
1092
1093 complete(&as->xfer_completion);
1094
1095 } else if (pending & (SPI_BIT(RDRF) | SPI_BIT(RXFTHF))) {
1096 atmel_spi_lock(as);
1097
1098 if (as->current_remaining_bytes) {
1099 ret = IRQ_HANDLED;
1100 xfer = as->current_transfer;
1101 atmel_spi_pump_pio_data(as, xfer);
1102 if (!as->current_remaining_bytes)
1103 spi_writel(as, IDR, pending);
1104
1105 complete(&as->xfer_completion);
1106 }
1107
1108 atmel_spi_unlock(as);
1109 } else {
1110 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
1111 ret = IRQ_HANDLED;
1112 spi_writel(as, IDR, pending);
1113 }
1114
1115 return ret;
1116 }
1117
1118 static irqreturn_t
atmel_spi_pdc_interrupt(int irq,void * dev_id)1119 atmel_spi_pdc_interrupt(int irq, void *dev_id)
1120 {
1121 struct spi_master *master = dev_id;
1122 struct atmel_spi *as = spi_master_get_devdata(master);
1123 u32 status, pending, imr;
1124 int ret = IRQ_NONE;
1125
1126 imr = spi_readl(as, IMR);
1127 status = spi_readl(as, SR);
1128 pending = status & imr;
1129
1130 if (pending & SPI_BIT(OVRES)) {
1131
1132 ret = IRQ_HANDLED;
1133
1134 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
1135 | SPI_BIT(OVRES)));
1136
1137 /* Clear any overrun happening while cleaning up */
1138 spi_readl(as, SR);
1139
1140 as->done_status = -EIO;
1141
1142 complete(&as->xfer_completion);
1143
1144 } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
1145 ret = IRQ_HANDLED;
1146
1147 spi_writel(as, IDR, pending);
1148
1149 complete(&as->xfer_completion);
1150 }
1151
1152 return ret;
1153 }
1154
atmel_word_delay_csr(struct spi_device * spi,struct atmel_spi * as)1155 static int atmel_word_delay_csr(struct spi_device *spi, struct atmel_spi *as)
1156 {
1157 struct spi_delay *delay = &spi->word_delay;
1158 u32 value = delay->value;
1159
1160 switch (delay->unit) {
1161 case SPI_DELAY_UNIT_NSECS:
1162 value /= 1000;
1163 break;
1164 case SPI_DELAY_UNIT_USECS:
1165 break;
1166 default:
1167 return -EINVAL;
1168 }
1169
1170 return (as->spi_clk / 1000000 * value) >> 5;
1171 }
1172
initialize_native_cs_for_gpio(struct atmel_spi * as)1173 static void initialize_native_cs_for_gpio(struct atmel_spi *as)
1174 {
1175 int i;
1176 struct spi_master *master = platform_get_drvdata(as->pdev);
1177
1178 if (!as->native_cs_free)
1179 return; /* already initialized */
1180
1181 if (!master->cs_gpiods)
1182 return; /* No CS GPIO */
1183
1184 /*
1185 * On the first version of the controller (AT91RM9200), CS0
1186 * can't be used associated with GPIO
1187 */
1188 if (atmel_spi_is_v2(as))
1189 i = 0;
1190 else
1191 i = 1;
1192
1193 for (; i < 4; i++)
1194 if (master->cs_gpiods[i])
1195 as->native_cs_free |= BIT(i);
1196
1197 if (as->native_cs_free)
1198 as->native_cs_for_gpio = ffs(as->native_cs_free);
1199 }
1200
atmel_spi_setup(struct spi_device * spi)1201 static int atmel_spi_setup(struct spi_device *spi)
1202 {
1203 struct atmel_spi *as;
1204 struct atmel_spi_device *asd;
1205 u32 csr;
1206 unsigned int bits = spi->bits_per_word;
1207 int chip_select;
1208 int word_delay_csr;
1209
1210 as = spi_master_get_devdata(spi->master);
1211
1212 /* see notes above re chipselect */
1213 if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH)) {
1214 dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
1215 return -EINVAL;
1216 }
1217
1218 /* Setup() is called during spi_register_controller(aka
1219 * spi_register_master) but after all membmers of the cs_gpiod
1220 * array have been filled, so we can looked for which native
1221 * CS will be free for using with GPIO
1222 */
1223 initialize_native_cs_for_gpio(as);
1224
1225 if (spi->cs_gpiod && as->native_cs_free) {
1226 dev_err(&spi->dev,
1227 "No native CS available to support this GPIO CS\n");
1228 return -EBUSY;
1229 }
1230
1231 if (spi->cs_gpiod)
1232 chip_select = as->native_cs_for_gpio;
1233 else
1234 chip_select = spi->chip_select;
1235
1236 csr = SPI_BF(BITS, bits - 8);
1237 if (spi->mode & SPI_CPOL)
1238 csr |= SPI_BIT(CPOL);
1239 if (!(spi->mode & SPI_CPHA))
1240 csr |= SPI_BIT(NCPHA);
1241
1242 if (!spi->cs_gpiod)
1243 csr |= SPI_BIT(CSAAT);
1244 csr |= SPI_BF(DLYBS, 0);
1245
1246 word_delay_csr = atmel_word_delay_csr(spi, as);
1247 if (word_delay_csr < 0)
1248 return word_delay_csr;
1249
1250 /* DLYBCT adds delays between words. This is useful for slow devices
1251 * that need a bit of time to setup the next transfer.
1252 */
1253 csr |= SPI_BF(DLYBCT, word_delay_csr);
1254
1255 asd = spi->controller_state;
1256 if (!asd) {
1257 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
1258 if (!asd)
1259 return -ENOMEM;
1260
1261 spi->controller_state = asd;
1262 }
1263
1264 asd->csr = csr;
1265
1266 dev_dbg(&spi->dev,
1267 "setup: bpw %u mode 0x%x -> csr%d %08x\n",
1268 bits, spi->mode, spi->chip_select, csr);
1269
1270 if (!atmel_spi_is_v2(as))
1271 spi_writel(as, CSR0 + 4 * chip_select, csr);
1272
1273 return 0;
1274 }
1275
atmel_spi_one_transfer(struct spi_master * master,struct spi_message * msg,struct spi_transfer * xfer)1276 static int atmel_spi_one_transfer(struct spi_master *master,
1277 struct spi_message *msg,
1278 struct spi_transfer *xfer)
1279 {
1280 struct atmel_spi *as;
1281 struct spi_device *spi = msg->spi;
1282 u8 bits;
1283 u32 len;
1284 struct atmel_spi_device *asd;
1285 int timeout;
1286 int ret;
1287 unsigned long dma_timeout;
1288
1289 as = spi_master_get_devdata(master);
1290
1291 if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
1292 dev_dbg(&spi->dev, "missing rx or tx buf\n");
1293 return -EINVAL;
1294 }
1295
1296 asd = spi->controller_state;
1297 bits = (asd->csr >> 4) & 0xf;
1298 if (bits != xfer->bits_per_word - 8) {
1299 dev_dbg(&spi->dev,
1300 "you can't yet change bits_per_word in transfers\n");
1301 return -ENOPROTOOPT;
1302 }
1303
1304 /*
1305 * DMA map early, for performance (empties dcache ASAP) and
1306 * better fault reporting.
1307 */
1308 if ((!msg->is_dma_mapped)
1309 && as->use_pdc) {
1310 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
1311 return -ENOMEM;
1312 }
1313
1314 atmel_spi_set_xfer_speed(as, msg->spi, xfer);
1315
1316 as->done_status = 0;
1317 as->current_transfer = xfer;
1318 as->current_remaining_bytes = xfer->len;
1319 while (as->current_remaining_bytes) {
1320 reinit_completion(&as->xfer_completion);
1321
1322 if (as->use_pdc) {
1323 atmel_spi_pdc_next_xfer(master, msg, xfer);
1324 } else if (atmel_spi_use_dma(as, xfer)) {
1325 len = as->current_remaining_bytes;
1326 ret = atmel_spi_next_xfer_dma_submit(master,
1327 xfer, &len);
1328 if (ret) {
1329 dev_err(&spi->dev,
1330 "unable to use DMA, fallback to PIO\n");
1331 atmel_spi_next_xfer_pio(master, xfer);
1332 } else {
1333 as->current_remaining_bytes -= len;
1334 if (as->current_remaining_bytes < 0)
1335 as->current_remaining_bytes = 0;
1336 }
1337 } else {
1338 atmel_spi_next_xfer_pio(master, xfer);
1339 }
1340
1341 /* interrupts are disabled, so free the lock for schedule */
1342 atmel_spi_unlock(as);
1343 dma_timeout = wait_for_completion_timeout(&as->xfer_completion,
1344 SPI_DMA_TIMEOUT);
1345 atmel_spi_lock(as);
1346 if (WARN_ON(dma_timeout == 0)) {
1347 dev_err(&spi->dev, "spi transfer timeout\n");
1348 as->done_status = -EIO;
1349 }
1350
1351 if (as->done_status)
1352 break;
1353 }
1354
1355 if (as->done_status) {
1356 if (as->use_pdc) {
1357 dev_warn(master->dev.parent,
1358 "overrun (%u/%u remaining)\n",
1359 spi_readl(as, TCR), spi_readl(as, RCR));
1360
1361 /*
1362 * Clean up DMA registers and make sure the data
1363 * registers are empty.
1364 */
1365 spi_writel(as, RNCR, 0);
1366 spi_writel(as, TNCR, 0);
1367 spi_writel(as, RCR, 0);
1368 spi_writel(as, TCR, 0);
1369 for (timeout = 1000; timeout; timeout--)
1370 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1371 break;
1372 if (!timeout)
1373 dev_warn(master->dev.parent,
1374 "timeout waiting for TXEMPTY");
1375 while (spi_readl(as, SR) & SPI_BIT(RDRF))
1376 spi_readl(as, RDR);
1377
1378 /* Clear any overrun happening while cleaning up */
1379 spi_readl(as, SR);
1380
1381 } else if (atmel_spi_use_dma(as, xfer)) {
1382 atmel_spi_stop_dma(master);
1383 }
1384
1385 if (!msg->is_dma_mapped
1386 && as->use_pdc)
1387 atmel_spi_dma_unmap_xfer(master, xfer);
1388
1389 return 0;
1390
1391 } else {
1392 /* only update length if no error */
1393 msg->actual_length += xfer->len;
1394 }
1395
1396 if (!msg->is_dma_mapped
1397 && as->use_pdc)
1398 atmel_spi_dma_unmap_xfer(master, xfer);
1399
1400 spi_transfer_delay_exec(xfer);
1401
1402 if (xfer->cs_change) {
1403 if (list_is_last(&xfer->transfer_list,
1404 &msg->transfers)) {
1405 as->keep_cs = true;
1406 } else {
1407 cs_deactivate(as, msg->spi);
1408 udelay(10);
1409 cs_activate(as, msg->spi);
1410 }
1411 }
1412
1413 return 0;
1414 }
1415
atmel_spi_transfer_one_message(struct spi_master * master,struct spi_message * msg)1416 static int atmel_spi_transfer_one_message(struct spi_master *master,
1417 struct spi_message *msg)
1418 {
1419 struct atmel_spi *as;
1420 struct spi_transfer *xfer;
1421 struct spi_device *spi = msg->spi;
1422 int ret = 0;
1423
1424 as = spi_master_get_devdata(master);
1425
1426 dev_dbg(&spi->dev, "new message %p submitted for %s\n",
1427 msg, dev_name(&spi->dev));
1428
1429 atmel_spi_lock(as);
1430 cs_activate(as, spi);
1431
1432 as->keep_cs = false;
1433
1434 msg->status = 0;
1435 msg->actual_length = 0;
1436
1437 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1438 trace_spi_transfer_start(msg, xfer);
1439
1440 ret = atmel_spi_one_transfer(master, msg, xfer);
1441 if (ret)
1442 goto msg_done;
1443
1444 trace_spi_transfer_stop(msg, xfer);
1445 }
1446
1447 if (as->use_pdc)
1448 atmel_spi_disable_pdc_transfer(as);
1449
1450 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1451 dev_dbg(&spi->dev,
1452 " xfer %p: len %u tx %p/%pad rx %p/%pad\n",
1453 xfer, xfer->len,
1454 xfer->tx_buf, &xfer->tx_dma,
1455 xfer->rx_buf, &xfer->rx_dma);
1456 }
1457
1458 msg_done:
1459 if (!as->keep_cs)
1460 cs_deactivate(as, msg->spi);
1461
1462 atmel_spi_unlock(as);
1463
1464 msg->status = as->done_status;
1465 spi_finalize_current_message(spi->master);
1466
1467 return ret;
1468 }
1469
atmel_spi_cleanup(struct spi_device * spi)1470 static void atmel_spi_cleanup(struct spi_device *spi)
1471 {
1472 struct atmel_spi_device *asd = spi->controller_state;
1473
1474 if (!asd)
1475 return;
1476
1477 spi->controller_state = NULL;
1478 kfree(asd);
1479 }
1480
atmel_get_version(struct atmel_spi * as)1481 static inline unsigned int atmel_get_version(struct atmel_spi *as)
1482 {
1483 return spi_readl(as, VERSION) & 0x00000fff;
1484 }
1485
atmel_get_caps(struct atmel_spi * as)1486 static void atmel_get_caps(struct atmel_spi *as)
1487 {
1488 unsigned int version;
1489
1490 version = atmel_get_version(as);
1491
1492 as->caps.is_spi2 = version > 0x121;
1493 as->caps.has_wdrbt = version >= 0x210;
1494 as->caps.has_dma_support = version >= 0x212;
1495 as->caps.has_pdc_support = version < 0x212;
1496 }
1497
atmel_spi_init(struct atmel_spi * as)1498 static void atmel_spi_init(struct atmel_spi *as)
1499 {
1500 spi_writel(as, CR, SPI_BIT(SWRST));
1501 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1502
1503 /* It is recommended to enable FIFOs first thing after reset */
1504 if (as->fifo_size)
1505 spi_writel(as, CR, SPI_BIT(FIFOEN));
1506
1507 if (as->caps.has_wdrbt) {
1508 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
1509 | SPI_BIT(MSTR));
1510 } else {
1511 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
1512 }
1513
1514 if (as->use_pdc)
1515 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1516 spi_writel(as, CR, SPI_BIT(SPIEN));
1517 }
1518
atmel_spi_probe(struct platform_device * pdev)1519 static int atmel_spi_probe(struct platform_device *pdev)
1520 {
1521 struct resource *regs;
1522 int irq;
1523 struct clk *clk;
1524 int ret;
1525 struct spi_master *master;
1526 struct atmel_spi *as;
1527
1528 /* Select default pin state */
1529 pinctrl_pm_select_default_state(&pdev->dev);
1530
1531 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1532 if (!regs)
1533 return -ENXIO;
1534
1535 irq = platform_get_irq(pdev, 0);
1536 if (irq < 0)
1537 return irq;
1538
1539 clk = devm_clk_get(&pdev->dev, "spi_clk");
1540 if (IS_ERR(clk))
1541 return PTR_ERR(clk);
1542
1543 /* setup spi core then atmel-specific driver state */
1544 master = spi_alloc_master(&pdev->dev, sizeof(*as));
1545 if (!master)
1546 return -ENOMEM;
1547
1548 /* the spi->mode bits understood by this driver: */
1549 master->use_gpio_descriptors = true;
1550 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1551 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
1552 master->dev.of_node = pdev->dev.of_node;
1553 master->bus_num = pdev->id;
1554 master->num_chipselect = 4;
1555 master->setup = atmel_spi_setup;
1556 master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX);
1557 master->transfer_one_message = atmel_spi_transfer_one_message;
1558 master->cleanup = atmel_spi_cleanup;
1559 master->auto_runtime_pm = true;
1560 master->max_dma_len = SPI_MAX_DMA_XFER;
1561 master->can_dma = atmel_spi_can_dma;
1562 platform_set_drvdata(pdev, master);
1563
1564 as = spi_master_get_devdata(master);
1565
1566 spin_lock_init(&as->lock);
1567
1568 as->pdev = pdev;
1569 as->regs = devm_ioremap_resource(&pdev->dev, regs);
1570 if (IS_ERR(as->regs)) {
1571 ret = PTR_ERR(as->regs);
1572 goto out_unmap_regs;
1573 }
1574 as->phybase = regs->start;
1575 as->irq = irq;
1576 as->clk = clk;
1577
1578 init_completion(&as->xfer_completion);
1579
1580 atmel_get_caps(as);
1581
1582 as->use_dma = false;
1583 as->use_pdc = false;
1584 if (as->caps.has_dma_support) {
1585 ret = atmel_spi_configure_dma(master, as);
1586 if (ret == 0) {
1587 as->use_dma = true;
1588 } else if (ret == -EPROBE_DEFER) {
1589 goto out_unmap_regs;
1590 }
1591 } else if (as->caps.has_pdc_support) {
1592 as->use_pdc = true;
1593 }
1594
1595 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
1596 as->addr_rx_bbuf = dma_alloc_coherent(&pdev->dev,
1597 SPI_MAX_DMA_XFER,
1598 &as->dma_addr_rx_bbuf,
1599 GFP_KERNEL | GFP_DMA);
1600 if (!as->addr_rx_bbuf) {
1601 as->use_dma = false;
1602 } else {
1603 as->addr_tx_bbuf = dma_alloc_coherent(&pdev->dev,
1604 SPI_MAX_DMA_XFER,
1605 &as->dma_addr_tx_bbuf,
1606 GFP_KERNEL | GFP_DMA);
1607 if (!as->addr_tx_bbuf) {
1608 as->use_dma = false;
1609 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
1610 as->addr_rx_bbuf,
1611 as->dma_addr_rx_bbuf);
1612 }
1613 }
1614 if (!as->use_dma)
1615 dev_info(master->dev.parent,
1616 " can not allocate dma coherent memory\n");
1617 }
1618
1619 if (as->caps.has_dma_support && !as->use_dma)
1620 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
1621
1622 if (as->use_pdc) {
1623 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt,
1624 0, dev_name(&pdev->dev), master);
1625 } else {
1626 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt,
1627 0, dev_name(&pdev->dev), master);
1628 }
1629 if (ret)
1630 goto out_unmap_regs;
1631
1632 /* Initialize the hardware */
1633 ret = clk_prepare_enable(clk);
1634 if (ret)
1635 goto out_free_irq;
1636
1637 as->spi_clk = clk_get_rate(clk);
1638
1639 as->fifo_size = 0;
1640 if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size",
1641 &as->fifo_size)) {
1642 dev_info(&pdev->dev, "Using FIFO (%u data)\n", as->fifo_size);
1643 }
1644
1645 atmel_spi_init(as);
1646
1647 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1648 pm_runtime_use_autosuspend(&pdev->dev);
1649 pm_runtime_set_active(&pdev->dev);
1650 pm_runtime_enable(&pdev->dev);
1651
1652 ret = devm_spi_register_master(&pdev->dev, master);
1653 if (ret)
1654 goto out_free_dma;
1655
1656 /* go! */
1657 dev_info(&pdev->dev, "Atmel SPI Controller version 0x%x at 0x%08lx (irq %d)\n",
1658 atmel_get_version(as), (unsigned long)regs->start,
1659 irq);
1660
1661 return 0;
1662
1663 out_free_dma:
1664 pm_runtime_disable(&pdev->dev);
1665 pm_runtime_set_suspended(&pdev->dev);
1666
1667 if (as->use_dma)
1668 atmel_spi_release_dma(master);
1669
1670 spi_writel(as, CR, SPI_BIT(SWRST));
1671 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1672 clk_disable_unprepare(clk);
1673 out_free_irq:
1674 out_unmap_regs:
1675 spi_master_put(master);
1676 return ret;
1677 }
1678
atmel_spi_remove(struct platform_device * pdev)1679 static int atmel_spi_remove(struct platform_device *pdev)
1680 {
1681 struct spi_master *master = platform_get_drvdata(pdev);
1682 struct atmel_spi *as = spi_master_get_devdata(master);
1683
1684 pm_runtime_get_sync(&pdev->dev);
1685
1686 /* reset the hardware and block queue progress */
1687 if (as->use_dma) {
1688 atmel_spi_stop_dma(master);
1689 atmel_spi_release_dma(master);
1690 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
1691 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
1692 as->addr_tx_bbuf,
1693 as->dma_addr_tx_bbuf);
1694 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
1695 as->addr_rx_bbuf,
1696 as->dma_addr_rx_bbuf);
1697 }
1698 }
1699
1700 spin_lock_irq(&as->lock);
1701 spi_writel(as, CR, SPI_BIT(SWRST));
1702 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1703 spi_readl(as, SR);
1704 spin_unlock_irq(&as->lock);
1705
1706 clk_disable_unprepare(as->clk);
1707
1708 pm_runtime_put_noidle(&pdev->dev);
1709 pm_runtime_disable(&pdev->dev);
1710
1711 return 0;
1712 }
1713
1714 #ifdef CONFIG_PM
atmel_spi_runtime_suspend(struct device * dev)1715 static int atmel_spi_runtime_suspend(struct device *dev)
1716 {
1717 struct spi_master *master = dev_get_drvdata(dev);
1718 struct atmel_spi *as = spi_master_get_devdata(master);
1719
1720 clk_disable_unprepare(as->clk);
1721 pinctrl_pm_select_sleep_state(dev);
1722
1723 return 0;
1724 }
1725
atmel_spi_runtime_resume(struct device * dev)1726 static int atmel_spi_runtime_resume(struct device *dev)
1727 {
1728 struct spi_master *master = dev_get_drvdata(dev);
1729 struct atmel_spi *as = spi_master_get_devdata(master);
1730
1731 pinctrl_pm_select_default_state(dev);
1732
1733 return clk_prepare_enable(as->clk);
1734 }
1735
1736 #ifdef CONFIG_PM_SLEEP
atmel_spi_suspend(struct device * dev)1737 static int atmel_spi_suspend(struct device *dev)
1738 {
1739 struct spi_master *master = dev_get_drvdata(dev);
1740 int ret;
1741
1742 /* Stop the queue running */
1743 ret = spi_master_suspend(master);
1744 if (ret)
1745 return ret;
1746
1747 if (!pm_runtime_suspended(dev))
1748 atmel_spi_runtime_suspend(dev);
1749
1750 return 0;
1751 }
1752
atmel_spi_resume(struct device * dev)1753 static int atmel_spi_resume(struct device *dev)
1754 {
1755 struct spi_master *master = dev_get_drvdata(dev);
1756 struct atmel_spi *as = spi_master_get_devdata(master);
1757 int ret;
1758
1759 ret = clk_prepare_enable(as->clk);
1760 if (ret)
1761 return ret;
1762
1763 atmel_spi_init(as);
1764
1765 clk_disable_unprepare(as->clk);
1766
1767 if (!pm_runtime_suspended(dev)) {
1768 ret = atmel_spi_runtime_resume(dev);
1769 if (ret)
1770 return ret;
1771 }
1772
1773 /* Start the queue running */
1774 return spi_master_resume(master);
1775 }
1776 #endif
1777
1778 static const struct dev_pm_ops atmel_spi_pm_ops = {
1779 SET_SYSTEM_SLEEP_PM_OPS(atmel_spi_suspend, atmel_spi_resume)
1780 SET_RUNTIME_PM_OPS(atmel_spi_runtime_suspend,
1781 atmel_spi_runtime_resume, NULL)
1782 };
1783 #define ATMEL_SPI_PM_OPS (&atmel_spi_pm_ops)
1784 #else
1785 #define ATMEL_SPI_PM_OPS NULL
1786 #endif
1787
1788 static const struct of_device_id atmel_spi_dt_ids[] = {
1789 { .compatible = "atmel,at91rm9200-spi" },
1790 { /* sentinel */ }
1791 };
1792
1793 MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
1794
1795 static struct platform_driver atmel_spi_driver = {
1796 .driver = {
1797 .name = "atmel_spi",
1798 .pm = ATMEL_SPI_PM_OPS,
1799 .of_match_table = atmel_spi_dt_ids,
1800 },
1801 .probe = atmel_spi_probe,
1802 .remove = atmel_spi_remove,
1803 };
1804 module_platform_driver(atmel_spi_driver);
1805
1806 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1807 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1808 MODULE_LICENSE("GPL");
1809 MODULE_ALIAS("platform:atmel_spi");
1810