1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // HiSilicon SPI Controller Driver for Kunpeng SoCs
4 //
5 // Copyright (c) 2021 HiSilicon Technologies Co., Ltd.
6 // Author: Jay Fang <f.fangjian@huawei.com>
7 //
8 // This code is based on spi-dw-core.c.
9
10 #include <linux/acpi.h>
11 #include <linux/bitfield.h>
12 #include <linux/delay.h>
13 #include <linux/err.h>
14 #include <linux/interrupt.h>
15 #include <linux/module.h>
16 #include <linux/property.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
19 #include <linux/spi/spi.h>
20
21 /* Register offsets */
22 #define HISI_SPI_CSCR 0x00 /* cs control register */
23 #define HISI_SPI_CR 0x04 /* spi common control register */
24 #define HISI_SPI_ENR 0x08 /* spi enable register */
25 #define HISI_SPI_FIFOC 0x0c /* fifo level control register */
26 #define HISI_SPI_IMR 0x10 /* interrupt mask register */
27 #define HISI_SPI_DIN 0x14 /* data in register */
28 #define HISI_SPI_DOUT 0x18 /* data out register */
29 #define HISI_SPI_SR 0x1c /* status register */
30 #define HISI_SPI_RISR 0x20 /* raw interrupt status register */
31 #define HISI_SPI_ISR 0x24 /* interrupt status register */
32 #define HISI_SPI_ICR 0x28 /* interrupt clear register */
33 #define HISI_SPI_VERSION 0xe0 /* version register */
34
35 /* Bit fields in HISI_SPI_CR */
36 #define CR_LOOP_MASK GENMASK(1, 1)
37 #define CR_CPOL_MASK GENMASK(2, 2)
38 #define CR_CPHA_MASK GENMASK(3, 3)
39 #define CR_DIV_PRE_MASK GENMASK(11, 4)
40 #define CR_DIV_POST_MASK GENMASK(19, 12)
41 #define CR_BPW_MASK GENMASK(24, 20)
42 #define CR_SPD_MODE_MASK GENMASK(25, 25)
43
44 /* Bit fields in HISI_SPI_FIFOC */
45 #define FIFOC_TX_MASK GENMASK(5, 3)
46 #define FIFOC_RX_MASK GENMASK(11, 9)
47
48 /* Bit fields in HISI_SPI_IMR, 4 bits */
49 #define IMR_RXOF BIT(0) /* Receive Overflow */
50 #define IMR_RXTO BIT(1) /* Receive Timeout */
51 #define IMR_RX BIT(2) /* Receive */
52 #define IMR_TX BIT(3) /* Transmit */
53 #define IMR_MASK (IMR_RXOF | IMR_RXTO | IMR_RX | IMR_TX)
54
55 /* Bit fields in HISI_SPI_SR, 5 bits */
56 #define SR_TXE BIT(0) /* Transmit FIFO empty */
57 #define SR_TXNF BIT(1) /* Transmit FIFO not full */
58 #define SR_RXNE BIT(2) /* Receive FIFO not empty */
59 #define SR_RXF BIT(3) /* Receive FIFO full */
60 #define SR_BUSY BIT(4) /* Busy Flag */
61
62 /* Bit fields in HISI_SPI_ISR, 4 bits */
63 #define ISR_RXOF BIT(0) /* Receive Overflow */
64 #define ISR_RXTO BIT(1) /* Receive Timeout */
65 #define ISR_RX BIT(2) /* Receive */
66 #define ISR_TX BIT(3) /* Transmit */
67 #define ISR_MASK (ISR_RXOF | ISR_RXTO | ISR_RX | ISR_TX)
68
69 /* Bit fields in HISI_SPI_ICR, 2 bits */
70 #define ICR_RXOF BIT(0) /* Receive Overflow */
71 #define ICR_RXTO BIT(1) /* Receive Timeout */
72 #define ICR_MASK (ICR_RXOF | ICR_RXTO)
73
74 #define DIV_POST_MAX 0xFF
75 #define DIV_POST_MIN 0x00
76 #define DIV_PRE_MAX 0xFE
77 #define DIV_PRE_MIN 0x02
78 #define CLK_DIV_MAX ((1 + DIV_POST_MAX) * DIV_PRE_MAX)
79 #define CLK_DIV_MIN ((1 + DIV_POST_MIN) * DIV_PRE_MIN)
80
81 #define DEFAULT_NUM_CS 1
82
83 #define HISI_SPI_WAIT_TIMEOUT_MS 10UL
84
85 enum hisi_spi_rx_level_trig {
86 HISI_SPI_RX_1,
87 HISI_SPI_RX_4,
88 HISI_SPI_RX_8,
89 HISI_SPI_RX_16,
90 HISI_SPI_RX_32,
91 HISI_SPI_RX_64,
92 HISI_SPI_RX_128
93 };
94
95 enum hisi_spi_tx_level_trig {
96 HISI_SPI_TX_1_OR_LESS,
97 HISI_SPI_TX_4_OR_LESS,
98 HISI_SPI_TX_8_OR_LESS,
99 HISI_SPI_TX_16_OR_LESS,
100 HISI_SPI_TX_32_OR_LESS,
101 HISI_SPI_TX_64_OR_LESS,
102 HISI_SPI_TX_128_OR_LESS
103 };
104
105 enum hisi_spi_frame_n_bytes {
106 HISI_SPI_N_BYTES_NULL,
107 HISI_SPI_N_BYTES_U8,
108 HISI_SPI_N_BYTES_U16,
109 HISI_SPI_N_BYTES_U32 = 4
110 };
111
112 /* Slave spi_dev related */
113 struct hisi_chip_data {
114 u32 cr;
115 u32 speed_hz; /* baud rate */
116 u16 clk_div; /* baud rate divider */
117
118 /* clk_div = (1 + div_post) * div_pre */
119 u8 div_post; /* value from 0 to 255 */
120 u8 div_pre; /* value from 2 to 254 (even only!) */
121 };
122
123 struct hisi_spi {
124 struct device *dev;
125
126 void __iomem *regs;
127 int irq;
128 u32 fifo_len; /* depth of the FIFO buffer */
129
130 /* Current message transfer state info */
131 const void *tx;
132 unsigned int tx_len;
133 void *rx;
134 unsigned int rx_len;
135 u8 n_bytes; /* current is a 1/2/4 bytes op */
136 };
137
hisi_spi_busy(struct hisi_spi * hs)138 static u32 hisi_spi_busy(struct hisi_spi *hs)
139 {
140 return readl(hs->regs + HISI_SPI_SR) & SR_BUSY;
141 }
142
hisi_spi_rx_not_empty(struct hisi_spi * hs)143 static u32 hisi_spi_rx_not_empty(struct hisi_spi *hs)
144 {
145 return readl(hs->regs + HISI_SPI_SR) & SR_RXNE;
146 }
147
hisi_spi_tx_not_full(struct hisi_spi * hs)148 static u32 hisi_spi_tx_not_full(struct hisi_spi *hs)
149 {
150 return readl(hs->regs + HISI_SPI_SR) & SR_TXNF;
151 }
152
hisi_spi_flush_fifo(struct hisi_spi * hs)153 static void hisi_spi_flush_fifo(struct hisi_spi *hs)
154 {
155 unsigned long limit = loops_per_jiffy << 1;
156
157 do {
158 while (hisi_spi_rx_not_empty(hs))
159 readl(hs->regs + HISI_SPI_DOUT);
160 } while (hisi_spi_busy(hs) && limit--);
161 }
162
163 /* Disable the controller and all interrupts */
hisi_spi_disable(struct hisi_spi * hs)164 static void hisi_spi_disable(struct hisi_spi *hs)
165 {
166 writel(0, hs->regs + HISI_SPI_ENR);
167 writel(IMR_MASK, hs->regs + HISI_SPI_IMR);
168 writel(ICR_MASK, hs->regs + HISI_SPI_ICR);
169 }
170
hisi_spi_n_bytes(struct spi_transfer * transfer)171 static u8 hisi_spi_n_bytes(struct spi_transfer *transfer)
172 {
173 if (transfer->bits_per_word <= 8)
174 return HISI_SPI_N_BYTES_U8;
175 else if (transfer->bits_per_word <= 16)
176 return HISI_SPI_N_BYTES_U16;
177 else
178 return HISI_SPI_N_BYTES_U32;
179 }
180
hisi_spi_reader(struct hisi_spi * hs)181 static void hisi_spi_reader(struct hisi_spi *hs)
182 {
183 u32 max = min_t(u32, hs->rx_len, hs->fifo_len);
184 u32 rxw;
185
186 while (hisi_spi_rx_not_empty(hs) && max--) {
187 rxw = readl(hs->regs + HISI_SPI_DOUT);
188 /* Check the transfer's original "rx" is not null */
189 if (hs->rx) {
190 switch (hs->n_bytes) {
191 case HISI_SPI_N_BYTES_U8:
192 *(u8 *)(hs->rx) = rxw;
193 break;
194 case HISI_SPI_N_BYTES_U16:
195 *(u16 *)(hs->rx) = rxw;
196 break;
197 case HISI_SPI_N_BYTES_U32:
198 *(u32 *)(hs->rx) = rxw;
199 break;
200 }
201 hs->rx += hs->n_bytes;
202 }
203 --hs->rx_len;
204 }
205 }
206
hisi_spi_writer(struct hisi_spi * hs)207 static void hisi_spi_writer(struct hisi_spi *hs)
208 {
209 u32 max = min_t(u32, hs->tx_len, hs->fifo_len);
210 u32 txw = 0;
211
212 while (hisi_spi_tx_not_full(hs) && max--) {
213 /* Check the transfer's original "tx" is not null */
214 if (hs->tx) {
215 switch (hs->n_bytes) {
216 case HISI_SPI_N_BYTES_U8:
217 txw = *(u8 *)(hs->tx);
218 break;
219 case HISI_SPI_N_BYTES_U16:
220 txw = *(u16 *)(hs->tx);
221 break;
222 case HISI_SPI_N_BYTES_U32:
223 txw = *(u32 *)(hs->tx);
224 break;
225 }
226 hs->tx += hs->n_bytes;
227 }
228 writel(txw, hs->regs + HISI_SPI_DIN);
229 --hs->tx_len;
230 }
231 }
232
__hisi_calc_div_reg(struct hisi_chip_data * chip)233 static void __hisi_calc_div_reg(struct hisi_chip_data *chip)
234 {
235 chip->div_pre = DIV_PRE_MAX;
236 while (chip->div_pre >= DIV_PRE_MIN) {
237 if (chip->clk_div % chip->div_pre == 0)
238 break;
239
240 chip->div_pre -= 2;
241 }
242
243 if (chip->div_pre > chip->clk_div)
244 chip->div_pre = chip->clk_div;
245
246 chip->div_post = (chip->clk_div / chip->div_pre) - 1;
247 }
248
hisi_calc_effective_speed(struct spi_controller * master,struct hisi_chip_data * chip,u32 speed_hz)249 static u32 hisi_calc_effective_speed(struct spi_controller *master,
250 struct hisi_chip_data *chip, u32 speed_hz)
251 {
252 u32 effective_speed;
253
254 /* Note clock divider doesn't support odd numbers */
255 chip->clk_div = DIV_ROUND_UP(master->max_speed_hz, speed_hz) + 1;
256 chip->clk_div &= 0xfffe;
257 if (chip->clk_div > CLK_DIV_MAX)
258 chip->clk_div = CLK_DIV_MAX;
259
260 effective_speed = master->max_speed_hz / chip->clk_div;
261 if (chip->speed_hz != effective_speed) {
262 __hisi_calc_div_reg(chip);
263 chip->speed_hz = effective_speed;
264 }
265
266 return effective_speed;
267 }
268
hisi_spi_prepare_cr(struct spi_device * spi)269 static u32 hisi_spi_prepare_cr(struct spi_device *spi)
270 {
271 u32 cr = FIELD_PREP(CR_SPD_MODE_MASK, 1);
272
273 cr |= FIELD_PREP(CR_CPHA_MASK, (spi->mode & SPI_CPHA) ? 1 : 0);
274 cr |= FIELD_PREP(CR_CPOL_MASK, (spi->mode & SPI_CPOL) ? 1 : 0);
275 cr |= FIELD_PREP(CR_LOOP_MASK, (spi->mode & SPI_LOOP) ? 1 : 0);
276
277 return cr;
278 }
279
hisi_spi_hw_init(struct hisi_spi * hs)280 static void hisi_spi_hw_init(struct hisi_spi *hs)
281 {
282 hisi_spi_disable(hs);
283
284 /* FIFO default config */
285 writel(FIELD_PREP(FIFOC_TX_MASK, HISI_SPI_TX_64_OR_LESS) |
286 FIELD_PREP(FIFOC_RX_MASK, HISI_SPI_RX_16),
287 hs->regs + HISI_SPI_FIFOC);
288
289 hs->fifo_len = 256;
290 }
291
hisi_spi_irq(int irq,void * dev_id)292 static irqreturn_t hisi_spi_irq(int irq, void *dev_id)
293 {
294 struct spi_controller *master = dev_id;
295 struct hisi_spi *hs = spi_controller_get_devdata(master);
296 u32 irq_status = readl(hs->regs + HISI_SPI_ISR) & ISR_MASK;
297
298 if (!irq_status)
299 return IRQ_NONE;
300
301 if (!master->cur_msg)
302 return IRQ_HANDLED;
303
304 /* Error handling */
305 if (irq_status & ISR_RXOF) {
306 dev_err(hs->dev, "interrupt_transfer: fifo overflow\n");
307 master->cur_msg->status = -EIO;
308 goto finalize_transfer;
309 }
310
311 /*
312 * Read data from the Rx FIFO every time. If there is
313 * nothing left to receive, finalize the transfer.
314 */
315 hisi_spi_reader(hs);
316 if (!hs->rx_len)
317 goto finalize_transfer;
318
319 /* Send data out when Tx FIFO IRQ triggered */
320 if (irq_status & ISR_TX)
321 hisi_spi_writer(hs);
322
323 return IRQ_HANDLED;
324
325 finalize_transfer:
326 hisi_spi_disable(hs);
327 spi_finalize_current_transfer(master);
328 return IRQ_HANDLED;
329 }
330
hisi_spi_transfer_one(struct spi_controller * master,struct spi_device * spi,struct spi_transfer * transfer)331 static int hisi_spi_transfer_one(struct spi_controller *master,
332 struct spi_device *spi, struct spi_transfer *transfer)
333 {
334 struct hisi_spi *hs = spi_controller_get_devdata(master);
335 struct hisi_chip_data *chip = spi_get_ctldata(spi);
336 u32 cr = chip->cr;
337
338 /* Update per transfer options for speed and bpw */
339 transfer->effective_speed_hz =
340 hisi_calc_effective_speed(master, chip, transfer->speed_hz);
341 cr |= FIELD_PREP(CR_DIV_PRE_MASK, chip->div_pre);
342 cr |= FIELD_PREP(CR_DIV_POST_MASK, chip->div_post);
343 cr |= FIELD_PREP(CR_BPW_MASK, transfer->bits_per_word - 1);
344 writel(cr, hs->regs + HISI_SPI_CR);
345
346 hisi_spi_flush_fifo(hs);
347
348 hs->n_bytes = hisi_spi_n_bytes(transfer);
349 hs->tx = transfer->tx_buf;
350 hs->tx_len = transfer->len / hs->n_bytes;
351 hs->rx = transfer->rx_buf;
352 hs->rx_len = hs->tx_len;
353
354 /*
355 * Ensure that the transfer data above has been updated
356 * before the interrupt to start.
357 */
358 smp_mb();
359
360 /* Enable all interrupts and the controller */
361 writel(~(u32)IMR_MASK, hs->regs + HISI_SPI_IMR);
362 writel(1, hs->regs + HISI_SPI_ENR);
363
364 return 1;
365 }
366
hisi_spi_handle_err(struct spi_controller * master,struct spi_message * msg)367 static void hisi_spi_handle_err(struct spi_controller *master,
368 struct spi_message *msg)
369 {
370 struct hisi_spi *hs = spi_controller_get_devdata(master);
371
372 hisi_spi_disable(hs);
373
374 /*
375 * Wait for interrupt handler that is
376 * already in timeout to complete.
377 */
378 msleep(HISI_SPI_WAIT_TIMEOUT_MS);
379 }
380
hisi_spi_setup(struct spi_device * spi)381 static int hisi_spi_setup(struct spi_device *spi)
382 {
383 struct hisi_chip_data *chip;
384
385 /* Only alloc on first setup */
386 chip = spi_get_ctldata(spi);
387 if (!chip) {
388 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
389 if (!chip)
390 return -ENOMEM;
391 spi_set_ctldata(spi, chip);
392 }
393
394 chip->cr = hisi_spi_prepare_cr(spi);
395
396 return 0;
397 }
398
hisi_spi_cleanup(struct spi_device * spi)399 static void hisi_spi_cleanup(struct spi_device *spi)
400 {
401 struct hisi_chip_data *chip = spi_get_ctldata(spi);
402
403 kfree(chip);
404 spi_set_ctldata(spi, NULL);
405 }
406
hisi_spi_probe(struct platform_device * pdev)407 static int hisi_spi_probe(struct platform_device *pdev)
408 {
409 struct device *dev = &pdev->dev;
410 struct spi_controller *master;
411 struct hisi_spi *hs;
412 int ret, irq;
413
414 irq = platform_get_irq(pdev, 0);
415 if (irq < 0)
416 return irq;
417
418 master = devm_spi_alloc_master(dev, sizeof(*hs));
419 if (!master)
420 return -ENOMEM;
421
422 platform_set_drvdata(pdev, master);
423
424 hs = spi_controller_get_devdata(master);
425 hs->dev = dev;
426 hs->irq = irq;
427
428 hs->regs = devm_platform_ioremap_resource(pdev, 0);
429 if (IS_ERR(hs->regs))
430 return PTR_ERR(hs->regs);
431
432 /* Specify maximum SPI clocking speed (master only) by firmware */
433 ret = device_property_read_u32(dev, "spi-max-frequency",
434 &master->max_speed_hz);
435 if (ret) {
436 dev_err(dev, "failed to get max SPI clocking speed, ret=%d\n",
437 ret);
438 return -EINVAL;
439 }
440
441 ret = device_property_read_u16(dev, "num-cs",
442 &master->num_chipselect);
443 if (ret)
444 master->num_chipselect = DEFAULT_NUM_CS;
445
446 master->use_gpio_descriptors = true;
447 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
448 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
449 master->bus_num = pdev->id;
450 master->setup = hisi_spi_setup;
451 master->cleanup = hisi_spi_cleanup;
452 master->transfer_one = hisi_spi_transfer_one;
453 master->handle_err = hisi_spi_handle_err;
454 master->dev.fwnode = dev->fwnode;
455
456 hisi_spi_hw_init(hs);
457
458 ret = devm_request_irq(dev, hs->irq, hisi_spi_irq, 0, dev_name(dev),
459 master);
460 if (ret < 0) {
461 dev_err(dev, "failed to get IRQ=%d, ret=%d\n", hs->irq, ret);
462 return ret;
463 }
464
465 ret = spi_register_controller(master);
466 if (ret) {
467 dev_err(dev, "failed to register spi master, ret=%d\n", ret);
468 return ret;
469 }
470
471 dev_info(dev, "hw version:0x%x max-freq:%u kHz\n",
472 readl(hs->regs + HISI_SPI_VERSION),
473 master->max_speed_hz / 1000);
474
475 return 0;
476 }
477
hisi_spi_remove(struct platform_device * pdev)478 static int hisi_spi_remove(struct platform_device *pdev)
479 {
480 struct spi_controller *master = platform_get_drvdata(pdev);
481
482 spi_unregister_controller(master);
483
484 return 0;
485 }
486
487 static const struct acpi_device_id hisi_spi_acpi_match[] = {
488 {"HISI03E1", 0},
489 {}
490 };
491 MODULE_DEVICE_TABLE(acpi, hisi_spi_acpi_match);
492
493 static struct platform_driver hisi_spi_driver = {
494 .probe = hisi_spi_probe,
495 .remove = hisi_spi_remove,
496 .driver = {
497 .name = "hisi-kunpeng-spi",
498 .acpi_match_table = hisi_spi_acpi_match,
499 },
500 };
501 module_platform_driver(hisi_spi_driver);
502
503 MODULE_AUTHOR("Jay Fang <f.fangjian@huawei.com>");
504 MODULE_DESCRIPTION("HiSilicon SPI Controller Driver for Kunpeng SoCs");
505 MODULE_LICENSE("GPL v2");
506