1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Copyright 2018 SiFive, Inc.
4 //
5 // SiFive SPI controller driver (master mode only)
6 //
7 // Author: SiFive, Inc.
8 // sifive@sifive.com
9 
10 #include <linux/clk.h>
11 #include <linux/module.h>
12 #include <linux/interrupt.h>
13 #include <linux/of.h>
14 #include <linux/platform_device.h>
15 #include <linux/spi/spi.h>
16 #include <linux/io.h>
17 #include <linux/log2.h>
18 
19 #define SIFIVE_SPI_DRIVER_NAME           "sifive_spi"
20 
21 #define SIFIVE_SPI_MAX_CS                32
22 #define SIFIVE_SPI_DEFAULT_DEPTH         8
23 #define SIFIVE_SPI_DEFAULT_MAX_BITS      8
24 
25 /* register offsets */
26 #define SIFIVE_SPI_REG_SCKDIV            0x00 /* Serial clock divisor */
27 #define SIFIVE_SPI_REG_SCKMODE           0x04 /* Serial clock mode */
28 #define SIFIVE_SPI_REG_CSID              0x10 /* Chip select ID */
29 #define SIFIVE_SPI_REG_CSDEF             0x14 /* Chip select default */
30 #define SIFIVE_SPI_REG_CSMODE            0x18 /* Chip select mode */
31 #define SIFIVE_SPI_REG_DELAY0            0x28 /* Delay control 0 */
32 #define SIFIVE_SPI_REG_DELAY1            0x2c /* Delay control 1 */
33 #define SIFIVE_SPI_REG_FMT               0x40 /* Frame format */
34 #define SIFIVE_SPI_REG_TXDATA            0x48 /* Tx FIFO data */
35 #define SIFIVE_SPI_REG_RXDATA            0x4c /* Rx FIFO data */
36 #define SIFIVE_SPI_REG_TXMARK            0x50 /* Tx FIFO watermark */
37 #define SIFIVE_SPI_REG_RXMARK            0x54 /* Rx FIFO watermark */
38 #define SIFIVE_SPI_REG_FCTRL             0x60 /* SPI flash interface control */
39 #define SIFIVE_SPI_REG_FFMT              0x64 /* SPI flash instruction format */
40 #define SIFIVE_SPI_REG_IE                0x70 /* Interrupt Enable Register */
41 #define SIFIVE_SPI_REG_IP                0x74 /* Interrupt Pendings Register */
42 
43 /* sckdiv bits */
44 #define SIFIVE_SPI_SCKDIV_DIV_MASK       0xfffU
45 
46 /* sckmode bits */
47 #define SIFIVE_SPI_SCKMODE_PHA           BIT(0)
48 #define SIFIVE_SPI_SCKMODE_POL           BIT(1)
49 #define SIFIVE_SPI_SCKMODE_MODE_MASK     (SIFIVE_SPI_SCKMODE_PHA | \
50 					  SIFIVE_SPI_SCKMODE_POL)
51 
52 /* csmode bits */
53 #define SIFIVE_SPI_CSMODE_MODE_AUTO      0U
54 #define SIFIVE_SPI_CSMODE_MODE_HOLD      2U
55 #define SIFIVE_SPI_CSMODE_MODE_OFF       3U
56 
57 /* delay0 bits */
58 #define SIFIVE_SPI_DELAY0_CSSCK(x)       ((u32)(x))
59 #define SIFIVE_SPI_DELAY0_CSSCK_MASK     0xffU
60 #define SIFIVE_SPI_DELAY0_SCKCS(x)       ((u32)(x) << 16)
61 #define SIFIVE_SPI_DELAY0_SCKCS_MASK     (0xffU << 16)
62 
63 /* delay1 bits */
64 #define SIFIVE_SPI_DELAY1_INTERCS(x)     ((u32)(x))
65 #define SIFIVE_SPI_DELAY1_INTERCS_MASK   0xffU
66 #define SIFIVE_SPI_DELAY1_INTERXFR(x)    ((u32)(x) << 16)
67 #define SIFIVE_SPI_DELAY1_INTERXFR_MASK  (0xffU << 16)
68 
69 /* fmt bits */
70 #define SIFIVE_SPI_FMT_PROTO_SINGLE      0U
71 #define SIFIVE_SPI_FMT_PROTO_DUAL        1U
72 #define SIFIVE_SPI_FMT_PROTO_QUAD        2U
73 #define SIFIVE_SPI_FMT_PROTO_MASK        3U
74 #define SIFIVE_SPI_FMT_ENDIAN            BIT(2)
75 #define SIFIVE_SPI_FMT_DIR               BIT(3)
76 #define SIFIVE_SPI_FMT_LEN(x)            ((u32)(x) << 16)
77 #define SIFIVE_SPI_FMT_LEN_MASK          (0xfU << 16)
78 
79 /* txdata bits */
80 #define SIFIVE_SPI_TXDATA_DATA_MASK      0xffU
81 #define SIFIVE_SPI_TXDATA_FULL           BIT(31)
82 
83 /* rxdata bits */
84 #define SIFIVE_SPI_RXDATA_DATA_MASK      0xffU
85 #define SIFIVE_SPI_RXDATA_EMPTY          BIT(31)
86 
87 /* ie and ip bits */
88 #define SIFIVE_SPI_IP_TXWM               BIT(0)
89 #define SIFIVE_SPI_IP_RXWM               BIT(1)
90 
91 struct sifive_spi {
92 	void __iomem      *regs;        /* virt. address of control registers */
93 	struct clk        *clk;         /* bus clock */
94 	unsigned int      fifo_depth;   /* fifo depth in words */
95 	u32               cs_inactive;  /* level of the CS pins when inactive */
96 	struct completion done;         /* wake-up from interrupt */
97 };
98 
sifive_spi_write(struct sifive_spi * spi,int offset,u32 value)99 static void sifive_spi_write(struct sifive_spi *spi, int offset, u32 value)
100 {
101 	iowrite32(value, spi->regs + offset);
102 }
103 
sifive_spi_read(struct sifive_spi * spi,int offset)104 static u32 sifive_spi_read(struct sifive_spi *spi, int offset)
105 {
106 	return ioread32(spi->regs + offset);
107 }
108 
sifive_spi_init(struct sifive_spi * spi)109 static void sifive_spi_init(struct sifive_spi *spi)
110 {
111 	/* Watermark interrupts are disabled by default */
112 	sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
113 
114 	/* Default watermark FIFO threshold values */
115 	sifive_spi_write(spi, SIFIVE_SPI_REG_TXMARK, 1);
116 	sifive_spi_write(spi, SIFIVE_SPI_REG_RXMARK, 0);
117 
118 	/* Set CS/SCK Delays and Inactive Time to defaults */
119 	sifive_spi_write(spi, SIFIVE_SPI_REG_DELAY0,
120 			 SIFIVE_SPI_DELAY0_CSSCK(1) |
121 			 SIFIVE_SPI_DELAY0_SCKCS(1));
122 	sifive_spi_write(spi, SIFIVE_SPI_REG_DELAY1,
123 			 SIFIVE_SPI_DELAY1_INTERCS(1) |
124 			 SIFIVE_SPI_DELAY1_INTERXFR(0));
125 
126 	/* Exit specialized memory-mapped SPI flash mode */
127 	sifive_spi_write(spi, SIFIVE_SPI_REG_FCTRL, 0);
128 }
129 
130 static int
sifive_spi_prepare_message(struct spi_master * master,struct spi_message * msg)131 sifive_spi_prepare_message(struct spi_master *master, struct spi_message *msg)
132 {
133 	struct sifive_spi *spi = spi_master_get_devdata(master);
134 	struct spi_device *device = msg->spi;
135 
136 	/* Update the chip select polarity */
137 	if (device->mode & SPI_CS_HIGH)
138 		spi->cs_inactive &= ~BIT(device->chip_select);
139 	else
140 		spi->cs_inactive |= BIT(device->chip_select);
141 	sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive);
142 
143 	/* Select the correct device */
144 	sifive_spi_write(spi, SIFIVE_SPI_REG_CSID, device->chip_select);
145 
146 	/* Set clock mode */
147 	sifive_spi_write(spi, SIFIVE_SPI_REG_SCKMODE,
148 			 device->mode & SIFIVE_SPI_SCKMODE_MODE_MASK);
149 
150 	return 0;
151 }
152 
sifive_spi_set_cs(struct spi_device * device,bool is_high)153 static void sifive_spi_set_cs(struct spi_device *device, bool is_high)
154 {
155 	struct sifive_spi *spi = spi_master_get_devdata(device->master);
156 
157 	/* Reverse polarity is handled by SCMR/CPOL. Not inverted CS. */
158 	if (device->mode & SPI_CS_HIGH)
159 		is_high = !is_high;
160 
161 	sifive_spi_write(spi, SIFIVE_SPI_REG_CSMODE, is_high ?
162 			 SIFIVE_SPI_CSMODE_MODE_AUTO :
163 			 SIFIVE_SPI_CSMODE_MODE_HOLD);
164 }
165 
166 static int
sifive_spi_prep_transfer(struct sifive_spi * spi,struct spi_device * device,struct spi_transfer * t)167 sifive_spi_prep_transfer(struct sifive_spi *spi, struct spi_device *device,
168 			 struct spi_transfer *t)
169 {
170 	u32 cr;
171 	unsigned int mode;
172 
173 	/* Calculate and program the clock rate */
174 	cr = DIV_ROUND_UP(clk_get_rate(spi->clk) >> 1, t->speed_hz) - 1;
175 	cr &= SIFIVE_SPI_SCKDIV_DIV_MASK;
176 	sifive_spi_write(spi, SIFIVE_SPI_REG_SCKDIV, cr);
177 
178 	mode = max_t(unsigned int, t->rx_nbits, t->tx_nbits);
179 
180 	/* Set frame format */
181 	cr = SIFIVE_SPI_FMT_LEN(t->bits_per_word);
182 	switch (mode) {
183 	case SPI_NBITS_QUAD:
184 		cr |= SIFIVE_SPI_FMT_PROTO_QUAD;
185 		break;
186 	case SPI_NBITS_DUAL:
187 		cr |= SIFIVE_SPI_FMT_PROTO_DUAL;
188 		break;
189 	default:
190 		cr |= SIFIVE_SPI_FMT_PROTO_SINGLE;
191 		break;
192 	}
193 	if (device->mode & SPI_LSB_FIRST)
194 		cr |= SIFIVE_SPI_FMT_ENDIAN;
195 	if (!t->rx_buf)
196 		cr |= SIFIVE_SPI_FMT_DIR;
197 	sifive_spi_write(spi, SIFIVE_SPI_REG_FMT, cr);
198 
199 	/* We will want to poll if the time we need to wait is
200 	 * less than the context switching time.
201 	 * Let's call that threshold 5us. The operation will take:
202 	 *    (8/mode) * fifo_depth / hz <= 5 * 10^-6
203 	 *    1600000 * fifo_depth <= hz * mode
204 	 */
205 	return 1600000 * spi->fifo_depth <= t->speed_hz * mode;
206 }
207 
sifive_spi_irq(int irq,void * dev_id)208 static irqreturn_t sifive_spi_irq(int irq, void *dev_id)
209 {
210 	struct sifive_spi *spi = dev_id;
211 	u32 ip = sifive_spi_read(spi, SIFIVE_SPI_REG_IP);
212 
213 	if (ip & (SIFIVE_SPI_IP_TXWM | SIFIVE_SPI_IP_RXWM)) {
214 		/* Disable interrupts until next transfer */
215 		sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
216 		complete(&spi->done);
217 		return IRQ_HANDLED;
218 	}
219 
220 	return IRQ_NONE;
221 }
222 
sifive_spi_wait(struct sifive_spi * spi,u32 bit,int poll)223 static void sifive_spi_wait(struct sifive_spi *spi, u32 bit, int poll)
224 {
225 	if (poll) {
226 		u32 cr;
227 
228 		do {
229 			cr = sifive_spi_read(spi, SIFIVE_SPI_REG_IP);
230 		} while (!(cr & bit));
231 	} else {
232 		reinit_completion(&spi->done);
233 		sifive_spi_write(spi, SIFIVE_SPI_REG_IE, bit);
234 		wait_for_completion(&spi->done);
235 	}
236 }
237 
sifive_spi_tx(struct sifive_spi * spi,const u8 * tx_ptr)238 static void sifive_spi_tx(struct sifive_spi *spi, const u8 *tx_ptr)
239 {
240 	WARN_ON_ONCE((sifive_spi_read(spi, SIFIVE_SPI_REG_TXDATA)
241 				& SIFIVE_SPI_TXDATA_FULL) != 0);
242 	sifive_spi_write(spi, SIFIVE_SPI_REG_TXDATA,
243 			 *tx_ptr & SIFIVE_SPI_TXDATA_DATA_MASK);
244 }
245 
sifive_spi_rx(struct sifive_spi * spi,u8 * rx_ptr)246 static void sifive_spi_rx(struct sifive_spi *spi, u8 *rx_ptr)
247 {
248 	u32 data = sifive_spi_read(spi, SIFIVE_SPI_REG_RXDATA);
249 
250 	WARN_ON_ONCE((data & SIFIVE_SPI_RXDATA_EMPTY) != 0);
251 	*rx_ptr = data & SIFIVE_SPI_RXDATA_DATA_MASK;
252 }
253 
254 static int
sifive_spi_transfer_one(struct spi_master * master,struct spi_device * device,struct spi_transfer * t)255 sifive_spi_transfer_one(struct spi_master *master, struct spi_device *device,
256 			struct spi_transfer *t)
257 {
258 	struct sifive_spi *spi = spi_master_get_devdata(master);
259 	int poll = sifive_spi_prep_transfer(spi, device, t);
260 	const u8 *tx_ptr = t->tx_buf;
261 	u8 *rx_ptr = t->rx_buf;
262 	unsigned int remaining_words = t->len;
263 
264 	while (remaining_words) {
265 		unsigned int n_words = min(remaining_words, spi->fifo_depth);
266 		unsigned int i;
267 
268 		/* Enqueue n_words for transmission */
269 		for (i = 0; i < n_words; i++)
270 			sifive_spi_tx(spi, tx_ptr++);
271 
272 		if (rx_ptr) {
273 			/* Wait for transmission + reception to complete */
274 			sifive_spi_write(spi, SIFIVE_SPI_REG_RXMARK,
275 					 n_words - 1);
276 			sifive_spi_wait(spi, SIFIVE_SPI_IP_RXWM, poll);
277 
278 			/* Read out all the data from the RX FIFO */
279 			for (i = 0; i < n_words; i++)
280 				sifive_spi_rx(spi, rx_ptr++);
281 		} else {
282 			/* Wait for transmission to complete */
283 			sifive_spi_wait(spi, SIFIVE_SPI_IP_TXWM, poll);
284 		}
285 
286 		remaining_words -= n_words;
287 	}
288 
289 	return 0;
290 }
291 
sifive_spi_probe(struct platform_device * pdev)292 static int sifive_spi_probe(struct platform_device *pdev)
293 {
294 	struct sifive_spi *spi;
295 	int ret, irq, num_cs;
296 	u32 cs_bits, max_bits_per_word;
297 	struct spi_master *master;
298 
299 	master = spi_alloc_master(&pdev->dev, sizeof(struct sifive_spi));
300 	if (!master) {
301 		dev_err(&pdev->dev, "out of memory\n");
302 		return -ENOMEM;
303 	}
304 
305 	spi = spi_master_get_devdata(master);
306 	init_completion(&spi->done);
307 	platform_set_drvdata(pdev, master);
308 
309 	spi->regs = devm_platform_ioremap_resource(pdev, 0);
310 	if (IS_ERR(spi->regs)) {
311 		ret = PTR_ERR(spi->regs);
312 		goto put_master;
313 	}
314 
315 	spi->clk = devm_clk_get(&pdev->dev, NULL);
316 	if (IS_ERR(spi->clk)) {
317 		dev_err(&pdev->dev, "Unable to find bus clock\n");
318 		ret = PTR_ERR(spi->clk);
319 		goto put_master;
320 	}
321 
322 	irq = platform_get_irq(pdev, 0);
323 	if (irq < 0) {
324 		ret = irq;
325 		goto put_master;
326 	}
327 
328 	/* Optional parameters */
329 	ret =
330 	  of_property_read_u32(pdev->dev.of_node, "sifive,fifo-depth",
331 			       &spi->fifo_depth);
332 	if (ret < 0)
333 		spi->fifo_depth = SIFIVE_SPI_DEFAULT_DEPTH;
334 
335 	ret =
336 	  of_property_read_u32(pdev->dev.of_node, "sifive,max-bits-per-word",
337 			       &max_bits_per_word);
338 
339 	if (!ret && max_bits_per_word < 8) {
340 		dev_err(&pdev->dev, "Only 8bit SPI words supported by the driver\n");
341 		ret = -EINVAL;
342 		goto put_master;
343 	}
344 
345 	/* Spin up the bus clock before hitting registers */
346 	ret = clk_prepare_enable(spi->clk);
347 	if (ret) {
348 		dev_err(&pdev->dev, "Unable to enable bus clock\n");
349 		goto put_master;
350 	}
351 
352 	/* probe the number of CS lines */
353 	spi->cs_inactive = sifive_spi_read(spi, SIFIVE_SPI_REG_CSDEF);
354 	sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, 0xffffffffU);
355 	cs_bits = sifive_spi_read(spi, SIFIVE_SPI_REG_CSDEF);
356 	sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive);
357 	if (!cs_bits) {
358 		dev_err(&pdev->dev, "Could not auto probe CS lines\n");
359 		ret = -EINVAL;
360 		goto disable_clk;
361 	}
362 
363 	num_cs = ilog2(cs_bits) + 1;
364 	if (num_cs > SIFIVE_SPI_MAX_CS) {
365 		dev_err(&pdev->dev, "Invalid number of spi slaves\n");
366 		ret = -EINVAL;
367 		goto disable_clk;
368 	}
369 
370 	/* Define our master */
371 	master->dev.of_node = pdev->dev.of_node;
372 	master->bus_num = pdev->id;
373 	master->num_chipselect = num_cs;
374 	master->mode_bits = SPI_CPHA | SPI_CPOL
375 			  | SPI_CS_HIGH | SPI_LSB_FIRST
376 			  | SPI_TX_DUAL | SPI_TX_QUAD
377 			  | SPI_RX_DUAL | SPI_RX_QUAD;
378 	/* TODO: add driver support for bits_per_word < 8
379 	 * we need to "left-align" the bits (unless SPI_LSB_FIRST)
380 	 */
381 	master->bits_per_word_mask = SPI_BPW_MASK(8);
382 	master->flags = SPI_CONTROLLER_MUST_TX | SPI_MASTER_GPIO_SS;
383 	master->prepare_message = sifive_spi_prepare_message;
384 	master->set_cs = sifive_spi_set_cs;
385 	master->transfer_one = sifive_spi_transfer_one;
386 
387 	pdev->dev.dma_mask = NULL;
388 	/* Configure the SPI master hardware */
389 	sifive_spi_init(spi);
390 
391 	/* Register for SPI Interrupt */
392 	ret = devm_request_irq(&pdev->dev, irq, sifive_spi_irq, 0,
393 			       dev_name(&pdev->dev), spi);
394 	if (ret) {
395 		dev_err(&pdev->dev, "Unable to bind to interrupt\n");
396 		goto disable_clk;
397 	}
398 
399 	dev_info(&pdev->dev, "mapped; irq=%d, cs=%d\n",
400 		 irq, master->num_chipselect);
401 
402 	ret = devm_spi_register_master(&pdev->dev, master);
403 	if (ret < 0) {
404 		dev_err(&pdev->dev, "spi_register_master failed\n");
405 		goto disable_clk;
406 	}
407 
408 	return 0;
409 
410 disable_clk:
411 	clk_disable_unprepare(spi->clk);
412 put_master:
413 	spi_master_put(master);
414 
415 	return ret;
416 }
417 
sifive_spi_remove(struct platform_device * pdev)418 static int sifive_spi_remove(struct platform_device *pdev)
419 {
420 	struct spi_master *master = platform_get_drvdata(pdev);
421 	struct sifive_spi *spi = spi_master_get_devdata(master);
422 
423 	/* Disable all the interrupts just in case */
424 	sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
425 	clk_disable_unprepare(spi->clk);
426 
427 	return 0;
428 }
429 
430 static const struct of_device_id sifive_spi_of_match[] = {
431 	{ .compatible = "sifive,spi0", },
432 	{}
433 };
434 MODULE_DEVICE_TABLE(of, sifive_spi_of_match);
435 
436 static struct platform_driver sifive_spi_driver = {
437 	.probe = sifive_spi_probe,
438 	.remove = sifive_spi_remove,
439 	.driver = {
440 		.name = SIFIVE_SPI_DRIVER_NAME,
441 		.of_match_table = sifive_spi_of_match,
442 	},
443 };
444 module_platform_driver(sifive_spi_driver);
445 
446 MODULE_AUTHOR("SiFive, Inc. <sifive@sifive.com>");
447 MODULE_DESCRIPTION("SiFive SPI driver");
448 MODULE_LICENSE("GPL");
449