1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Motorola/Freescale IMX serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Author: Sascha Hauer <sascha@saschahauer.de>
8 * Copyright (C) 2004 Pengutronix
9 */
10
11 #include <linux/module.h>
12 #include <linux/ioport.h>
13 #include <linux/init.h>
14 #include <linux/console.h>
15 #include <linux/sysrq.h>
16 #include <linux/platform_device.h>
17 #include <linux/tty.h>
18 #include <linux/tty_flip.h>
19 #include <linux/serial_core.h>
20 #include <linux/serial.h>
21 #include <linux/clk.h>
22 #include <linux/delay.h>
23 #include <linux/ktime.h>
24 #include <linux/pinctrl/consumer.h>
25 #include <linux/rational.h>
26 #include <linux/slab.h>
27 #include <linux/of.h>
28 #include <linux/of_device.h>
29 #include <linux/io.h>
30 #include <linux/dma-mapping.h>
31
32 #include <asm/irq.h>
33 #include <linux/platform_data/dma-imx.h>
34
35 #include "serial_mctrl_gpio.h"
36
37 /* Register definitions */
38 #define URXD0 0x0 /* Receiver Register */
39 #define URTX0 0x40 /* Transmitter Register */
40 #define UCR1 0x80 /* Control Register 1 */
41 #define UCR2 0x84 /* Control Register 2 */
42 #define UCR3 0x88 /* Control Register 3 */
43 #define UCR4 0x8c /* Control Register 4 */
44 #define UFCR 0x90 /* FIFO Control Register */
45 #define USR1 0x94 /* Status Register 1 */
46 #define USR2 0x98 /* Status Register 2 */
47 #define UESC 0x9c /* Escape Character Register */
48 #define UTIM 0xa0 /* Escape Timer Register */
49 #define UBIR 0xa4 /* BRM Incremental Register */
50 #define UBMR 0xa8 /* BRM Modulator Register */
51 #define UBRC 0xac /* Baud Rate Count Register */
52 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
53 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
54 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
55
56 /* UART Control Register Bit Fields.*/
57 #define URXD_DUMMY_READ (1<<16)
58 #define URXD_CHARRDY (1<<15)
59 #define URXD_ERR (1<<14)
60 #define URXD_OVRRUN (1<<13)
61 #define URXD_FRMERR (1<<12)
62 #define URXD_BRK (1<<11)
63 #define URXD_PRERR (1<<10)
64 #define URXD_RX_DATA (0xFF<<0)
65 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
66 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
67 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
68 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
69 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
70 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
71 #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
72 #define UCR1_IREN (1<<7) /* Infrared interface enable */
73 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
74 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
75 #define UCR1_SNDBRK (1<<4) /* Send break */
76 #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
77 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
78 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
79 #define UCR1_DOZE (1<<1) /* Doze */
80 #define UCR1_UARTEN (1<<0) /* UART enabled */
81 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
82 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
83 #define UCR2_CTSC (1<<13) /* CTS pin control */
84 #define UCR2_CTS (1<<12) /* Clear to send */
85 #define UCR2_ESCEN (1<<11) /* Escape enable */
86 #define UCR2_PREN (1<<8) /* Parity enable */
87 #define UCR2_PROE (1<<7) /* Parity odd/even */
88 #define UCR2_STPB (1<<6) /* Stop */
89 #define UCR2_WS (1<<5) /* Word size */
90 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
91 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
92 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
93 #define UCR2_RXEN (1<<1) /* Receiver enabled */
94 #define UCR2_SRST (1<<0) /* SW reset */
95 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
96 #define UCR3_PARERREN (1<<12) /* Parity enable */
97 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
98 #define UCR3_DSR (1<<10) /* Data set ready */
99 #define UCR3_DCD (1<<9) /* Data carrier detect */
100 #define UCR3_RI (1<<8) /* Ring indicator */
101 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
102 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
103 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
104 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
105 #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
106 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
107 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
108 #define UCR3_BPEN (1<<0) /* Preset registers enable */
109 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
110 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
111 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
112 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
113 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
114 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
115 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
116 #define UCR4_IRSC (1<<5) /* IR special case */
117 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
118 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
119 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
120 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
121 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
122 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
123 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
124 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
125 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
126 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
127 #define USR1_RTSS (1<<14) /* RTS pin status */
128 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
129 #define USR1_RTSD (1<<12) /* RTS delta */
130 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
131 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
132 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
133 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
134 #define USR1_DTRD (1<<7) /* DTR Delta */
135 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
136 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
137 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
138 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
139 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
140 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
141 #define USR2_IDLE (1<<12) /* Idle condition */
142 #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
143 #define USR2_RIIN (1<<9) /* Ring Indicator Input */
144 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
145 #define USR2_WAKE (1<<7) /* Wake */
146 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
147 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
148 #define USR2_TXDC (1<<3) /* Transmitter complete */
149 #define USR2_BRCD (1<<2) /* Break condition */
150 #define USR2_ORE (1<<1) /* Overrun error */
151 #define USR2_RDR (1<<0) /* Recv data ready */
152 #define UTS_FRCPERR (1<<13) /* Force parity error */
153 #define UTS_LOOP (1<<12) /* Loop tx and rx */
154 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
155 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
156 #define UTS_TXFULL (1<<4) /* TxFIFO full */
157 #define UTS_RXFULL (1<<3) /* RxFIFO full */
158 #define UTS_SOFTRST (1<<0) /* Software reset */
159
160 /* We've been assigned a range on the "Low-density serial ports" major */
161 #define SERIAL_IMX_MAJOR 207
162 #define MINOR_START 16
163 #define DEV_NAME "ttymxc"
164
165 /*
166 * This determines how often we check the modem status signals
167 * for any change. They generally aren't connected to an IRQ
168 * so we have to poll them. We also check immediately before
169 * filling the TX fifo incase CTS has been dropped.
170 */
171 #define MCTRL_TIMEOUT (250*HZ/1000)
172
173 #define DRIVER_NAME "IMX-uart"
174
175 #define UART_NR 8
176
177 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
178 enum imx_uart_type {
179 IMX1_UART,
180 IMX21_UART,
181 IMX53_UART,
182 IMX6Q_UART,
183 };
184
185 /* device type dependent stuff */
186 struct imx_uart_data {
187 unsigned uts_reg;
188 enum imx_uart_type devtype;
189 };
190
191 enum imx_tx_state {
192 OFF,
193 WAIT_AFTER_RTS,
194 SEND,
195 WAIT_AFTER_SEND,
196 };
197
198 struct imx_port {
199 struct uart_port port;
200 struct timer_list timer;
201 unsigned int old_status;
202 unsigned int have_rtscts:1;
203 unsigned int have_rtsgpio:1;
204 unsigned int dte_mode:1;
205 unsigned int inverted_tx:1;
206 unsigned int inverted_rx:1;
207 struct clk *clk_ipg;
208 struct clk *clk_per;
209 const struct imx_uart_data *devdata;
210
211 struct mctrl_gpios *gpios;
212
213 /* shadow registers */
214 unsigned int ucr1;
215 unsigned int ucr2;
216 unsigned int ucr3;
217 unsigned int ucr4;
218 unsigned int ufcr;
219
220 /* DMA fields */
221 unsigned int dma_is_enabled:1;
222 unsigned int dma_is_rxing:1;
223 unsigned int dma_is_txing:1;
224 struct dma_chan *dma_chan_rx, *dma_chan_tx;
225 struct scatterlist rx_sgl, tx_sgl[2];
226 void *rx_buf;
227 struct circ_buf rx_ring;
228 unsigned int rx_periods;
229 dma_cookie_t rx_cookie;
230 unsigned int tx_bytes;
231 unsigned int dma_tx_nents;
232 unsigned int saved_reg[10];
233 bool context_saved;
234
235 enum imx_tx_state tx_state;
236 struct hrtimer trigger_start_tx;
237 struct hrtimer trigger_stop_tx;
238 };
239
240 struct imx_port_ucrs {
241 unsigned int ucr1;
242 unsigned int ucr2;
243 unsigned int ucr3;
244 };
245
246 static struct imx_uart_data imx_uart_devdata[] = {
247 [IMX1_UART] = {
248 .uts_reg = IMX1_UTS,
249 .devtype = IMX1_UART,
250 },
251 [IMX21_UART] = {
252 .uts_reg = IMX21_UTS,
253 .devtype = IMX21_UART,
254 },
255 [IMX53_UART] = {
256 .uts_reg = IMX21_UTS,
257 .devtype = IMX53_UART,
258 },
259 [IMX6Q_UART] = {
260 .uts_reg = IMX21_UTS,
261 .devtype = IMX6Q_UART,
262 },
263 };
264
265 static const struct of_device_id imx_uart_dt_ids[] = {
266 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
267 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
268 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
269 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
270 { /* sentinel */ }
271 };
272 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
273
imx_uart_writel(struct imx_port * sport,u32 val,u32 offset)274 static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
275 {
276 switch (offset) {
277 case UCR1:
278 sport->ucr1 = val;
279 break;
280 case UCR2:
281 sport->ucr2 = val;
282 break;
283 case UCR3:
284 sport->ucr3 = val;
285 break;
286 case UCR4:
287 sport->ucr4 = val;
288 break;
289 case UFCR:
290 sport->ufcr = val;
291 break;
292 default:
293 break;
294 }
295 writel(val, sport->port.membase + offset);
296 }
297
imx_uart_readl(struct imx_port * sport,u32 offset)298 static u32 imx_uart_readl(struct imx_port *sport, u32 offset)
299 {
300 switch (offset) {
301 case UCR1:
302 return sport->ucr1;
303 break;
304 case UCR2:
305 /*
306 * UCR2_SRST is the only bit in the cached registers that might
307 * differ from the value that was last written. As it only
308 * automatically becomes one after being cleared, reread
309 * conditionally.
310 */
311 if (!(sport->ucr2 & UCR2_SRST))
312 sport->ucr2 = readl(sport->port.membase + offset);
313 return sport->ucr2;
314 break;
315 case UCR3:
316 return sport->ucr3;
317 break;
318 case UCR4:
319 return sport->ucr4;
320 break;
321 case UFCR:
322 return sport->ufcr;
323 break;
324 default:
325 return readl(sport->port.membase + offset);
326 }
327 }
328
imx_uart_uts_reg(struct imx_port * sport)329 static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
330 {
331 return sport->devdata->uts_reg;
332 }
333
imx_uart_is_imx1(struct imx_port * sport)334 static inline int imx_uart_is_imx1(struct imx_port *sport)
335 {
336 return sport->devdata->devtype == IMX1_UART;
337 }
338
imx_uart_is_imx21(struct imx_port * sport)339 static inline int imx_uart_is_imx21(struct imx_port *sport)
340 {
341 return sport->devdata->devtype == IMX21_UART;
342 }
343
imx_uart_is_imx53(struct imx_port * sport)344 static inline int imx_uart_is_imx53(struct imx_port *sport)
345 {
346 return sport->devdata->devtype == IMX53_UART;
347 }
348
imx_uart_is_imx6q(struct imx_port * sport)349 static inline int imx_uart_is_imx6q(struct imx_port *sport)
350 {
351 return sport->devdata->devtype == IMX6Q_UART;
352 }
353 /*
354 * Save and restore functions for UCR1, UCR2 and UCR3 registers
355 */
356 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
imx_uart_ucrs_save(struct imx_port * sport,struct imx_port_ucrs * ucr)357 static void imx_uart_ucrs_save(struct imx_port *sport,
358 struct imx_port_ucrs *ucr)
359 {
360 /* save control registers */
361 ucr->ucr1 = imx_uart_readl(sport, UCR1);
362 ucr->ucr2 = imx_uart_readl(sport, UCR2);
363 ucr->ucr3 = imx_uart_readl(sport, UCR3);
364 }
365
imx_uart_ucrs_restore(struct imx_port * sport,struct imx_port_ucrs * ucr)366 static void imx_uart_ucrs_restore(struct imx_port *sport,
367 struct imx_port_ucrs *ucr)
368 {
369 /* restore control registers */
370 imx_uart_writel(sport, ucr->ucr1, UCR1);
371 imx_uart_writel(sport, ucr->ucr2, UCR2);
372 imx_uart_writel(sport, ucr->ucr3, UCR3);
373 }
374 #endif
375
376 /* called with port.lock taken and irqs caller dependent */
imx_uart_rts_active(struct imx_port * sport,u32 * ucr2)377 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
378 {
379 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
380
381 sport->port.mctrl |= TIOCM_RTS;
382 mctrl_gpio_set(sport->gpios, sport->port.mctrl);
383 }
384
385 /* called with port.lock taken and irqs caller dependent */
imx_uart_rts_inactive(struct imx_port * sport,u32 * ucr2)386 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
387 {
388 *ucr2 &= ~UCR2_CTSC;
389 *ucr2 |= UCR2_CTS;
390
391 sport->port.mctrl &= ~TIOCM_RTS;
392 mctrl_gpio_set(sport->gpios, sport->port.mctrl);
393 }
394
start_hrtimer_ms(struct hrtimer * hrt,unsigned long msec)395 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
396 {
397 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
398 }
399
400 /* called with port.lock taken and irqs off */
imx_uart_start_rx(struct uart_port * port)401 static void imx_uart_start_rx(struct uart_port *port)
402 {
403 struct imx_port *sport = (struct imx_port *)port;
404 unsigned int ucr1, ucr2;
405
406 ucr1 = imx_uart_readl(sport, UCR1);
407 ucr2 = imx_uart_readl(sport, UCR2);
408
409 ucr2 |= UCR2_RXEN;
410
411 if (sport->dma_is_enabled) {
412 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
413 } else {
414 ucr1 |= UCR1_RRDYEN;
415 ucr2 |= UCR2_ATEN;
416 }
417
418 /* Write UCR2 first as it includes RXEN */
419 imx_uart_writel(sport, ucr2, UCR2);
420 imx_uart_writel(sport, ucr1, UCR1);
421 }
422
423 /* called with port.lock taken and irqs off */
imx_uart_stop_tx(struct uart_port * port)424 static void imx_uart_stop_tx(struct uart_port *port)
425 {
426 struct imx_port *sport = (struct imx_port *)port;
427 u32 ucr1, ucr4, usr2;
428
429 if (sport->tx_state == OFF)
430 return;
431
432 /*
433 * We are maybe in the SMP context, so if the DMA TX thread is running
434 * on other cpu, we have to wait for it to finish.
435 */
436 if (sport->dma_is_txing)
437 return;
438
439 ucr1 = imx_uart_readl(sport, UCR1);
440 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
441
442 usr2 = imx_uart_readl(sport, USR2);
443 if (!(usr2 & USR2_TXDC)) {
444 /* The shifter is still busy, so retry once TC triggers */
445 return;
446 }
447
448 ucr4 = imx_uart_readl(sport, UCR4);
449 ucr4 &= ~UCR4_TCEN;
450 imx_uart_writel(sport, ucr4, UCR4);
451
452 /* in rs485 mode disable transmitter */
453 if (port->rs485.flags & SER_RS485_ENABLED) {
454 if (sport->tx_state == SEND) {
455 sport->tx_state = WAIT_AFTER_SEND;
456 start_hrtimer_ms(&sport->trigger_stop_tx,
457 port->rs485.delay_rts_after_send);
458 return;
459 }
460
461 if (sport->tx_state == WAIT_AFTER_RTS ||
462 sport->tx_state == WAIT_AFTER_SEND) {
463 u32 ucr2;
464
465 hrtimer_try_to_cancel(&sport->trigger_start_tx);
466
467 ucr2 = imx_uart_readl(sport, UCR2);
468 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
469 imx_uart_rts_active(sport, &ucr2);
470 else
471 imx_uart_rts_inactive(sport, &ucr2);
472 imx_uart_writel(sport, ucr2, UCR2);
473
474 imx_uart_start_rx(port);
475
476 sport->tx_state = OFF;
477 }
478 } else {
479 sport->tx_state = OFF;
480 }
481 }
482
483 /* called with port.lock taken and irqs off */
imx_uart_stop_rx(struct uart_port * port)484 static void imx_uart_stop_rx(struct uart_port *port)
485 {
486 struct imx_port *sport = (struct imx_port *)port;
487 u32 ucr1, ucr2;
488
489 ucr1 = imx_uart_readl(sport, UCR1);
490 ucr2 = imx_uart_readl(sport, UCR2);
491
492 if (sport->dma_is_enabled) {
493 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
494 } else {
495 ucr1 &= ~UCR1_RRDYEN;
496 ucr2 &= ~UCR2_ATEN;
497 }
498 imx_uart_writel(sport, ucr1, UCR1);
499
500 ucr2 &= ~UCR2_RXEN;
501 imx_uart_writel(sport, ucr2, UCR2);
502 }
503
504 /* called with port.lock taken and irqs off */
imx_uart_enable_ms(struct uart_port * port)505 static void imx_uart_enable_ms(struct uart_port *port)
506 {
507 struct imx_port *sport = (struct imx_port *)port;
508
509 mod_timer(&sport->timer, jiffies);
510
511 mctrl_gpio_enable_ms(sport->gpios);
512 }
513
514 static void imx_uart_dma_tx(struct imx_port *sport);
515
516 /* called with port.lock taken and irqs off */
imx_uart_transmit_buffer(struct imx_port * sport)517 static inline void imx_uart_transmit_buffer(struct imx_port *sport)
518 {
519 struct circ_buf *xmit = &sport->port.state->xmit;
520
521 if (sport->port.x_char) {
522 /* Send next char */
523 imx_uart_writel(sport, sport->port.x_char, URTX0);
524 sport->port.icount.tx++;
525 sport->port.x_char = 0;
526 return;
527 }
528
529 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
530 imx_uart_stop_tx(&sport->port);
531 return;
532 }
533
534 if (sport->dma_is_enabled) {
535 u32 ucr1;
536 /*
537 * We've just sent a X-char Ensure the TX DMA is enabled
538 * and the TX IRQ is disabled.
539 **/
540 ucr1 = imx_uart_readl(sport, UCR1);
541 ucr1 &= ~UCR1_TRDYEN;
542 if (sport->dma_is_txing) {
543 ucr1 |= UCR1_TXDMAEN;
544 imx_uart_writel(sport, ucr1, UCR1);
545 } else {
546 imx_uart_writel(sport, ucr1, UCR1);
547 imx_uart_dma_tx(sport);
548 }
549
550 return;
551 }
552
553 while (!uart_circ_empty(xmit) &&
554 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) {
555 /* send xmit->buf[xmit->tail]
556 * out the port here */
557 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0);
558 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
559 sport->port.icount.tx++;
560 }
561
562 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
563 uart_write_wakeup(&sport->port);
564
565 if (uart_circ_empty(xmit))
566 imx_uart_stop_tx(&sport->port);
567 }
568
imx_uart_dma_tx_callback(void * data)569 static void imx_uart_dma_tx_callback(void *data)
570 {
571 struct imx_port *sport = data;
572 struct scatterlist *sgl = &sport->tx_sgl[0];
573 struct circ_buf *xmit = &sport->port.state->xmit;
574 unsigned long flags;
575 u32 ucr1;
576
577 spin_lock_irqsave(&sport->port.lock, flags);
578
579 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
580
581 ucr1 = imx_uart_readl(sport, UCR1);
582 ucr1 &= ~UCR1_TXDMAEN;
583 imx_uart_writel(sport, ucr1, UCR1);
584
585 /* update the stat */
586 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
587 sport->port.icount.tx += sport->tx_bytes;
588
589 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
590
591 sport->dma_is_txing = 0;
592
593 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
594 uart_write_wakeup(&sport->port);
595
596 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
597 imx_uart_dma_tx(sport);
598 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
599 u32 ucr4 = imx_uart_readl(sport, UCR4);
600 ucr4 |= UCR4_TCEN;
601 imx_uart_writel(sport, ucr4, UCR4);
602 }
603
604 spin_unlock_irqrestore(&sport->port.lock, flags);
605 }
606
607 /* called with port.lock taken and irqs off */
imx_uart_dma_tx(struct imx_port * sport)608 static void imx_uart_dma_tx(struct imx_port *sport)
609 {
610 struct circ_buf *xmit = &sport->port.state->xmit;
611 struct scatterlist *sgl = sport->tx_sgl;
612 struct dma_async_tx_descriptor *desc;
613 struct dma_chan *chan = sport->dma_chan_tx;
614 struct device *dev = sport->port.dev;
615 u32 ucr1, ucr4;
616 int ret;
617
618 if (sport->dma_is_txing)
619 return;
620
621 ucr4 = imx_uart_readl(sport, UCR4);
622 ucr4 &= ~UCR4_TCEN;
623 imx_uart_writel(sport, ucr4, UCR4);
624
625 sport->tx_bytes = uart_circ_chars_pending(xmit);
626
627 if (xmit->tail < xmit->head || xmit->head == 0) {
628 sport->dma_tx_nents = 1;
629 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
630 } else {
631 sport->dma_tx_nents = 2;
632 sg_init_table(sgl, 2);
633 sg_set_buf(sgl, xmit->buf + xmit->tail,
634 UART_XMIT_SIZE - xmit->tail);
635 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
636 }
637
638 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
639 if (ret == 0) {
640 dev_err(dev, "DMA mapping error for TX.\n");
641 return;
642 }
643 desc = dmaengine_prep_slave_sg(chan, sgl, ret,
644 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
645 if (!desc) {
646 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
647 DMA_TO_DEVICE);
648 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
649 return;
650 }
651 desc->callback = imx_uart_dma_tx_callback;
652 desc->callback_param = sport;
653
654 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
655 uart_circ_chars_pending(xmit));
656
657 ucr1 = imx_uart_readl(sport, UCR1);
658 ucr1 |= UCR1_TXDMAEN;
659 imx_uart_writel(sport, ucr1, UCR1);
660
661 /* fire it */
662 sport->dma_is_txing = 1;
663 dmaengine_submit(desc);
664 dma_async_issue_pending(chan);
665 return;
666 }
667
668 /* called with port.lock taken and irqs off */
imx_uart_start_tx(struct uart_port * port)669 static void imx_uart_start_tx(struct uart_port *port)
670 {
671 struct imx_port *sport = (struct imx_port *)port;
672 u32 ucr1;
673
674 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit))
675 return;
676
677 /*
678 * We cannot simply do nothing here if sport->tx_state == SEND already
679 * because UCR1_TXMPTYEN might already have been cleared in
680 * imx_uart_stop_tx(), but tx_state is still SEND.
681 */
682
683 if (port->rs485.flags & SER_RS485_ENABLED) {
684 if (sport->tx_state == OFF) {
685 u32 ucr2 = imx_uart_readl(sport, UCR2);
686 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
687 imx_uart_rts_active(sport, &ucr2);
688 else
689 imx_uart_rts_inactive(sport, &ucr2);
690 imx_uart_writel(sport, ucr2, UCR2);
691
692 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
693 imx_uart_stop_rx(port);
694
695 sport->tx_state = WAIT_AFTER_RTS;
696 start_hrtimer_ms(&sport->trigger_start_tx,
697 port->rs485.delay_rts_before_send);
698 return;
699 }
700
701 if (sport->tx_state == WAIT_AFTER_SEND
702 || sport->tx_state == WAIT_AFTER_RTS) {
703
704 hrtimer_try_to_cancel(&sport->trigger_stop_tx);
705
706 /*
707 * Enable transmitter and shifter empty irq only if DMA
708 * is off. In the DMA case this is done in the
709 * tx-callback.
710 */
711 if (!sport->dma_is_enabled) {
712 u32 ucr4 = imx_uart_readl(sport, UCR4);
713 ucr4 |= UCR4_TCEN;
714 imx_uart_writel(sport, ucr4, UCR4);
715 }
716
717 sport->tx_state = SEND;
718 }
719 } else {
720 sport->tx_state = SEND;
721 }
722
723 if (!sport->dma_is_enabled) {
724 ucr1 = imx_uart_readl(sport, UCR1);
725 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
726 }
727
728 if (sport->dma_is_enabled) {
729 if (sport->port.x_char) {
730 /* We have X-char to send, so enable TX IRQ and
731 * disable TX DMA to let TX interrupt to send X-char */
732 ucr1 = imx_uart_readl(sport, UCR1);
733 ucr1 &= ~UCR1_TXDMAEN;
734 ucr1 |= UCR1_TRDYEN;
735 imx_uart_writel(sport, ucr1, UCR1);
736 return;
737 }
738
739 if (!uart_circ_empty(&port->state->xmit) &&
740 !uart_tx_stopped(port))
741 imx_uart_dma_tx(sport);
742 return;
743 }
744 }
745
__imx_uart_rtsint(int irq,void * dev_id)746 static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id)
747 {
748 struct imx_port *sport = dev_id;
749 u32 usr1;
750
751 imx_uart_writel(sport, USR1_RTSD, USR1);
752 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
753 uart_handle_cts_change(&sport->port, !!usr1);
754 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
755
756 return IRQ_HANDLED;
757 }
758
imx_uart_rtsint(int irq,void * dev_id)759 static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
760 {
761 struct imx_port *sport = dev_id;
762 irqreturn_t ret;
763
764 spin_lock(&sport->port.lock);
765
766 ret = __imx_uart_rtsint(irq, dev_id);
767
768 spin_unlock(&sport->port.lock);
769
770 return ret;
771 }
772
imx_uart_txint(int irq,void * dev_id)773 static irqreturn_t imx_uart_txint(int irq, void *dev_id)
774 {
775 struct imx_port *sport = dev_id;
776
777 spin_lock(&sport->port.lock);
778 imx_uart_transmit_buffer(sport);
779 spin_unlock(&sport->port.lock);
780 return IRQ_HANDLED;
781 }
782
__imx_uart_rxint(int irq,void * dev_id)783 static irqreturn_t __imx_uart_rxint(int irq, void *dev_id)
784 {
785 struct imx_port *sport = dev_id;
786 unsigned int rx, flg, ignored = 0;
787 struct tty_port *port = &sport->port.state->port;
788
789 while (imx_uart_readl(sport, USR2) & USR2_RDR) {
790 u32 usr2;
791
792 flg = TTY_NORMAL;
793 sport->port.icount.rx++;
794
795 rx = imx_uart_readl(sport, URXD0);
796
797 usr2 = imx_uart_readl(sport, USR2);
798 if (usr2 & USR2_BRCD) {
799 imx_uart_writel(sport, USR2_BRCD, USR2);
800 if (uart_handle_break(&sport->port))
801 continue;
802 }
803
804 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
805 continue;
806
807 if (unlikely(rx & URXD_ERR)) {
808 if (rx & URXD_BRK)
809 sport->port.icount.brk++;
810 else if (rx & URXD_PRERR)
811 sport->port.icount.parity++;
812 else if (rx & URXD_FRMERR)
813 sport->port.icount.frame++;
814 if (rx & URXD_OVRRUN)
815 sport->port.icount.overrun++;
816
817 if (rx & sport->port.ignore_status_mask) {
818 if (++ignored > 100)
819 goto out;
820 continue;
821 }
822
823 rx &= (sport->port.read_status_mask | 0xFF);
824
825 if (rx & URXD_BRK)
826 flg = TTY_BREAK;
827 else if (rx & URXD_PRERR)
828 flg = TTY_PARITY;
829 else if (rx & URXD_FRMERR)
830 flg = TTY_FRAME;
831 if (rx & URXD_OVRRUN)
832 flg = TTY_OVERRUN;
833
834 sport->port.sysrq = 0;
835 }
836
837 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
838 goto out;
839
840 if (tty_insert_flip_char(port, rx, flg) == 0)
841 sport->port.icount.buf_overrun++;
842 }
843
844 out:
845 tty_flip_buffer_push(port);
846
847 return IRQ_HANDLED;
848 }
849
imx_uart_rxint(int irq,void * dev_id)850 static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
851 {
852 struct imx_port *sport = dev_id;
853 irqreturn_t ret;
854
855 spin_lock(&sport->port.lock);
856
857 ret = __imx_uart_rxint(irq, dev_id);
858
859 spin_unlock(&sport->port.lock);
860
861 return ret;
862 }
863
864 static void imx_uart_clear_rx_errors(struct imx_port *sport);
865
866 /*
867 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
868 */
imx_uart_get_hwmctrl(struct imx_port * sport)869 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
870 {
871 unsigned int tmp = TIOCM_DSR;
872 unsigned usr1 = imx_uart_readl(sport, USR1);
873 unsigned usr2 = imx_uart_readl(sport, USR2);
874
875 if (usr1 & USR1_RTSS)
876 tmp |= TIOCM_CTS;
877
878 /* in DCE mode DCDIN is always 0 */
879 if (!(usr2 & USR2_DCDIN))
880 tmp |= TIOCM_CAR;
881
882 if (sport->dte_mode)
883 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
884 tmp |= TIOCM_RI;
885
886 return tmp;
887 }
888
889 /*
890 * Handle any change of modem status signal since we were last called.
891 */
imx_uart_mctrl_check(struct imx_port * sport)892 static void imx_uart_mctrl_check(struct imx_port *sport)
893 {
894 unsigned int status, changed;
895
896 status = imx_uart_get_hwmctrl(sport);
897 changed = status ^ sport->old_status;
898
899 if (changed == 0)
900 return;
901
902 sport->old_status = status;
903
904 if (changed & TIOCM_RI && status & TIOCM_RI)
905 sport->port.icount.rng++;
906 if (changed & TIOCM_DSR)
907 sport->port.icount.dsr++;
908 if (changed & TIOCM_CAR)
909 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
910 if (changed & TIOCM_CTS)
911 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
912
913 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
914 }
915
imx_uart_int(int irq,void * dev_id)916 static irqreturn_t imx_uart_int(int irq, void *dev_id)
917 {
918 struct imx_port *sport = dev_id;
919 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
920 irqreturn_t ret = IRQ_NONE;
921
922 spin_lock(&sport->port.lock);
923
924 usr1 = imx_uart_readl(sport, USR1);
925 usr2 = imx_uart_readl(sport, USR2);
926 ucr1 = imx_uart_readl(sport, UCR1);
927 ucr2 = imx_uart_readl(sport, UCR2);
928 ucr3 = imx_uart_readl(sport, UCR3);
929 ucr4 = imx_uart_readl(sport, UCR4);
930
931 /*
932 * Even if a condition is true that can trigger an irq only handle it if
933 * the respective irq source is enabled. This prevents some undesired
934 * actions, for example if a character that sits in the RX FIFO and that
935 * should be fetched via DMA is tried to be fetched using PIO. Or the
936 * receiver is currently off and so reading from URXD0 results in an
937 * exception. So just mask the (raw) status bits for disabled irqs.
938 */
939 if ((ucr1 & UCR1_RRDYEN) == 0)
940 usr1 &= ~USR1_RRDY;
941 if ((ucr2 & UCR2_ATEN) == 0)
942 usr1 &= ~USR1_AGTIM;
943 if ((ucr1 & UCR1_TRDYEN) == 0)
944 usr1 &= ~USR1_TRDY;
945 if ((ucr4 & UCR4_TCEN) == 0)
946 usr2 &= ~USR2_TXDC;
947 if ((ucr3 & UCR3_DTRDEN) == 0)
948 usr1 &= ~USR1_DTRD;
949 if ((ucr1 & UCR1_RTSDEN) == 0)
950 usr1 &= ~USR1_RTSD;
951 if ((ucr3 & UCR3_AWAKEN) == 0)
952 usr1 &= ~USR1_AWAKE;
953 if ((ucr4 & UCR4_OREN) == 0)
954 usr2 &= ~USR2_ORE;
955
956 if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
957 imx_uart_writel(sport, USR1_AGTIM, USR1);
958
959 __imx_uart_rxint(irq, dev_id);
960 ret = IRQ_HANDLED;
961 }
962
963 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
964 imx_uart_transmit_buffer(sport);
965 ret = IRQ_HANDLED;
966 }
967
968 if (usr1 & USR1_DTRD) {
969 imx_uart_writel(sport, USR1_DTRD, USR1);
970
971 imx_uart_mctrl_check(sport);
972
973 ret = IRQ_HANDLED;
974 }
975
976 if (usr1 & USR1_RTSD) {
977 __imx_uart_rtsint(irq, dev_id);
978 ret = IRQ_HANDLED;
979 }
980
981 if (usr1 & USR1_AWAKE) {
982 imx_uart_writel(sport, USR1_AWAKE, USR1);
983 ret = IRQ_HANDLED;
984 }
985
986 if (usr2 & USR2_ORE) {
987 sport->port.icount.overrun++;
988 imx_uart_writel(sport, USR2_ORE, USR2);
989 ret = IRQ_HANDLED;
990 }
991
992 spin_unlock(&sport->port.lock);
993
994 return ret;
995 }
996
997 /*
998 * Return TIOCSER_TEMT when transmitter is not busy.
999 */
imx_uart_tx_empty(struct uart_port * port)1000 static unsigned int imx_uart_tx_empty(struct uart_port *port)
1001 {
1002 struct imx_port *sport = (struct imx_port *)port;
1003 unsigned int ret;
1004
1005 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1006
1007 /* If the TX DMA is working, return 0. */
1008 if (sport->dma_is_txing)
1009 ret = 0;
1010
1011 return ret;
1012 }
1013
1014 /* called with port.lock taken and irqs off */
imx_uart_get_mctrl(struct uart_port * port)1015 static unsigned int imx_uart_get_mctrl(struct uart_port *port)
1016 {
1017 struct imx_port *sport = (struct imx_port *)port;
1018 unsigned int ret = imx_uart_get_hwmctrl(sport);
1019
1020 mctrl_gpio_get(sport->gpios, &ret);
1021
1022 return ret;
1023 }
1024
1025 /* called with port.lock taken and irqs off */
imx_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)1026 static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1027 {
1028 struct imx_port *sport = (struct imx_port *)port;
1029 u32 ucr3, uts;
1030
1031 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
1032 u32 ucr2;
1033
1034 /*
1035 * Turn off autoRTS if RTS is lowered and restore autoRTS
1036 * setting if RTS is raised.
1037 */
1038 ucr2 = imx_uart_readl(sport, UCR2);
1039 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
1040 if (mctrl & TIOCM_RTS) {
1041 ucr2 |= UCR2_CTS;
1042 /*
1043 * UCR2_IRTS is unset if and only if the port is
1044 * configured for CRTSCTS, so we use inverted UCR2_IRTS
1045 * to get the state to restore to.
1046 */
1047 if (!(ucr2 & UCR2_IRTS))
1048 ucr2 |= UCR2_CTSC;
1049 }
1050 imx_uart_writel(sport, ucr2, UCR2);
1051 }
1052
1053 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
1054 if (!(mctrl & TIOCM_DTR))
1055 ucr3 |= UCR3_DSR;
1056 imx_uart_writel(sport, ucr3, UCR3);
1057
1058 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
1059 if (mctrl & TIOCM_LOOP)
1060 uts |= UTS_LOOP;
1061 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1062
1063 mctrl_gpio_set(sport->gpios, mctrl);
1064 }
1065
1066 /*
1067 * Interrupts always disabled.
1068 */
imx_uart_break_ctl(struct uart_port * port,int break_state)1069 static void imx_uart_break_ctl(struct uart_port *port, int break_state)
1070 {
1071 struct imx_port *sport = (struct imx_port *)port;
1072 unsigned long flags;
1073 u32 ucr1;
1074
1075 spin_lock_irqsave(&sport->port.lock, flags);
1076
1077 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1078
1079 if (break_state != 0)
1080 ucr1 |= UCR1_SNDBRK;
1081
1082 imx_uart_writel(sport, ucr1, UCR1);
1083
1084 spin_unlock_irqrestore(&sport->port.lock, flags);
1085 }
1086
1087 /*
1088 * This is our per-port timeout handler, for checking the
1089 * modem status signals.
1090 */
imx_uart_timeout(struct timer_list * t)1091 static void imx_uart_timeout(struct timer_list *t)
1092 {
1093 struct imx_port *sport = from_timer(sport, t, timer);
1094 unsigned long flags;
1095
1096 if (sport->port.state) {
1097 spin_lock_irqsave(&sport->port.lock, flags);
1098 imx_uart_mctrl_check(sport);
1099 spin_unlock_irqrestore(&sport->port.lock, flags);
1100
1101 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1102 }
1103 }
1104
1105 /*
1106 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1107 * [1] the RX DMA buffer is full.
1108 * [2] the aging timer expires
1109 *
1110 * Condition [2] is triggered when a character has been sitting in the FIFO
1111 * for at least 8 byte durations.
1112 */
imx_uart_dma_rx_callback(void * data)1113 static void imx_uart_dma_rx_callback(void *data)
1114 {
1115 struct imx_port *sport = data;
1116 struct dma_chan *chan = sport->dma_chan_rx;
1117 struct scatterlist *sgl = &sport->rx_sgl;
1118 struct tty_port *port = &sport->port.state->port;
1119 struct dma_tx_state state;
1120 struct circ_buf *rx_ring = &sport->rx_ring;
1121 enum dma_status status;
1122 unsigned int w_bytes = 0;
1123 unsigned int r_bytes;
1124 unsigned int bd_size;
1125
1126 status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1127
1128 if (status == DMA_ERROR) {
1129 imx_uart_clear_rx_errors(sport);
1130 return;
1131 }
1132
1133 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1134
1135 /*
1136 * The state-residue variable represents the empty space
1137 * relative to the entire buffer. Taking this in consideration
1138 * the head is always calculated base on the buffer total
1139 * length - DMA transaction residue. The UART script from the
1140 * SDMA firmware will jump to the next buffer descriptor,
1141 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1142 * Taking this in consideration the tail is always at the
1143 * beginning of the buffer descriptor that contains the head.
1144 */
1145
1146 /* Calculate the head */
1147 rx_ring->head = sg_dma_len(sgl) - state.residue;
1148
1149 /* Calculate the tail. */
1150 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1151 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1152
1153 if (rx_ring->head <= sg_dma_len(sgl) &&
1154 rx_ring->head > rx_ring->tail) {
1155
1156 /* Move data from tail to head */
1157 r_bytes = rx_ring->head - rx_ring->tail;
1158
1159 /* CPU claims ownership of RX DMA buffer */
1160 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1161 DMA_FROM_DEVICE);
1162
1163 w_bytes = tty_insert_flip_string(port,
1164 sport->rx_buf + rx_ring->tail, r_bytes);
1165
1166 /* UART retrieves ownership of RX DMA buffer */
1167 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1168 DMA_FROM_DEVICE);
1169
1170 if (w_bytes != r_bytes)
1171 sport->port.icount.buf_overrun++;
1172
1173 sport->port.icount.rx += w_bytes;
1174 } else {
1175 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1176 WARN_ON(rx_ring->head <= rx_ring->tail);
1177 }
1178 }
1179
1180 if (w_bytes) {
1181 tty_flip_buffer_push(port);
1182 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1183 }
1184 }
1185
1186 /* RX DMA buffer periods */
1187 #define RX_DMA_PERIODS 16
1188 #define RX_BUF_SIZE (RX_DMA_PERIODS * PAGE_SIZE / 4)
1189
imx_uart_start_rx_dma(struct imx_port * sport)1190 static int imx_uart_start_rx_dma(struct imx_port *sport)
1191 {
1192 struct scatterlist *sgl = &sport->rx_sgl;
1193 struct dma_chan *chan = sport->dma_chan_rx;
1194 struct device *dev = sport->port.dev;
1195 struct dma_async_tx_descriptor *desc;
1196 int ret;
1197
1198 sport->rx_ring.head = 0;
1199 sport->rx_ring.tail = 0;
1200 sport->rx_periods = RX_DMA_PERIODS;
1201
1202 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
1203 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1204 if (ret == 0) {
1205 dev_err(dev, "DMA mapping error for RX.\n");
1206 return -EINVAL;
1207 }
1208
1209 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1210 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1211 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1212
1213 if (!desc) {
1214 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1215 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1216 return -EINVAL;
1217 }
1218 desc->callback = imx_uart_dma_rx_callback;
1219 desc->callback_param = sport;
1220
1221 dev_dbg(dev, "RX: prepare for the DMA.\n");
1222 sport->dma_is_rxing = 1;
1223 sport->rx_cookie = dmaengine_submit(desc);
1224 dma_async_issue_pending(chan);
1225 return 0;
1226 }
1227
imx_uart_clear_rx_errors(struct imx_port * sport)1228 static void imx_uart_clear_rx_errors(struct imx_port *sport)
1229 {
1230 struct tty_port *port = &sport->port.state->port;
1231 u32 usr1, usr2;
1232
1233 usr1 = imx_uart_readl(sport, USR1);
1234 usr2 = imx_uart_readl(sport, USR2);
1235
1236 if (usr2 & USR2_BRCD) {
1237 sport->port.icount.brk++;
1238 imx_uart_writel(sport, USR2_BRCD, USR2);
1239 uart_handle_break(&sport->port);
1240 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1241 sport->port.icount.buf_overrun++;
1242 tty_flip_buffer_push(port);
1243 } else {
1244 if (usr1 & USR1_FRAMERR) {
1245 sport->port.icount.frame++;
1246 imx_uart_writel(sport, USR1_FRAMERR, USR1);
1247 } else if (usr1 & USR1_PARITYERR) {
1248 sport->port.icount.parity++;
1249 imx_uart_writel(sport, USR1_PARITYERR, USR1);
1250 }
1251 }
1252
1253 if (usr2 & USR2_ORE) {
1254 sport->port.icount.overrun++;
1255 imx_uart_writel(sport, USR2_ORE, USR2);
1256 }
1257
1258 }
1259
1260 #define TXTL_DEFAULT 2 /* reset default */
1261 #define RXTL_DEFAULT 1 /* reset default */
1262 #define TXTL_DMA 8 /* DMA burst setting */
1263 #define RXTL_DMA 9 /* DMA burst setting */
1264
imx_uart_setup_ufcr(struct imx_port * sport,unsigned char txwl,unsigned char rxwl)1265 static void imx_uart_setup_ufcr(struct imx_port *sport,
1266 unsigned char txwl, unsigned char rxwl)
1267 {
1268 unsigned int val;
1269
1270 /* set receiver / transmitter trigger level */
1271 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1272 val |= txwl << UFCR_TXTL_SHF | rxwl;
1273 imx_uart_writel(sport, val, UFCR);
1274 }
1275
imx_uart_dma_exit(struct imx_port * sport)1276 static void imx_uart_dma_exit(struct imx_port *sport)
1277 {
1278 if (sport->dma_chan_rx) {
1279 dmaengine_terminate_sync(sport->dma_chan_rx);
1280 dma_release_channel(sport->dma_chan_rx);
1281 sport->dma_chan_rx = NULL;
1282 sport->rx_cookie = -EINVAL;
1283 kfree(sport->rx_buf);
1284 sport->rx_buf = NULL;
1285 }
1286
1287 if (sport->dma_chan_tx) {
1288 dmaengine_terminate_sync(sport->dma_chan_tx);
1289 dma_release_channel(sport->dma_chan_tx);
1290 sport->dma_chan_tx = NULL;
1291 }
1292 }
1293
imx_uart_dma_init(struct imx_port * sport)1294 static int imx_uart_dma_init(struct imx_port *sport)
1295 {
1296 struct dma_slave_config slave_config = {};
1297 struct device *dev = sport->port.dev;
1298 int ret;
1299
1300 /* Prepare for RX : */
1301 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1302 if (!sport->dma_chan_rx) {
1303 dev_dbg(dev, "cannot get the DMA channel.\n");
1304 ret = -EINVAL;
1305 goto err;
1306 }
1307
1308 slave_config.direction = DMA_DEV_TO_MEM;
1309 slave_config.src_addr = sport->port.mapbase + URXD0;
1310 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1311 /* one byte less than the watermark level to enable the aging timer */
1312 slave_config.src_maxburst = RXTL_DMA - 1;
1313 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1314 if (ret) {
1315 dev_err(dev, "error in RX dma configuration.\n");
1316 goto err;
1317 }
1318
1319 sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL);
1320 if (!sport->rx_buf) {
1321 ret = -ENOMEM;
1322 goto err;
1323 }
1324 sport->rx_ring.buf = sport->rx_buf;
1325
1326 /* Prepare for TX : */
1327 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1328 if (!sport->dma_chan_tx) {
1329 dev_err(dev, "cannot get the TX DMA channel!\n");
1330 ret = -EINVAL;
1331 goto err;
1332 }
1333
1334 slave_config.direction = DMA_MEM_TO_DEV;
1335 slave_config.dst_addr = sport->port.mapbase + URTX0;
1336 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1337 slave_config.dst_maxburst = TXTL_DMA;
1338 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1339 if (ret) {
1340 dev_err(dev, "error in TX dma configuration.");
1341 goto err;
1342 }
1343
1344 return 0;
1345 err:
1346 imx_uart_dma_exit(sport);
1347 return ret;
1348 }
1349
imx_uart_enable_dma(struct imx_port * sport)1350 static void imx_uart_enable_dma(struct imx_port *sport)
1351 {
1352 u32 ucr1;
1353
1354 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1355
1356 /* set UCR1 */
1357 ucr1 = imx_uart_readl(sport, UCR1);
1358 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1359 imx_uart_writel(sport, ucr1, UCR1);
1360
1361 sport->dma_is_enabled = 1;
1362 }
1363
imx_uart_disable_dma(struct imx_port * sport)1364 static void imx_uart_disable_dma(struct imx_port *sport)
1365 {
1366 u32 ucr1;
1367
1368 /* clear UCR1 */
1369 ucr1 = imx_uart_readl(sport, UCR1);
1370 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1371 imx_uart_writel(sport, ucr1, UCR1);
1372
1373 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1374
1375 sport->dma_is_enabled = 0;
1376 }
1377
1378 /* half the RX buffer size */
1379 #define CTSTL 16
1380
imx_uart_startup(struct uart_port * port)1381 static int imx_uart_startup(struct uart_port *port)
1382 {
1383 struct imx_port *sport = (struct imx_port *)port;
1384 int retval, i;
1385 unsigned long flags;
1386 int dma_is_inited = 0;
1387 u32 ucr1, ucr2, ucr3, ucr4;
1388
1389 retval = clk_prepare_enable(sport->clk_per);
1390 if (retval)
1391 return retval;
1392 retval = clk_prepare_enable(sport->clk_ipg);
1393 if (retval) {
1394 clk_disable_unprepare(sport->clk_per);
1395 return retval;
1396 }
1397
1398 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1399
1400 /* disable the DREN bit (Data Ready interrupt enable) before
1401 * requesting IRQs
1402 */
1403 ucr4 = imx_uart_readl(sport, UCR4);
1404
1405 /* set the trigger level for CTS */
1406 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1407 ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1408
1409 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1410
1411 /* Can we enable the DMA support? */
1412 if (!uart_console(port) && imx_uart_dma_init(sport) == 0)
1413 dma_is_inited = 1;
1414
1415 spin_lock_irqsave(&sport->port.lock, flags);
1416 /* Reset fifo's and state machines */
1417 i = 100;
1418
1419 ucr2 = imx_uart_readl(sport, UCR2);
1420 ucr2 &= ~UCR2_SRST;
1421 imx_uart_writel(sport, ucr2, UCR2);
1422
1423 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1424 udelay(1);
1425
1426 /*
1427 * Finally, clear and enable interrupts
1428 */
1429 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1430 imx_uart_writel(sport, USR2_ORE, USR2);
1431
1432 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1433 ucr1 |= UCR1_UARTEN;
1434 if (sport->have_rtscts)
1435 ucr1 |= UCR1_RTSDEN;
1436
1437 imx_uart_writel(sport, ucr1, UCR1);
1438
1439 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR);
1440 if (!sport->dma_is_enabled)
1441 ucr4 |= UCR4_OREN;
1442 if (sport->inverted_rx)
1443 ucr4 |= UCR4_INVR;
1444 imx_uart_writel(sport, ucr4, UCR4);
1445
1446 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT;
1447 /*
1448 * configure tx polarity before enabling tx
1449 */
1450 if (sport->inverted_tx)
1451 ucr3 |= UCR3_INVT;
1452
1453 if (!imx_uart_is_imx1(sport)) {
1454 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1455
1456 if (sport->dte_mode)
1457 /* disable broken interrupts */
1458 ucr3 &= ~(UCR3_RI | UCR3_DCD);
1459 }
1460 imx_uart_writel(sport, ucr3, UCR3);
1461
1462 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1463 ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1464 if (!sport->have_rtscts)
1465 ucr2 |= UCR2_IRTS;
1466 /*
1467 * make sure the edge sensitive RTS-irq is disabled,
1468 * we're using RTSD instead.
1469 */
1470 if (!imx_uart_is_imx1(sport))
1471 ucr2 &= ~UCR2_RTSEN;
1472 imx_uart_writel(sport, ucr2, UCR2);
1473
1474 /*
1475 * Enable modem status interrupts
1476 */
1477 imx_uart_enable_ms(&sport->port);
1478
1479 if (dma_is_inited) {
1480 imx_uart_enable_dma(sport);
1481 imx_uart_start_rx_dma(sport);
1482 } else {
1483 ucr1 = imx_uart_readl(sport, UCR1);
1484 ucr1 |= UCR1_RRDYEN;
1485 imx_uart_writel(sport, ucr1, UCR1);
1486
1487 ucr2 = imx_uart_readl(sport, UCR2);
1488 ucr2 |= UCR2_ATEN;
1489 imx_uart_writel(sport, ucr2, UCR2);
1490 }
1491
1492 spin_unlock_irqrestore(&sport->port.lock, flags);
1493
1494 return 0;
1495 }
1496
imx_uart_shutdown(struct uart_port * port)1497 static void imx_uart_shutdown(struct uart_port *port)
1498 {
1499 struct imx_port *sport = (struct imx_port *)port;
1500 unsigned long flags;
1501 u32 ucr1, ucr2, ucr4;
1502
1503 if (sport->dma_is_enabled) {
1504 dmaengine_terminate_sync(sport->dma_chan_tx);
1505 if (sport->dma_is_txing) {
1506 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1507 sport->dma_tx_nents, DMA_TO_DEVICE);
1508 sport->dma_is_txing = 0;
1509 }
1510 dmaengine_terminate_sync(sport->dma_chan_rx);
1511 if (sport->dma_is_rxing) {
1512 dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1513 1, DMA_FROM_DEVICE);
1514 sport->dma_is_rxing = 0;
1515 }
1516
1517 spin_lock_irqsave(&sport->port.lock, flags);
1518 imx_uart_stop_tx(port);
1519 imx_uart_stop_rx(port);
1520 imx_uart_disable_dma(sport);
1521 spin_unlock_irqrestore(&sport->port.lock, flags);
1522 imx_uart_dma_exit(sport);
1523 }
1524
1525 mctrl_gpio_disable_ms(sport->gpios);
1526
1527 spin_lock_irqsave(&sport->port.lock, flags);
1528 ucr2 = imx_uart_readl(sport, UCR2);
1529 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
1530 imx_uart_writel(sport, ucr2, UCR2);
1531 spin_unlock_irqrestore(&sport->port.lock, flags);
1532
1533 /*
1534 * Stop our timer.
1535 */
1536 del_timer_sync(&sport->timer);
1537
1538 /*
1539 * Disable all interrupts, port and break condition.
1540 */
1541
1542 spin_lock_irqsave(&sport->port.lock, flags);
1543
1544 ucr1 = imx_uart_readl(sport, UCR1);
1545 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN);
1546 imx_uart_writel(sport, ucr1, UCR1);
1547
1548 ucr4 = imx_uart_readl(sport, UCR4);
1549 ucr4 &= ~(UCR4_OREN | UCR4_TCEN);
1550 imx_uart_writel(sport, ucr4, UCR4);
1551
1552 spin_unlock_irqrestore(&sport->port.lock, flags);
1553
1554 clk_disable_unprepare(sport->clk_per);
1555 clk_disable_unprepare(sport->clk_ipg);
1556 }
1557
1558 /* called with port.lock taken and irqs off */
imx_uart_flush_buffer(struct uart_port * port)1559 static void imx_uart_flush_buffer(struct uart_port *port)
1560 {
1561 struct imx_port *sport = (struct imx_port *)port;
1562 struct scatterlist *sgl = &sport->tx_sgl[0];
1563 u32 ucr2;
1564 int i = 100, ubir, ubmr, uts;
1565
1566 if (!sport->dma_chan_tx)
1567 return;
1568
1569 sport->tx_bytes = 0;
1570 dmaengine_terminate_all(sport->dma_chan_tx);
1571 if (sport->dma_is_txing) {
1572 u32 ucr1;
1573
1574 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1575 DMA_TO_DEVICE);
1576 ucr1 = imx_uart_readl(sport, UCR1);
1577 ucr1 &= ~UCR1_TXDMAEN;
1578 imx_uart_writel(sport, ucr1, UCR1);
1579 sport->dma_is_txing = 0;
1580 }
1581
1582 /*
1583 * According to the Reference Manual description of the UART SRST bit:
1584 *
1585 * "Reset the transmit and receive state machines,
1586 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1587 * and UTS[6-3]".
1588 *
1589 * We don't need to restore the old values from USR1, USR2, URXD and
1590 * UTXD. UBRC is read only, so only save/restore the other three
1591 * registers.
1592 */
1593 ubir = imx_uart_readl(sport, UBIR);
1594 ubmr = imx_uart_readl(sport, UBMR);
1595 uts = imx_uart_readl(sport, IMX21_UTS);
1596
1597 ucr2 = imx_uart_readl(sport, UCR2);
1598 ucr2 &= ~UCR2_SRST;
1599 imx_uart_writel(sport, ucr2, UCR2);
1600
1601 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1602 udelay(1);
1603
1604 /* Restore the registers */
1605 imx_uart_writel(sport, ubir, UBIR);
1606 imx_uart_writel(sport, ubmr, UBMR);
1607 imx_uart_writel(sport, uts, IMX21_UTS);
1608 }
1609
1610 static void
imx_uart_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)1611 imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1612 struct ktermios *old)
1613 {
1614 struct imx_port *sport = (struct imx_port *)port;
1615 unsigned long flags;
1616 u32 ucr2, old_ucr2, ufcr;
1617 unsigned int baud, quot;
1618 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1619 unsigned long div;
1620 unsigned long num, denom, old_ubir, old_ubmr;
1621 uint64_t tdiv64;
1622
1623 /*
1624 * We only support CS7 and CS8.
1625 */
1626 while ((termios->c_cflag & CSIZE) != CS7 &&
1627 (termios->c_cflag & CSIZE) != CS8) {
1628 termios->c_cflag &= ~CSIZE;
1629 termios->c_cflag |= old_csize;
1630 old_csize = CS8;
1631 }
1632
1633 del_timer_sync(&sport->timer);
1634
1635 /*
1636 * Ask the core to calculate the divisor for us.
1637 */
1638 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1639 quot = uart_get_divisor(port, baud);
1640
1641 spin_lock_irqsave(&sport->port.lock, flags);
1642
1643 /*
1644 * Read current UCR2 and save it for future use, then clear all the bits
1645 * except those we will or may need to preserve.
1646 */
1647 old_ucr2 = imx_uart_readl(sport, UCR2);
1648 ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS);
1649
1650 ucr2 |= UCR2_SRST | UCR2_IRTS;
1651 if ((termios->c_cflag & CSIZE) == CS8)
1652 ucr2 |= UCR2_WS;
1653
1654 if (!sport->have_rtscts)
1655 termios->c_cflag &= ~CRTSCTS;
1656
1657 if (port->rs485.flags & SER_RS485_ENABLED) {
1658 /*
1659 * RTS is mandatory for rs485 operation, so keep
1660 * it under manual control and keep transmitter
1661 * disabled.
1662 */
1663 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1664 imx_uart_rts_active(sport, &ucr2);
1665 else
1666 imx_uart_rts_inactive(sport, &ucr2);
1667
1668 } else if (termios->c_cflag & CRTSCTS) {
1669 /*
1670 * Only let receiver control RTS output if we were not requested
1671 * to have RTS inactive (which then should take precedence).
1672 */
1673 if (ucr2 & UCR2_CTS)
1674 ucr2 |= UCR2_CTSC;
1675 }
1676
1677 if (termios->c_cflag & CRTSCTS)
1678 ucr2 &= ~UCR2_IRTS;
1679 if (termios->c_cflag & CSTOPB)
1680 ucr2 |= UCR2_STPB;
1681 if (termios->c_cflag & PARENB) {
1682 ucr2 |= UCR2_PREN;
1683 if (termios->c_cflag & PARODD)
1684 ucr2 |= UCR2_PROE;
1685 }
1686
1687 sport->port.read_status_mask = 0;
1688 if (termios->c_iflag & INPCK)
1689 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1690 if (termios->c_iflag & (BRKINT | PARMRK))
1691 sport->port.read_status_mask |= URXD_BRK;
1692
1693 /*
1694 * Characters to ignore
1695 */
1696 sport->port.ignore_status_mask = 0;
1697 if (termios->c_iflag & IGNPAR)
1698 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1699 if (termios->c_iflag & IGNBRK) {
1700 sport->port.ignore_status_mask |= URXD_BRK;
1701 /*
1702 * If we're ignoring parity and break indicators,
1703 * ignore overruns too (for real raw support).
1704 */
1705 if (termios->c_iflag & IGNPAR)
1706 sport->port.ignore_status_mask |= URXD_OVRRUN;
1707 }
1708
1709 if ((termios->c_cflag & CREAD) == 0)
1710 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1711
1712 /*
1713 * Update the per-port timeout.
1714 */
1715 uart_update_timeout(port, termios->c_cflag, baud);
1716
1717 /* custom-baudrate handling */
1718 div = sport->port.uartclk / (baud * 16);
1719 if (baud == 38400 && quot != div)
1720 baud = sport->port.uartclk / (quot * 16);
1721
1722 div = sport->port.uartclk / (baud * 16);
1723 if (div > 7)
1724 div = 7;
1725 if (!div)
1726 div = 1;
1727
1728 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1729 1 << 16, 1 << 16, &num, &denom);
1730
1731 tdiv64 = sport->port.uartclk;
1732 tdiv64 *= num;
1733 do_div(tdiv64, denom * 16 * div);
1734 tty_termios_encode_baud_rate(termios,
1735 (speed_t)tdiv64, (speed_t)tdiv64);
1736
1737 num -= 1;
1738 denom -= 1;
1739
1740 ufcr = imx_uart_readl(sport, UFCR);
1741 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1742 imx_uart_writel(sport, ufcr, UFCR);
1743
1744 /*
1745 * Two registers below should always be written both and in this
1746 * particular order. One consequence is that we need to check if any of
1747 * them changes and then update both. We do need the check for change
1748 * as even writing the same values seem to "restart"
1749 * transmission/receiving logic in the hardware, that leads to data
1750 * breakage even when rate doesn't in fact change. E.g., user switches
1751 * RTS/CTS handshake and suddenly gets broken bytes.
1752 */
1753 old_ubir = imx_uart_readl(sport, UBIR);
1754 old_ubmr = imx_uart_readl(sport, UBMR);
1755 if (old_ubir != num || old_ubmr != denom) {
1756 imx_uart_writel(sport, num, UBIR);
1757 imx_uart_writel(sport, denom, UBMR);
1758 }
1759
1760 if (!imx_uart_is_imx1(sport))
1761 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1762 IMX21_ONEMS);
1763
1764 imx_uart_writel(sport, ucr2, UCR2);
1765
1766 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1767 imx_uart_enable_ms(&sport->port);
1768
1769 spin_unlock_irqrestore(&sport->port.lock, flags);
1770 }
1771
imx_uart_type(struct uart_port * port)1772 static const char *imx_uart_type(struct uart_port *port)
1773 {
1774 struct imx_port *sport = (struct imx_port *)port;
1775
1776 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1777 }
1778
1779 /*
1780 * Configure/autoconfigure the port.
1781 */
imx_uart_config_port(struct uart_port * port,int flags)1782 static void imx_uart_config_port(struct uart_port *port, int flags)
1783 {
1784 struct imx_port *sport = (struct imx_port *)port;
1785
1786 if (flags & UART_CONFIG_TYPE)
1787 sport->port.type = PORT_IMX;
1788 }
1789
1790 /*
1791 * Verify the new serial_struct (for TIOCSSERIAL).
1792 * The only change we allow are to the flags and type, and
1793 * even then only between PORT_IMX and PORT_UNKNOWN
1794 */
1795 static int
imx_uart_verify_port(struct uart_port * port,struct serial_struct * ser)1796 imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1797 {
1798 struct imx_port *sport = (struct imx_port *)port;
1799 int ret = 0;
1800
1801 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1802 ret = -EINVAL;
1803 if (sport->port.irq != ser->irq)
1804 ret = -EINVAL;
1805 if (ser->io_type != UPIO_MEM)
1806 ret = -EINVAL;
1807 if (sport->port.uartclk / 16 != ser->baud_base)
1808 ret = -EINVAL;
1809 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1810 ret = -EINVAL;
1811 if (sport->port.iobase != ser->port)
1812 ret = -EINVAL;
1813 if (ser->hub6 != 0)
1814 ret = -EINVAL;
1815 return ret;
1816 }
1817
1818 #if defined(CONFIG_CONSOLE_POLL)
1819
imx_uart_poll_init(struct uart_port * port)1820 static int imx_uart_poll_init(struct uart_port *port)
1821 {
1822 struct imx_port *sport = (struct imx_port *)port;
1823 unsigned long flags;
1824 u32 ucr1, ucr2;
1825 int retval;
1826
1827 retval = clk_prepare_enable(sport->clk_ipg);
1828 if (retval)
1829 return retval;
1830 retval = clk_prepare_enable(sport->clk_per);
1831 if (retval)
1832 clk_disable_unprepare(sport->clk_ipg);
1833
1834 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1835
1836 spin_lock_irqsave(&sport->port.lock, flags);
1837
1838 /*
1839 * Be careful about the order of enabling bits here. First enable the
1840 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1841 * This prevents that a character that already sits in the RX fifo is
1842 * triggering an irq but the try to fetch it from there results in an
1843 * exception because UARTEN or RXEN is still off.
1844 */
1845 ucr1 = imx_uart_readl(sport, UCR1);
1846 ucr2 = imx_uart_readl(sport, UCR2);
1847
1848 if (imx_uart_is_imx1(sport))
1849 ucr1 |= IMX1_UCR1_UARTCLKEN;
1850
1851 ucr1 |= UCR1_UARTEN;
1852 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1853
1854 ucr2 |= UCR2_RXEN | UCR2_TXEN;
1855 ucr2 &= ~UCR2_ATEN;
1856
1857 imx_uart_writel(sport, ucr1, UCR1);
1858 imx_uart_writel(sport, ucr2, UCR2);
1859
1860 /* now enable irqs */
1861 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1862 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1863
1864 spin_unlock_irqrestore(&sport->port.lock, flags);
1865
1866 return 0;
1867 }
1868
imx_uart_poll_get_char(struct uart_port * port)1869 static int imx_uart_poll_get_char(struct uart_port *port)
1870 {
1871 struct imx_port *sport = (struct imx_port *)port;
1872 if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1873 return NO_POLL_CHAR;
1874
1875 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
1876 }
1877
imx_uart_poll_put_char(struct uart_port * port,unsigned char c)1878 static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
1879 {
1880 struct imx_port *sport = (struct imx_port *)port;
1881 unsigned int status;
1882
1883 /* drain */
1884 do {
1885 status = imx_uart_readl(sport, USR1);
1886 } while (~status & USR1_TRDY);
1887
1888 /* write */
1889 imx_uart_writel(sport, c, URTX0);
1890
1891 /* flush */
1892 do {
1893 status = imx_uart_readl(sport, USR2);
1894 } while (~status & USR2_TXDC);
1895 }
1896 #endif
1897
1898 /* called with port.lock taken and irqs off or from .probe without locking */
imx_uart_rs485_config(struct uart_port * port,struct serial_rs485 * rs485conf)1899 static int imx_uart_rs485_config(struct uart_port *port,
1900 struct serial_rs485 *rs485conf)
1901 {
1902 struct imx_port *sport = (struct imx_port *)port;
1903 u32 ucr2;
1904
1905 /* RTS is required to control the transmitter */
1906 if (!sport->have_rtscts && !sport->have_rtsgpio)
1907 rs485conf->flags &= ~SER_RS485_ENABLED;
1908
1909 if (rs485conf->flags & SER_RS485_ENABLED) {
1910 /* Enable receiver if low-active RTS signal is requested */
1911 if (sport->have_rtscts && !sport->have_rtsgpio &&
1912 !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
1913 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1914
1915 /* disable transmitter */
1916 ucr2 = imx_uart_readl(sport, UCR2);
1917 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1918 imx_uart_rts_active(sport, &ucr2);
1919 else
1920 imx_uart_rts_inactive(sport, &ucr2);
1921 imx_uart_writel(sport, ucr2, UCR2);
1922 }
1923
1924 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1925 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1926 rs485conf->flags & SER_RS485_RX_DURING_TX)
1927 imx_uart_start_rx(port);
1928
1929 port->rs485 = *rs485conf;
1930
1931 return 0;
1932 }
1933
1934 static const struct uart_ops imx_uart_pops = {
1935 .tx_empty = imx_uart_tx_empty,
1936 .set_mctrl = imx_uart_set_mctrl,
1937 .get_mctrl = imx_uart_get_mctrl,
1938 .stop_tx = imx_uart_stop_tx,
1939 .start_tx = imx_uart_start_tx,
1940 .stop_rx = imx_uart_stop_rx,
1941 .enable_ms = imx_uart_enable_ms,
1942 .break_ctl = imx_uart_break_ctl,
1943 .startup = imx_uart_startup,
1944 .shutdown = imx_uart_shutdown,
1945 .flush_buffer = imx_uart_flush_buffer,
1946 .set_termios = imx_uart_set_termios,
1947 .type = imx_uart_type,
1948 .config_port = imx_uart_config_port,
1949 .verify_port = imx_uart_verify_port,
1950 #if defined(CONFIG_CONSOLE_POLL)
1951 .poll_init = imx_uart_poll_init,
1952 .poll_get_char = imx_uart_poll_get_char,
1953 .poll_put_char = imx_uart_poll_put_char,
1954 #endif
1955 };
1956
1957 static struct imx_port *imx_uart_ports[UART_NR];
1958
1959 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
imx_uart_console_putchar(struct uart_port * port,int ch)1960 static void imx_uart_console_putchar(struct uart_port *port, int ch)
1961 {
1962 struct imx_port *sport = (struct imx_port *)port;
1963
1964 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
1965 barrier();
1966
1967 imx_uart_writel(sport, ch, URTX0);
1968 }
1969
1970 /*
1971 * Interrupts are disabled on entering
1972 */
1973 static void
imx_uart_console_write(struct console * co,const char * s,unsigned int count)1974 imx_uart_console_write(struct console *co, const char *s, unsigned int count)
1975 {
1976 struct imx_port *sport = imx_uart_ports[co->index];
1977 struct imx_port_ucrs old_ucr;
1978 unsigned int ucr1;
1979 unsigned long flags = 0;
1980 int locked = 1;
1981
1982 if (sport->port.sysrq)
1983 locked = 0;
1984 else if (oops_in_progress)
1985 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1986 else
1987 spin_lock_irqsave(&sport->port.lock, flags);
1988
1989 /*
1990 * First, save UCR1/2/3 and then disable interrupts
1991 */
1992 imx_uart_ucrs_save(sport, &old_ucr);
1993 ucr1 = old_ucr.ucr1;
1994
1995 if (imx_uart_is_imx1(sport))
1996 ucr1 |= IMX1_UCR1_UARTCLKEN;
1997 ucr1 |= UCR1_UARTEN;
1998 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1999
2000 imx_uart_writel(sport, ucr1, UCR1);
2001
2002 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
2003
2004 uart_console_write(&sport->port, s, count, imx_uart_console_putchar);
2005
2006 /*
2007 * Finally, wait for transmitter to become empty
2008 * and restore UCR1/2/3
2009 */
2010 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC));
2011
2012 imx_uart_ucrs_restore(sport, &old_ucr);
2013
2014 if (locked)
2015 spin_unlock_irqrestore(&sport->port.lock, flags);
2016 }
2017
2018 /*
2019 * If the port was already initialised (eg, by a boot loader),
2020 * try to determine the current setup.
2021 */
2022 static void __init
imx_uart_console_get_options(struct imx_port * sport,int * baud,int * parity,int * bits)2023 imx_uart_console_get_options(struct imx_port *sport, int *baud,
2024 int *parity, int *bits)
2025 {
2026
2027 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
2028 /* ok, the port was enabled */
2029 unsigned int ucr2, ubir, ubmr, uartclk;
2030 unsigned int baud_raw;
2031 unsigned int ucfr_rfdiv;
2032
2033 ucr2 = imx_uart_readl(sport, UCR2);
2034
2035 *parity = 'n';
2036 if (ucr2 & UCR2_PREN) {
2037 if (ucr2 & UCR2_PROE)
2038 *parity = 'o';
2039 else
2040 *parity = 'e';
2041 }
2042
2043 if (ucr2 & UCR2_WS)
2044 *bits = 8;
2045 else
2046 *bits = 7;
2047
2048 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
2049 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
2050
2051 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
2052 if (ucfr_rfdiv == 6)
2053 ucfr_rfdiv = 7;
2054 else
2055 ucfr_rfdiv = 6 - ucfr_rfdiv;
2056
2057 uartclk = clk_get_rate(sport->clk_per);
2058 uartclk /= ucfr_rfdiv;
2059
2060 { /*
2061 * The next code provides exact computation of
2062 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2063 * without need of float support or long long division,
2064 * which would be required to prevent 32bit arithmetic overflow
2065 */
2066 unsigned int mul = ubir + 1;
2067 unsigned int div = 16 * (ubmr + 1);
2068 unsigned int rem = uartclk % div;
2069
2070 baud_raw = (uartclk / div) * mul;
2071 baud_raw += (rem * mul + div / 2) / div;
2072 *baud = (baud_raw + 50) / 100 * 100;
2073 }
2074
2075 if (*baud != baud_raw)
2076 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
2077 baud_raw, *baud);
2078 }
2079 }
2080
2081 static int __init
imx_uart_console_setup(struct console * co,char * options)2082 imx_uart_console_setup(struct console *co, char *options)
2083 {
2084 struct imx_port *sport;
2085 int baud = 9600;
2086 int bits = 8;
2087 int parity = 'n';
2088 int flow = 'n';
2089 int retval;
2090
2091 /*
2092 * Check whether an invalid uart number has been specified, and
2093 * if so, search for the first available port that does have
2094 * console support.
2095 */
2096 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2097 co->index = 0;
2098 sport = imx_uart_ports[co->index];
2099 if (sport == NULL)
2100 return -ENODEV;
2101
2102 /* For setting the registers, we only need to enable the ipg clock. */
2103 retval = clk_prepare_enable(sport->clk_ipg);
2104 if (retval)
2105 goto error_console;
2106
2107 if (options)
2108 uart_parse_options(options, &baud, &parity, &bits, &flow);
2109 else
2110 imx_uart_console_get_options(sport, &baud, &parity, &bits);
2111
2112 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2113
2114 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2115
2116 if (retval) {
2117 clk_disable_unprepare(sport->clk_ipg);
2118 goto error_console;
2119 }
2120
2121 retval = clk_prepare_enable(sport->clk_per);
2122 if (retval)
2123 clk_disable_unprepare(sport->clk_ipg);
2124
2125 error_console:
2126 return retval;
2127 }
2128
2129 static struct uart_driver imx_uart_uart_driver;
2130 static struct console imx_uart_console = {
2131 .name = DEV_NAME,
2132 .write = imx_uart_console_write,
2133 .device = uart_console_device,
2134 .setup = imx_uart_console_setup,
2135 .flags = CON_PRINTBUFFER,
2136 .index = -1,
2137 .data = &imx_uart_uart_driver,
2138 };
2139
2140 #define IMX_CONSOLE &imx_uart_console
2141
2142 #else
2143 #define IMX_CONSOLE NULL
2144 #endif
2145
2146 static struct uart_driver imx_uart_uart_driver = {
2147 .owner = THIS_MODULE,
2148 .driver_name = DRIVER_NAME,
2149 .dev_name = DEV_NAME,
2150 .major = SERIAL_IMX_MAJOR,
2151 .minor = MINOR_START,
2152 .nr = ARRAY_SIZE(imx_uart_ports),
2153 .cons = IMX_CONSOLE,
2154 };
2155
imx_trigger_start_tx(struct hrtimer * t)2156 static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t)
2157 {
2158 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx);
2159 unsigned long flags;
2160
2161 spin_lock_irqsave(&sport->port.lock, flags);
2162 if (sport->tx_state == WAIT_AFTER_RTS)
2163 imx_uart_start_tx(&sport->port);
2164 spin_unlock_irqrestore(&sport->port.lock, flags);
2165
2166 return HRTIMER_NORESTART;
2167 }
2168
imx_trigger_stop_tx(struct hrtimer * t)2169 static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t)
2170 {
2171 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx);
2172 unsigned long flags;
2173
2174 spin_lock_irqsave(&sport->port.lock, flags);
2175 if (sport->tx_state == WAIT_AFTER_SEND)
2176 imx_uart_stop_tx(&sport->port);
2177 spin_unlock_irqrestore(&sport->port.lock, flags);
2178
2179 return HRTIMER_NORESTART;
2180 }
2181
imx_uart_probe(struct platform_device * pdev)2182 static int imx_uart_probe(struct platform_device *pdev)
2183 {
2184 struct device_node *np = pdev->dev.of_node;
2185 struct imx_port *sport;
2186 void __iomem *base;
2187 int ret = 0;
2188 u32 ucr1;
2189 struct resource *res;
2190 int txirq, rxirq, rtsirq;
2191
2192 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2193 if (!sport)
2194 return -ENOMEM;
2195
2196 sport->devdata = of_device_get_match_data(&pdev->dev);
2197
2198 ret = of_alias_get_id(np, "serial");
2199 if (ret < 0) {
2200 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2201 return ret;
2202 }
2203 sport->port.line = ret;
2204
2205 if (of_get_property(np, "uart-has-rtscts", NULL) ||
2206 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
2207 sport->have_rtscts = 1;
2208
2209 if (of_get_property(np, "fsl,dte-mode", NULL))
2210 sport->dte_mode = 1;
2211
2212 if (of_get_property(np, "rts-gpios", NULL))
2213 sport->have_rtsgpio = 1;
2214
2215 if (of_get_property(np, "fsl,inverted-tx", NULL))
2216 sport->inverted_tx = 1;
2217
2218 if (of_get_property(np, "fsl,inverted-rx", NULL))
2219 sport->inverted_rx = 1;
2220
2221 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2222 dev_err(&pdev->dev, "serial%d out of range\n",
2223 sport->port.line);
2224 return -EINVAL;
2225 }
2226
2227 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2228 base = devm_ioremap_resource(&pdev->dev, res);
2229 if (IS_ERR(base))
2230 return PTR_ERR(base);
2231
2232 rxirq = platform_get_irq(pdev, 0);
2233 if (rxirq < 0)
2234 return rxirq;
2235 txirq = platform_get_irq_optional(pdev, 1);
2236 rtsirq = platform_get_irq_optional(pdev, 2);
2237
2238 sport->port.dev = &pdev->dev;
2239 sport->port.mapbase = res->start;
2240 sport->port.membase = base;
2241 sport->port.type = PORT_IMX;
2242 sport->port.iotype = UPIO_MEM;
2243 sport->port.irq = rxirq;
2244 sport->port.fifosize = 32;
2245 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE);
2246 sport->port.ops = &imx_uart_pops;
2247 sport->port.rs485_config = imx_uart_rs485_config;
2248 sport->port.flags = UPF_BOOT_AUTOCONF;
2249 timer_setup(&sport->timer, imx_uart_timeout, 0);
2250
2251 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2252 if (IS_ERR(sport->gpios))
2253 return PTR_ERR(sport->gpios);
2254
2255 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2256 if (IS_ERR(sport->clk_ipg)) {
2257 ret = PTR_ERR(sport->clk_ipg);
2258 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2259 return ret;
2260 }
2261
2262 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2263 if (IS_ERR(sport->clk_per)) {
2264 ret = PTR_ERR(sport->clk_per);
2265 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2266 return ret;
2267 }
2268
2269 sport->port.uartclk = clk_get_rate(sport->clk_per);
2270
2271 /* For register access, we only need to enable the ipg clock. */
2272 ret = clk_prepare_enable(sport->clk_ipg);
2273 if (ret) {
2274 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret);
2275 return ret;
2276 }
2277
2278 /* initialize shadow register values */
2279 sport->ucr1 = readl(sport->port.membase + UCR1);
2280 sport->ucr2 = readl(sport->port.membase + UCR2);
2281 sport->ucr3 = readl(sport->port.membase + UCR3);
2282 sport->ucr4 = readl(sport->port.membase + UCR4);
2283 sport->ufcr = readl(sport->port.membase + UFCR);
2284
2285 ret = uart_get_rs485_mode(&sport->port);
2286 if (ret) {
2287 clk_disable_unprepare(sport->clk_ipg);
2288 return ret;
2289 }
2290
2291 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2292 (!sport->have_rtscts && !sport->have_rtsgpio))
2293 dev_err(&pdev->dev, "no RTS control, disabling rs485\n");
2294
2295 /*
2296 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2297 * signal cannot be set low during transmission in case the
2298 * receiver is off (limitation of the i.MX UART IP).
2299 */
2300 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2301 sport->have_rtscts && !sport->have_rtsgpio &&
2302 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2303 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2304 dev_err(&pdev->dev,
2305 "low-active RTS not possible when receiver is off, enabling receiver\n");
2306
2307 imx_uart_rs485_config(&sport->port, &sport->port.rs485);
2308
2309 /* Disable interrupts before requesting them */
2310 ucr1 = imx_uart_readl(sport, UCR1);
2311 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN);
2312 imx_uart_writel(sport, ucr1, UCR1);
2313
2314 if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2315 /*
2316 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2317 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2318 * and DCD (when they are outputs) or enables the respective
2319 * irqs. So set this bit early, i.e. before requesting irqs.
2320 */
2321 u32 ufcr = imx_uart_readl(sport, UFCR);
2322 if (!(ufcr & UFCR_DCEDTE))
2323 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2324
2325 /*
2326 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2327 * enabled later because they cannot be cleared
2328 * (confirmed on i.MX25) which makes them unusable.
2329 */
2330 imx_uart_writel(sport,
2331 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2332 UCR3);
2333
2334 } else {
2335 u32 ucr3 = UCR3_DSR;
2336 u32 ufcr = imx_uart_readl(sport, UFCR);
2337 if (ufcr & UFCR_DCEDTE)
2338 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2339
2340 if (!imx_uart_is_imx1(sport))
2341 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2342 imx_uart_writel(sport, ucr3, UCR3);
2343 }
2344
2345 clk_disable_unprepare(sport->clk_ipg);
2346
2347 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2348 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2349 sport->trigger_start_tx.function = imx_trigger_start_tx;
2350 sport->trigger_stop_tx.function = imx_trigger_stop_tx;
2351
2352 /*
2353 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2354 * chips only have one interrupt.
2355 */
2356 if (txirq > 0) {
2357 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2358 dev_name(&pdev->dev), sport);
2359 if (ret) {
2360 dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2361 ret);
2362 return ret;
2363 }
2364
2365 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2366 dev_name(&pdev->dev), sport);
2367 if (ret) {
2368 dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2369 ret);
2370 return ret;
2371 }
2372
2373 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
2374 dev_name(&pdev->dev), sport);
2375 if (ret) {
2376 dev_err(&pdev->dev, "failed to request rts irq: %d\n",
2377 ret);
2378 return ret;
2379 }
2380 } else {
2381 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2382 dev_name(&pdev->dev), sport);
2383 if (ret) {
2384 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2385 return ret;
2386 }
2387 }
2388
2389 imx_uart_ports[sport->port.line] = sport;
2390
2391 platform_set_drvdata(pdev, sport);
2392
2393 return uart_add_one_port(&imx_uart_uart_driver, &sport->port);
2394 }
2395
imx_uart_remove(struct platform_device * pdev)2396 static int imx_uart_remove(struct platform_device *pdev)
2397 {
2398 struct imx_port *sport = platform_get_drvdata(pdev);
2399
2400 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2401 }
2402
imx_uart_restore_context(struct imx_port * sport)2403 static void imx_uart_restore_context(struct imx_port *sport)
2404 {
2405 unsigned long flags;
2406
2407 spin_lock_irqsave(&sport->port.lock, flags);
2408 if (!sport->context_saved) {
2409 spin_unlock_irqrestore(&sport->port.lock, flags);
2410 return;
2411 }
2412
2413 imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2414 imx_uart_writel(sport, sport->saved_reg[5], UESC);
2415 imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2416 imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2417 imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2418 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2419 imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2420 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2421 imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2422 imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2423 sport->context_saved = false;
2424 spin_unlock_irqrestore(&sport->port.lock, flags);
2425 }
2426
imx_uart_save_context(struct imx_port * sport)2427 static void imx_uart_save_context(struct imx_port *sport)
2428 {
2429 unsigned long flags;
2430
2431 /* Save necessary regs */
2432 spin_lock_irqsave(&sport->port.lock, flags);
2433 sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2434 sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2435 sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2436 sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2437 sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2438 sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2439 sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2440 sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2441 sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2442 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2443 sport->context_saved = true;
2444 spin_unlock_irqrestore(&sport->port.lock, flags);
2445 }
2446
imx_uart_enable_wakeup(struct imx_port * sport,bool on)2447 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2448 {
2449 u32 ucr3;
2450
2451 ucr3 = imx_uart_readl(sport, UCR3);
2452 if (on) {
2453 imx_uart_writel(sport, USR1_AWAKE, USR1);
2454 ucr3 |= UCR3_AWAKEN;
2455 } else {
2456 ucr3 &= ~UCR3_AWAKEN;
2457 }
2458 imx_uart_writel(sport, ucr3, UCR3);
2459
2460 if (sport->have_rtscts) {
2461 u32 ucr1 = imx_uart_readl(sport, UCR1);
2462 if (on)
2463 ucr1 |= UCR1_RTSDEN;
2464 else
2465 ucr1 &= ~UCR1_RTSDEN;
2466 imx_uart_writel(sport, ucr1, UCR1);
2467 }
2468 }
2469
imx_uart_suspend_noirq(struct device * dev)2470 static int imx_uart_suspend_noirq(struct device *dev)
2471 {
2472 struct imx_port *sport = dev_get_drvdata(dev);
2473
2474 imx_uart_save_context(sport);
2475
2476 clk_disable(sport->clk_ipg);
2477
2478 pinctrl_pm_select_sleep_state(dev);
2479
2480 return 0;
2481 }
2482
imx_uart_resume_noirq(struct device * dev)2483 static int imx_uart_resume_noirq(struct device *dev)
2484 {
2485 struct imx_port *sport = dev_get_drvdata(dev);
2486 int ret;
2487
2488 pinctrl_pm_select_default_state(dev);
2489
2490 ret = clk_enable(sport->clk_ipg);
2491 if (ret)
2492 return ret;
2493
2494 imx_uart_restore_context(sport);
2495
2496 return 0;
2497 }
2498
imx_uart_suspend(struct device * dev)2499 static int imx_uart_suspend(struct device *dev)
2500 {
2501 struct imx_port *sport = dev_get_drvdata(dev);
2502 int ret;
2503
2504 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2505 disable_irq(sport->port.irq);
2506
2507 ret = clk_prepare_enable(sport->clk_ipg);
2508 if (ret)
2509 return ret;
2510
2511 /* enable wakeup from i.MX UART */
2512 imx_uart_enable_wakeup(sport, true);
2513
2514 return 0;
2515 }
2516
imx_uart_resume(struct device * dev)2517 static int imx_uart_resume(struct device *dev)
2518 {
2519 struct imx_port *sport = dev_get_drvdata(dev);
2520
2521 /* disable wakeup from i.MX UART */
2522 imx_uart_enable_wakeup(sport, false);
2523
2524 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2525 enable_irq(sport->port.irq);
2526
2527 clk_disable_unprepare(sport->clk_ipg);
2528
2529 return 0;
2530 }
2531
imx_uart_freeze(struct device * dev)2532 static int imx_uart_freeze(struct device *dev)
2533 {
2534 struct imx_port *sport = dev_get_drvdata(dev);
2535
2536 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2537
2538 return clk_prepare_enable(sport->clk_ipg);
2539 }
2540
imx_uart_thaw(struct device * dev)2541 static int imx_uart_thaw(struct device *dev)
2542 {
2543 struct imx_port *sport = dev_get_drvdata(dev);
2544
2545 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2546
2547 clk_disable_unprepare(sport->clk_ipg);
2548
2549 return 0;
2550 }
2551
2552 static const struct dev_pm_ops imx_uart_pm_ops = {
2553 .suspend_noirq = imx_uart_suspend_noirq,
2554 .resume_noirq = imx_uart_resume_noirq,
2555 .freeze_noirq = imx_uart_suspend_noirq,
2556 .restore_noirq = imx_uart_resume_noirq,
2557 .suspend = imx_uart_suspend,
2558 .resume = imx_uart_resume,
2559 .freeze = imx_uart_freeze,
2560 .thaw = imx_uart_thaw,
2561 .restore = imx_uart_thaw,
2562 };
2563
2564 static struct platform_driver imx_uart_platform_driver = {
2565 .probe = imx_uart_probe,
2566 .remove = imx_uart_remove,
2567
2568 .driver = {
2569 .name = "imx-uart",
2570 .of_match_table = imx_uart_dt_ids,
2571 .pm = &imx_uart_pm_ops,
2572 },
2573 };
2574
imx_uart_init(void)2575 static int __init imx_uart_init(void)
2576 {
2577 int ret = uart_register_driver(&imx_uart_uart_driver);
2578
2579 if (ret)
2580 return ret;
2581
2582 ret = platform_driver_register(&imx_uart_platform_driver);
2583 if (ret != 0)
2584 uart_unregister_driver(&imx_uart_uart_driver);
2585
2586 return ret;
2587 }
2588
imx_uart_exit(void)2589 static void __exit imx_uart_exit(void)
2590 {
2591 platform_driver_unregister(&imx_uart_platform_driver);
2592 uart_unregister_driver(&imx_uart_uart_driver);
2593 }
2594
2595 module_init(imx_uart_init);
2596 module_exit(imx_uart_exit);
2597
2598 MODULE_AUTHOR("Sascha Hauer");
2599 MODULE_DESCRIPTION("IMX generic serial port driver");
2600 MODULE_LICENSE("GPL");
2601 MODULE_ALIAS("platform:imx-uart");
2602