1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __SOC_MEDIATEK_INFRACFG_H
3 #define __SOC_MEDIATEK_INFRACFG_H
4 
5 #define MT8192_TOP_AXI_PROT_EN_STA1			0x228
6 #define MT8192_TOP_AXI_PROT_EN_1_STA1			0x258
7 #define MT8192_TOP_AXI_PROT_EN_SET			0x2a0
8 #define MT8192_TOP_AXI_PROT_EN_CLR			0x2a4
9 #define MT8192_TOP_AXI_PROT_EN_1_SET			0x2a8
10 #define MT8192_TOP_AXI_PROT_EN_1_CLR			0x2ac
11 #define MT8192_TOP_AXI_PROT_EN_MM_SET			0x2d4
12 #define MT8192_TOP_AXI_PROT_EN_MM_CLR			0x2d8
13 #define MT8192_TOP_AXI_PROT_EN_MM_STA1			0x2ec
14 #define MT8192_TOP_AXI_PROT_EN_2_SET			0x714
15 #define MT8192_TOP_AXI_PROT_EN_2_CLR			0x718
16 #define MT8192_TOP_AXI_PROT_EN_2_STA1			0x724
17 #define MT8192_TOP_AXI_PROT_EN_VDNR_SET			0xb84
18 #define MT8192_TOP_AXI_PROT_EN_VDNR_CLR			0xb88
19 #define MT8192_TOP_AXI_PROT_EN_VDNR_STA1		0xb90
20 #define MT8192_TOP_AXI_PROT_EN_MM_2_SET			0xdcc
21 #define MT8192_TOP_AXI_PROT_EN_MM_2_CLR			0xdd0
22 #define MT8192_TOP_AXI_PROT_EN_MM_2_STA1		0xdd8
23 
24 #define MT8192_TOP_AXI_PROT_EN_DISP			(BIT(6) | BIT(23))
25 #define MT8192_TOP_AXI_PROT_EN_CONN			(BIT(13) | BIT(18))
26 #define MT8192_TOP_AXI_PROT_EN_CONN_2ND			BIT(14)
27 #define MT8192_TOP_AXI_PROT_EN_MFG1			GENMASK(22, 21)
28 #define MT8192_TOP_AXI_PROT_EN_1_CONN			BIT(10)
29 #define MT8192_TOP_AXI_PROT_EN_1_MFG1			BIT(21)
30 #define MT8192_TOP_AXI_PROT_EN_1_CAM			BIT(22)
31 #define MT8192_TOP_AXI_PROT_EN_2_CAM			BIT(0)
32 #define MT8192_TOP_AXI_PROT_EN_2_ADSP			BIT(3)
33 #define MT8192_TOP_AXI_PROT_EN_2_AUDIO			BIT(4)
34 #define MT8192_TOP_AXI_PROT_EN_2_MFG1			GENMASK(6, 5)
35 #define MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND		BIT(7)
36 #define MT8192_TOP_AXI_PROT_EN_MM_CAM			(BIT(0) | BIT(2))
37 #define MT8192_TOP_AXI_PROT_EN_MM_DISP			(BIT(0) | BIT(2) | \
38 							BIT(10) | BIT(12) | \
39 							BIT(14) | BIT(16) | \
40 							BIT(24) | BIT(26))
41 #define MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND		(BIT(1) | BIT(3))
42 #define MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND		(BIT(1) | BIT(3) | \
43 							BIT(15) | BIT(17) | \
44 							BIT(25) | BIT(27))
45 #define MT8192_TOP_AXI_PROT_EN_MM_ISP2			BIT(14)
46 #define MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND		BIT(15)
47 #define MT8192_TOP_AXI_PROT_EN_MM_IPE			BIT(16)
48 #define MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND		BIT(17)
49 #define MT8192_TOP_AXI_PROT_EN_MM_VDEC			BIT(24)
50 #define MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND		BIT(25)
51 #define MT8192_TOP_AXI_PROT_EN_MM_VENC			BIT(26)
52 #define MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND		BIT(27)
53 #define MT8192_TOP_AXI_PROT_EN_MM_2_ISP			BIT(8)
54 #define MT8192_TOP_AXI_PROT_EN_MM_2_DISP		(BIT(8) | BIT(12))
55 #define MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND		BIT(9)
56 #define MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND		(BIT(9) | BIT(13))
57 #define MT8192_TOP_AXI_PROT_EN_MM_2_MDP			BIT(12)
58 #define MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND		BIT(13)
59 #define MT8192_TOP_AXI_PROT_EN_VDNR_CAM			BIT(21)
60 
61 #define MT8183_TOP_AXI_PROT_EN_STA1			0x228
62 #define MT8183_TOP_AXI_PROT_EN_STA1_1			0x258
63 #define MT8183_TOP_AXI_PROT_EN_SET			0x2a0
64 #define MT8183_TOP_AXI_PROT_EN_CLR			0x2a4
65 #define MT8183_TOP_AXI_PROT_EN_1_SET			0x2a8
66 #define MT8183_TOP_AXI_PROT_EN_1_CLR			0x2ac
67 #define MT8183_TOP_AXI_PROT_EN_MCU_SET			0x2c4
68 #define MT8183_TOP_AXI_PROT_EN_MCU_CLR			0x2c8
69 #define MT8183_TOP_AXI_PROT_EN_MCU_STA1			0x2e4
70 #define MT8183_TOP_AXI_PROT_EN_MM_SET			0x2d4
71 #define MT8183_TOP_AXI_PROT_EN_MM_CLR			0x2d8
72 #define MT8183_TOP_AXI_PROT_EN_MM_STA1			0x2ec
73 
74 #define MT8183_TOP_AXI_PROT_EN_DISP			(BIT(10) | BIT(11))
75 #define MT8183_TOP_AXI_PROT_EN_CONN			(BIT(13) | BIT(14))
76 #define MT8183_TOP_AXI_PROT_EN_MFG			(BIT(21) | BIT(22))
77 #define MT8183_TOP_AXI_PROT_EN_CAM			BIT(28)
78 #define MT8183_TOP_AXI_PROT_EN_VPU_TOP			BIT(27)
79 #define MT8183_TOP_AXI_PROT_EN_1_DISP			(BIT(16) | BIT(17))
80 #define MT8183_TOP_AXI_PROT_EN_1_MFG			GENMASK(21, 19)
81 #define MT8183_TOP_AXI_PROT_EN_MM_ISP			(BIT(3) | BIT(8))
82 #define MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND		BIT(10)
83 #define MT8183_TOP_AXI_PROT_EN_MM_CAM			(BIT(4) | BIT(5) | \
84 							 BIT(9) | BIT(13))
85 #define MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP		(GENMASK(9, 6) | \
86 							 BIT(12))
87 #define MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND		(BIT(10) | BIT(11))
88 #define MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND		BIT(11)
89 #define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND	(BIT(0) | BIT(2) | \
90 							 BIT(4))
91 #define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND	(BIT(1) | BIT(3) | \
92 							 BIT(5))
93 #define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0		BIT(6)
94 #define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1		BIT(7)
95 
96 #define MT8183_SMI_COMMON_CLAMP_EN			0x3c0
97 #define MT8183_SMI_COMMON_CLAMP_EN_SET			0x3c4
98 #define MT8183_SMI_COMMON_CLAMP_EN_CLR			0x3c8
99 
100 #define MT8183_SMI_COMMON_SMI_CLAMP_DISP		GENMASK(7, 0)
101 #define MT8183_SMI_COMMON_SMI_CLAMP_VENC		BIT(1)
102 #define MT8183_SMI_COMMON_SMI_CLAMP_ISP			BIT(2)
103 #define MT8183_SMI_COMMON_SMI_CLAMP_CAM			(BIT(3) | BIT(4))
104 #define MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP		(BIT(5) | BIT(6))
105 #define MT8183_SMI_COMMON_SMI_CLAMP_VDEC		BIT(7)
106 
107 #define MT8173_TOP_AXI_PROT_EN_MCI_M2		BIT(0)
108 #define MT8173_TOP_AXI_PROT_EN_MM_M0		BIT(1)
109 #define MT8173_TOP_AXI_PROT_EN_MM_M1		BIT(2)
110 #define MT8173_TOP_AXI_PROT_EN_MMAPB_S		BIT(6)
111 #define MT8173_TOP_AXI_PROT_EN_L2C_M2		BIT(9)
112 #define MT8173_TOP_AXI_PROT_EN_L2SS_SMI		BIT(11)
113 #define MT8173_TOP_AXI_PROT_EN_L2SS_ADD		BIT(12)
114 #define MT8173_TOP_AXI_PROT_EN_CCI_M2		BIT(13)
115 #define MT8173_TOP_AXI_PROT_EN_MFG_S		BIT(14)
116 #define MT8173_TOP_AXI_PROT_EN_PERI_M0		BIT(15)
117 #define MT8173_TOP_AXI_PROT_EN_PERI_M1		BIT(16)
118 #define MT8173_TOP_AXI_PROT_EN_DEBUGSYS		BIT(17)
119 #define MT8173_TOP_AXI_PROT_EN_CQ_DMA		BIT(18)
120 #define MT8173_TOP_AXI_PROT_EN_GCPU		BIT(19)
121 #define MT8173_TOP_AXI_PROT_EN_IOMMU		BIT(20)
122 #define MT8173_TOP_AXI_PROT_EN_MFG_M0		BIT(21)
123 #define MT8173_TOP_AXI_PROT_EN_MFG_M1		BIT(22)
124 #define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT	BIT(23)
125 
126 #define MT8167_TOP_AXI_PROT_EN_MM_EMI		BIT(1)
127 #define MT8167_TOP_AXI_PROT_EN_MCU_MFG		BIT(2)
128 #define MT8167_TOP_AXI_PROT_EN_CONN_EMI		BIT(4)
129 #define MT8167_TOP_AXI_PROT_EN_MFG_EMI		BIT(5)
130 #define MT8167_TOP_AXI_PROT_EN_CONN_MCU		BIT(8)
131 #define MT8167_TOP_AXI_PROT_EN_MCU_CONN		BIT(9)
132 #define MT8167_TOP_AXI_PROT_EN_MCU_MM		BIT(11)
133 
134 #define MT2701_TOP_AXI_PROT_EN_MM_M0		BIT(1)
135 #define MT2701_TOP_AXI_PROT_EN_CONN_M		BIT(2)
136 #define MT2701_TOP_AXI_PROT_EN_CONN_S		BIT(8)
137 
138 #define MT7622_TOP_AXI_PROT_EN_ETHSYS		(BIT(3) | BIT(17))
139 #define MT7622_TOP_AXI_PROT_EN_HIF0		(BIT(24) | BIT(25))
140 #define MT7622_TOP_AXI_PROT_EN_HIF1		(BIT(26) | BIT(27) | \
141 						 BIT(28))
142 #define MT7622_TOP_AXI_PROT_EN_WB		(BIT(2) | BIT(6) | \
143 						 BIT(7) | BIT(8))
144 
145 #define INFRA_TOPAXI_PROTECTEN			0x0220
146 #define INFRA_TOPAXI_PROTECTSTA1		0x0228
147 #define INFRA_TOPAXI_PROTECTEN_SET		0x0260
148 #define INFRA_TOPAXI_PROTECTEN_CLR		0x0264
149 
150 #define REG_INFRA_MISC				0xf00
151 #define F_DDR_4GB_SUPPORT_EN			BIT(13)
152 
153 int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask,
154 		bool reg_update);
155 int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
156 		bool reg_update);
157 #endif /* __SOC_MEDIATEK_INFRACFG_H */
158