1 /* 2 * Copyright © 2018 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Xiang Haihao <haihao.xiang@intel.com> 26 * 27 */ 28 29 #ifndef GEN10_HUC_COMMON_H 30 #define GEN10_HUC_COMMON_H 31 32 struct gen10_huc_pipe_mode_select_parameter { 33 uint32_t huc_stream_object_enabled; 34 uint32_t indirect_stream_out_enabled; 35 uint32_t media_soft_reset_counter; 36 }; 37 38 struct gen10_huc_imem_state_parameter { 39 uint32_t huc_firmware_descriptor; 40 }; 41 42 struct gen10_huc_dmem_state_parameter { 43 struct i965_gpe_resource *huc_data_source_res; 44 uint32_t huc_data_destination_base_address; 45 uint32_t huc_data_length; 46 }; 47 48 struct gen10_huc_virtual_addr_parameter { 49 struct { 50 struct i965_gpe_resource *huc_surface_res; 51 uint32_t offset; 52 uint32_t is_target; 53 } regions[16]; 54 }; 55 56 struct gen10_huc_ind_obj_base_addr_parameter { 57 struct i965_gpe_resource *huc_indirect_stream_in_object_res; 58 struct i965_gpe_resource *huc_indirect_stream_out_object_res; 59 }; 60 61 struct gen10_huc_stream_object_parameter { 62 uint32_t indirect_stream_in_data_length; 63 uint32_t indirect_stream_in_start_address; 64 uint32_t indirect_stream_out_start_address; 65 uint32_t huc_bitstream_enabled; 66 uint32_t length_mode; 67 uint32_t stream_out; 68 uint32_t emulation_prevention_byte_removal; 69 uint32_t start_code_search_engine; 70 uint8_t start_code_byte2; 71 uint8_t start_code_byte1; 72 uint8_t start_code_byte0; 73 }; 74 75 struct gen10_huc_start_parameter { 76 uint32_t last_stream_object; 77 }; 78 79 void 80 gen10_huc_pipe_mode_select(VADriverContextP ctx, 81 struct intel_batchbuffer *batch, 82 struct gen10_huc_pipe_mode_select_parameter *params); 83 84 void 85 gen10_huc_imem_state(VADriverContextP ctx, 86 struct intel_batchbuffer *batch, 87 struct gen10_huc_imem_state_parameter *params); 88 89 void 90 gen10_huc_dmem_state(VADriverContextP ctx, 91 struct intel_batchbuffer *batch, 92 struct gen10_huc_dmem_state_parameter *params); 93 94 void 95 gen10_huc_virtual_addr_state(VADriverContextP ctx, 96 struct intel_batchbuffer *batch, 97 struct gen10_huc_virtual_addr_parameter *params); 98 99 void 100 gen10_huc_ind_obj_base_addr_state(VADriverContextP ctx, 101 struct intel_batchbuffer *batch, 102 struct gen10_huc_ind_obj_base_addr_parameter *params); 103 104 void 105 gen10_huc_stream_object(VADriverContextP ctx, 106 struct intel_batchbuffer *batch, 107 struct gen10_huc_stream_object_parameter *params); 108 109 void 110 gen10_huc_start(VADriverContextP ctx, 111 struct intel_batchbuffer *batch, 112 struct gen10_huc_start_parameter *params); 113 114 #endif /* GEN10_HUC_COMMON_H */ 115