1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWAR OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chen, Peng <chen.c.peng@intel.com>
26 *
27 */
28
29 #include <stdio.h>
30 #include <stdlib.h>
31 #include <stdbool.h>
32 #include <string.h>
33 #include <math.h>
34 #include <assert.h>
35 #include <va/va.h>
36
37 #include "intel_batchbuffer.h"
38 #include "intel_driver.h"
39
40 #include "i965_defines.h"
41 #include "i965_drv_video.h"
42 #include "i965_encoder.h"
43 #include "i965_encoder_common.h"
44 #include "i965_encoder_utils.h"
45 #include "i965_encoder_api.h"
46 #include "gen9_hevc_enc_kernels.h"
47 #include "gen9_hevc_enc_kernels_binary.h"
48 #include "gen9_hevc_enc_utils.h"
49 #include "gen9_hevc_encoder.h"
50 #include "gen9_hevc_enc_const_def.h"
51
52 static void *hevc_enc_kernel_ptr = NULL;
53 static int hevc_enc_kernel_size = 0;
54
55 static bool
gen9_hevc_get_kernel_header_and_size(void * pvbinary,int binary_size,GEN9_ENC_OPERATION operation,int krnstate_idx,struct i965_kernel * ret_kernel)56 gen9_hevc_get_kernel_header_and_size(void *pvbinary,
57 int binary_size,
58 GEN9_ENC_OPERATION operation,
59 int krnstate_idx,
60 struct i965_kernel *ret_kernel)
61 {
62 typedef uint32_t BIN_PTR[4];
63
64 char *bin_start;
65 gen9_hevc_enc_kernels_header_bxt *pkh_table = NULL;
66 gen9_hevc_enc_kernel_header *pcurr_header = NULL, *pinvalid_entry, *pnext_header;
67 int next_krnoffset;
68
69 if (!pvbinary || !ret_kernel)
70 return false;
71
72 bin_start = (char *)pvbinary;
73 pkh_table = (gen9_hevc_enc_kernels_header_bxt *)pvbinary;
74 pinvalid_entry = (gen9_hevc_enc_kernel_header *)(pkh_table + 1);
75 next_krnoffset = binary_size;
76
77 switch (operation) {
78 case GEN9_ENC_SCALING2X:
79 pcurr_header = &pkh_table->HEVC_ENC_I_2xDownSampling_Kernel;
80 break;
81 case GEN9_ENC_SCALING4X:
82 pcurr_header = &pkh_table->HEVC_ENC_I_DS4HME;
83 break;
84 case GEN9_ENC_ME:
85 if (krnstate_idx)
86 pcurr_header = &pkh_table->HEVC_ENC_P_HME;
87 else
88 pcurr_header = &pkh_table->HEVC_ENC_B_HME;
89 break;
90 case GEN9_ENC_BRC:
91 switch (krnstate_idx) {
92 case GEN9_HEVC_ENC_BRC_COARSE_INTRA:
93 pcurr_header = &pkh_table->HEVC_ENC_I_COARSE;
94 break;
95 case GEN9_HEVC_ENC_BRC_INIT:
96 pcurr_header = &pkh_table->HEVC_ENC_BRC_Init;
97 break;
98 case GEN9_HEVC_ENC_BRC_RESET:
99 pcurr_header = &pkh_table->HEVC_ENC_BRC_Reset;
100 break;
101 case GEN9_HEVC_ENC_BRC_FRAME_UPDATE:
102 pcurr_header = &pkh_table->HEVC_ENC_BRC_Update;
103 break;
104 case GEN9_HEVC_ENC_BRC_LCU_UPDATE:
105 pcurr_header = &pkh_table->HEVC_ENC_BRC_LCU_Update;
106 break;
107 default:
108 break;
109 }
110 break;
111 case GEN9_ENC_MBENC:
112 switch (krnstate_idx) {
113 case GEN9_HEVC_ENC_MBENC_2xSCALING:
114 case GEN9_HEVC_ENC_MBENC_32x32MD:
115 case GEN9_HEVC_ENC_MBENC_16x16SAD:
116 case GEN9_HEVC_ENC_MBENC_16x16MD:
117 case GEN9_HEVC_ENC_MBENC_8x8PU:
118 case GEN9_HEVC_ENC_MBENC_8x8FMODE:
119 case GEN9_HEVC_ENC_MBENC_32x32INTRACHECK:
120 case GEN9_HEVC_ENC_MBENC_BENC:
121 pcurr_header = &pkh_table->HEVC_ENC_I_2xDownSampling_Kernel;
122 pcurr_header += krnstate_idx;
123 break;
124 case GEN9_HEVC_ENC_MBENC_BPAK:
125 pcurr_header = &pkh_table->HEVC_ENC_PB_Pak;
126 break;
127 case GEN9_HEVC_ENC_MBENC_WIDI:
128 pcurr_header = &pkh_table->HEVC_ENC_PB_Widi;
129 break;
130 case GEN9_HEVC_MBENC_PENC:
131 pcurr_header = &pkh_table->HEVC_ENC_P_MB;
132 break;
133 case GEN9_HEVC_MBENC_P_WIDI:
134 pcurr_header = &pkh_table->HEVC_ENC_P_Widi;
135 break;
136 case GEN9_HEVC_ENC_MBENC_DS_COMBINED:
137 pcurr_header = &pkh_table->HEVC_ENC_DS_Combined;
138 break;
139 default:
140 break;
141 }
142 break;
143 default:
144 break;
145 }
146
147 if (!pcurr_header ||
148 ((pcurr_header->kernel_start_pointer << 6) >= binary_size))
149 return false;
150
151 ret_kernel->bin = (const BIN_PTR *)(bin_start + (pcurr_header->kernel_start_pointer << 6));
152
153 pnext_header = (pcurr_header + 1);
154 if (pnext_header < pinvalid_entry)
155 next_krnoffset = pnext_header->kernel_start_pointer << 6;
156
157 ret_kernel->size = next_krnoffset - (pcurr_header->kernel_start_pointer << 6);
158
159 return true;
160 }
161
162 static void
gen9_hevc_store_reg_mem(VADriverContextP ctx,struct intel_batchbuffer * batch,dri_bo * bo,unsigned int offset,unsigned int mmio_offset)163 gen9_hevc_store_reg_mem(VADriverContextP ctx,
164 struct intel_batchbuffer *batch,
165 dri_bo *bo,
166 unsigned int offset,
167 unsigned int mmio_offset)
168 {
169 struct gpe_mi_store_register_mem_parameter mi_store_reg_mem_param;
170
171 memset((void *)&mi_store_reg_mem_param, 0,
172 sizeof(mi_store_reg_mem_param));
173 mi_store_reg_mem_param.bo = bo;
174 mi_store_reg_mem_param.offset = offset;
175 mi_store_reg_mem_param.mmio_offset = mmio_offset;
176 gen8_gpe_mi_store_register_mem(ctx, batch, &mi_store_reg_mem_param);
177 }
178
179 static void
gen9_hevc_load_reg_mem(VADriverContextP ctx,struct intel_batchbuffer * batch,dri_bo * bo,unsigned int offset,unsigned int mmio_offset)180 gen9_hevc_load_reg_mem(VADriverContextP ctx,
181 struct intel_batchbuffer *batch,
182 dri_bo *bo,
183 unsigned int offset,
184 unsigned int mmio_offset)
185 {
186 struct gpe_mi_load_register_mem_parameter mi_load_reg_mem_param;
187
188 memset((void *)&mi_load_reg_mem_param, 0,
189 sizeof(mi_load_reg_mem_param));
190 mi_load_reg_mem_param.bo = bo;
191 mi_load_reg_mem_param.offset = offset;
192 mi_load_reg_mem_param.mmio_offset = mmio_offset;
193 gen8_gpe_mi_load_register_mem(ctx, batch, &mi_load_reg_mem_param);
194 }
195
196 static void
gen9_hevc_conditional_end(VADriverContextP ctx,struct intel_batchbuffer * batch,dri_bo * bo,unsigned int offset,unsigned int data)197 gen9_hevc_conditional_end(VADriverContextP ctx,
198 struct intel_batchbuffer *batch,
199 dri_bo *bo,
200 unsigned int offset,
201 unsigned int data)
202 {
203 struct gpe_mi_conditional_batch_buffer_end_parameter mi_cond_end;
204
205 memset(&mi_cond_end, 0, sizeof(mi_cond_end));
206 mi_cond_end.offset = offset;
207 mi_cond_end.bo = bo;
208 mi_cond_end.compare_data = data;
209 mi_cond_end.compare_mask_mode_disabled = 0;
210 gen9_gpe_mi_conditional_batch_buffer_end(ctx, batch,
211 &mi_cond_end);
212 }
213
214 static VAStatus
gen9_hevc_ensure_surface(VADriverContextP ctx,struct gen9_hevc_encoder_state * priv_state,struct object_surface * obj_surface,int reallocate_flag)215 gen9_hevc_ensure_surface(VADriverContextP ctx,
216 struct gen9_hevc_encoder_state *priv_state,
217 struct object_surface *obj_surface,
218 int reallocate_flag)
219 {
220 VAStatus va_status = VA_STATUS_SUCCESS;
221 int update = 0;
222 unsigned int fourcc = VA_FOURCC_NV12;
223
224 if (!obj_surface) {
225 va_status = VA_STATUS_ERROR_INVALID_PARAMETER;
226
227 goto EXIT;
228 }
229
230 if ((priv_state->bit_depth_luma_minus8 > 0)
231 || (priv_state->bit_depth_chroma_minus8 > 0)) {
232 if (obj_surface->fourcc != VA_FOURCC_P010) {
233 update = 1;
234 fourcc = VA_FOURCC_P010;
235 }
236 } else if (obj_surface->fourcc != VA_FOURCC_NV12) {
237 update = 1;
238 fourcc = VA_FOURCC_NV12;
239 }
240
241 /* (Re-)allocate the underlying surface buffer store, if necessary */
242 if (!obj_surface->bo || update) {
243 if (reallocate_flag) {
244 struct i965_driver_data * const i965 = i965_driver_data(ctx);
245
246 i965_destroy_surface_storage(obj_surface);
247
248 va_status = i965_check_alloc_surface_bo(ctx,
249 obj_surface,
250 i965->codec_info->has_tiled_surface,
251 fourcc,
252 SUBSAMPLE_YUV420);
253 } else
254 va_status = VA_STATUS_ERROR_INVALID_PARAMETER;
255 }
256
257 EXIT:
258 return va_status;
259 }
260
261 static void
gen9_hevc_free_surface_private(void ** data)262 gen9_hevc_free_surface_private(void **data)
263 {
264 struct gen9_hevc_surface_priv *surface_priv = NULL;
265 int i = 0;
266
267 surface_priv = (struct gen9_hevc_surface_priv *)(*data);
268 if (!surface_priv)
269 return;
270
271 for (i = 0; i < HEVC_SCALED_SURFS_NUM; i++) {
272 if (surface_priv->scaled_surface_obj[i]) {
273 i965_DestroySurfaces(surface_priv->ctx, &surface_priv->scaled_surface_id[i], 1);
274 surface_priv->scaled_surface_id[i] = VA_INVALID_SURFACE;
275 surface_priv->scaled_surface_obj[i] = NULL;
276 }
277 }
278
279 if (surface_priv->surface_obj_nv12) {
280 i965_DestroySurfaces(surface_priv->ctx, &surface_priv->surface_id_nv12, 1);
281 surface_priv->surface_id_nv12 = VA_INVALID_SURFACE;
282 surface_priv->surface_obj_nv12 = NULL;
283 }
284
285 if (surface_priv->motion_vector_temporal_bo)
286 dri_bo_unreference(surface_priv->motion_vector_temporal_bo);
287
288 free(surface_priv);
289 }
290
291 static VAStatus
gen9_hevc_init_surface_private(VADriverContextP ctx,struct generic_enc_codec_state * generic_state,struct gen9_hevc_encoder_state * priv_state,struct object_surface * obj_surface)292 gen9_hevc_init_surface_private(VADriverContextP ctx,
293 struct generic_enc_codec_state *generic_state,
294 struct gen9_hevc_encoder_state *priv_state,
295 struct object_surface *obj_surface)
296 {
297 struct i965_driver_data *i965 = i965_driver_data(ctx);
298 struct gen9_hevc_surface_priv *surface_priv = NULL;
299 int size = 0;
300
301 if (!obj_surface || !obj_surface->bo)
302 return VA_STATUS_ERROR_INVALID_SURFACE;
303
304 if (obj_surface->private_data &&
305 obj_surface->free_private_data != gen9_hevc_free_surface_private) {
306 obj_surface->free_private_data(&obj_surface->private_data);
307 obj_surface->private_data = NULL;
308 }
309
310 if (obj_surface->private_data) {
311 surface_priv = (struct gen9_hevc_surface_priv *)obj_surface->private_data;
312
313 surface_priv->surface_nv12_valid = 0;
314 } else {
315 surface_priv = calloc(1, sizeof(*surface_priv));
316 if (!surface_priv)
317 return VA_STATUS_ERROR_ALLOCATION_FAILED;
318
319 surface_priv->ctx = ctx;
320 surface_priv->surface_reff = obj_surface;
321
322 obj_surface->private_data = (void *)surface_priv;
323 obj_surface->free_private_data = gen9_hevc_free_surface_private;
324
325 // alloc motion vector temporal buffer
326 size = MAX(((priv_state->picture_width + 63) >> 6) *
327 ((priv_state->picture_height + 15) >> 4),
328 ((priv_state->picture_width + 31) >> 5) *
329 ((priv_state->picture_height + 31) >> 5));
330 size = ALIGN(size, 2) * 64;
331 surface_priv->motion_vector_temporal_bo =
332 dri_bo_alloc(i965->intel.bufmgr,
333 "motion vector temporal buffer",
334 size,
335 0x1000);
336 if (!surface_priv->motion_vector_temporal_bo)
337 return VA_STATUS_ERROR_ALLOCATION_FAILED;
338
339 //alloc HME surfaces
340 i965_CreateSurfaces(ctx,
341 priv_state->frame_width_4x,
342 priv_state->frame_height_4x,
343 VA_RT_FORMAT_YUV420,
344 1,
345 &surface_priv->scaled_surface_id[HEVC_SCALED_SURF_4X_ID]);
346
347 surface_priv->scaled_surface_obj[HEVC_SCALED_SURF_4X_ID] =
348 SURFACE(surface_priv->scaled_surface_id[HEVC_SCALED_SURF_4X_ID]);
349
350 if (!surface_priv->scaled_surface_obj[HEVC_SCALED_SURF_4X_ID])
351 return VA_STATUS_ERROR_ALLOCATION_FAILED;
352
353 i965_check_alloc_surface_bo(ctx, surface_priv->scaled_surface_obj[HEVC_SCALED_SURF_4X_ID], 1,
354 VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
355
356 if (generic_state->b16xme_supported) {
357 i965_CreateSurfaces(ctx,
358 priv_state->frame_width_16x,
359 priv_state->frame_height_16x,
360 VA_RT_FORMAT_YUV420,
361 1,
362 &surface_priv->scaled_surface_id[HEVC_SCALED_SURF_16X_ID]);
363 surface_priv->scaled_surface_obj[HEVC_SCALED_SURF_16X_ID] =
364 SURFACE(surface_priv->scaled_surface_id[HEVC_SCALED_SURF_16X_ID]);
365
366 if (!surface_priv->scaled_surface_obj[HEVC_SCALED_SURF_16X_ID])
367 return VA_STATUS_ERROR_ALLOCATION_FAILED;
368
369 i965_check_alloc_surface_bo(ctx, surface_priv->scaled_surface_obj[HEVC_SCALED_SURF_16X_ID], 1,
370 VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
371 }
372
373 if (generic_state->b32xme_supported) {
374 i965_CreateSurfaces(ctx,
375 priv_state->frame_width_32x,
376 priv_state->frame_height_32x,
377 VA_RT_FORMAT_YUV420,
378 1,
379 &surface_priv->scaled_surface_id[HEVC_SCALED_SURF_32X_ID]);
380 surface_priv->scaled_surface_obj[HEVC_SCALED_SURF_32X_ID] =
381 SURFACE(surface_priv->scaled_surface_id[HEVC_SCALED_SURF_32X_ID]);
382
383 if (!surface_priv->scaled_surface_obj[HEVC_SCALED_SURF_32X_ID])
384 return VA_STATUS_ERROR_ALLOCATION_FAILED;
385
386 i965_check_alloc_surface_bo(ctx, surface_priv->scaled_surface_obj[HEVC_SCALED_SURF_32X_ID], 1,
387 VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
388 }
389
390 if (obj_surface->fourcc == VA_FOURCC_P010) {
391 i965_CreateSurfaces(ctx,
392 priv_state->frame_width_in_max_lcu,
393 priv_state->frame_height_in_max_lcu,
394 VA_RT_FORMAT_YUV420,
395 1,
396 &surface_priv->surface_id_nv12);
397 surface_priv->surface_obj_nv12 = SURFACE(surface_priv->surface_id_nv12);
398
399 if (!surface_priv->surface_obj_nv12)
400 return VA_STATUS_ERROR_ALLOCATION_FAILED;
401
402 i965_check_alloc_surface_bo(ctx, surface_priv->surface_obj_nv12, 1,
403 VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
404 }
405 }
406
407 return VA_STATUS_SUCCESS;
408 }
409
410 static void
gen9_hevc_enc_free_resources(struct encoder_vme_mfc_context * vme_context)411 gen9_hevc_enc_free_resources(struct encoder_vme_mfc_context *vme_context)
412 {
413 struct gen9_hevc_encoder_context *priv_ctx = NULL;
414 int i;
415
416 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
417
418 if (!priv_ctx)
419 return;
420
421 i965_free_gpe_resource(&priv_ctx->res_brc_pic_states_write_buffer);
422 i965_free_gpe_resource(&priv_ctx->res_brc_history_buffer);
423 i965_free_gpe_resource(&priv_ctx->res_brc_intra_dist_buffer);
424 i965_free_gpe_resource(&priv_ctx->res_brc_pak_statistic_buffer);
425 i965_free_gpe_resource(&priv_ctx->res_brc_input_buffer_for_enc_kernels);
426 i965_free_gpe_resource(&priv_ctx->res_brc_constant_data_buffer);
427
428 i965_free_gpe_resource(&priv_ctx->res_mb_code_surface);
429 i965_free_gpe_resource(&priv_ctx->res_min_distortion_buffer);
430 i965_free_gpe_resource(&priv_ctx->res_brc_mb_qp_buffer);
431
432 // free VME buffers
433 i965_free_gpe_resource(&priv_ctx->res_flatness_check_surface);
434 i965_free_gpe_resource(&priv_ctx->res_brc_me_dist_buffer);
435 i965_free_gpe_resource(&priv_ctx->s4x_memv_distortion_buffer);
436 i965_free_gpe_resource(&priv_ctx->s4x_memv_data_buffer);
437 i965_free_gpe_resource(&priv_ctx->s16x_memv_data_buffer);
438 i965_free_gpe_resource(&priv_ctx->s32x_memv_data_buffer);
439 i965_free_gpe_resource(&priv_ctx->res_32x32_pu_output_buffer);
440 i965_free_gpe_resource(&priv_ctx->res_simplest_intra_buffer);
441 i965_free_gpe_resource(&priv_ctx->res_kernel_debug);
442 i965_free_gpe_resource(&priv_ctx->res_sad_16x16_pu_buffer);
443 i965_free_gpe_resource(&priv_ctx->res_vme_8x8_mode_buffer);
444 i965_free_gpe_resource(&priv_ctx->res_intra_mode_buffer);
445 i965_free_gpe_resource(&priv_ctx->res_intra_distortion_buffer);
446 i965_free_gpe_resource(&priv_ctx->res_vme_uni_sic_buffer);
447 i965_free_gpe_resource(&priv_ctx->res_con_corrent_thread_buffer);
448 i965_free_gpe_resource(&priv_ctx->res_mv_index_buffer);
449 i965_free_gpe_resource(&priv_ctx->res_mvp_index_buffer);
450 i965_free_gpe_resource(&priv_ctx->res_roi_buffer);
451 i965_free_gpe_resource(&priv_ctx->res_mb_statistics_buffer);
452 i965_free_gpe_resource(&priv_ctx->res_slice_map_buffer);
453
454 if (priv_ctx->scaled_2x_surface_obj) {
455 i965_DestroySurfaces(priv_ctx->ctx, &priv_ctx->scaled_2x_surface_id, 1);
456 priv_ctx->scaled_2x_surface_obj = NULL;
457 }
458
459 // free PAK buffers
460 i965_free_gpe_resource(&priv_ctx->deblocking_filter_line_buffer);
461 i965_free_gpe_resource(&priv_ctx->deblocking_filter_tile_line_buffer);
462 i965_free_gpe_resource(&priv_ctx->deblocking_filter_tile_column_buffer);
463 i965_free_gpe_resource(&priv_ctx->metadata_line_buffer);
464 i965_free_gpe_resource(&priv_ctx->metadata_tile_line_buffer);
465 i965_free_gpe_resource(&priv_ctx->metadata_tile_column_buffer);
466 i965_free_gpe_resource(&priv_ctx->sao_line_buffer);
467 i965_free_gpe_resource(&priv_ctx->sao_tile_line_buffer);
468 i965_free_gpe_resource(&priv_ctx->sao_tile_column_buffer);
469 i965_free_gpe_resource(&priv_ctx->res_brc_pic_states_read_buffer);
470
471 for (i = 0; i < GEN9_MAX_MV_TEMPORAL_BUFFERS; i++) {
472 dri_bo_unreference(priv_ctx->mv_temporal_buffer[i].bo);
473 priv_ctx->mv_temporal_buffer[i].bo = NULL;
474 }
475
476 priv_ctx->res_inited = 0;
477 }
478
479 #define ALLOC_GPE_RESOURCE(RES, NAME, SIZE) \
480 do{ \
481 i965_free_gpe_resource(&priv_ctx->RES); \
482 if (!i965_allocate_gpe_resource(i965->intel.bufmgr, \
483 &priv_ctx->RES, \
484 SIZE, \
485 NAME)) \
486 goto FAIL; \
487 } while(0);
488
489 #define ALLOC_GPE_2D_RESOURCE(RES, NAME, W, H, P) \
490 do{ \
491 i965_free_gpe_resource(&priv_ctx->RES); \
492 if (!i965_gpe_allocate_2d_resource(i965->intel.bufmgr, \
493 &priv_ctx->RES, \
494 (ALIGN(W, 64)), H, \
495 (ALIGN(P, 64)), \
496 NAME)) \
497 goto FAIL; \
498 } while(0);
499
500 static VAStatus
gen9_hevc_enc_alloc_resources(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)501 gen9_hevc_enc_alloc_resources(VADriverContextP ctx,
502 struct encode_state *encode_state,
503 struct intel_encoder_context *encoder_context)
504 {
505 struct i965_driver_data *i965 = i965_driver_data(ctx);
506 struct encoder_vme_mfc_context *vme_context = NULL;
507 struct gen9_hevc_encoder_context *priv_ctx = NULL;
508 struct generic_enc_codec_state *generic_state = NULL;
509 struct gen9_hevc_encoder_state *priv_state = NULL;
510 int res_size = 0, size_shift = 0;
511 int width = 0, height = 0;
512
513 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
514 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
515 generic_state = (struct generic_enc_codec_state *)vme_context->generic_enc_state;
516 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
517
518 if (priv_ctx->res_inited)
519 return VA_STATUS_SUCCESS;
520
521 res_size = priv_state->mb_code_size;
522 ALLOC_GPE_RESOURCE(res_mb_code_surface,
523 "Mb code surface", res_size);
524
525 res_size = priv_state->pic_state_size * generic_state->num_pak_passes;
526 ALLOC_GPE_RESOURCE(res_brc_pic_states_write_buffer,
527 "Brc pic status write buffer",
528 res_size);
529
530 res_size = priv_state->pic_state_size * generic_state->num_pak_passes;
531 ALLOC_GPE_RESOURCE(res_brc_pic_states_read_buffer,
532 "Brc pic status read buffer",
533 res_size);
534
535 res_size = GEN9_HEVC_ENC_BRC_HISTORY_BUFFER_SIZE;
536 ALLOC_GPE_RESOURCE(res_brc_history_buffer,
537 "Brc history buffer",
538 res_size);
539
540 res_size = GEN9_HEVC_ENC_BRC_PAK_STATISTCS_SIZE;
541 ALLOC_GPE_RESOURCE(res_brc_pak_statistic_buffer,
542 "Brc pak statistic buffer",
543 res_size);
544
545 res_size = 1024;
546 ALLOC_GPE_RESOURCE(res_brc_input_buffer_for_enc_kernels,
547 "Brc input buffer for enc kernels buffer",
548 res_size);
549
550 width = ALIGN(priv_state->downscaled_width_4x_in_mb * 8, 64);
551 height = ALIGN(priv_state->downscaled_height_4x_in_mb * 4, 8) * 2;
552 ALLOC_GPE_2D_RESOURCE(res_brc_intra_dist_buffer,
553 "Brc intra distortion buffer",
554 width, height, width);
555
556 width = ALIGN(GEN9_HEVC_ENC_BRC_CONSTANT_SURFACE_WIDTH, 64);
557 height = GEN9_HEVC_ENC_BRC_CONSTANT_SURFACE_HEIGHT;
558 ALLOC_GPE_2D_RESOURCE(res_brc_constant_data_buffer,
559 "Brc constant data buffer",
560 width, height, width);
561
562 width = ALIGN((priv_state->frame_width_4x * 4 + 31) >> 4, 64);
563 height = ALIGN((priv_state->frame_height_4x * 4 + 31) >> 5, 4);
564 ALLOC_GPE_2D_RESOURCE(res_brc_mb_qp_buffer,
565 "Brc mb qp buffer",
566 width, height, width);
567
568 //HME scaling buffer allocation
569 width = ALIGN(priv_state->downscaled_width_4x_in_mb * 8, 64);
570 height = ALIGN(priv_state->downscaled_height_4x_in_mb * 4, 8);
571 ALLOC_GPE_2D_RESOURCE(res_brc_me_dist_buffer,
572 "Brc me distortion buffer",
573 width, height, width);
574
575 if (generic_state->hme_supported) {
576 width = ALIGN(priv_state->downscaled_width_4x_in_mb * 8, 64);
577 height = ALIGN(priv_state->downscaled_height_4x_in_mb * 4 * 10, 8) * 2;
578 ALLOC_GPE_2D_RESOURCE(s4x_memv_distortion_buffer,
579 "4x MEMV distortion buffer",
580 width, height, width);
581
582 width = ALIGN(priv_state->downscaled_width_4x_in_mb * 32, 64);
583 height = priv_state->downscaled_height_4x_in_mb * 4 * 10;
584 ALLOC_GPE_2D_RESOURCE(s4x_memv_data_buffer,
585 "4x MEMV data buffer",
586 width, height, width);
587
588 if (generic_state->b16xme_supported) {
589 width = ALIGN(priv_state->downscaled_width_16x_in_mb * 32, 64);
590 height = priv_state->downscaled_height_16x_in_mb * 2 * 4 * 10;
591 ALLOC_GPE_2D_RESOURCE(s16x_memv_data_buffer,
592 "16x MEMV data buffer",
593 width, height, width);
594
595 if (generic_state->b32xme_supported) {
596 width = ALIGN(priv_state->downscaled_width_32x_in_mb * 32, 64);
597 height = priv_state->downscaled_height_32x_in_mb * 2 * 4 * 10;
598 ALLOC_GPE_2D_RESOURCE(s32x_memv_data_buffer,
599 "32x MEMV data buffer",
600 width, height, width);
601 }
602 }
603 }
604
605 if (priv_state->flatness_check_supported) {
606 width = ALIGN(priv_state->width_in_mb * 4, 64);
607 height = priv_state->downscaled_height_4x_in_mb * 4;
608 ALLOC_GPE_2D_RESOURCE(res_flatness_check_surface,
609 "Flatness check buffer",
610 width, height, width);
611 }
612
613 if (priv_ctx->scaled_2x_surface_obj)
614 i965_DestroySurfaces(priv_ctx->ctx, &priv_ctx->scaled_2x_surface_id, 1);
615
616 width = priv_state->frame_width_in_max_lcu >> 1;
617 height = priv_state->frame_height_in_max_lcu >> 1;
618 if (priv_state->bit_depth_luma_minus8) {
619 width = ALIGN(width, 32);
620 height = ALIGN(height, 32);
621 }
622
623 i965_CreateSurfaces(ctx,
624 width,
625 height,
626 VA_RT_FORMAT_YUV420,
627 1,
628 &priv_ctx->scaled_2x_surface_id);
629 priv_ctx->scaled_2x_surface_obj =
630 SURFACE(priv_ctx->scaled_2x_surface_id);
631
632 if (!priv_ctx->scaled_2x_surface_obj)
633 goto FAIL;
634
635 i965_check_alloc_surface_bo(ctx, priv_ctx->scaled_2x_surface_obj, 1,
636 VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
637
638 res_size = (priv_state->frame_width_in_max_lcu >> 5) *
639 (priv_state->frame_height_in_max_lcu >> 5) *
640 32;
641 ALLOC_GPE_RESOURCE(res_32x32_pu_output_buffer,
642 "32x32 pu output buffer",
643 res_size);
644
645 width = priv_state->frame_width_in_max_lcu >> 3;
646 height = priv_state->frame_height_in_max_lcu >> 5;
647 ALLOC_GPE_2D_RESOURCE(res_slice_map_buffer,
648 "Slice map buffer",
649 width, height, width);
650
651 res_size = 8192 * 1024;
652 ALLOC_GPE_RESOURCE(res_kernel_debug,
653 "kernel debug",
654 res_size);
655
656 width = priv_state->frame_width_in_max_lcu >> 3;
657 height = priv_state->frame_height_in_max_lcu >> 5;
658 ALLOC_GPE_2D_RESOURCE(res_simplest_intra_buffer,
659 "Simplest intra buffer",
660 width, height, width);
661
662 res_size = (priv_state->frame_width_in_max_lcu >> 4) *
663 (priv_state->frame_height_in_max_lcu >> 4) * 8 * 4;
664 ALLOC_GPE_RESOURCE(res_sad_16x16_pu_buffer,
665 "Sad 16x16 pu",
666 res_size);
667
668 res_size = (priv_state->frame_width_in_max_lcu >> 4) *
669 (priv_state->frame_height_in_max_lcu >> 4) * 32;
670 ALLOC_GPE_RESOURCE(res_vme_8x8_mode_buffer,
671 "Vme 8x8 mode",
672 res_size);
673
674 res_size = (priv_state->frame_width_in_max_lcu >> 3) *
675 (priv_state->frame_height_in_max_lcu >> 3) * 32;
676 ALLOC_GPE_RESOURCE(res_intra_mode_buffer,
677 "Intra mode",
678 res_size);
679
680 res_size = (priv_state->frame_width_in_max_lcu >> 4) *
681 (priv_state->frame_height_in_max_lcu >> 4) * 16;
682 ALLOC_GPE_RESOURCE(res_intra_distortion_buffer,
683 "Intra distortion",
684 res_size);
685
686 width = priv_state->frame_width_in_max_lcu >> 1;
687 height = priv_state->frame_height_in_max_lcu >> 4;
688 ALLOC_GPE_2D_RESOURCE(res_min_distortion_buffer,
689 "Min distortion buffer",
690 width, height, width);
691
692 res_size = priv_state->frame_width_in_max_lcu *
693 priv_state->frame_height_in_max_lcu;
694 ALLOC_GPE_RESOURCE(res_vme_uni_sic_buffer,
695 "Vme uni sic buffer",
696 res_size);
697
698 width = sizeof(gen9_hevc_mbenc_control_region);
699 height = GEN9_HEVC_ENC_CONCURRENT_SURFACE_HEIGHT;
700 ALLOC_GPE_2D_RESOURCE(res_con_corrent_thread_buffer,
701 "Con corrent thread buffer",
702 width, height, width);
703
704 res_size = priv_state->frame_width_in_max_lcu *
705 priv_state->frame_height_in_max_lcu / 4;
706 ALLOC_GPE_RESOURCE(res_mv_index_buffer,
707 "Mv index buffer",
708 res_size);
709
710 res_size = priv_state->frame_width_in_max_lcu *
711 priv_state->frame_height_in_max_lcu / 2;
712 ALLOC_GPE_RESOURCE(res_mvp_index_buffer,
713 "Mvp index buffer",
714 res_size);
715
716 width = ALIGN(priv_state->width_in_mb * 4, 64);
717 height = ALIGN(priv_state->height_in_mb, 8);
718 ALLOC_GPE_2D_RESOURCE(res_roi_buffer,
719 "ROI buffer",
720 width, height, width);
721
722 res_size = priv_state->width_in_mb *
723 priv_state->height_in_mb * 52;
724 ALLOC_GPE_RESOURCE(res_mb_statistics_buffer,
725 "MB statistics buffer",
726 res_size);
727
728 // PAK pipe buffer allocation
729 size_shift = (priv_state->bit_depth_luma_minus8 ||
730 priv_state->bit_depth_chroma_minus8) ? 2 : 3;
731
732 res_size = ALIGN(priv_state->picture_width, 32) >> size_shift;
733 ALLOC_GPE_RESOURCE(deblocking_filter_line_buffer,
734 "Deblocking filter line buffer",
735 res_size << 6);
736 ALLOC_GPE_RESOURCE(deblocking_filter_tile_line_buffer,
737 "Deblocking filter tile line buffer",
738 res_size << 6);
739
740 res_size = ALIGN(priv_state->picture_height +
741 priv_state->height_in_lcu * 6, 32) >> size_shift;
742 ALLOC_GPE_RESOURCE(deblocking_filter_tile_column_buffer,
743 "Deblocking filter tile column buffer",
744 res_size << 6);
745
746 res_size = (((priv_state->picture_width + 15) >> 4) * 188 +
747 priv_state->width_in_lcu * 9 + 1023) >> 9;
748 ALLOC_GPE_RESOURCE(metadata_line_buffer,
749 "metadata line buffer",
750 res_size << 6);
751
752 res_size = (((priv_state->picture_width + 15) >> 4) * 172 +
753 priv_state->width_in_lcu * 9 + 1023) >> 9;
754 ALLOC_GPE_RESOURCE(metadata_tile_line_buffer,
755 "metadata tile line buffer",
756 res_size << 6);
757
758 res_size = (((priv_state->picture_height + 15) >> 4) * 176 +
759 priv_state->height_in_lcu * 89 + 1023) >> 9;
760 ALLOC_GPE_RESOURCE(metadata_tile_column_buffer,
761 "metadata tile column buffer",
762 res_size << 6);
763
764 res_size = ALIGN(((priv_state->picture_width >> 1) +
765 priv_state->width_in_lcu * 3), 16) >> size_shift;
766 ALLOC_GPE_RESOURCE(sao_line_buffer,
767 "sao line buffer",
768 res_size << 6);
769
770 res_size = ALIGN(((priv_state->picture_width >> 1) +
771 priv_state->width_in_lcu * 6), 16) >> size_shift;
772 ALLOC_GPE_RESOURCE(sao_tile_line_buffer,
773 "sao tile line buffer",
774 res_size << 6);
775
776 res_size = ALIGN(((priv_state->picture_height >> 1) +
777 priv_state->height_in_lcu * 6), 16) >> size_shift;
778 ALLOC_GPE_RESOURCE(sao_tile_column_buffer,
779 "sao tile column buffer",
780 res_size << 6);
781
782 priv_ctx->res_inited = 1;
783 return VA_STATUS_SUCCESS;
784
785 FAIL:
786 gen9_hevc_enc_free_resources(vme_context);
787 return VA_STATUS_ERROR_ALLOCATION_FAILED;
788 }
789
790 #define VME_IMPLEMENTATION_START
791
792 static void
gen9_hevc_set_gpe_1d_surface(VADriverContextP ctx,struct gen9_hevc_encoder_context * priv_ctx,struct i965_gpe_context * gpe_context,GEN9_HEVC_ENC_SURFACE_TYPE surface_type,int bti_idx,int is_raw_buffer,int size,unsigned int offset,struct i965_gpe_resource * gpe_buffer,dri_bo * bo)793 gen9_hevc_set_gpe_1d_surface(VADriverContextP ctx,
794 struct gen9_hevc_encoder_context *priv_ctx,
795 struct i965_gpe_context *gpe_context,
796 GEN9_HEVC_ENC_SURFACE_TYPE surface_type,
797 int bti_idx,
798 int is_raw_buffer,
799 int size,
800 unsigned int offset,
801 struct i965_gpe_resource *gpe_buffer,
802 dri_bo *bo)
803 {
804 if (!gpe_buffer && !bo) {
805 gpe_buffer = priv_ctx->gpe_surfaces[surface_type].gpe_resource;
806 bo = priv_ctx->gpe_surfaces[surface_type].bo;
807 }
808
809 if (gpe_buffer)
810 i965_add_buffer_gpe_surface(ctx, gpe_context,
811 gpe_buffer, is_raw_buffer,
812 size == 0 ? gpe_buffer->size - offset : size,
813 offset, bti_idx);
814 else if (bo)
815 gen9_add_dri_buffer_gpe_surface(ctx, gpe_context,
816 bo, is_raw_buffer,
817 size == 0 ? bo->size - offset : size,
818 offset, bti_idx);
819 }
820
821 static void
gen9_hevc_set_gpe_2d_surface(VADriverContextP ctx,struct gen9_hevc_encoder_context * priv_ctx,struct i965_gpe_context * gpe_context,GEN9_HEVC_ENC_SURFACE_TYPE surface_type,int bti_idx,int has_uv_surface,int is_media_block_rw,unsigned int format,struct i965_gpe_resource * gpe_buffer,struct object_surface * surface_object)822 gen9_hevc_set_gpe_2d_surface(VADriverContextP ctx,
823 struct gen9_hevc_encoder_context *priv_ctx,
824 struct i965_gpe_context *gpe_context,
825 GEN9_HEVC_ENC_SURFACE_TYPE surface_type,
826 int bti_idx,
827 int has_uv_surface,
828 int is_media_block_rw,
829 unsigned int format,
830 struct i965_gpe_resource *gpe_buffer,
831 struct object_surface *surface_object)
832 {
833 if (!gpe_buffer && !surface_object) {
834 gpe_buffer = priv_ctx->gpe_surfaces[surface_type].gpe_resource;
835 surface_object = priv_ctx->gpe_surfaces[surface_type].surface_object;
836 }
837
838 if (gpe_buffer) {
839 i965_add_buffer_2d_gpe_surface(ctx,
840 gpe_context,
841 gpe_buffer,
842 is_media_block_rw,
843 format,
844 bti_idx);
845 } else if (surface_object) {
846 i965_add_2d_gpe_surface(ctx, gpe_context,
847 surface_object,
848 0, is_media_block_rw, format,
849 bti_idx);
850
851 if (has_uv_surface)
852 i965_add_2d_gpe_surface(ctx, gpe_context,
853 surface_object,
854 1, is_media_block_rw, format,
855 bti_idx + 1);
856 }
857 }
858
859 static void
gen9_hevc_set_gpe_adv_surface(VADriverContextP ctx,struct gen9_hevc_encoder_context * priv_ctx,struct i965_gpe_context * gpe_context,GEN9_HEVC_ENC_SURFACE_TYPE surface_type,int bti_idx,struct object_surface * surface_object)860 gen9_hevc_set_gpe_adv_surface(VADriverContextP ctx,
861 struct gen9_hevc_encoder_context *priv_ctx,
862 struct i965_gpe_context *gpe_context,
863 GEN9_HEVC_ENC_SURFACE_TYPE surface_type,
864 int bti_idx,
865 struct object_surface *surface_object)
866 {
867 if (!surface_object)
868 surface_object = priv_ctx->gpe_surfaces[surface_type].surface_object;
869
870 if (surface_object)
871 i965_add_adv_gpe_surface(ctx, gpe_context,
872 surface_object, bti_idx);
873 }
874
875 static void
gen9_hevc_add_gpe_surface(struct gen9_hevc_encoder_context * priv_ctx,GEN9_HEVC_ENC_SURFACE_TYPE surface_type,struct i965_gpe_resource * gpe_buffer,struct object_surface * surface_object)876 gen9_hevc_add_gpe_surface(struct gen9_hevc_encoder_context *priv_ctx,
877 GEN9_HEVC_ENC_SURFACE_TYPE surface_type,
878 struct i965_gpe_resource *gpe_buffer,
879 struct object_surface *surface_object)
880 {
881 if (gpe_buffer && gpe_buffer->bo)
882 priv_ctx->gpe_surfaces[surface_type].gpe_resource = gpe_buffer;
883 else if (surface_object)
884 priv_ctx->gpe_surfaces[surface_type].surface_object = surface_object;
885 }
886
887 static void
gen9_hevc_init_gpe_surfaces_table(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)888 gen9_hevc_init_gpe_surfaces_table(VADriverContextP ctx,
889 struct encode_state *encode_state,
890 struct intel_encoder_context *encoder_context)
891 {
892 struct encoder_vme_mfc_context *vme_context = NULL;
893 struct gen9_hevc_encoder_context *priv_ctx = NULL;
894 struct gen9_hevc_surface_priv *surface_priv = NULL;
895
896 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
897 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
898
899 if (encode_state->reconstructed_object->fourcc == VA_FOURCC_P010) {
900 surface_priv = (struct gen9_hevc_surface_priv *)encode_state->reconstructed_object->private_data;
901
902 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_RAW_Y, NULL,
903 surface_priv->surface_obj_nv12);
904 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_RAW_Y_UV, NULL,
905 surface_priv->surface_obj_nv12);
906 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_RAW_VME, NULL,
907 surface_priv->surface_obj_nv12);
908 } else {
909 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_RAW_Y, NULL,
910 encode_state->input_yuv_object);
911 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_RAW_Y_UV, NULL,
912 encode_state->input_yuv_object);
913 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_RAW_VME, NULL,
914 encode_state->input_yuv_object);
915 }
916
917 if (priv_ctx->scaled_2x_surface_obj) {
918 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_Y_2X, NULL,
919 priv_ctx->scaled_2x_surface_obj);
920 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_Y_2X_VME, NULL,
921 priv_ctx->scaled_2x_surface_obj);
922 }
923
924 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_BRC_HISTORY,
925 &priv_ctx->res_brc_history_buffer,
926 NULL);
927 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_BRC_PAST_PAK_INFO,
928 &priv_ctx->res_brc_pak_statistic_buffer,
929 NULL);
930 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_HCP_PAK,
931 &priv_ctx->res_mb_code_surface,
932 NULL);
933 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_CU_RECORD,
934 &priv_ctx->res_mb_code_surface,
935 NULL);
936 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_32x32_PU_OUTPUT,
937 &priv_ctx->res_32x32_pu_output_buffer,
938 NULL);
939 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_SLICE_MAP,
940 &priv_ctx->res_slice_map_buffer,
941 NULL);
942 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_BRC_INPUT,
943 &priv_ctx->res_brc_input_buffer_for_enc_kernels,
944 NULL);
945 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_LCU_QP,
946 &priv_ctx->res_brc_mb_qp_buffer,
947 NULL);
948 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_ROI,
949 &priv_ctx->res_roi_buffer,
950 NULL);
951 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_RAW_MBSTAT,
952 &priv_ctx->res_mb_statistics_buffer,
953 NULL);
954 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_BRC_DATA,
955 &priv_ctx->res_brc_constant_data_buffer,
956 NULL);
957 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_KERNEL_DEBUG,
958 &priv_ctx->res_kernel_debug,
959 NULL);
960 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_SIMPLIFIED_INTRA,
961 &priv_ctx->res_simplest_intra_buffer,
962 NULL);
963 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_HME_MVP,
964 &priv_ctx->s4x_memv_data_buffer,
965 NULL);
966 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_HME_DIST,
967 &priv_ctx->s4x_memv_distortion_buffer,
968 NULL);
969 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_16x16PU_SAD,
970 &priv_ctx->res_sad_16x16_pu_buffer,
971 NULL);
972 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_VME_8x8,
973 &priv_ctx->res_vme_8x8_mode_buffer,
974 NULL);
975 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_INTRA_MODE,
976 &priv_ctx->res_intra_mode_buffer,
977 NULL);
978 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_INTRA_DIST,
979 &priv_ctx->res_intra_distortion_buffer,
980 NULL);
981 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_MIN_DIST,
982 &priv_ctx->res_min_distortion_buffer,
983 NULL);
984 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_VME_UNI_SIC_DATA,
985 &priv_ctx->res_vme_uni_sic_buffer,
986 NULL);
987 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_CONCURRENT_THREAD,
988 &priv_ctx->res_con_corrent_thread_buffer,
989 NULL);
990 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_MB_MV_INDEX,
991 &priv_ctx->res_mv_index_buffer,
992 NULL);
993 gen9_hevc_add_gpe_surface(priv_ctx, HEVC_ENC_SURFACE_MVP_INDEX,
994 &priv_ctx->res_mvp_index_buffer,
995 NULL);
996 }
997
998 static VAStatus
gen9_hevc_enc_check_parameters(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)999 gen9_hevc_enc_check_parameters(VADriverContextP ctx,
1000 struct encode_state *encode_state,
1001 struct intel_encoder_context *encoder_context)
1002 {
1003 VAEncSequenceParameterBufferHEVC *seq_param = NULL;
1004 VAEncPictureParameterBufferHEVC *pic_param = NULL;
1005 VAEncSliceParameterBufferHEVC *slice_param = NULL;
1006 int i = 0, j = 0;
1007
1008 seq_param = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
1009 pic_param = (VAEncPictureParameterBufferHEVC *)encode_state->pic_param_ext->buffer;
1010
1011 for (i = 0; i < encode_state->num_slice_params_ext; i++) {
1012 slice_param = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[i]->buffer;
1013
1014 if (slice_param->slice_fields.bits.slice_temporal_mvp_enabled_flag &&
1015 slice_param->slice_fields.bits.collocated_from_l0_flag &&
1016 (pic_param->collocated_ref_pic_index == 0xff ||
1017 pic_param->collocated_ref_pic_index > GEN9_MAX_REF_SURFACES))
1018 slice_param->slice_fields.bits.slice_temporal_mvp_enabled_flag = 0;
1019
1020 if (slice_param->num_ref_idx_l0_active_minus1 > GEN9_HEVC_NUM_MAX_REF_L0 - 1 ||
1021 slice_param->num_ref_idx_l1_active_minus1 > GEN9_HEVC_NUM_MAX_REF_L1 - 1)
1022 return VA_STATUS_ERROR_ATTR_NOT_SUPPORTED;
1023 }
1024
1025 i = 1 << (seq_param->log2_diff_max_min_luma_coding_block_size +
1026 seq_param->log2_min_luma_coding_block_size_minus3 + 3);
1027 if (i < GEN9_HEVC_ENC_MIN_LCU_SIZE ||
1028 i > GEN9_HEVC_ENC_MAX_LCU_SIZE)
1029 return VA_STATUS_ERROR_ATTR_NOT_SUPPORTED;
1030
1031 //The TU max size in SPS must be the same as the CU max size in SPS
1032 i = seq_param->log2_min_transform_block_size_minus2 +
1033 seq_param->log2_diff_max_min_transform_block_size + 2;
1034 j = seq_param->log2_min_luma_coding_block_size_minus3 +
1035 seq_param->log2_diff_max_min_luma_coding_block_size + 3;
1036
1037 if (i != j)
1038 return VA_STATUS_ERROR_ATTR_NOT_SUPPORTED;
1039
1040 slice_param = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
1041 i = pic_param->pic_init_qp + slice_param->slice_qp_delta;
1042 j = -seq_param->seq_fields.bits.bit_depth_luma_minus8 * 6;
1043 if (i < j || i > 51)
1044 return VA_STATUS_ERROR_INVALID_PARAMETER;
1045
1046 return VA_STATUS_SUCCESS;
1047 }
1048
1049 static void
gen9_hevc_enc_init_seq_parameters(struct gen9_hevc_encoder_context * priv_ctx,struct generic_enc_codec_state * generic_state,struct gen9_hevc_encoder_state * priv_state,VAEncSequenceParameterBufferHEVC * seq_param)1050 gen9_hevc_enc_init_seq_parameters(struct gen9_hevc_encoder_context *priv_ctx,
1051 struct generic_enc_codec_state *generic_state,
1052 struct gen9_hevc_encoder_state *priv_state,
1053 VAEncSequenceParameterBufferHEVC *seq_param)
1054 {
1055 int new = 0, m = 0, n = 0;
1056
1057 if (priv_state->picture_width != seq_param->pic_width_in_luma_samples ||
1058 priv_state->picture_height != seq_param->pic_height_in_luma_samples ||
1059 priv_state->bit_depth_luma_minus8 != seq_param->seq_fields.bits.bit_depth_luma_minus8 ||
1060 priv_state->bit_depth_chroma_minus8 != seq_param->seq_fields.bits.bit_depth_chroma_minus8)
1061 new = 1;
1062
1063 if (!new)
1064 return;
1065
1066 priv_state->bit_depth_luma_minus8 = seq_param->seq_fields.bits.bit_depth_luma_minus8;
1067 priv_state->bit_depth_chroma_minus8 = seq_param->seq_fields.bits.bit_depth_chroma_minus8;
1068 priv_state->cu_size = 1 << (seq_param->log2_min_luma_coding_block_size_minus3 + 3);
1069 priv_state->lcu_size = 1 << (seq_param->log2_diff_max_min_luma_coding_block_size +
1070 seq_param->log2_min_luma_coding_block_size_minus3 + 3);
1071 priv_state->picture_width = (seq_param->pic_width_in_luma_samples / priv_state->cu_size) * priv_state->cu_size;
1072 priv_state->picture_height = (seq_param->pic_height_in_luma_samples / priv_state->cu_size) * priv_state->cu_size;
1073 priv_state->width_in_lcu = ALIGN(priv_state->picture_width, priv_state->lcu_size) / priv_state->lcu_size;
1074 priv_state->height_in_lcu = ALIGN(priv_state->picture_height, priv_state->lcu_size) / priv_state->lcu_size;
1075 priv_state->width_in_cu = ALIGN(priv_state->picture_width, priv_state->cu_size) / priv_state->cu_size;
1076 priv_state->height_in_cu = ALIGN(priv_state->picture_height, priv_state->cu_size) / priv_state->cu_size;
1077 priv_state->width_in_mb = ALIGN(priv_state->picture_width, 16) / 16;
1078 priv_state->height_in_mb = ALIGN(priv_state->picture_height, 16) / 16;
1079
1080 m = (priv_state->picture_width + GEN9_HEVC_ENC_MIN_LCU_SIZE - 1) / GEN9_HEVC_ENC_MIN_LCU_SIZE;
1081 n = (priv_state->picture_height + GEN9_HEVC_ENC_MIN_LCU_SIZE - 1) / GEN9_HEVC_ENC_MIN_LCU_SIZE;
1082 priv_state->mb_data_offset = ALIGN(m * n * priv_state->pak_obj_size, 0x1000);
1083
1084 m = ALIGN(priv_state->picture_width, GEN9_HEVC_ENC_MAX_LCU_SIZE) / 8;
1085 n = ALIGN(priv_state->picture_height, GEN9_HEVC_ENC_MAX_LCU_SIZE) / 8;
1086 priv_state->mb_code_size = priv_state->mb_data_offset +
1087 ALIGN(m * n * priv_state->cu_record_size, 0x1000);
1088
1089 priv_state->frame_width_in_max_lcu = ALIGN(priv_state->picture_width, 32);
1090 priv_state->frame_height_in_max_lcu = ALIGN(priv_state->picture_height, 32);
1091 priv_state->frame_width_4x = ALIGN(priv_state->picture_width / 4, 16);
1092 priv_state->frame_height_4x = ALIGN(priv_state->picture_height / 4, 16);
1093 priv_state->frame_width_16x = ALIGN(priv_state->picture_width / 16, 16);
1094 priv_state->frame_height_16x = ALIGN(priv_state->picture_height / 16, 16);
1095 priv_state->frame_width_32x = ALIGN(priv_state->picture_width / 32, 16);
1096 priv_state->frame_height_32x = ALIGN(priv_state->picture_height / 32, 16);
1097
1098 priv_state->downscaled_width_4x_in_mb = priv_state->frame_width_4x / 16;
1099 if (priv_state->bit_depth_luma_minus8) {
1100 priv_state->downscaled_width_4x_in_mb = ALIGN(priv_state->downscaled_width_4x_in_mb * 16, 32) /
1101 16;
1102 priv_state->frame_width_4x = priv_state->downscaled_width_4x_in_mb * 16;
1103 }
1104
1105 priv_state->downscaled_height_4x_in_mb = priv_state->frame_height_4x / 16;
1106 priv_state->downscaled_width_16x_in_mb = priv_state->frame_width_16x / 16;
1107 priv_state->downscaled_height_16x_in_mb = priv_state->frame_height_16x / 16;
1108 priv_state->downscaled_width_32x_in_mb = priv_state->frame_width_32x / 16;
1109 priv_state->downscaled_height_32x_in_mb = priv_state->frame_height_32x / 16;
1110 priv_state->flatness_check_enable = priv_state->flatness_check_supported;
1111 priv_state->widi_first_intra_refresh = 1;
1112
1113 generic_state->hme_supported = GEN9_HEVC_HME_SUPPORTED;
1114 generic_state->b16xme_supported = GEN9_HEVC_16XME_SUPPORTED;
1115 generic_state->b32xme_supported = GEN9_HEVC_32XME_SUPPORTED;
1116 if (generic_state->hme_supported &&
1117 (priv_state->frame_width_4x < GEN9_HEVC_VME_MIN_ALLOWED_SIZE ||
1118 priv_state->frame_height_4x < GEN9_HEVC_VME_MIN_ALLOWED_SIZE)) {
1119 generic_state->b16xme_supported = 0;
1120 generic_state->b32xme_supported = 0;
1121
1122 if (priv_state->frame_width_4x < GEN9_HEVC_VME_MIN_ALLOWED_SIZE) {
1123 priv_state->frame_width_4x = GEN9_HEVC_VME_MIN_ALLOWED_SIZE;
1124 priv_state->downscaled_width_4x_in_mb = priv_state->frame_width_4x / 16;
1125 }
1126
1127 if (priv_state->frame_height_4x < GEN9_HEVC_VME_MIN_ALLOWED_SIZE) {
1128 priv_state->frame_height_4x = GEN9_HEVC_VME_MIN_ALLOWED_SIZE;
1129 priv_state->downscaled_height_4x_in_mb = priv_state->frame_height_4x / 16;
1130 }
1131 } else if (generic_state->b16xme_supported &&
1132 (priv_state->frame_width_16x < GEN9_HEVC_VME_MIN_ALLOWED_SIZE ||
1133 priv_state->frame_height_16x < GEN9_HEVC_VME_MIN_ALLOWED_SIZE)) {
1134 generic_state->b32xme_supported = 0;
1135
1136 if (priv_state->frame_width_16x < GEN9_HEVC_VME_MIN_ALLOWED_SIZE) {
1137 priv_state->frame_width_16x = GEN9_HEVC_VME_MIN_ALLOWED_SIZE;
1138 priv_state->downscaled_width_16x_in_mb = priv_state->frame_width_16x / 16;
1139 }
1140
1141 if (priv_state->frame_height_16x < GEN9_HEVC_VME_MIN_ALLOWED_SIZE) {
1142 priv_state->frame_height_16x = GEN9_HEVC_VME_MIN_ALLOWED_SIZE;
1143 priv_state->downscaled_height_16x_in_mb = priv_state->frame_height_16x / 16;
1144 }
1145 } else if (generic_state->b32xme_supported &&
1146 (priv_state->frame_width_32x < GEN9_HEVC_VME_MIN_ALLOWED_SIZE ||
1147 priv_state->frame_height_32x < GEN9_HEVC_VME_MIN_ALLOWED_SIZE)) {
1148 if (priv_state->frame_width_32x < GEN9_HEVC_VME_MIN_ALLOWED_SIZE) {
1149 priv_state->frame_width_32x = GEN9_HEVC_VME_MIN_ALLOWED_SIZE;
1150 priv_state->downscaled_width_32x_in_mb = priv_state->frame_width_32x / 16;
1151 }
1152
1153 if (priv_state->frame_height_32x < GEN9_HEVC_VME_MIN_ALLOWED_SIZE) {
1154 priv_state->frame_height_32x = GEN9_HEVC_VME_MIN_ALLOWED_SIZE;
1155 priv_state->downscaled_height_32x_in_mb = priv_state->frame_height_32x / 16;
1156 }
1157 }
1158
1159 priv_state->gop_ref_dist = seq_param->ip_period;
1160 priv_state->gop_size = seq_param->intra_period;
1161 priv_state->frame_number = 0;
1162
1163 priv_ctx->res_inited = 0;
1164 }
1165
1166 static void
gen9_hevc_enc_init_pic_parameters(struct generic_enc_codec_state * generic_state,struct gen9_hevc_encoder_state * priv_state,VAEncSequenceParameterBufferHEVC * seq_param,VAEncPictureParameterBufferHEVC * pic_param,VAEncSliceParameterBufferHEVC * slice_param)1167 gen9_hevc_enc_init_pic_parameters(struct generic_enc_codec_state *generic_state,
1168 struct gen9_hevc_encoder_state *priv_state,
1169 VAEncSequenceParameterBufferHEVC *seq_param,
1170 VAEncPictureParameterBufferHEVC *pic_param,
1171 VAEncSliceParameterBufferHEVC *slice_param)
1172 {
1173 unsigned int log2_max_coding_block_size = 0, raw_ctu_bits = 0;
1174
1175 priv_state->picture_coding_type = slice_param->slice_type;
1176
1177 priv_state->ctu_max_bitsize_allowed = pic_param->ctu_max_bitsize_allowed;
1178 log2_max_coding_block_size = seq_param->log2_min_luma_coding_block_size_minus3 + 3 +
1179 seq_param->log2_diff_max_min_luma_coding_block_size;
1180 raw_ctu_bits = (1 << (2 * log2_max_coding_block_size + 3)) +
1181 (1 << (2 * log2_max_coding_block_size + 2));
1182 raw_ctu_bits = (5 * raw_ctu_bits / 3);
1183
1184 if (priv_state->ctu_max_bitsize_allowed == 0 ||
1185 priv_state->ctu_max_bitsize_allowed > raw_ctu_bits)
1186 priv_state->ctu_max_bitsize_allowed = raw_ctu_bits;
1187 }
1188
1189 static void
gen9_hevc_enc_init_slice_parameters(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)1190 gen9_hevc_enc_init_slice_parameters(VADriverContextP ctx,
1191 struct encode_state *encode_state,
1192 struct intel_encoder_context *encoder_context)
1193 {
1194 struct encoder_vme_mfc_context *vme_context = NULL;
1195 struct gen9_hevc_encoder_state *priv_state = NULL;
1196 VAEncPictureParameterBufferHEVC *pic_param = NULL;
1197 VAEncSliceParameterBufferHEVC *slice_param = NULL;
1198 int i = 0, j = 0;
1199
1200 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
1201 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
1202 pic_param = (VAEncPictureParameterBufferHEVC *)encode_state->pic_param_ext->buffer;
1203
1204 priv_state->low_delay = 1;
1205 priv_state->arbitrary_num_mb_in_slice = 0;
1206
1207 for (i = 0; i < encode_state->num_slice_params_ext; i++) {
1208 slice_param = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[i]->buffer;
1209
1210 if (slice_param->slice_type == HEVC_SLICE_B && priv_state->low_delay) {
1211 for (j = 0; j <= slice_param->num_ref_idx_l0_active_minus1; j++) {
1212 if (pic_param->decoded_curr_pic.pic_order_cnt <
1213 slice_param->ref_pic_list0[j].pic_order_cnt)
1214 priv_state->low_delay = 0;
1215 }
1216
1217 for (j = 0; j <= slice_param->num_ref_idx_l1_active_minus1; j++) {
1218 if (pic_param->decoded_curr_pic.pic_order_cnt <
1219 slice_param->ref_pic_list1[j].pic_order_cnt)
1220 priv_state->low_delay = 0;
1221 }
1222 }
1223
1224 if (!priv_state->arbitrary_num_mb_in_slice &&
1225 (slice_param->num_ctu_in_slice % priv_state->width_in_lcu))
1226 priv_state->arbitrary_num_mb_in_slice = 1;
1227 }
1228 }
1229
1230 static VAStatus
gen9_hevc_enc_init_parameters(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)1231 gen9_hevc_enc_init_parameters(VADriverContextP ctx,
1232 struct encode_state *encode_state,
1233 struct intel_encoder_context *encoder_context)
1234 {
1235 struct i965_driver_data *i965 = i965_driver_data(ctx);
1236 struct encoder_vme_mfc_context *vme_context = NULL;
1237 struct generic_enc_codec_state *generic_state = NULL;
1238 struct gen9_hevc_encoder_context *priv_ctx = NULL;
1239 struct gen9_hevc_encoder_state *priv_state = NULL;
1240 VAEncPictureParameterBufferHEVC *pic_param = NULL;
1241 VAEncSequenceParameterBufferHEVC *seq_param = NULL;
1242 VAEncSliceParameterBufferHEVC *slice_param = NULL;
1243 struct object_buffer *obj_buffer = NULL;
1244 VAStatus va_status = VA_STATUS_SUCCESS;
1245
1246 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
1247 generic_state = (struct generic_enc_codec_state *)vme_context->generic_enc_state;
1248 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
1249 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
1250 pic_param = (VAEncPictureParameterBufferHEVC *)encode_state->pic_param_ext->buffer;
1251 seq_param = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
1252 slice_param = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
1253
1254 if (!pic_param || !seq_param || !slice_param)
1255 return VA_STATUS_ERROR_INVALID_PARAMETER;
1256
1257 va_status = gen9_hevc_enc_check_parameters(ctx, encode_state, encoder_context);
1258 if (va_status != VA_STATUS_SUCCESS)
1259 return va_status;
1260
1261 gen9_hevc_enc_init_seq_parameters(priv_ctx, generic_state, priv_state, seq_param);
1262 gen9_hevc_enc_init_pic_parameters(generic_state, priv_state, seq_param, pic_param, slice_param);
1263 gen9_hevc_enc_init_slice_parameters(ctx, encode_state, encoder_context);
1264
1265 if (priv_state->picture_coding_type == HEVC_SLICE_I) {
1266 generic_state->hme_enabled = 0;
1267 generic_state->b16xme_enabled = 0;
1268 generic_state->b32xme_enabled = 0;
1269 } else {
1270 generic_state->hme_enabled = generic_state->hme_supported;
1271 generic_state->b16xme_enabled = generic_state->b16xme_supported;
1272 generic_state->b32xme_enabled = generic_state->b32xme_supported;
1273 }
1274
1275 obj_buffer = BUFFER(pic_param->coded_buf);
1276 if (!obj_buffer ||
1277 !obj_buffer->buffer_store ||
1278 !obj_buffer->buffer_store->bo) {
1279 va_status = VA_STATUS_ERROR_INVALID_PARAMETER;
1280 goto EXIT;
1281 }
1282 encode_state->coded_buf_object = obj_buffer;
1283 priv_state->status_buffer.bo = obj_buffer->buffer_store->bo;
1284
1285 va_status = gen9_hevc_ensure_surface(ctx, priv_state,
1286 encode_state->input_yuv_object, 0);
1287 if (va_status != VA_STATUS_SUCCESS)
1288 goto EXIT;
1289
1290 va_status = gen9_hevc_ensure_surface(ctx, priv_state,
1291 encode_state->reconstructed_object, 1);
1292 if (va_status != VA_STATUS_SUCCESS)
1293 goto EXIT;
1294
1295 #if 0
1296 if (encode_state->input_yuv_object->orig_width > priv_state->picture_width)
1297 encode_state->input_yuv_object->orig_width = priv_state->picture_width;
1298
1299 if (encode_state->input_yuv_object->orig_height > priv_state->picture_height)
1300 encode_state->input_yuv_object->orig_height = priv_state->picture_height;
1301
1302
1303 if (encode_state->reconstructed_object->orig_width > priv_state->picture_width)
1304 encode_state->reconstructed_object->orig_width = priv_state->picture_width;
1305
1306 if (encode_state->reconstructed_object->orig_height > priv_state->picture_height)
1307 encode_state->reconstructed_object->orig_height = priv_state->picture_height;
1308 #endif
1309
1310 va_status = gen9_hevc_init_surface_private(ctx, generic_state, priv_state,
1311 encode_state->reconstructed_object);
1312 if (va_status != VA_STATUS_SUCCESS)
1313 goto EXIT;
1314
1315 {
1316 struct gen9_hevc_surface_priv *surface_priv = NULL;
1317
1318 surface_priv = (struct gen9_hevc_surface_priv *)encode_state->reconstructed_object->private_data;
1319
1320 surface_priv->qp_value = pic_param->pic_init_qp + slice_param->slice_qp_delta;
1321 }
1322
1323 va_status = gen9_hevc_enc_alloc_resources(ctx, encode_state,
1324 encoder_context);
1325 if (va_status != VA_STATUS_SUCCESS)
1326 goto EXIT;
1327
1328 gen9_hevc_init_gpe_surfaces_table(ctx, encode_state,
1329 encoder_context);
1330
1331 EXIT:
1332 return va_status;
1333 }
1334
1335 // VME&BRC implementation
1336
1337 static void
gen9_hevc_vme_init_gpe_context(VADriverContextP ctx,struct i965_gpe_context * gpe_context,unsigned int curbe_size,unsigned int inline_data_size)1338 gen9_hevc_vme_init_gpe_context(VADriverContextP ctx,
1339 struct i965_gpe_context *gpe_context,
1340 unsigned int curbe_size,
1341 unsigned int inline_data_size)
1342 {
1343 struct i965_driver_data *i965 = i965_driver_data(ctx);
1344
1345 gpe_context->curbe.length = curbe_size;
1346
1347 gpe_context->sampler.entry_size = 0;
1348 gpe_context->sampler.max_entries = 0;
1349
1350 gpe_context->idrt.entry_size = ALIGN(sizeof(struct gen8_interface_descriptor_data), 64);
1351 gpe_context->idrt.max_entries = 1;
1352
1353 gpe_context->surface_state_binding_table.max_entries = MAX_HEVC_KERNELS_ENCODER_SURFACES;
1354 gpe_context->surface_state_binding_table.binding_table_offset = 0;
1355 gpe_context->surface_state_binding_table.surface_state_offset = ALIGN(MAX_HEVC_KERNELS_ENCODER_SURFACES * 4, 64);
1356 gpe_context->surface_state_binding_table.length = ALIGN(MAX_HEVC_KERNELS_ENCODER_SURFACES * 4, 64) + ALIGN(MAX_HEVC_KERNELS_ENCODER_SURFACES * SURFACE_STATE_PADDED_SIZE_GEN9, 64);
1357
1358 if (i965->intel.eu_total > 0)
1359 gpe_context->vfe_state.max_num_threads = 6 * i965->intel.eu_total;
1360 else
1361 gpe_context->vfe_state.max_num_threads = 112;
1362
1363 gpe_context->vfe_state.curbe_allocation_size = MAX(1, ALIGN(gpe_context->curbe.length, 32) >> 5);
1364 gpe_context->vfe_state.urb_entry_size = MAX(1, ALIGN(inline_data_size, 32) >> 5);
1365 gpe_context->vfe_state.num_urb_entries = (MAX_HEVC_KERNELS_URB_SIZE -
1366 gpe_context->vfe_state.curbe_allocation_size -
1367 ((gpe_context->idrt.entry_size >> 5) *
1368 gpe_context->idrt.max_entries)) /
1369 gpe_context->vfe_state.urb_entry_size;
1370 gpe_context->vfe_state.num_urb_entries = CLAMP(gpe_context->vfe_state.num_urb_entries, 1, 64);
1371 gpe_context->vfe_state.gpgpu_mode = 0;
1372 }
1373
1374 static void
gen9_hevc_vme_init_scoreboard(struct i965_gpe_context * gpe_context,unsigned int mask,unsigned int enable,unsigned int type)1375 gen9_hevc_vme_init_scoreboard(struct i965_gpe_context *gpe_context,
1376 unsigned int mask,
1377 unsigned int enable,
1378 unsigned int type)
1379 {
1380 gpe_context->vfe_desc5.scoreboard0.mask = mask;
1381 gpe_context->vfe_desc5.scoreboard0.type = type;
1382 gpe_context->vfe_desc5.scoreboard0.enable = enable;
1383
1384 gpe_context->vfe_desc6.scoreboard1.delta_x0 = -1;
1385 gpe_context->vfe_desc6.scoreboard1.delta_y0 = 0;
1386
1387 gpe_context->vfe_desc6.scoreboard1.delta_x1 = 0;
1388 gpe_context->vfe_desc6.scoreboard1.delta_y1 = -1;
1389
1390 gpe_context->vfe_desc6.scoreboard1.delta_x2 = 1;
1391 gpe_context->vfe_desc6.scoreboard1.delta_y2 = -1;
1392
1393 gpe_context->vfe_desc6.scoreboard1.delta_x3 = -1;
1394 gpe_context->vfe_desc6.scoreboard1.delta_y3 = -1;
1395
1396 gpe_context->vfe_desc7.scoreboard2.delta_x4 = -1;
1397 gpe_context->vfe_desc7.scoreboard2.delta_y4 = 1;
1398
1399 gpe_context->vfe_desc7.scoreboard2.delta_x5 = 0;
1400 gpe_context->vfe_desc7.scoreboard2.delta_y5 = -2;
1401
1402 gpe_context->vfe_desc7.scoreboard2.delta_x6 = 1;
1403 gpe_context->vfe_desc7.scoreboard2.delta_y6 = -2;
1404
1405 gpe_context->vfe_desc7.scoreboard2.delta_x7 = -1;
1406 gpe_context->vfe_desc7.scoreboard2.delta_y7 = -2;
1407 }
1408
1409 static void
gen9_hevc_vme_set_scoreboard_26z(struct i965_gpe_context * gpe_context,unsigned int mask,unsigned int enable,unsigned int type)1410 gen9_hevc_vme_set_scoreboard_26z(struct i965_gpe_context *gpe_context,
1411 unsigned int mask,
1412 unsigned int enable,
1413 unsigned int type)
1414 {
1415 gpe_context->vfe_desc5.scoreboard0.mask = mask;
1416 gpe_context->vfe_desc5.scoreboard0.type = type;
1417 gpe_context->vfe_desc5.scoreboard0.enable = enable;
1418
1419 gpe_context->vfe_desc6.scoreboard1.delta_x0 = -1;
1420 gpe_context->vfe_desc6.scoreboard1.delta_y0 = 3;
1421
1422 gpe_context->vfe_desc6.scoreboard1.delta_x1 = -1;
1423 gpe_context->vfe_desc6.scoreboard1.delta_y1 = 1;
1424
1425 gpe_context->vfe_desc6.scoreboard1.delta_x2 = -1;
1426 gpe_context->vfe_desc6.scoreboard1.delta_y2 = -1;
1427
1428 gpe_context->vfe_desc6.scoreboard1.delta_x3 = 0;
1429 gpe_context->vfe_desc6.scoreboard1.delta_y3 = -1;
1430
1431 gpe_context->vfe_desc7.scoreboard2.delta_x4 = 0;
1432 gpe_context->vfe_desc7.scoreboard2.delta_y4 = -2;
1433
1434 gpe_context->vfe_desc7.scoreboard2.delta_x5 = 0;
1435 gpe_context->vfe_desc7.scoreboard2.delta_y5 = -3;
1436
1437 gpe_context->vfe_desc7.scoreboard2.delta_x6 = 1;
1438 gpe_context->vfe_desc7.scoreboard2.delta_y6 = -2;
1439
1440 gpe_context->vfe_desc7.scoreboard2.delta_x7 = 1;
1441 gpe_context->vfe_desc7.scoreboard2.delta_y7 = -3;
1442 }
1443
1444 static void
gen9_hevc_vme_set_scoreboard_26(struct i965_gpe_context * gpe_context,unsigned int mask,unsigned int enable,unsigned int type)1445 gen9_hevc_vme_set_scoreboard_26(struct i965_gpe_context *gpe_context,
1446 unsigned int mask,
1447 unsigned int enable,
1448 unsigned int type)
1449 {
1450 gpe_context->vfe_desc5.scoreboard0.mask = mask;
1451 gpe_context->vfe_desc5.scoreboard0.type = type;
1452 gpe_context->vfe_desc5.scoreboard0.enable = enable;
1453
1454 gpe_context->vfe_desc6.scoreboard1.delta_x0 = -1;
1455 gpe_context->vfe_desc6.scoreboard1.delta_y0 = 0;
1456
1457 gpe_context->vfe_desc6.scoreboard1.delta_x1 = -1;
1458 gpe_context->vfe_desc6.scoreboard1.delta_y1 = -1;
1459
1460 gpe_context->vfe_desc6.scoreboard1.delta_x2 = 0;
1461 gpe_context->vfe_desc6.scoreboard1.delta_y2 = -1;
1462
1463 gpe_context->vfe_desc6.scoreboard1.delta_x3 = 1;
1464 gpe_context->vfe_desc6.scoreboard1.delta_y3 = -1;
1465 }
1466
1467 static void
gen9_hevc_init_object_walker(struct hevc_enc_kernel_walker_parameter * hevc_walker_param,struct gpe_media_object_walker_parameter * gpe_param)1468 gen9_hevc_init_object_walker(struct hevc_enc_kernel_walker_parameter *hevc_walker_param,
1469 struct gpe_media_object_walker_parameter *gpe_param)
1470 {
1471 memset(gpe_param, 0, sizeof(*gpe_param));
1472
1473 gpe_param->use_scoreboard = hevc_walker_param->use_scoreboard;
1474 gpe_param->block_resolution.x = hevc_walker_param->resolution_x;
1475 gpe_param->block_resolution.y = hevc_walker_param->resolution_y;
1476 gpe_param->global_resolution.x = hevc_walker_param->resolution_x;
1477 gpe_param->global_resolution.y = hevc_walker_param->resolution_y;
1478 gpe_param->global_outer_loop_stride.x = hevc_walker_param->resolution_x;
1479 gpe_param->global_outer_loop_stride.y = 0;
1480 gpe_param->global_inner_loop_unit.x = 0;
1481 gpe_param->global_inner_loop_unit.y = hevc_walker_param->resolution_y;
1482 gpe_param->local_loop_exec_count = 0xFFFF;
1483 gpe_param->global_loop_exec_count = 0xFFFF;
1484
1485 if (hevc_walker_param->no_dependency) {
1486 gpe_param->scoreboard_mask = 0;
1487 gpe_param->use_scoreboard = 0;
1488 gpe_param->local_outer_loop_stride.x = 0;
1489 gpe_param->local_outer_loop_stride.y = 1;
1490 gpe_param->local_inner_loop_unit.x = 1;
1491 gpe_param->local_inner_loop_unit.y = 0;
1492 gpe_param->local_end.x = hevc_walker_param->resolution_x - 1;
1493 gpe_param->local_end.y = 0;
1494 }
1495 }
1496
1497 static void
gen9_hevc_init_object_walker_26z(struct gen9_hevc_encoder_state * priv_state,struct i965_gpe_context * gpe_context,struct gpe_media_object_walker_parameter * gpe_param,int split_count,unsigned int max_slight_height,int use_hw_scoreboard,int scoreboard_type)1498 gen9_hevc_init_object_walker_26z(struct gen9_hevc_encoder_state *priv_state,
1499 struct i965_gpe_context *gpe_context,
1500 struct gpe_media_object_walker_parameter *gpe_param,
1501 int split_count,
1502 unsigned int max_slight_height,
1503 int use_hw_scoreboard,
1504 int scoreboard_type)
1505 {
1506 int width = priv_state->width_in_mb;
1507 int height = max_slight_height * 2;
1508 int ts_width = ((width + 3) & 0xfffc) >> 1;
1509 int lcu_width = (width + 1) >> 1;
1510 int lcu_height = (height + 1) >> 1;
1511 int tmp1 = ((lcu_width + 1) >> 1) + ((lcu_width + ((lcu_height - 1) << 1)) + (2 * split_count - 1)) /
1512 (2 * split_count);
1513
1514 gpe_param->use_scoreboard = use_hw_scoreboard;
1515 gpe_param->scoreboard_mask = 0xFF;
1516 gpe_param->global_resolution.x = ts_width;
1517 gpe_param->global_resolution.y = 4 * tmp1;
1518 gpe_param->global_start.x = 0;
1519 gpe_param->global_start.y = 0;
1520 gpe_param->global_outer_loop_stride.x = ts_width;
1521 gpe_param->global_outer_loop_stride.y = 0;
1522 gpe_param->global_inner_loop_unit.x = 0;
1523 gpe_param->global_inner_loop_unit.y = 4 * tmp1;
1524 gpe_param->block_resolution.x = ts_width;
1525 gpe_param->block_resolution.y = 4 * tmp1;
1526 gpe_param->local_start.x = ts_width;
1527 gpe_param->local_start.y = 0;
1528 gpe_param->local_end.x = 0;
1529 gpe_param->local_end.y = 0;
1530 gpe_param->local_outer_loop_stride.x = 1;
1531 gpe_param->local_outer_loop_stride.y = 0;
1532 gpe_param->local_inner_loop_unit.x = -2;
1533 gpe_param->local_inner_loop_unit.y = 4;
1534 gpe_param->middle_loop_extra_steps = 3;
1535 gpe_param->mid_loop_unit_x = 0;
1536 gpe_param->mid_loop_unit_y = 1;
1537 gpe_param->global_loop_exec_count = 0;
1538 gpe_param->local_loop_exec_count = ((lcu_width + (lcu_height - 1) * 2 + 2 * split_count - 1) /
1539 (2 * split_count)) * 2 -
1540 1;
1541
1542 gen9_hevc_vme_set_scoreboard_26z(gpe_context, 0xff, use_hw_scoreboard, scoreboard_type);
1543 }
1544
1545 static void
gen9_hevc_init_object_walker_26(struct gen9_hevc_encoder_state * priv_state,struct i965_gpe_context * gpe_context,struct gpe_media_object_walker_parameter * gpe_param,int split_count,unsigned int max_slight_height,int use_hw_scoreboard,int scoreboard_type)1546 gen9_hevc_init_object_walker_26(struct gen9_hevc_encoder_state *priv_state,
1547 struct i965_gpe_context *gpe_context,
1548 struct gpe_media_object_walker_parameter *gpe_param,
1549 int split_count,
1550 unsigned int max_slight_height,
1551 int use_hw_scoreboard,
1552 int scoreboard_type)
1553 {
1554 int width = priv_state->width_in_mb;
1555 int height = max_slight_height;
1556 int ts_width = (width + 1) & 0xfffe;
1557 int ts_height = (height + 1) & 0xfffe;
1558 int tmp1 = ((ts_width + 1) >> 1) +
1559 ((ts_width + ((ts_height - 1) << 1)) +
1560 (2 * split_count - 1)) / (2 * split_count);
1561
1562 gpe_param->use_scoreboard = use_hw_scoreboard;
1563 gpe_param->scoreboard_mask = 0x0f;
1564 gpe_param->global_resolution.x = ts_width;
1565 gpe_param->global_resolution.y = tmp1;
1566 gpe_param->global_start.x = 0;
1567 gpe_param->global_start.y = 0;
1568 gpe_param->global_outer_loop_stride.x = ts_width;
1569 gpe_param->global_outer_loop_stride.y = 0;
1570 gpe_param->global_inner_loop_unit.x = 0;
1571 gpe_param->global_inner_loop_unit.y = tmp1;
1572 gpe_param->block_resolution.x = ts_width;
1573 gpe_param->block_resolution.y = tmp1;
1574 gpe_param->local_start.x = ts_width;
1575 gpe_param->local_start.y = 0;
1576 gpe_param->local_end.x = 0;
1577 gpe_param->local_end.y = 0;
1578 gpe_param->local_outer_loop_stride.x = 1;
1579 gpe_param->local_outer_loop_stride.y = 0;
1580 gpe_param->local_inner_loop_unit.x = -2;
1581 gpe_param->local_inner_loop_unit.y = 1;
1582 gpe_param->middle_loop_extra_steps = 0;
1583 gpe_param->mid_loop_unit_x = 0;
1584 gpe_param->mid_loop_unit_y = 0;
1585 gpe_param->global_loop_exec_count = 0;
1586 gpe_param->local_loop_exec_count = (width + (height - 1) * 2 + split_count - 1) /
1587 split_count;
1588
1589 gen9_hevc_vme_set_scoreboard_26(gpe_context, 0xff, use_hw_scoreboard, scoreboard_type);
1590 }
1591
1592 static void
gen9_hevc_run_object_walker(VADriverContextP ctx,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context,struct gpe_media_object_walker_parameter * param,int media_state)1593 gen9_hevc_run_object_walker(VADriverContextP ctx,
1594 struct intel_encoder_context *encoder_context,
1595 struct i965_gpe_context *gpe_context,
1596 struct gpe_media_object_walker_parameter *param,
1597 int media_state)
1598 {
1599 struct intel_batchbuffer *batch = encoder_context->base.batch;
1600
1601 intel_batchbuffer_start_atomic(batch, 0x1000);
1602
1603 intel_batchbuffer_emit_mi_flush(batch);
1604
1605 gen9_gpe_pipeline_setup(ctx, gpe_context, batch);
1606 gen8_gpe_media_object_walker(ctx, gpe_context, batch, param);
1607 gen8_gpe_media_state_flush(ctx, gpe_context, batch);
1608 gen9_gpe_pipeline_end(ctx, gpe_context, batch);
1609
1610 intel_batchbuffer_end_atomic(batch);
1611
1612 intel_batchbuffer_flush(batch);
1613 }
1614
1615 static void
gen9_hevc_run_object(VADriverContextP ctx,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context,struct gpe_media_object_parameter * param,int media_state)1616 gen9_hevc_run_object(VADriverContextP ctx,
1617 struct intel_encoder_context *encoder_context,
1618 struct i965_gpe_context *gpe_context,
1619 struct gpe_media_object_parameter *param,
1620 int media_state)
1621 {
1622 struct intel_batchbuffer *batch = encoder_context->base.batch;
1623
1624 intel_batchbuffer_start_atomic(batch, 0x1000);
1625
1626 intel_batchbuffer_emit_mi_flush(batch);
1627
1628 gen9_gpe_pipeline_setup(ctx, gpe_context, batch);
1629 gen8_gpe_media_object(ctx, gpe_context, batch, param);
1630 gen8_gpe_media_state_flush(ctx, gpe_context, batch);
1631
1632 gen9_gpe_pipeline_end(ctx, gpe_context, batch);
1633
1634 intel_batchbuffer_end_atomic(batch);
1635
1636 intel_batchbuffer_flush(batch);
1637 }
1638
1639 static void
gen9_hevc_get_b_mbenc_default_curbe(enum HEVC_TU_MODE tu_mode,int slice_type,void ** curbe_ptr,int * curbe_size)1640 gen9_hevc_get_b_mbenc_default_curbe(enum HEVC_TU_MODE tu_mode,
1641 int slice_type,
1642 void **curbe_ptr,
1643 int *curbe_size)
1644 {
1645 if (tu_mode == HEVC_TU_BEST_SPEED) {
1646 if (slice_type == HEVC_SLICE_I) {
1647 *curbe_size = sizeof(HEVC_ENC_ENCB_TU7_I_CURBE_DATA);
1648 *curbe_ptr = (void *)HEVC_ENC_ENCB_TU7_I_CURBE_DATA;
1649 } else if (slice_type == HEVC_SLICE_P) {
1650 *curbe_size = sizeof(HEVC_ENC_ENCB_TU7_P_CURBE_DATA);
1651 *curbe_ptr = (void *)HEVC_ENC_ENCB_TU7_P_CURBE_DATA;
1652 } else {
1653 *curbe_size = sizeof(HEVC_ENC_ENCB_TU7_B_CURBE_DATA);
1654 *curbe_ptr = (void *)HEVC_ENC_ENCB_TU7_B_CURBE_DATA;
1655 }
1656 } else if (tu_mode == HEVC_TU_RT_SPEED) {
1657 if (slice_type == HEVC_SLICE_P) {
1658 *curbe_size = sizeof(HEVC_ENC_ENCB_TU4_P_CURBE_DATA);
1659 *curbe_ptr = (void *)HEVC_ENC_ENCB_TU4_P_CURBE_DATA;
1660 } else {
1661 *curbe_size = sizeof(HEVC_ENC_ENCB_TU4_B_CURBE_DATA);
1662 *curbe_ptr = (void *)HEVC_ENC_ENCB_TU4_B_CURBE_DATA;
1663 }
1664 } else {
1665 if (slice_type == HEVC_SLICE_P) {
1666 *curbe_size = sizeof(HEVC_ENC_ENCB_TU1_P_CURBE_DATA);
1667 *curbe_ptr = (void *)HEVC_ENC_ENCB_TU1_P_CURBE_DATA;
1668 } else {
1669 *curbe_size = sizeof(HEVC_ENC_ENCB_TU1_B_CURBE_DATA);
1670 *curbe_ptr = (void *)HEVC_ENC_ENCB_TU1_B_CURBE_DATA;
1671 }
1672 }
1673 }
1674
1675 // BRC start
1676
1677 static void
gen9_hevc_configure_roi(struct encode_state * encode_state,struct intel_encoder_context * encoder_context)1678 gen9_hevc_configure_roi(struct encode_state *encode_state,
1679 struct intel_encoder_context *encoder_context)
1680 {
1681 struct encoder_vme_mfc_context *vme_context = NULL;
1682 struct gen9_hevc_encoder_state *priv_state = NULL;
1683 int i = 0;
1684
1685 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
1686 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
1687
1688 priv_state->num_roi = MIN(encoder_context->brc.num_roi, I965_MAX_NUM_ROI_REGIONS);
1689 priv_state->roi_value_is_qp_delta = encoder_context->brc.roi_value_is_qp_delta;
1690
1691 for (i = 0; i < priv_state->num_roi; i++) {
1692 priv_state->roi[i].left = encoder_context->brc.roi[i].left >> 4;
1693 priv_state->roi[i].right = encoder_context->brc.roi[i].right >> 4;
1694 priv_state->roi[i].top = encoder_context->brc.roi[i].top >> 4;
1695 priv_state->roi[i].bottom = encoder_context->brc.roi[i].bottom >> 4;
1696 priv_state->roi[i].value = encoder_context->brc.roi[i].value;
1697 }
1698 }
1699
1700 static void
gen9_hevc_brc_prepare(struct encode_state * encode_state,struct intel_encoder_context * encoder_context)1701 gen9_hevc_brc_prepare(struct encode_state *encode_state,
1702 struct intel_encoder_context *encoder_context)
1703 {
1704 struct encoder_vme_mfc_context *vme_context = NULL;
1705 struct generic_enc_codec_state *generic_state = NULL;
1706 struct gen9_hevc_encoder_state *priv_state = NULL;
1707 enum HEVC_BRC_METHOD brc_method = HEVC_BRC_CQP;
1708 int internal_tu_mode = encoder_context->quality_level;
1709 int brc_reset = 0;
1710
1711 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
1712 generic_state = (struct generic_enc_codec_state *)vme_context->generic_enc_state;
1713 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
1714
1715 if (encoder_context->rate_control_mode & VA_RC_CBR)
1716 brc_method = HEVC_BRC_CBR;
1717 else if (encoder_context->rate_control_mode & VA_RC_VBR)
1718 brc_method = HEVC_BRC_VBR;
1719 else if (encoder_context->rate_control_mode & VA_RC_VCM)
1720 brc_method = HEVC_BRC_VCM;
1721
1722 if (internal_tu_mode >= HEVC_TU_RT_SPEED ||
1723 internal_tu_mode == 0)
1724 internal_tu_mode = internal_tu_mode >= HEVC_TU_BEST_SPEED ?
1725 HEVC_TU_BEST_SPEED : HEVC_TU_RT_SPEED;
1726 else
1727 internal_tu_mode = HEVC_TU_BEST_QUALITY;
1728
1729 brc_reset = priv_state->brc_method != brc_method ||
1730 priv_state->tu_mode != internal_tu_mode;
1731
1732 if (!generic_state->brc_inited ||
1733 encoder_context->brc.need_reset ||
1734 brc_reset) {
1735 priv_state->tu_mode = internal_tu_mode;
1736 if (priv_state->tu_mode == HEVC_TU_BEST_QUALITY)
1737 priv_state->num_regions_in_slice = 1;
1738 else
1739 priv_state->num_regions_in_slice = 4;
1740
1741 if (internal_tu_mode == HEVC_TU_BEST_SPEED)
1742 priv_state->walking_pattern_26 = 1;
1743 else
1744 priv_state->walking_pattern_26 = 0;
1745
1746 if (brc_method == HEVC_BRC_CQP) {
1747 generic_state->brc_enabled = 0;
1748 generic_state->num_pak_passes = 1;
1749 priv_state->lcu_brc_enabled = 0;
1750 } else {
1751 generic_state->brc_enabled = 1;
1752 generic_state->num_pak_passes = 4;
1753
1754 if (brc_method == HEVC_BRC_VCM ||
1755 encoder_context->brc.mb_rate_control[0] == 0)
1756 priv_state->lcu_brc_enabled = (priv_state->tu_mode == HEVC_TU_BEST_QUALITY);
1757 else if (brc_method == HEVC_BRC_ICQ ||
1758 encoder_context->brc.mb_rate_control[0] == 1)
1759 priv_state->lcu_brc_enabled = 1;
1760 else
1761 priv_state->lcu_brc_enabled = 0;
1762
1763 priv_state->max_bit_rate_in_kbs =
1764 ALIGN(encoder_context->brc.bits_per_second[0], HEVC_BRC_KBPS) /
1765 HEVC_BRC_KBPS;
1766
1767 if (brc_method == HEVC_BRC_CBR) {
1768 priv_state->target_bit_rate_in_kbs = priv_state->max_bit_rate_in_kbs;
1769 priv_state->min_bit_rate_in_kbs = priv_state->max_bit_rate_in_kbs;
1770 } else {
1771 if (encoder_context->brc.target_percentage[0] > HEVC_BRC_MIN_TARGET_PERCENTAGE)
1772 priv_state->min_bit_rate_in_kbs = priv_state->max_bit_rate_in_kbs *
1773 (2 * encoder_context->brc.target_percentage[0] - 100) /
1774 100;
1775 else
1776 priv_state->min_bit_rate_in_kbs = 0;
1777
1778 priv_state->target_bit_rate_in_kbs = priv_state->max_bit_rate_in_kbs *
1779 encoder_context->brc.target_percentage[0] / 100;
1780
1781 brc_reset = 1;
1782 }
1783
1784 if (encoder_context->brc.framerate[0].den)
1785 priv_state->frames_per_100s = encoder_context->brc.framerate[0].num * 100 /
1786 encoder_context->brc.framerate[0].den;
1787
1788 priv_state->init_vbv_buffer_fullness_in_bit =
1789 encoder_context->brc.hrd_initial_buffer_fullness;
1790 priv_state->vbv_buffer_size_in_bit =
1791 encoder_context->brc.hrd_buffer_size;
1792 }
1793
1794 priv_state->brc_method = brc_method;
1795 generic_state->brc_need_reset = brc_reset;
1796 encoder_context->brc.need_reset = 0;
1797 }
1798
1799 gen9_hevc_configure_roi(encode_state, encoder_context);
1800 }
1801
1802 static void
gen9_hevc_brc_init_rest_set_curbe(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context,int reset)1803 gen9_hevc_brc_init_rest_set_curbe(VADriverContextP ctx,
1804 struct encode_state *encode_state,
1805 struct intel_encoder_context *encoder_context,
1806 struct i965_gpe_context *gpe_context,
1807 int reset)
1808 {
1809 struct encoder_vme_mfc_context *vme_context = NULL;
1810 struct gen9_hevc_encoder_state *priv_state = NULL;
1811 gen9_hevc_brc_initreset_curbe_data *cmd = NULL;
1812 VAEncSequenceParameterBufferHEVC *seq_param = NULL;
1813 double input_bits_per_frame = 0;
1814 double bps_ratio = 0;
1815
1816 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
1817 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
1818 seq_param = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
1819
1820 cmd = i965_gpe_context_map_curbe(gpe_context);
1821 if (!cmd)
1822 return;
1823
1824 memcpy((void *)cmd, GEN9_HEVC_BRCINIT_CURBE_DATA, sizeof(GEN9_HEVC_BRCINIT_CURBE_DATA));
1825
1826 cmd->dw0.profile_level_max_frame = gen9_hevc_get_profile_level_max_frame(seq_param,
1827 priv_state->user_max_frame_size,
1828 priv_state->frames_per_100s);
1829 cmd->dw1.init_buf_full = priv_state->init_vbv_buffer_fullness_in_bit;
1830 cmd->dw2.buf_size = priv_state->vbv_buffer_size_in_bit;
1831 cmd->dw3.targe_bit_rate = priv_state->target_bit_rate_in_kbs * HEVC_BRC_KBPS;
1832 cmd->dw4.maximum_bit_rate = priv_state->max_bit_rate_in_kbs * HEVC_BRC_KBPS;
1833
1834 cmd->dw9.frame_width = priv_state->picture_width;
1835 cmd->dw10.frame_height = priv_state->picture_height;
1836 cmd->dw12.number_slice = encode_state->num_slice_params_ext;
1837 cmd->dw6.frame_rate_m = priv_state->frames_per_100s;
1838 cmd->dw7.frame_rate_d = 100;
1839 cmd->dw8.brc_flag = 0;
1840 cmd->dw8.brc_flag |= (priv_state->lcu_brc_enabled) ? 0 : HEVC_BRCINIT_DISABLE_MBBRC;
1841 cmd->dw25.acqp_buffer = 1;
1842
1843 if (priv_state->brc_method == HEVC_BRC_CBR) {
1844 cmd->dw4.maximum_bit_rate = cmd->dw3.targe_bit_rate;
1845 cmd->dw8.brc_flag |= HEVC_BRCINIT_ISCBR;
1846 } else if (priv_state->brc_method == HEVC_BRC_VBR) {
1847 if (cmd->dw4.maximum_bit_rate < cmd->dw3.targe_bit_rate)
1848 cmd->dw4.maximum_bit_rate = cmd->dw3.targe_bit_rate * 2;
1849 cmd->dw8.brc_flag |= HEVC_BRCINIT_ISVBR;
1850 } else if (priv_state->brc_method == HEVC_BRC_AVBR) {
1851 cmd->dw4.maximum_bit_rate = priv_state->target_bit_rate_in_kbs * HEVC_BRC_KBPS;
1852 cmd->dw8.brc_flag |= HEVC_BRCINIT_ISAVBR;
1853 } else if (priv_state->brc_method == HEVC_BRC_ICQ) {
1854 cmd->dw25.acqp_buffer = priv_state->crf_quality_factor;
1855 cmd->dw8.brc_flag |= HEVC_BRCINIT_ISICQ;
1856 } else if (priv_state->brc_method == HEVC_BRC_VCM) {
1857 cmd->dw4.maximum_bit_rate = priv_state->target_bit_rate_in_kbs * HEVC_BRC_KBPS;
1858 cmd->dw8.brc_flag |= HEVC_BRCINIT_ISVCM;
1859 }
1860
1861 if (priv_state->num_b_in_gop[1] ||
1862 priv_state->num_b_in_gop[2]) {
1863 cmd->dw8.brc_param_a = priv_state->gop_size / priv_state->gop_ref_dist;
1864 cmd->dw9.brc_param_b = cmd->dw8.brc_param_a;
1865 cmd->dw13.brc_param_c = cmd->dw8.brc_param_a * 2;
1866 cmd->dw14.brc_param_d = priv_state->gop_size - cmd->dw8.brc_param_a -
1867 cmd->dw9.brc_param_b - cmd->dw13.brc_param_c;
1868
1869 if (!priv_state->num_b_in_gop[2])
1870 cmd->dw14.max_brc_level = 3;
1871 else
1872 cmd->dw14.max_brc_level = 4;
1873 } else {
1874 cmd->dw14.max_brc_level = 1;
1875 cmd->dw8.brc_param_a = priv_state->gop_ref_dist ? (priv_state->gop_size - 1) / priv_state->gop_ref_dist : 0;
1876 cmd->dw9.brc_param_b = priv_state->gop_size - 1 - cmd->dw8.brc_param_a;
1877 }
1878
1879 cmd->dw10.avbr_accuracy = GEN9_HEVC_AVBR_ACCURACY;
1880 cmd->dw11.avbr_convergence = GEN9_HEVC_AVBR_CONVERGENCE;
1881
1882 input_bits_per_frame = (double)(cmd->dw4.maximum_bit_rate) *
1883 (double)(cmd->dw7.frame_rate_d) /
1884 (double)(cmd->dw6.frame_rate_m);
1885 if (cmd->dw2.buf_size < (unsigned int)input_bits_per_frame * 4)
1886 cmd->dw2.buf_size = (unsigned int)input_bits_per_frame * 4;
1887
1888 if (cmd->dw1.init_buf_full == 0)
1889 cmd->dw1.init_buf_full = cmd->dw2.buf_size * 7 / 8;
1890
1891 if (cmd->dw1.init_buf_full < (unsigned int)(input_bits_per_frame * 2))
1892 cmd->dw1.init_buf_full = (unsigned int)(input_bits_per_frame * 2);
1893
1894 if (cmd->dw1.init_buf_full > cmd->dw2.buf_size)
1895 cmd->dw1.init_buf_full = cmd->dw2.buf_size;
1896
1897 if (priv_state->brc_method == HEVC_BRC_AVBR) {
1898 cmd->dw2.buf_size = priv_state->target_bit_rate_in_kbs * 2 * HEVC_BRC_KBPS;
1899 cmd->dw1.init_buf_full = (unsigned int)(cmd->dw2.buf_size * 3 / 4);
1900 }
1901
1902 bps_ratio = input_bits_per_frame / (cmd->dw2.buf_size / 30);
1903 bps_ratio = (bps_ratio < 0.1) ? 0.1 : (bps_ratio > 3.5) ? 3.5 : bps_ratio;
1904
1905 cmd->dw19.deviation_threshold0_pbframe = (unsigned int)(-50 * pow(0.90, bps_ratio));
1906 cmd->dw19.deviation_threshold1_pbframe = (unsigned int)(-50 * pow(0.66, bps_ratio));
1907 cmd->dw19.deviation_threshold2_pbframe = (unsigned int)(-50 * pow(0.46, bps_ratio));
1908 cmd->dw19.deviation_threshold3_pbframe = (unsigned int)(-50 * pow(0.3, bps_ratio));
1909
1910 cmd->dw20.deviation_threshold4_pbframe = (unsigned int)(50 * pow(0.3, bps_ratio));
1911 cmd->dw20.deviation_threshold5_pbframe = (unsigned int)(50 * pow(0.46, bps_ratio));
1912 cmd->dw20.deviation_threshold6_pbframe = (unsigned int)(50 * pow(0.7, bps_ratio));
1913 cmd->dw20.deviation_threshold7_pbframe = (unsigned int)(50 * pow(0.9, bps_ratio));
1914
1915 cmd->dw21.deviation_threshold0_vbr_control = (unsigned int)(-50 * pow(0.9, bps_ratio));
1916 cmd->dw21.deviation_threshold1_vbr_control = (unsigned int)(-50 * pow(0.7, bps_ratio));
1917 cmd->dw21.deviation_threshold2_vbr_control = (unsigned int)(-50 * pow(0.5, bps_ratio));
1918 cmd->dw21.deviation_threshold3_vbr_control = (unsigned int)(-50 * pow(0.3, bps_ratio));
1919
1920 cmd->dw22.deviation_threshold4_vbr_control = (unsigned int)(100 * pow(0.4, bps_ratio));
1921 cmd->dw22.deviation_threshold5_vbr_control = (unsigned int)(100 * pow(0.5, bps_ratio));
1922 cmd->dw22.deviation_threshold6_vbr_control = (unsigned int)(100 * pow(0.75, bps_ratio));
1923 cmd->dw22.deviation_threshold7_vbr_control = (unsigned int)(100 * pow(0.9, bps_ratio));
1924
1925 cmd->dw23.deviation_threshold0_iframe = (unsigned int)(-50 * pow(0.8, bps_ratio));
1926 cmd->dw23.deviation_threshold1_iframe = (unsigned int)(-50 * pow(0.6, bps_ratio));
1927 cmd->dw23.deviation_threshold2_iframe = (unsigned int)(-50 * pow(0.34, bps_ratio));
1928 cmd->dw23.deviation_threshold3_iframe = (unsigned int)(-50 * pow(0.2, bps_ratio));
1929
1930 cmd->dw24.deviation_threshold4_iframe = (unsigned int)(50 * pow(0.2, bps_ratio));
1931 cmd->dw24.deviation_threshold5_iframe = (unsigned int)(50 * pow(0.4, bps_ratio));
1932 cmd->dw24.deviation_threshold6_iframe = (unsigned int)(50 * pow(0.66, bps_ratio));
1933 cmd->dw24.deviation_threshold7_iframe = (unsigned int)(50 * pow(0.9, bps_ratio));
1934
1935 if (!reset)
1936 priv_state->brc_init_current_target_buf_full_in_bits = cmd->dw1.init_buf_full;
1937
1938 priv_state->brc_init_reset_buf_size_in_bits = (double)cmd->dw2.buf_size;
1939 priv_state->brc_init_reset_input_bits_per_frame = input_bits_per_frame;
1940
1941 i965_gpe_context_unmap_curbe(gpe_context);
1942 }
1943
1944 static void
gen9_hevc_brc_init_rest_set_surfaces(VADriverContextP ctx,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)1945 gen9_hevc_brc_init_rest_set_surfaces(VADriverContextP ctx,
1946 struct intel_encoder_context *encoder_context,
1947 struct i965_gpe_context *gpe_context)
1948 {
1949 struct encoder_vme_mfc_context *vme_context = NULL;
1950 struct gen9_hevc_encoder_context *priv_ctx = NULL;
1951 int bti_idx = 0;
1952
1953 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
1954 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
1955
1956 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
1957 HEVC_ENC_SURFACE_BRC_HISTORY, bti_idx++,
1958 0, 0, 0, NULL, NULL);
1959
1960 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
1961 HEVC_ENC_SURFACE_BRC_ME_DIST, bti_idx++,
1962 0, 1, I965_SURFACEFORMAT_R8_UNORM,
1963 &priv_ctx->res_brc_me_dist_buffer, NULL);
1964 }
1965
1966 static void
gen9_hevc_brc_init_reset(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,int reset)1967 gen9_hevc_brc_init_reset(VADriverContextP ctx,
1968 struct encode_state *encode_state,
1969 struct intel_encoder_context *encoder_context,
1970 int reset)
1971 {
1972 struct encoder_vme_mfc_context *vme_context = NULL;
1973 struct gen9_hevc_encoder_context *priv_ctx = NULL;
1974
1975 struct i965_gpe_context *gpe_context = NULL;
1976 struct gpe_media_object_parameter param;
1977 int media_state = HEVC_ENC_MEDIA_STATE_BRC_INIT_RESET;
1978 int gpe_idx = reset ? HEVC_BRC_RESET_IDX : HEVC_BRC_INIT_IDX;
1979
1980 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
1981 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
1982 gpe_context = &priv_ctx->brc_context.gpe_contexts[gpe_idx];
1983
1984 gen8_gpe_context_init(ctx, gpe_context);
1985 gen9_gpe_reset_binding_table(ctx, gpe_context);
1986 gen9_hevc_brc_init_rest_set_curbe(ctx, encode_state, encoder_context, gpe_context,
1987 reset);
1988 gen9_hevc_brc_init_rest_set_surfaces(ctx, encoder_context, gpe_context);
1989 gen8_gpe_setup_interface_data(ctx, gpe_context);
1990
1991 memset(¶m, 0, sizeof(param));
1992 gen9_hevc_run_object(ctx, encoder_context, gpe_context, ¶m,
1993 media_state);
1994 }
1995
1996 static void
gen9_hevc_brc_intra_dist_set_curbe(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)1997 gen9_hevc_brc_intra_dist_set_curbe(VADriverContextP ctx,
1998 struct encode_state *encode_state,
1999 struct intel_encoder_context *encoder_context,
2000 struct i965_gpe_context *gpe_context)
2001 {
2002 struct encoder_vme_mfc_context *vme_context = NULL;
2003 struct gen9_hevc_encoder_state *priv_state = NULL;
2004 gen9_hevc_brc_coarse_intra_curbe_data *cmd = NULL;
2005 int bti_idx = 0;
2006
2007 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
2008 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
2009
2010 cmd = i965_gpe_context_map_curbe(gpe_context);
2011 if (!cmd)
2012 return;
2013
2014 memset((void *)cmd, 0, sizeof(*cmd));
2015
2016 cmd->dw0.picture_width_in_luma_samples = priv_state->frame_width_4x;
2017 cmd->dw0.picture_height_in_luma_samples = priv_state->frame_height_4x;
2018
2019 cmd->dw1.inter_sad = 2;
2020 cmd->dw1.intra_sad = 2;
2021
2022 cmd->dw8.bti_src_y4 = bti_idx++;
2023 cmd->dw9.bti_intra_dist = bti_idx++;
2024 cmd->dw10.bti_vme_intra = bti_idx++;
2025
2026 i965_gpe_context_unmap_curbe(gpe_context);
2027 }
2028
2029 static void
gen9_hevc_brc_intra_dist_set_surfaces(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)2030 gen9_hevc_brc_intra_dist_set_surfaces(VADriverContextP ctx,
2031 struct encode_state *encode_state,
2032 struct intel_encoder_context *encoder_context,
2033 struct i965_gpe_context *gpe_context)
2034 {
2035 struct encoder_vme_mfc_context *vme_context = NULL;
2036 struct gen9_hevc_encoder_context *priv_ctx = NULL;
2037 struct object_surface *obj_surface;
2038 struct gen9_hevc_surface_priv *surface_priv;
2039 int bti_idx = 0;
2040
2041 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
2042 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
2043
2044 obj_surface = encode_state->reconstructed_object;
2045 surface_priv = (struct gen9_hevc_surface_priv *)(obj_surface->private_data);
2046 obj_surface = surface_priv->scaled_surface_obj[HEVC_SCALED_SURF_4X_ID];
2047
2048 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
2049 HEVC_ENC_SURFACE_Y_4X, bti_idx++,
2050 0, 1, I965_SURFACEFORMAT_R8_UNORM,
2051 NULL, obj_surface);
2052
2053 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
2054 HEVC_ENC_SURFACE_BRC_ME_DIST, bti_idx++,
2055 0, 1, I965_SURFACEFORMAT_R8_UNORM,
2056 &priv_ctx->res_brc_intra_dist_buffer, NULL);
2057
2058 gen9_hevc_set_gpe_adv_surface(ctx, priv_ctx, gpe_context,
2059 HEVC_ENC_SURFACE_Y_4X_VME, bti_idx++,
2060 obj_surface);
2061 }
2062
2063 static void
gen9_hevc_brc_intra_dist(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)2064 gen9_hevc_brc_intra_dist(VADriverContextP ctx,
2065 struct encode_state *encode_state,
2066 struct intel_encoder_context *encoder_context)
2067 {
2068 struct encoder_vme_mfc_context *vme_context = NULL;
2069 struct gen9_hevc_encoder_context *priv_ctx = NULL;
2070 struct gen9_hevc_encoder_state *priv_state = NULL;
2071 struct i965_gpe_context *gpe_context = NULL;
2072 struct gpe_media_object_walker_parameter param;
2073 struct hevc_enc_kernel_walker_parameter hevc_walker_param;
2074 int media_state = HEVC_ENC_MEDIA_STATE_ENC_I_FRAME_DIST;
2075 int gpe_idx = HEVC_BRC_COARSE_INTRA_IDX;
2076
2077 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
2078 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
2079 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
2080 gpe_context = &priv_ctx->brc_context.gpe_contexts[gpe_idx];
2081
2082 gen8_gpe_context_init(ctx, gpe_context);
2083 gen9_gpe_reset_binding_table(ctx, gpe_context);
2084 gen9_hevc_brc_intra_dist_set_curbe(ctx, encode_state, encoder_context, gpe_context);
2085 gen9_hevc_brc_intra_dist_set_surfaces(ctx, encode_state, encoder_context, gpe_context);
2086 gen8_gpe_setup_interface_data(ctx, gpe_context);
2087
2088 memset((void *)&hevc_walker_param, 0, sizeof(hevc_walker_param));
2089 hevc_walker_param.resolution_x = priv_state->downscaled_width_4x_in_mb;
2090 hevc_walker_param.resolution_y = priv_state->downscaled_height_4x_in_mb;
2091 hevc_walker_param.no_dependency = 1;
2092 gen9_hevc_init_object_walker(&hevc_walker_param, ¶m);
2093 gen9_hevc_run_object_walker(ctx, encoder_context, gpe_context, ¶m,
2094 media_state);
2095 }
2096
gen9_hevc_get_brc_frame_type(unsigned int pic_type,int low_delay)2097 static GEN9_HEVC_BRC_UPDATE_FRAME_TYPE gen9_hevc_get_brc_frame_type(unsigned int pic_type,
2098 int low_delay)
2099 {
2100 if (pic_type == HEVC_SLICE_I)
2101 return HEVC_BRC_FTYPE_I;
2102 else if (pic_type == HEVC_SLICE_P)
2103 return HEVC_BRC_FTYPE_P_OR_LB;
2104 else
2105 return low_delay ? HEVC_BRC_FTYPE_P_OR_LB : HEVC_BRC_FTYPE_B;
2106 }
2107
2108 static void
gen9_hevc_brc_update_set_roi_curbe(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,gen9_hevc_brc_udpate_curbe_data * cmd)2109 gen9_hevc_brc_update_set_roi_curbe(VADriverContextP ctx,
2110 struct encode_state *encode_state,
2111 struct intel_encoder_context *encoder_context,
2112 gen9_hevc_brc_udpate_curbe_data *cmd)
2113 {
2114 struct encoder_vme_mfc_context *vme_context = NULL;
2115 struct generic_enc_codec_state *generic_state = NULL;
2116 struct gen9_hevc_encoder_state *priv_state = NULL;
2117 struct intel_roi *roi_par = NULL;
2118 unsigned int roi_size = 0, roi_ratio = 0;
2119 int i = 0;
2120
2121 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
2122 generic_state = (struct generic_enc_codec_state *)vme_context->generic_enc_state;
2123 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
2124
2125 cmd->dw6.cqp_value = 0;
2126 cmd->dw6.roi_flag = 1 | (generic_state->brc_enabled << 1) |
2127 (priv_state->video_surveillance_flag << 2);
2128
2129 for (i = 0; i < priv_state->num_roi; i++) {
2130 roi_par = &priv_state->roi[i];
2131 roi_size += abs(roi_par->right - roi_par->left) *
2132 abs(roi_par->bottom - roi_par->top) * 256;
2133 }
2134
2135 if (roi_size)
2136 roi_ratio = MIN(2 * (priv_state->width_in_mb * priv_state->height_in_mb * 256 / roi_size - 1),
2137 51);
2138
2139 cmd->dw6.roi_ratio = roi_ratio;
2140 cmd->dw7.frame_width_in_lcu = priv_state->frame_width_in_max_lcu;
2141
2142 if (!generic_state->brc_enabled) {
2143 VAEncPictureParameterBufferHEVC *pic_param = NULL;
2144 VAEncSliceParameterBufferHEVC *slice_param = NULL;
2145
2146 pic_param = (VAEncPictureParameterBufferHEVC *)encode_state->pic_param_ext->buffer;
2147 slice_param = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
2148
2149 cmd->dw1.frame_number = priv_state->frame_number;
2150 cmd->dw6.cqp_value = pic_param->pic_init_qp + slice_param->slice_qp_delta;
2151 cmd->dw5.curr_frame_type = gen9_hevc_get_brc_frame_type(priv_state->picture_coding_type,
2152 priv_state->low_delay);
2153 }
2154 }
2155
2156 static void
gen9_hevc_brc_update_lcu_based_set_roi_parameters(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)2157 gen9_hevc_brc_update_lcu_based_set_roi_parameters(VADriverContextP ctx,
2158 struct encode_state *encode_state,
2159 struct intel_encoder_context *encoder_context,
2160 struct i965_gpe_context *gpe_context)
2161 {
2162 struct encoder_vme_mfc_context *vme_context = NULL;
2163 struct gen9_hevc_encoder_context *priv_ctx = NULL;
2164 struct generic_enc_codec_state *generic_state = NULL;
2165 struct gen9_hevc_encoder_state *priv_state = NULL;
2166 struct intel_roi *roi_par = NULL;
2167 unsigned int width_in_mb_aligned = 0;
2168 unsigned int roi_level, qp_delta;
2169 unsigned int mb_num = 0;
2170 unsigned int *pdata = NULL;
2171 unsigned int out_data = 0;
2172 int i = 0;
2173
2174 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
2175 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
2176 generic_state = (struct generic_enc_codec_state *)vme_context->generic_enc_state;
2177 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
2178
2179 width_in_mb_aligned = ALIGN(priv_state->width_in_mb * 4, 64);
2180 mb_num = priv_state->width_in_mb * priv_state->height_in_mb;
2181
2182 pdata = i965_map_gpe_resource(&priv_ctx->res_roi_buffer);
2183 if (!pdata)
2184 return;
2185
2186 for (i = 0 ; i < mb_num; i++) {
2187 int cur_mb_y = i / priv_state->width_in_mb;
2188 int cur_mb_x = i - cur_mb_y * priv_state->width_in_mb;
2189 int roi_idx = 0;
2190
2191 out_data = 0;
2192
2193 for (roi_idx = (priv_state->num_roi - 1); roi_idx >= 0; roi_idx--) {
2194 roi_par = &priv_state->roi[roi_idx];
2195
2196 roi_level = qp_delta = 0;
2197 if (generic_state->brc_enabled && !priv_state->roi_value_is_qp_delta)
2198 roi_level = roi_par->value * 5;
2199 else
2200 qp_delta = roi_par->value;
2201
2202 if (roi_level == 0 && qp_delta == 0)
2203 continue;
2204
2205 if ((cur_mb_x >= roi_par->left) &&
2206 (cur_mb_x < roi_par->right) &&
2207 (cur_mb_y >= roi_par->top) &&
2208 (cur_mb_y < roi_par->bottom))
2209 out_data = 15 | (((roi_level) & 0xFF) << 8) | ((qp_delta & 0xFF) << 16);
2210 else if ((cur_mb_x >= roi_par->left - 1) &&
2211 (cur_mb_x < roi_par->right + 1) &&
2212 (cur_mb_y >= roi_par->top - 1) &&
2213 (cur_mb_y < roi_par->bottom + 1))
2214 out_data = 14 | (((roi_level) & 0xFF) << 8) | ((qp_delta & 0xFF) << 16);
2215 else if ((cur_mb_x >= roi_par->left - 2) &&
2216 (cur_mb_x < roi_par->right + 2) &&
2217 (cur_mb_y >= roi_par->top - 2) &&
2218 (cur_mb_y < roi_par->bottom + 2))
2219 out_data = 13 | (((roi_level) & 0xFF) << 8) | ((qp_delta & 0xFF) << 16);
2220 else if ((cur_mb_x >= roi_par->left - 3) &&
2221 (cur_mb_x < roi_par->right + 3) &&
2222 (cur_mb_y >= roi_par->top - 3) &&
2223 (cur_mb_y < roi_par->bottom + 3)) {
2224 out_data = 12 | (((roi_level) & 0xFF) << 8) | ((qp_delta & 0xFF) << 16);
2225 }
2226 }
2227
2228 pdata[(cur_mb_y * (width_in_mb_aligned >> 2)) + cur_mb_x] = out_data;
2229 }
2230
2231 i965_unmap_gpe_resource(&priv_ctx->res_roi_buffer);
2232 }
2233
2234 static void
gen9_hevc_brc_update_lcu_based_set_curbe(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)2235 gen9_hevc_brc_update_lcu_based_set_curbe(VADriverContextP ctx,
2236 struct encode_state *encode_state,
2237 struct intel_encoder_context *encoder_context,
2238 struct i965_gpe_context *gpe_context)
2239 {
2240 struct encoder_vme_mfc_context *vme_context = NULL;
2241 struct gen9_hevc_encoder_context *priv_ctx = NULL;
2242 struct generic_enc_codec_state *generic_state = NULL;
2243 struct gen9_hevc_encoder_state *priv_state = NULL;
2244 gen9_hevc_brc_udpate_curbe_data *cmd = NULL, *frame_cmd = NULL;
2245
2246 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
2247 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
2248 generic_state = (struct generic_enc_codec_state *)vme_context->generic_enc_state;
2249 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
2250
2251 cmd = i965_gpe_context_map_curbe(gpe_context);
2252 if (!cmd)
2253 return;
2254
2255 if (generic_state->brc_enabled) {
2256 frame_cmd = i965_gpe_context_map_curbe(&priv_ctx->brc_context.gpe_contexts[HEVC_BRC_FRAME_UPDATE_IDX]);
2257
2258 if (!frame_cmd)
2259 return;
2260
2261 memcpy((void *)cmd, (void *)frame_cmd, sizeof(*cmd));
2262
2263 i965_gpe_context_unmap_curbe(&priv_ctx->brc_context.gpe_contexts[HEVC_BRC_FRAME_UPDATE_IDX]);
2264 } else {
2265 memcpy((void *)cmd, GEN9_HEVC_BRCUPDATE_CURBE_DATA,
2266 sizeof(GEN9_HEVC_BRCUPDATE_CURBE_DATA));
2267 }
2268
2269 if (priv_state->num_roi)
2270 gen9_hevc_brc_update_set_roi_curbe(ctx, encode_state, encoder_context, cmd);
2271
2272 i965_gpe_context_unmap_curbe(gpe_context);
2273 }
2274
2275 static void
gen9_hevc_brc_update_lcu_based_set_surfaces(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)2276 gen9_hevc_brc_update_lcu_based_set_surfaces(VADriverContextP ctx,
2277 struct encode_state *encode_state,
2278 struct intel_encoder_context *encoder_context,
2279 struct i965_gpe_context *gpe_context)
2280 {
2281 struct encoder_vme_mfc_context *vme_context = NULL;
2282 struct gen9_hevc_encoder_context *priv_ctx = NULL;
2283 struct gen9_hevc_encoder_state *priv_state = NULL;
2284 int bti_idx = 0;
2285
2286 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
2287 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
2288 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
2289
2290 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
2291 HEVC_ENC_SURFACE_BRC_HISTORY, bti_idx++,
2292 0, 0, 0, NULL, NULL);
2293
2294 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
2295 HEVC_ENC_SURFACE_BRC_ME_DIST, bti_idx++,
2296 0, 1, I965_SURFACEFORMAT_R8_UNORM,
2297 priv_state->picture_coding_type == HEVC_SLICE_I ?
2298 &priv_ctx->res_brc_intra_dist_buffer :
2299 &priv_ctx->res_brc_me_dist_buffer,
2300 NULL);
2301
2302 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
2303 HEVC_ENC_SURFACE_BRC_ME_DIST, bti_idx++,
2304 0, 1, I965_SURFACEFORMAT_R8_UNORM,
2305 &priv_ctx->res_brc_intra_dist_buffer, NULL);
2306
2307 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
2308 HEVC_ENC_SURFACE_HME_MVP, bti_idx++,
2309 0, 1, I965_SURFACEFORMAT_R8_UNORM,
2310 NULL, NULL);
2311
2312 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
2313 HEVC_ENC_SURFACE_LCU_QP, bti_idx++,
2314 0, 1, I965_SURFACEFORMAT_R8_UNORM,
2315 NULL, NULL);
2316
2317 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
2318 HEVC_ENC_SURFACE_ROI, bti_idx++,
2319 0, 1, I965_SURFACEFORMAT_R8_UNORM,
2320 NULL, NULL);
2321 }
2322
2323 static void
gen9_hevc_brc_update_lcu_based(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)2324 gen9_hevc_brc_update_lcu_based(VADriverContextP ctx,
2325 struct encode_state *encode_state,
2326 struct intel_encoder_context *encoder_context)
2327 {
2328 struct encoder_vme_mfc_context *vme_context = NULL;
2329 struct gen9_hevc_encoder_context *priv_ctx = NULL;
2330 struct gen9_hevc_encoder_state *priv_state = NULL;
2331 struct i965_gpe_context *gpe_context = NULL;
2332 struct gpe_media_object_walker_parameter param;
2333 struct hevc_enc_kernel_walker_parameter hevc_walker_param;
2334 int media_state = HEVC_ENC_MEDIA_STATE_HEVC_BRC_LCU_UPDATE;
2335 int gpe_idx = HEVC_BRC_LCU_UPDATE_IDX;
2336
2337 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
2338 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
2339 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
2340 gpe_context = &priv_ctx->brc_context.gpe_contexts[gpe_idx];
2341
2342 gen8_gpe_context_init(ctx, gpe_context);
2343 gen9_gpe_reset_binding_table(ctx, gpe_context);
2344
2345 if (priv_state->num_roi)
2346 gen9_hevc_brc_update_lcu_based_set_roi_parameters(ctx, encode_state, encoder_context,
2347 gpe_context);
2348
2349 gen9_hevc_brc_update_lcu_based_set_curbe(ctx, encode_state, encoder_context, gpe_context);
2350 gen9_hevc_brc_update_lcu_based_set_surfaces(ctx, encode_state, encoder_context, gpe_context);
2351 gen8_gpe_setup_interface_data(ctx, gpe_context);
2352
2353 memset((void *)&hevc_walker_param, 0, sizeof(hevc_walker_param));
2354 hevc_walker_param.resolution_x = ALIGN(priv_state->picture_width, 128) >> 7;
2355 hevc_walker_param.resolution_y = ALIGN(priv_state->picture_height, 128) >> 7;
2356 hevc_walker_param.no_dependency = 1;
2357 gen9_hevc_init_object_walker(&hevc_walker_param, ¶m);
2358 gen9_hevc_run_object_walker(ctx, encoder_context, gpe_context, ¶m,
2359 media_state);
2360 }
2361
2362 static void
gen9_hevc_add_pic_state(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_resource * pic_state_ptr,int pic_state_offset,int brc_update)2363 gen9_hevc_add_pic_state(VADriverContextP ctx,
2364 struct encode_state *encode_state,
2365 struct intel_encoder_context *encoder_context,
2366 struct i965_gpe_resource *pic_state_ptr,
2367 int pic_state_offset,
2368 int brc_update)
2369 {
2370 struct i965_driver_data *i965 = i965_driver_data(ctx);
2371 struct encoder_vme_mfc_context *pak_context = NULL;
2372 struct gen9_hevc_encoder_state *priv_state = NULL;
2373 VAEncPictureParameterBufferHEVC *pic_param = NULL;
2374 VAEncSequenceParameterBufferHEVC *seq_param = NULL;
2375 unsigned int tmp_data[31], *cmd_ptr = NULL;
2376 int cmd_size = 0;
2377
2378 pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
2379 priv_state = (struct gen9_hevc_encoder_state *)pak_context->private_enc_state;
2380
2381 pic_param = (VAEncPictureParameterBufferHEVC *)encode_state->pic_param_ext->buffer;
2382 seq_param = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
2383
2384 cmd_ptr = tmp_data;
2385 cmd_size = (IS_KBL(i965->intel.device_info) || IS_GLK(i965->intel.device_info)) ? 31 : 19;
2386 memset((void *)tmp_data, 0, 4 * cmd_size);
2387
2388 if (IS_KBL(i965->intel.device_info) || IS_GLK(i965->intel.device_info))
2389 *cmd_ptr++ = HCP_PIC_STATE | (31 - 2);
2390 else
2391 *cmd_ptr++ = HCP_PIC_STATE | (19 - 2);
2392
2393 *cmd_ptr++ = (priv_state->height_in_cu - 1) << 16 |
2394 0 << 14 |
2395 (priv_state->width_in_cu - 1);
2396 *cmd_ptr++ = (seq_param->log2_min_transform_block_size_minus2 +
2397 seq_param->log2_diff_max_min_transform_block_size) << 6 |
2398 seq_param->log2_min_transform_block_size_minus2 << 4 |
2399 (seq_param->log2_min_luma_coding_block_size_minus3 +
2400 seq_param->log2_diff_max_min_luma_coding_block_size) << 2 |
2401 seq_param->log2_min_luma_coding_block_size_minus3;
2402 *cmd_ptr++ = 0;
2403 *cmd_ptr++ = ((IS_KBL(i965->intel.device_info) || IS_GLK(i965->intel.device_info)) ? 1 : 0) << 27 |
2404 seq_param->seq_fields.bits.strong_intra_smoothing_enabled_flag << 26 |
2405 pic_param->pic_fields.bits.transquant_bypass_enabled_flag << 25 |
2406 ((IS_KBL(i965->intel.device_info) || IS_GLK(i965->intel.device_info)) ? 0 : priv_state->ctu_max_bitsize_allowed > 0) << 24 |
2407 seq_param->seq_fields.bits.amp_enabled_flag << 23 |
2408 pic_param->pic_fields.bits.transform_skip_enabled_flag << 22 |
2409 0 << 21 |
2410 0 << 20 |
2411 pic_param->pic_fields.bits.weighted_pred_flag << 19 |
2412 pic_param->pic_fields.bits.weighted_bipred_flag << 18 |
2413 0 << 17 |
2414 pic_param->pic_fields.bits.entropy_coding_sync_enabled_flag << 16 |
2415 0 << 15 |
2416 pic_param->pic_fields.bits.sign_data_hiding_enabled_flag << 13 |
2417 pic_param->log2_parallel_merge_level_minus2 << 10 |
2418 pic_param->pic_fields.bits.constrained_intra_pred_flag << 9 |
2419 seq_param->seq_fields.bits.pcm_loop_filter_disabled_flag << 8 |
2420 (pic_param->diff_cu_qp_delta_depth & 0x03) << 6 |
2421 pic_param->pic_fields.bits.cu_qp_delta_enabled_flag << 5 |
2422 0 << 4 |
2423 seq_param->seq_fields.bits.sample_adaptive_offset_enabled_flag << 3 |
2424 0;
2425 *cmd_ptr++ = seq_param->seq_fields.bits.bit_depth_luma_minus8 << 27 |
2426 seq_param->seq_fields.bits.bit_depth_chroma_minus8 << 24 |
2427 ((IS_KBL(i965->intel.device_info) || IS_GLK(i965->intel.device_info)) ? 0 : 7) << 20 |
2428 ((IS_KBL(i965->intel.device_info) || IS_GLK(i965->intel.device_info)) ? 0 : 7) << 16 |
2429 seq_param->max_transform_hierarchy_depth_inter << 13 |
2430 seq_param->max_transform_hierarchy_depth_intra << 10 |
2431 (pic_param->pps_cr_qp_offset & 0x1f) << 5 |
2432 (pic_param->pps_cb_qp_offset & 0x1f);
2433
2434 *cmd_ptr++ = 0 << 29 |
2435 priv_state->ctu_max_bitsize_allowed;
2436 if (brc_update)
2437 *(cmd_ptr - 1) |= 0 << 31 |
2438 1 << 26 |
2439 1 << 25 |
2440 0 << 24 |
2441 (pic_state_offset ? 1 : 0) << 16;
2442
2443 *cmd_ptr++ = 0 << 31 |
2444 0;
2445 *cmd_ptr++ = 0 << 31 |
2446 0;
2447 *cmd_ptr++ = 0 << 16 |
2448 0;
2449 *cmd_ptr++ = 0;
2450 *cmd_ptr++ = 0;
2451 *cmd_ptr++ = 0;
2452 *cmd_ptr++ = 0;
2453 *cmd_ptr++ = 0;
2454 *cmd_ptr++ = 0;
2455 *cmd_ptr++ = 0;
2456 *cmd_ptr++ = 0;
2457 *cmd_ptr++ = 0 << 30 |
2458 0;
2459
2460 if (IS_KBL(i965->intel.device_info) || IS_GLK(i965->intel.device_info)) {
2461 int i = 0;
2462
2463 for (i = 0; i < 12; i++)
2464 *cmd_ptr++ = 0;
2465 }
2466
2467 if (pic_state_ptr) {
2468 char *pdata = i965_map_gpe_resource(pic_state_ptr);
2469
2470 if (!pdata)
2471 return;
2472
2473 memcpy(pdata + pic_state_offset, tmp_data, cmd_size * 4);
2474
2475 pdata += pic_state_offset + cmd_size * 4;
2476
2477 *(unsigned int *)pdata++ = MI_BATCH_BUFFER_END;
2478
2479 i965_unmap_gpe_resource(pic_state_ptr);
2480 } else {
2481 struct intel_batchbuffer *batch = encoder_context->base.batch;
2482
2483 BEGIN_BCS_BATCH(batch, cmd_size);
2484
2485 intel_batchbuffer_data(batch, tmp_data, cmd_size * 4);
2486
2487 ADVANCE_BCS_BATCH(batch);
2488 }
2489 }
2490
2491 static void
gen9_hevc_brc_update_set_pic_states(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)2492 gen9_hevc_brc_update_set_pic_states(VADriverContextP ctx,
2493 struct encode_state *encode_state,
2494 struct intel_encoder_context *encoder_context)
2495 {
2496 struct encoder_vme_mfc_context *vme_context = NULL;
2497 struct gen9_hevc_encoder_context *priv_ctx = NULL;
2498 struct generic_enc_codec_state *generic_state = NULL;
2499 struct gen9_hevc_encoder_state *priv_state = NULL;
2500 int i = 0, offset = 0;
2501
2502 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
2503 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
2504 generic_state = (struct generic_enc_codec_state *)vme_context->generic_enc_state;
2505 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
2506
2507 for (i = 0; i < generic_state->num_pak_passes; i++) {
2508 gen9_hevc_add_pic_state(ctx, encode_state, encoder_context,
2509 &priv_ctx->res_brc_pic_states_read_buffer,
2510 offset, 1);
2511
2512 offset += priv_state->pic_state_size;
2513 }
2514 }
2515
2516 static void
gen9_hevc_brc_update_set_constant(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)2517 gen9_hevc_brc_update_set_constant(VADriverContextP ctx,
2518 struct encode_state *encode_state,
2519 struct intel_encoder_context *encoder_context)
2520 {
2521 struct encoder_vme_mfc_context *vme_context = NULL;
2522 struct gen9_hevc_encoder_context *priv_ctx = NULL;
2523 struct gen9_hevc_encoder_state *priv_state = NULL;
2524 unsigned int width, height, size;
2525 unsigned char *pdata = NULL;
2526 int idx = 0;
2527
2528 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
2529 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
2530 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
2531
2532 pdata = i965_map_gpe_resource(&priv_ctx->res_brc_constant_data_buffer);
2533 if (!pdata)
2534 return;
2535
2536 width = ALIGN(GEN9_HEVC_ENC_BRC_CONSTANT_SURFACE_WIDTH, 64);
2537 height = GEN9_HEVC_ENC_BRC_CONSTANT_SURFACE_HEIGHT;
2538 size = width * height;
2539 memset((void *)pdata, 0, size);
2540
2541 memcpy((void *)pdata, GEN9_HEVC_BRCUPDATE_QP_ADJUST, GEN9_HEVC_BRCUPDATE_QP_ADJUST_SIZE);
2542 pdata += GEN9_HEVC_BRCUPDATE_QP_ADJUST_SIZE;
2543
2544 if (priv_state->picture_coding_type == HEVC_SLICE_I)
2545 memset((void *)pdata, 0, GEN9_HEVC_ENC_SKIP_VAL_SIZE);
2546 else {
2547 gen9_hevc_mbenc_b_mb_enc_curbe_data *curbe_cmd = NULL;
2548 int curbe_size = 0;
2549
2550 gen9_hevc_get_b_mbenc_default_curbe(priv_state->tu_mode,
2551 priv_state->picture_coding_type,
2552 (void **)&curbe_cmd,
2553 &curbe_size);
2554
2555 idx = curbe_cmd->dw3.block_based_skip_enable ? 1 : 0;
2556 memcpy((void *)pdata, GEN9_HEVC_ENC_SKIP_THREAD[idx], sizeof(GEN9_HEVC_ENC_SKIP_THREAD[idx]));
2557 }
2558 pdata += GEN9_HEVC_ENC_SKIP_VAL_SIZE;
2559
2560 memcpy((void *)pdata, GEN9_HEVC_ENC_BRC_LAMBDA_HAAR, sizeof(GEN9_HEVC_ENC_BRC_LAMBDA_HAAR));
2561 pdata += GEN9_HEVC_ENC_BRC_LAMBDA_TABLE_SIZE;
2562
2563 idx = (priv_state->picture_coding_type == HEVC_SLICE_I) ? 0 :
2564 (priv_state->picture_coding_type == HEVC_SLICE_P) ? 1 : 2;
2565 memcpy((void *)pdata, GEN9_HEVC_ENC_BRC_MVCOST_HAAR[idx], sizeof(GEN9_HEVC_ENC_BRC_MVCOST_HAAR[idx]));
2566
2567 i965_unmap_gpe_resource(&priv_ctx->res_brc_constant_data_buffer);
2568 }
2569
2570 static
gen9_hevc_get_start_code_offset(unsigned char * ptr,unsigned int size)2571 unsigned int gen9_hevc_get_start_code_offset(unsigned char *ptr,
2572 unsigned int size)
2573 {
2574 unsigned int count = 0;
2575
2576 while (count < size && *ptr != 0x01) {
2577 if (*ptr != 0)
2578 break;
2579
2580 count++;
2581 ptr++;
2582 }
2583
2584 return count + 1;
2585 }
2586
2587 static
gen9_hevc_get_emulation_num(unsigned char * ptr,unsigned int size)2588 unsigned int gen9_hevc_get_emulation_num(unsigned char *ptr,
2589 unsigned int size)
2590 {
2591 unsigned int emulation_num = 0;
2592 unsigned int header_offset = 0;
2593 unsigned int zero_count = 0;
2594 int i = 0;
2595
2596 header_offset = gen9_hevc_get_start_code_offset(ptr, size);
2597 ptr += header_offset;
2598
2599 for (i = 0 ; i < (size - header_offset); i++, ptr++) {
2600 if (zero_count == 2 && !(*ptr & 0xFC)) {
2601 zero_count = 0;
2602 emulation_num++;
2603 }
2604
2605 if (*ptr == 0x00)
2606 zero_count++;
2607 else
2608 zero_count = 0;
2609 }
2610
2611 return emulation_num;
2612 }
2613
2614 #define HEVC_ENC_START_CODE_NAL_OFFSET (2)
2615
2616 static unsigned int
gen9_hevc_get_pic_header_size(struct encode_state * encode_state)2617 gen9_hevc_get_pic_header_size(struct encode_state *encode_state)
2618 {
2619 VAEncPackedHeaderParameterBuffer *param = NULL;
2620 unsigned int header_begin = 0;
2621 unsigned int accum_size = 0;
2622 unsigned char *header_data = NULL;
2623 unsigned int length_in_bytes = 0;
2624 int packed_type = 0;
2625 int idx = 0, count = 0, idx_offset = 0;
2626 int i = 0, slice_idx = 0, start_index = 0;
2627
2628 for (i = 0; i < 4; i++) {
2629 idx_offset = 0;
2630 switch (i) {
2631 case 0:
2632 packed_type = VAEncPackedHeaderHEVC_VPS;
2633 break;
2634 case 1:
2635 packed_type = VAEncPackedHeaderHEVC_VPS;
2636 idx_offset = 1;
2637 break;
2638 case 2:
2639 packed_type = VAEncPackedHeaderHEVC_PPS;
2640 break;
2641 case 3:
2642 packed_type = VAEncPackedHeaderHEVC_SEI;
2643 break;
2644 default:
2645 break;
2646 }
2647
2648 idx = va_enc_packed_type_to_idx(packed_type) + idx_offset;
2649 if (encode_state->packed_header_data[idx]) {
2650 param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer;
2651 header_data = (unsigned char *)encode_state->packed_header_data[idx]->buffer;
2652 length_in_bytes = (param->bit_length + 7) / 8;
2653
2654 header_begin = gen9_hevc_get_start_code_offset(header_data, length_in_bytes) +
2655 HEVC_ENC_START_CODE_NAL_OFFSET;
2656
2657 accum_size += length_in_bytes;
2658 if (!param->has_emulation_bytes)
2659 accum_size += gen9_hevc_get_emulation_num(header_data,
2660 length_in_bytes);
2661 }
2662 }
2663
2664 for (slice_idx = 0; slice_idx < encode_state->num_slice_params_ext; slice_idx++) {
2665 count = encode_state->slice_rawdata_count[slice_idx];
2666 start_index = encode_state->slice_rawdata_index[slice_idx] &
2667 SLICE_PACKED_DATA_INDEX_MASK;
2668
2669 for (i = 0; i < count; i++) {
2670 param = (VAEncPackedHeaderParameterBuffer *)
2671 (encode_state->packed_header_params_ext[start_index + i]->buffer);
2672
2673 if (param->type == VAEncPackedHeaderSlice)
2674 continue;
2675
2676 header_data = (unsigned char *)encode_state->packed_header_data[start_index]->buffer;
2677 length_in_bytes = (param->bit_length + 7) / 8;
2678
2679 accum_size += length_in_bytes;
2680 if (!param->has_emulation_bytes)
2681 accum_size += gen9_hevc_get_emulation_num(header_data,
2682 length_in_bytes);
2683 }
2684 }
2685
2686 header_begin = MIN(header_begin, accum_size);
2687
2688 return ((accum_size - header_begin) * 8);
2689 }
2690
2691 static void
gen9_hevc_brc_update_set_curbe(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)2692 gen9_hevc_brc_update_set_curbe(VADriverContextP ctx,
2693 struct encode_state *encode_state,
2694 struct intel_encoder_context *encoder_context,
2695 struct i965_gpe_context *gpe_context)
2696 {
2697 struct encoder_vme_mfc_context *vme_context = NULL;
2698 struct generic_enc_codec_state *generic_state = NULL;
2699 struct gen9_hevc_encoder_state *priv_state = NULL;
2700 gen9_hevc_brc_udpate_curbe_data *cmd = NULL;
2701
2702 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
2703 generic_state = (struct generic_enc_codec_state *)vme_context->generic_enc_state;
2704 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
2705
2706 cmd = i965_gpe_context_map_curbe(gpe_context);
2707 if (!cmd)
2708 return;
2709
2710 memcpy((void *)cmd, GEN9_HEVC_BRCUPDATE_CURBE_DATA,
2711 sizeof(GEN9_HEVC_BRCUPDATE_CURBE_DATA));
2712
2713 cmd->dw5.target_size_flag = 0;
2714 if (priv_state->brc_init_current_target_buf_full_in_bits >
2715 (double)priv_state->brc_init_reset_buf_size_in_bits) {
2716 priv_state->brc_init_current_target_buf_full_in_bits -=
2717 (double)priv_state->brc_init_reset_buf_size_in_bits;
2718 cmd->dw5.target_size_flag = 1;
2719 }
2720
2721 if (priv_state->num_skip_frames) {
2722 cmd->dw6.num_skipped_frames = priv_state->num_skip_frames;
2723 cmd->dw15.size_of_skipped_frames = priv_state->size_skip_frames;
2724
2725 priv_state->brc_init_current_target_buf_full_in_bits +=
2726 priv_state->brc_init_reset_input_bits_per_frame * priv_state->num_skip_frames;
2727 }
2728
2729 cmd->dw0.target_size = (unsigned int)priv_state->brc_init_current_target_buf_full_in_bits;
2730 cmd->dw1.frame_number = priv_state->frame_number;
2731 cmd->dw2.picture_header_size = gen9_hevc_get_pic_header_size(encode_state);
2732
2733 cmd->dw5.brc_flag = 0;
2734 cmd->dw5.curr_frame_type = gen9_hevc_get_brc_frame_type(priv_state->picture_coding_type,
2735 priv_state->low_delay);
2736
2737 cmd->dw5.max_num_paks = generic_state->num_pak_passes;
2738 cmd->dw14.parallel_mode = priv_state->parallel_brc;
2739
2740 priv_state->brc_init_current_target_buf_full_in_bits +=
2741 priv_state->brc_init_reset_input_bits_per_frame;
2742
2743 if (priv_state->brc_method == HEVC_BRC_AVBR) {
2744 cmd->dw3.start_gadj_frame0 = (unsigned int)((10 * GEN9_HEVC_AVBR_CONVERGENCE) / (double)150);
2745 cmd->dw3.start_gadj_frame1 = (unsigned int)((50 * GEN9_HEVC_AVBR_CONVERGENCE) / (double)150);
2746 cmd->dw4.start_gadj_frame2 = (unsigned int)((100 * GEN9_HEVC_AVBR_CONVERGENCE) / (double)150);
2747 cmd->dw4.start_gadj_frame3 = (unsigned int)((150 * GEN9_HEVC_AVBR_CONVERGENCE) / (double)150);
2748 cmd->dw11.g_rate_ratio_threshold0 = (unsigned int)((100 - (GEN9_HEVC_AVBR_ACCURACY / (double)30) * (100 - 40)));
2749 cmd->dw11.g_rate_ratio_threshold1 = (unsigned int)((100 - (GEN9_HEVC_AVBR_ACCURACY / (double)30) * (100 - 75)));
2750 cmd->dw12.g_rate_ratio_threshold2 = (unsigned int)((100 - (GEN9_HEVC_AVBR_ACCURACY / (double)30) * (100 - 97)));
2751 cmd->dw12.g_rate_ratio_threshold3 = (unsigned int)((100 + (GEN9_HEVC_AVBR_ACCURACY / (double)30) * (103 - 100)));
2752 cmd->dw12.g_rate_ratio_threshold4 = (unsigned int)((100 + (GEN9_HEVC_AVBR_ACCURACY / (double)30) * (125 - 100)));
2753 cmd->dw12.g_rate_ratio_threshold5 = (unsigned int)((100 + (GEN9_HEVC_AVBR_ACCURACY / (double)30) * (160 - 100)));
2754 } else {
2755 cmd->dw3.start_gadj_frame0 = 10;
2756 cmd->dw3.start_gadj_frame1 = 50;
2757 cmd->dw4.start_gadj_frame2 = 100;
2758 cmd->dw4.start_gadj_frame3 = 150;
2759 cmd->dw11.g_rate_ratio_threshold0 = 40;
2760 cmd->dw11.g_rate_ratio_threshold1 = 75;
2761 cmd->dw12.g_rate_ratio_threshold2 = 97;
2762 cmd->dw12.g_rate_ratio_threshold3 = 103;
2763 cmd->dw12.g_rate_ratio_threshold4 = 125;
2764 cmd->dw12.g_rate_ratio_threshold5 = 160;
2765 }
2766
2767 i965_gpe_context_unmap_curbe(gpe_context);
2768 }
2769
2770 static void
gen9_hevc_brc_update_set_surfaces(VADriverContextP ctx,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)2771 gen9_hevc_brc_update_set_surfaces(VADriverContextP ctx,
2772 struct intel_encoder_context *encoder_context,
2773 struct i965_gpe_context *gpe_context)
2774 {
2775 struct encoder_vme_mfc_context *vme_context = NULL;
2776 struct gen9_hevc_encoder_context *priv_ctx = NULL;
2777 struct gen9_hevc_encoder_state *priv_state = NULL;
2778 int bti_idx = 0;
2779
2780 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
2781 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
2782 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
2783
2784 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
2785 HEVC_ENC_SURFACE_BRC_HISTORY, bti_idx++,
2786 0, 0, 0, NULL, NULL);
2787
2788 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
2789 HEVC_ENC_SURFACE_BRC_PAST_PAK_INFO, bti_idx++,
2790 0, 0, 0, NULL, NULL);
2791
2792 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
2793 HEVC_ENC_SURFACE_BRC_HCP_PIC_STATE, bti_idx++,
2794 0, 0, 0, &priv_ctx->res_brc_pic_states_read_buffer,
2795 NULL);
2796
2797 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
2798 HEVC_ENC_SURFACE_BRC_HCP_PIC_STATE, bti_idx++,
2799 0, 0, 0, &priv_ctx->res_brc_pic_states_write_buffer,
2800 NULL);
2801
2802 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
2803 HEVC_ENC_SURFACE_BRC_INPUT, bti_idx++,
2804 0, 0, 0, NULL, NULL);
2805
2806 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
2807 HEVC_ENC_SURFACE_BRC_ME_DIST, bti_idx++,
2808 0, 1, I965_SURFACEFORMAT_R8_UNORM,
2809 priv_state->picture_coding_type == HEVC_SLICE_I ?
2810 &priv_ctx->res_brc_intra_dist_buffer :
2811 &priv_ctx->res_brc_me_dist_buffer,
2812 NULL);
2813
2814 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
2815 HEVC_ENC_SURFACE_BRC_DATA, bti_idx++,
2816 0, 1, I965_SURFACEFORMAT_R8_UNORM,
2817 NULL, NULL);
2818 }
2819
2820 static void
gen9_hevc_brc_update(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)2821 gen9_hevc_brc_update(VADriverContextP ctx,
2822 struct encode_state *encode_state,
2823 struct intel_encoder_context *encoder_context)
2824 {
2825 struct encoder_vme_mfc_context *vme_context = NULL;
2826 struct gen9_hevc_encoder_context *priv_ctx = NULL;
2827 struct gen9_hevc_encoder_state *priv_state = NULL;
2828 struct i965_gpe_context *gpe_context = NULL;
2829 struct gpe_media_object_parameter param;
2830 int media_state = HEVC_ENC_MEDIA_STATE_BRC_UPDATE;
2831 int gpe_idx = HEVC_BRC_FRAME_UPDATE_IDX;
2832
2833 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
2834 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
2835 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
2836 gpe_context = &priv_ctx->brc_context.gpe_contexts[gpe_idx];
2837
2838 gen8_gpe_context_init(ctx, gpe_context);
2839 gen9_gpe_reset_binding_table(ctx, gpe_context);
2840
2841 gen9_hevc_brc_update_set_pic_states(ctx, encode_state, encoder_context);
2842 gen9_hevc_brc_update_set_constant(ctx, encode_state, encoder_context);
2843 gen9_hevc_brc_update_set_curbe(ctx, encode_state, encoder_context, gpe_context);
2844 gen9_hevc_brc_update_set_surfaces(ctx, encoder_context, gpe_context);
2845
2846 gen8_gpe_setup_interface_data(ctx, gpe_context);
2847
2848 memset(¶m, 0, sizeof(param));
2849 gen9_hevc_run_object(ctx, encoder_context, gpe_context, ¶m,
2850 media_state);
2851
2852 if (priv_state->lcu_brc_enabled ||
2853 priv_state->num_roi)
2854 gen9_hevc_brc_update_lcu_based(ctx, encode_state, encoder_context);
2855 }
2856
2857 // Depth converstion for 10bits
2858
2859 static void
gen9_hevc_frame_depth_conversion_set_curbe(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context,GEN9_HEVC_DOWNSCALE_STAGE scale_stage)2860 gen9_hevc_frame_depth_conversion_set_curbe(VADriverContextP ctx,
2861 struct encode_state *encode_state,
2862 struct intel_encoder_context *encoder_context,
2863 struct i965_gpe_context *gpe_context,
2864 GEN9_HEVC_DOWNSCALE_STAGE scale_stage)
2865 {
2866 struct encoder_vme_mfc_context *vme_context = NULL;
2867 struct gen9_hevc_encoder_state *priv_state = NULL;
2868 gen95_hevc_mbenc_ds_combined_curbe_data *cmd = NULL;
2869 int bti_idx = 0;
2870
2871 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
2872 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
2873
2874 cmd = i965_gpe_context_map_curbe(gpe_context);
2875 if (!cmd)
2876 return;
2877
2878 memset((void *)cmd, 0, sizeof(*cmd));
2879
2880 cmd->dw0.pak_bitdepth_chroma = 10;
2881 cmd->dw0.pak_bitdepth_luma = 10;
2882 cmd->dw0.enc_bitdepth_chroma = 8;
2883 cmd->dw0.enc_bitdepth_luma = 8;
2884 cmd->dw0.rounding_value = 1;
2885 cmd->dw1.pic_format = 0;
2886 cmd->dw1.pic_convert_flag = 1;
2887 cmd->dw1.pic_down_scale = scale_stage;
2888 cmd->dw1.pic_mb_stat_output_cntrl = 0;
2889 cmd->dw2.orig_pic_width = priv_state->picture_width;
2890 cmd->dw2.orig_pic_height = priv_state->picture_height;
2891
2892 cmd->dw3.bti_surface_p010 = bti_idx++;
2893 bti_idx++;
2894 cmd->dw4.bti_surface_nv12 = bti_idx++;
2895 bti_idx++;
2896 cmd->dw5.bti_src_y_4xdownscaled = bti_idx++;
2897 cmd->dw6.bti_surf_mbstate = bti_idx++;
2898 cmd->dw7.bit_src_y_2xdownscaled = bti_idx++;
2899
2900 i965_gpe_context_unmap_curbe(gpe_context);
2901 }
2902
2903 static void
gen9_hevc_frame_depth_conversion_set_surfaces(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context,struct object_surface * src_surface,struct object_surface * dst_surface)2904 gen9_hevc_frame_depth_conversion_set_surfaces(VADriverContextP ctx,
2905 struct encode_state *encode_state,
2906 struct intel_encoder_context *encoder_context,
2907 struct i965_gpe_context *gpe_context,
2908 struct object_surface *src_surface,
2909 struct object_surface *dst_surface)
2910 {
2911 struct encoder_vme_mfc_context *vme_context = NULL;
2912 struct gen9_hevc_encoder_context *priv_ctx = NULL;
2913 struct gen9_hevc_surface_priv *surface_priv = NULL;
2914 int bti_idx = 0;
2915
2916 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
2917 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
2918 surface_priv = (struct gen9_hevc_surface_priv *)dst_surface->private_data;
2919
2920 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
2921 HEVC_ENC_SURFACE_RAW_10bit_Y_UV, bti_idx++,
2922 1, 1, I965_SURFACEFORMAT_R8_UNORM,
2923 NULL, src_surface);
2924 bti_idx++;
2925
2926 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
2927 HEVC_ENC_SURFACE_RAW_FC_8bit_Y_UV, bti_idx++,
2928 1, 1, I965_SURFACEFORMAT_R8_UNORM,
2929 NULL,
2930 surface_priv->surface_obj_nv12);
2931 bti_idx++;
2932
2933 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
2934 HEVC_ENC_SURFACE_Y_4X, bti_idx++,
2935 0, 1, I965_SURFACEFORMAT_R32_UNORM,
2936 NULL,
2937 surface_priv->scaled_surface_obj[HEVC_SCALED_SURF_4X_ID]);
2938
2939 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
2940 HEVC_ENC_SURFACE_RAW_MBSTAT, bti_idx++,
2941 0, 0, 0, NULL, NULL);
2942
2943 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
2944 HEVC_ENC_SURFACE_Y_2X, bti_idx++,
2945 0, 1, I965_SURFACEFORMAT_R32_UNORM,
2946 NULL, NULL);
2947 }
2948
2949 static void
gen9_hevc_frame_depth_conversion(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct object_surface * src_surface,struct object_surface * dst_surface,GEN9_HEVC_DOWNSCALE_STAGE scale_stage)2950 gen9_hevc_frame_depth_conversion(VADriverContextP ctx,
2951 struct encode_state *encode_state,
2952 struct intel_encoder_context *encoder_context,
2953 struct object_surface *src_surface,
2954 struct object_surface *dst_surface,
2955 GEN9_HEVC_DOWNSCALE_STAGE scale_stage)
2956 {
2957 struct encoder_vme_mfc_context *vme_context = NULL;
2958 struct gen9_hevc_encoder_context *priv_ctx = NULL;
2959 struct gen9_hevc_encoder_state *priv_state = NULL;
2960 struct gpe_media_object_walker_parameter param;
2961 struct hevc_enc_kernel_walker_parameter hevc_walker_param;
2962 struct i965_gpe_context *gpe_context = NULL;
2963 int media_state = HEVC_ENC_MEDIA_STATE_DS_COMBINED;
2964
2965 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
2966 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
2967 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
2968
2969 gpe_context = &priv_ctx->mbenc_context.gpe_contexts[HEVC_MBENC_DS_COMBINED_IDX];
2970
2971 gen8_gpe_context_init(ctx, gpe_context);
2972 gen9_gpe_reset_binding_table(ctx, gpe_context);
2973 gen9_hevc_frame_depth_conversion_set_curbe(ctx, encode_state, encoder_context, gpe_context,
2974 scale_stage);
2975 gen9_hevc_frame_depth_conversion_set_surfaces(ctx, encode_state, encoder_context, gpe_context,
2976 src_surface, dst_surface);
2977 gen8_gpe_setup_interface_data(ctx, gpe_context);
2978
2979 memset((void *)&hevc_walker_param, 0, sizeof(hevc_walker_param));
2980 hevc_walker_param.resolution_x = ALIGN(priv_state->picture_width >> 2, 32) >> 3;
2981 hevc_walker_param.resolution_y = ALIGN(priv_state->picture_height >> 2, 32) >> 3;
2982 hevc_walker_param.no_dependency = 1;
2983 gen9_hevc_init_object_walker(&hevc_walker_param, ¶m);
2984 gen9_hevc_run_object_walker(ctx, encoder_context, gpe_context, ¶m,
2985 media_state);
2986 }
2987
2988 static void
gen9_hevc_ref_frame_depth_conversion(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)2989 gen9_hevc_ref_frame_depth_conversion(VADriverContextP ctx,
2990 struct encode_state *encode_state,
2991 struct intel_encoder_context *encoder_context)
2992 {
2993 struct i965_driver_data *i965 = i965_driver_data(ctx);
2994 struct gen9_hevc_surface_priv *surface_priv = NULL;
2995 VAEncSliceParameterBufferHEVC *slice_param = NULL;
2996 struct object_surface *obj_surface = NULL;
2997 int i = 0;
2998
2999 slice_param = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
3000
3001 for (i = 0; i < slice_param->num_ref_idx_l0_active_minus1 + 1; i++) {
3002 obj_surface = SURFACE(slice_param->ref_pic_list0[i].picture_id);
3003 if (obj_surface) {
3004 surface_priv = (struct gen9_hevc_surface_priv *)obj_surface->private_data;
3005
3006 if (!surface_priv->surface_nv12_valid) {
3007 gen9_hevc_frame_depth_conversion(ctx, encode_state, encoder_context,
3008 obj_surface, obj_surface,
3009 HEVC_ENC_DS_DISABLED);
3010
3011 surface_priv->surface_reff = surface_priv->surface_obj_nv12;
3012 surface_priv->surface_nv12_valid = 1;
3013 }
3014 }
3015 }
3016
3017 for (i = 0; i < slice_param->num_ref_idx_l1_active_minus1 + 1; i++) {
3018 obj_surface = SURFACE(slice_param->ref_pic_list1[i].picture_id);
3019 if (obj_surface) {
3020 surface_priv = (struct gen9_hevc_surface_priv *)obj_surface->private_data;
3021
3022 if (!surface_priv->surface_nv12_valid) {
3023 gen9_hevc_frame_depth_conversion(ctx, encode_state, encoder_context,
3024 obj_surface, obj_surface,
3025 HEVC_ENC_DS_DISABLED);
3026
3027 surface_priv->surface_reff = surface_priv->surface_obj_nv12;
3028 surface_priv->surface_nv12_valid = 1;
3029 }
3030 }
3031 }
3032 }
3033
3034 // Scaling implementation
3035
3036 static void
gen9_hevc_scaling_set_curbe_2x(struct i965_gpe_context * gpe_context,struct gen9_hevc_scaling_parameter * scaling_param)3037 gen9_hevc_scaling_set_curbe_2x(struct i965_gpe_context *gpe_context,
3038 struct gen9_hevc_scaling_parameter *scaling_param)
3039 {
3040 gen9_hevc_scaling2x_curbe_data *cmd;
3041
3042 cmd = i965_gpe_context_map_curbe(gpe_context);
3043 if (!cmd)
3044 return;
3045
3046 memset((void *)cmd, 0, sizeof(*cmd));
3047
3048 cmd->dw0.input_picture_width = scaling_param->input_frame_width;
3049 cmd->dw0.input_picture_height = scaling_param->input_frame_height;
3050
3051 cmd->dw8.input_y_bti = GEN9_HEVC_SCALING_FRAME_SRC_Y_INDEX;
3052 cmd->dw9.output_y_bti = GEN9_HEVC_SCALING_FRAME_DST_Y_INDEX;
3053
3054 i965_gpe_context_unmap_curbe(gpe_context);
3055 }
3056
3057 static void
gen9_hevc_scaling_set_curbe_4x(struct i965_gpe_context * gpe_context,struct gen9_hevc_scaling_parameter * scaling_param)3058 gen9_hevc_scaling_set_curbe_4x(struct i965_gpe_context *gpe_context,
3059 struct gen9_hevc_scaling_parameter *scaling_param)
3060 {
3061 gen9_hevc_scaling4x_curbe_data *cmd;
3062
3063 cmd = i965_gpe_context_map_curbe(gpe_context);
3064 if (!cmd)
3065 return;
3066
3067 memset((void *)cmd, 0, sizeof(*cmd));
3068
3069 cmd->dw0.input_picture_width = scaling_param->input_frame_width;
3070 cmd->dw0.input_picture_height = scaling_param->input_frame_height;
3071
3072 cmd->dw1.input_y_bti = GEN9_HEVC_SCALING_FRAME_SRC_Y_INDEX;
3073 cmd->dw2.output_y_bti = GEN9_HEVC_SCALING_FRAME_DST_Y_INDEX;
3074
3075 cmd->dw5.flatness_threshold = 0;
3076 cmd->dw6.enable_mb_flatness_check = scaling_param->enable_mb_flatness_check;
3077 cmd->dw7.enable_mb_variance_output = scaling_param->enable_mb_variance_output;
3078 cmd->dw8.enable_mb_pixel_average_output = scaling_param->enable_mb_pixel_average_output;
3079
3080 if (cmd->dw6.enable_mb_flatness_check ||
3081 cmd->dw7.enable_mb_variance_output ||
3082 cmd->dw8.enable_mb_pixel_average_output)
3083 cmd->dw10.mbv_proc_stat_bti = GEN9_HEVC_SCALING_FRAME_MBVPROCSTATS_DST_INDEX;
3084
3085 i965_gpe_context_unmap_curbe(gpe_context);
3086 }
3087
3088 static void
gen9_hevc_scaling_set_curbe(struct gen9_hevc_scaling_parameter * scaling_param,struct i965_gpe_context * gpe_context)3089 gen9_hevc_scaling_set_curbe(struct gen9_hevc_scaling_parameter *scaling_param,
3090 struct i965_gpe_context *gpe_context)
3091 {
3092 if (scaling_param->use_32x_scaling)
3093 gen9_hevc_scaling_set_curbe_2x(gpe_context, scaling_param);
3094 else
3095 gen9_hevc_scaling_set_curbe_4x(gpe_context, scaling_param);
3096 }
3097
3098 static void
gen9_hevc_scaling_set_surfaces(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct gen9_hevc_scaling_parameter * scaling_param,struct i965_gpe_context * gpe_context)3099 gen9_hevc_scaling_set_surfaces(VADriverContextP ctx,
3100 struct encode_state *encode_state,
3101 struct intel_encoder_context *encoder_context,
3102 struct gen9_hevc_scaling_parameter *scaling_param,
3103 struct i965_gpe_context *gpe_context)
3104 {
3105 unsigned int surface_format;
3106
3107 if (scaling_param->scaling_out_use_32unorm_surf_fmt)
3108 surface_format = I965_SURFACEFORMAT_R32_UNORM;
3109 else if (scaling_param->scaling_out_use_16unorm_surf_fmt)
3110 surface_format = I965_SURFACEFORMAT_R16_UNORM;
3111 else
3112 surface_format = I965_SURFACEFORMAT_R8_UNORM;
3113
3114 i965_add_2d_gpe_surface(ctx, gpe_context,
3115 scaling_param->input_surface,
3116 0, 1, surface_format,
3117 GEN9_HEVC_SCALING_FRAME_SRC_Y_INDEX);
3118
3119 i965_add_2d_gpe_surface(ctx, gpe_context,
3120 scaling_param->output_surface,
3121 0, 1, surface_format,
3122 GEN9_HEVC_SCALING_FRAME_DST_Y_INDEX);
3123
3124 if ((scaling_param->enable_mb_flatness_check ||
3125 scaling_param->enable_mb_variance_output ||
3126 scaling_param->enable_mb_pixel_average_output) &&
3127 scaling_param->use_4x_scaling) {
3128 i965_add_buffer_2d_gpe_surface(ctx, gpe_context,
3129 scaling_param->pres_mbv_proc_stat_buffer,
3130 1,
3131 I965_SURFACEFORMAT_R8_UNORM,
3132 GEN9_HEVC_SCALING_FRAME_MBVPROCSTATS_DST_INDEX);
3133 }
3134 }
3135
3136 static void
gen9_hevc_kernel_scaling(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,enum HEVC_HME_TYPE hme_type)3137 gen9_hevc_kernel_scaling(VADriverContextP ctx,
3138 struct encode_state *encode_state,
3139 struct intel_encoder_context *encoder_context,
3140 enum HEVC_HME_TYPE hme_type)
3141 {
3142 struct encoder_vme_mfc_context *vme_context = NULL;
3143 struct gen9_hevc_encoder_context *priv_ctx = NULL;
3144 struct gen9_hevc_encoder_state *priv_state = NULL;
3145 struct gen9_hevc_surface_priv *surface_priv = NULL;
3146 struct gen9_hevc_scaling_parameter scaling_param;
3147 struct gpe_media_object_walker_parameter param;
3148 unsigned int downscaled_width_in_mb, downscaled_height_in_mb;
3149 struct hevc_enc_kernel_walker_parameter hevc_walker_param;
3150 struct i965_gpe_context *gpe_context = NULL;
3151 int gpe_idx = 0, media_state = 0;;
3152
3153 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
3154 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
3155 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
3156
3157 surface_priv = (struct gen9_hevc_surface_priv *)encode_state->reconstructed_object->private_data;
3158
3159 memset((void *)&scaling_param, 0, sizeof(scaling_param));
3160 switch (hme_type) {
3161 case HEVC_HME_4X:
3162 media_state = HEVC_ENC_MEDIA_STATE_4X_SCALING;
3163 gpe_idx = HEVC_ENC_SCALING_4X;
3164 downscaled_width_in_mb = priv_state->downscaled_width_4x_in_mb;
3165 downscaled_height_in_mb = priv_state->downscaled_height_4x_in_mb;
3166
3167 scaling_param.input_surface = encode_state->input_yuv_object;
3168 scaling_param.input_frame_width = priv_state->picture_width;
3169 scaling_param.input_frame_height = priv_state->picture_height;
3170
3171 scaling_param.output_surface = surface_priv->scaled_surface_obj[HEVC_SCALED_SURF_4X_ID];
3172 scaling_param.output_frame_width = priv_state->frame_width_4x;
3173 scaling_param.output_frame_height = priv_state->frame_height_4x;
3174
3175 scaling_param.enable_mb_flatness_check = priv_state->flatness_check_enable;
3176 scaling_param.enable_mb_variance_output = 0;
3177 scaling_param.enable_mb_pixel_average_output = 0;
3178 scaling_param.pres_mbv_proc_stat_buffer = &(priv_ctx->res_flatness_check_surface);
3179
3180 scaling_param.blk8x8_stat_enabled = 0;
3181 scaling_param.use_4x_scaling = 1;
3182 scaling_param.use_16x_scaling = 0;
3183 scaling_param.use_32x_scaling = 0;
3184 break;
3185 case HEVC_HME_16X:
3186 media_state = HEVC_ENC_MEDIA_STATE_16X_SCALING;
3187 gpe_idx = HEVC_ENC_SCALING_16X;
3188 downscaled_width_in_mb = priv_state->downscaled_width_16x_in_mb;
3189 downscaled_height_in_mb = priv_state->downscaled_height_16x_in_mb;
3190
3191 scaling_param.input_surface = surface_priv->scaled_surface_obj[HEVC_SCALED_SURF_4X_ID];
3192 scaling_param.input_frame_width = priv_state->frame_width_4x;
3193 scaling_param.input_frame_height = priv_state->frame_height_4x;
3194
3195 scaling_param.output_surface = surface_priv->scaled_surface_obj[HEVC_SCALED_SURF_16X_ID];
3196 scaling_param.output_frame_width = priv_state->frame_width_16x;
3197 scaling_param.output_frame_height = priv_state->frame_height_16x;
3198
3199 scaling_param.enable_mb_flatness_check = 0;
3200 scaling_param.enable_mb_variance_output = 0;
3201 scaling_param.enable_mb_pixel_average_output = 0;
3202
3203 scaling_param.blk8x8_stat_enabled = 0;
3204 scaling_param.use_4x_scaling = 0;
3205 scaling_param.use_16x_scaling = 1;
3206 scaling_param.use_32x_scaling = 0;
3207 break;
3208 case HEVC_HME_32X:
3209 media_state = HEVC_ENC_MEDIA_STATE_32X_SCALING;
3210 gpe_idx = HEVC_ENC_SCALING_32X;
3211 downscaled_width_in_mb = priv_state->downscaled_width_32x_in_mb;
3212 downscaled_height_in_mb = priv_state->downscaled_height_32x_in_mb;
3213
3214 scaling_param.input_surface = surface_priv->scaled_surface_obj[HEVC_SCALED_SURF_16X_ID];
3215 scaling_param.input_frame_width = priv_state->frame_width_16x;
3216 scaling_param.input_frame_height = priv_state->frame_height_16x;
3217
3218 scaling_param.output_surface = surface_priv->scaled_surface_obj[HEVC_SCALED_SURF_32X_ID];
3219 scaling_param.output_frame_width = priv_state->frame_width_32x;
3220 scaling_param.output_frame_height = priv_state->frame_height_32x;
3221
3222 scaling_param.enable_mb_flatness_check = 0;
3223 scaling_param.enable_mb_variance_output = 0;
3224 scaling_param.enable_mb_pixel_average_output = 0;
3225
3226 scaling_param.blk8x8_stat_enabled = 0;
3227 scaling_param.use_4x_scaling = 0;
3228 scaling_param.use_16x_scaling = 0;
3229 scaling_param.use_32x_scaling = 1;
3230 break;
3231 default:
3232 return;
3233 }
3234
3235 gpe_context = &priv_ctx->scaling_context.gpe_contexts[gpe_idx];
3236 gen8_gpe_context_init(ctx, gpe_context);
3237 gen9_gpe_reset_binding_table(ctx, gpe_context);
3238 gen9_hevc_scaling_set_curbe(&scaling_param, gpe_context);
3239
3240 if (hme_type == HEVC_HME_32X) {
3241 scaling_param.scaling_out_use_16unorm_surf_fmt = 1;
3242 scaling_param.scaling_out_use_32unorm_surf_fmt = 0;
3243 } else {
3244 scaling_param.scaling_out_use_16unorm_surf_fmt = 0;
3245 scaling_param.scaling_out_use_32unorm_surf_fmt = 1;
3246 }
3247
3248 gen9_hevc_scaling_set_surfaces(ctx, encode_state, encoder_context, &scaling_param,
3249 gpe_context);
3250 gen8_gpe_setup_interface_data(ctx, gpe_context);
3251
3252 memset((void *)&hevc_walker_param, 0, sizeof(hevc_walker_param));
3253 if (hme_type == HEVC_HME_32X) {
3254 hevc_walker_param.resolution_x = downscaled_width_in_mb;
3255 hevc_walker_param.resolution_y = downscaled_height_in_mb;
3256 } else {
3257 hevc_walker_param.resolution_x = downscaled_width_in_mb * 2;
3258 hevc_walker_param.resolution_y = downscaled_height_in_mb * 2;
3259 }
3260 hevc_walker_param.no_dependency = 1;
3261 gen9_hevc_init_object_walker(&hevc_walker_param, ¶m);
3262 gen9_hevc_run_object_walker(ctx, encoder_context, gpe_context, ¶m,
3263 media_state);
3264 }
3265
3266 static void
gen9_hevc_hme_scaling(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)3267 gen9_hevc_hme_scaling(VADriverContextP ctx,
3268 struct encode_state *encode_state,
3269 struct intel_encoder_context *encoder_context)
3270 {
3271 struct encoder_vme_mfc_context *vme_context = NULL;
3272 struct generic_enc_codec_state *generic_state = NULL;
3273 struct gen9_hevc_encoder_state *priv_state = NULL;
3274
3275 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
3276 generic_state = (struct generic_enc_codec_state *)vme_context->generic_enc_state;
3277 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
3278
3279 if (priv_state->bit_depth_luma_minus8)
3280 gen9_hevc_frame_depth_conversion(ctx, encode_state, encoder_context,
3281 encode_state->input_yuv_object,
3282 encode_state->reconstructed_object,
3283 HEVC_ENC_2xDS_4xDS_STAGE);
3284 else
3285 gen9_hevc_kernel_scaling(ctx, encode_state, encoder_context, HEVC_HME_4X);
3286
3287 if (generic_state->b16xme_supported) {
3288 gen9_hevc_kernel_scaling(ctx, encode_state, encoder_context, HEVC_HME_16X);
3289
3290 if (generic_state->b32xme_supported)
3291 gen9_hevc_kernel_scaling(ctx, encode_state, encoder_context, HEVC_HME_32X);
3292 }
3293 }
3294
3295 // ME implementation
3296
3297 static void
gen9_hevc_me_set_curbe(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,enum HEVC_HME_TYPE hme_type,struct i965_gpe_context * gpe_context)3298 gen9_hevc_me_set_curbe(VADriverContextP ctx,
3299 struct encode_state *encode_state,
3300 struct intel_encoder_context *encoder_context,
3301 enum HEVC_HME_TYPE hme_type,
3302 struct i965_gpe_context *gpe_context)
3303 {
3304 struct encoder_vme_mfc_context *vme_context = NULL;
3305 struct generic_enc_codec_state *generic_state = NULL;
3306 struct gen9_hevc_encoder_state *priv_state = NULL;
3307 gen9_hevc_me_curbe_data *cmd = NULL;
3308 VAEncPictureParameterBufferHEVC *pic_param = NULL;
3309 VAEncSliceParameterBufferHEVC *slice_param = NULL;
3310 unsigned int use_mv_from_prev_step = 0;
3311 unsigned int write_distortions = 0;
3312 unsigned int slice_qp = 0;
3313 unsigned int me_method = 0;
3314 unsigned int mv_shift_factor = 0, prev_mv_read_pos_factor = 0;
3315 unsigned int downscaled_width_in_mb, downscaled_height_in_mb;
3316
3317 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
3318 generic_state = (struct generic_enc_codec_state *)vme_context->generic_enc_state;
3319 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
3320 pic_param = (VAEncPictureParameterBufferHEVC *)encode_state->pic_param_ext->buffer;
3321 slice_param = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
3322
3323 switch (hme_type) {
3324 case HEVC_HME_4X :
3325 use_mv_from_prev_step = (generic_state->b16xme_enabled) ? 1 : 0;;
3326 write_distortions = 1;
3327 mv_shift_factor = 2;
3328 prev_mv_read_pos_factor = 0;
3329 downscaled_width_in_mb = ALIGN(priv_state->picture_width / 4, 16) / 16;
3330 downscaled_height_in_mb = ALIGN(priv_state->picture_height / 4, 16) / 16;
3331 break;
3332 case HEVC_HME_16X :
3333 use_mv_from_prev_step = (generic_state->b32xme_enabled) ? 1 : 0;
3334 write_distortions = 0;
3335 mv_shift_factor = 2;
3336 prev_mv_read_pos_factor = 1;
3337 downscaled_width_in_mb = ALIGN(priv_state->picture_width / 16, 16) / 16;
3338 downscaled_height_in_mb = ALIGN(priv_state->picture_height / 16, 16) / 16;
3339 break;
3340 case HEVC_HME_32X :
3341 use_mv_from_prev_step = 0;
3342 write_distortions = 0;
3343 mv_shift_factor = 1;
3344 prev_mv_read_pos_factor = 0;
3345 downscaled_width_in_mb = ALIGN(priv_state->picture_width / 32, 16) / 16;
3346 downscaled_height_in_mb = ALIGN(priv_state->picture_height / 32, 16) / 16;
3347 break;
3348 default:
3349 return;
3350 }
3351
3352 me_method = GEN9_HEVC_ME_METHOD[priv_state->tu_mode];
3353 slice_qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
3354
3355 cmd = i965_gpe_context_map_curbe(gpe_context);
3356 if (!cmd)
3357 return;
3358
3359 memcpy((void *)cmd, GEN9_HEVC_ME_INIT_CURBE_DATA, sizeof(gen9_hevc_me_curbe_data));
3360
3361 cmd->dw3.sub_pel_mode = 3;
3362 cmd->dw4.picture_height_minus1 = downscaled_height_in_mb - 1;
3363 cmd->dw4.picture_width = downscaled_width_in_mb;
3364 cmd->dw5.qp_prime_y = slice_qp;
3365 cmd->dw6.use_mv_from_prev_step = use_mv_from_prev_step;
3366 cmd->dw6.write_distortions = write_distortions;
3367 cmd->dw6.super_combine_dist = GEN9_HEVC_SUPER_COMBINE_DIST[priv_state->tu_mode];
3368 cmd->dw6.max_vmvr = 512;
3369
3370 if (priv_state->picture_coding_type != HEVC_SLICE_I) {
3371 cmd->dw13.num_ref_idx_l0_minus1 = slice_param->num_ref_idx_l0_active_minus1;
3372 if (priv_state->picture_coding_type == HEVC_SLICE_B) {
3373 cmd->dw1.bi_weight = 32;
3374 cmd->dw13.num_ref_idx_l1_minus1 = slice_param->num_ref_idx_l1_active_minus1;
3375 }
3376 }
3377
3378 cmd->dw15.prev_mv_read_pos_factor = prev_mv_read_pos_factor;
3379 cmd->dw15.mv_shift_factor = mv_shift_factor;
3380
3381 memcpy(&cmd->dw16, table_enc_search_path[GEN9_HEVC_ENC_MEMETHOD_TABLE][me_method], 14 * sizeof(unsigned int));
3382
3383 cmd->dw32._4x_memv_output_data_surf_index = GEN9_HEVC_ME_MV_DATA_SURFACE_INDEX;
3384 cmd->dw33._16x_32x_memv_input_data_surf_index = (hme_type == HEVC_HME_32X) ?
3385 GEN9_HEVC_ME_32X_MV_DATA_SURFACE_INDEX : GEN9_HEVC_ME_16X_MV_DATA_SURFACE_INDEX;
3386 cmd->dw34._4x_me_output_dist_surf_index = GEN9_HEVC_ME_DISTORTION_SURFACE_INDEX;
3387 cmd->dw35._4x_me_output_brc_dist_surf_index = GEN9_HEVC_ME_BRC_DISTORTION_INDEX;
3388 cmd->dw36.vme_fwd_inter_pred_surf_index = GEN9_HEVC_ME_CURR_FOR_FWD_REF_INDEX;
3389 cmd->dw37.vme_bdw_inter_pred_surf_index = GEN9_HEVC_ME_CURR_FOR_BWD_REF_INDEX;
3390
3391 i965_gpe_context_unmap_curbe(gpe_context);
3392 }
3393
3394 static void
gen9_hevc_me_set_surfaces(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,enum HEVC_HME_TYPE hme_type,struct i965_gpe_context * gpe_context)3395 gen9_hevc_me_set_surfaces(VADriverContextP ctx,
3396 struct encode_state *encode_state,
3397 struct intel_encoder_context *encoder_context,
3398 enum HEVC_HME_TYPE hme_type,
3399 struct i965_gpe_context *gpe_context)
3400 {
3401 struct i965_driver_data *i965 = i965_driver_data(ctx);
3402 struct encoder_vme_mfc_context *vme_context = NULL;
3403 struct gen9_hevc_encoder_context *priv_ctx = NULL;
3404 struct generic_enc_codec_state *generic_state = NULL;
3405 VAEncSliceParameterBufferHEVC *slice_param = NULL;
3406 struct gen9_hevc_surface_priv *surface_priv = NULL;
3407 struct object_surface *obj_surface = NULL;
3408 int scaled_surf_id = VA_INVALID_SURFACE, surface_id = VA_INVALID_SURFACE;
3409 int i = 0;
3410
3411 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
3412 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
3413 generic_state = (struct generic_enc_codec_state *)vme_context->generic_enc_state;
3414 slice_param = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
3415
3416 switch (hme_type) {
3417 case HEVC_HME_4X:
3418 scaled_surf_id = HEVC_SCALED_SURF_4X_ID;
3419 i965_add_buffer_2d_gpe_surface(ctx, gpe_context,
3420 &priv_ctx->s4x_memv_data_buffer,
3421 1,
3422 I965_SURFACEFORMAT_R8_UNORM,
3423 GEN9_HEVC_ME_MV_DATA_SURFACE_INDEX);
3424
3425 if (generic_state->b16xme_enabled)
3426 i965_add_buffer_2d_gpe_surface(ctx, gpe_context,
3427 &priv_ctx->s16x_memv_data_buffer,
3428 1,
3429 I965_SURFACEFORMAT_R8_UNORM,
3430 GEN9_HEVC_ME_16X_MV_DATA_SURFACE_INDEX);
3431
3432 i965_add_buffer_2d_gpe_surface(ctx, gpe_context,
3433 &priv_ctx->res_brc_me_dist_buffer,
3434 1,
3435 I965_SURFACEFORMAT_R8_UNORM,
3436 GEN9_HEVC_ME_BRC_DISTORTION_INDEX);
3437
3438 i965_add_buffer_2d_gpe_surface(ctx, gpe_context,
3439 &priv_ctx->s4x_memv_distortion_buffer,
3440 1,
3441 I965_SURFACEFORMAT_R8_UNORM,
3442 GEN9_HEVC_ME_DISTORTION_SURFACE_INDEX);
3443 break;
3444 case HEVC_HME_16X:
3445 scaled_surf_id = HEVC_SCALED_SURF_16X_ID;
3446
3447 i965_add_buffer_2d_gpe_surface(ctx, gpe_context,
3448 &priv_ctx->s16x_memv_data_buffer,
3449 1,
3450 I965_SURFACEFORMAT_R8_UNORM,
3451 GEN9_HEVC_ME_MV_DATA_SURFACE_INDEX);
3452
3453 if (generic_state->b32xme_enabled)
3454 i965_add_buffer_2d_gpe_surface(ctx, gpe_context,
3455 &priv_ctx->s32x_memv_data_buffer,
3456 1,
3457 I965_SURFACEFORMAT_R8_UNORM,
3458 GEN9_HEVC_ME_32X_MV_DATA_SURFACE_INDEX);
3459 else
3460 i965_add_buffer_2d_gpe_surface(ctx, gpe_context,
3461 &priv_ctx->s16x_memv_data_buffer,
3462 1,
3463 I965_SURFACEFORMAT_R8_UNORM,
3464 GEN9_HEVC_ME_16X_MV_DATA_SURFACE_INDEX);
3465 break;
3466 case HEVC_HME_32X:
3467 scaled_surf_id = HEVC_SCALED_SURF_32X_ID;
3468 i965_add_buffer_2d_gpe_surface(ctx, gpe_context,
3469 &priv_ctx->s32x_memv_data_buffer,
3470 1,
3471 I965_SURFACEFORMAT_R8_UNORM,
3472 GEN9_HEVC_ME_MV_DATA_SURFACE_INDEX);
3473 break;
3474 default:
3475 return;
3476 }
3477
3478 obj_surface = encode_state->reconstructed_object;
3479 surface_priv = (struct gen9_hevc_surface_priv *)obj_surface->private_data;
3480 i965_add_adv_gpe_surface(ctx, gpe_context,
3481 surface_priv->scaled_surface_obj[scaled_surf_id],
3482 GEN9_HEVC_ME_CURR_FOR_FWD_REF_INDEX);
3483
3484 for (i = 0; i < slice_param->num_ref_idx_l0_active_minus1 + 1; i++) {
3485 surface_id = slice_param->ref_pic_list0[i].picture_id;
3486 obj_surface = SURFACE(surface_id);
3487 if (!obj_surface || !obj_surface->private_data)
3488 break;
3489
3490 surface_priv = (struct gen9_hevc_surface_priv *)obj_surface->private_data;
3491 i965_add_adv_gpe_surface(ctx, gpe_context,
3492 surface_priv->scaled_surface_obj[scaled_surf_id],
3493 GEN9_HEVC_ME_CURR_FOR_FWD_REF_INDEX + i * 2 + 1);
3494 }
3495
3496 obj_surface = encode_state->reconstructed_object;
3497 surface_priv = (struct gen9_hevc_surface_priv *)obj_surface->private_data;
3498 i965_add_adv_gpe_surface(ctx, gpe_context,
3499 surface_priv->scaled_surface_obj[scaled_surf_id],
3500 GEN9_HEVC_ME_CURR_FOR_BWD_REF_INDEX);
3501
3502 for (i = 0; i < slice_param->num_ref_idx_l1_active_minus1 + 1; i++) {
3503 surface_id = slice_param->ref_pic_list1[i].picture_id;
3504 obj_surface = SURFACE(surface_id);
3505 if (!obj_surface || !obj_surface->private_data)
3506 break;
3507
3508 surface_priv = (struct gen9_hevc_surface_priv *)obj_surface->private_data;
3509 i965_add_adv_gpe_surface(ctx, gpe_context,
3510 surface_priv->scaled_surface_obj[scaled_surf_id],
3511 GEN9_HEVC_ME_CURR_FOR_BWD_REF_INDEX + i * 2 + 1);
3512 }
3513 }
3514
3515 static void
gen9_hevc_kernel_me(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,enum HEVC_HME_TYPE hme_type)3516 gen9_hevc_kernel_me(VADriverContextP ctx,
3517 struct encode_state *encode_state,
3518 struct intel_encoder_context *encoder_context,
3519 enum HEVC_HME_TYPE hme_type)
3520 {
3521 struct encoder_vme_mfc_context *vme_context = NULL;
3522 struct gen9_hevc_encoder_context *priv_ctx = NULL;
3523 struct gen9_hevc_encoder_state *priv_state = NULL;
3524 struct gpe_media_object_walker_parameter param;
3525 struct hevc_enc_kernel_walker_parameter hevc_walker_param;
3526 unsigned int downscaled_width_in_mb, downscaled_height_in_mb;
3527 struct i965_gpe_context *gpe_context;
3528 int media_state = 0;
3529
3530 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
3531 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
3532 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
3533
3534 switch (hme_type) {
3535 case HEVC_HME_4X:
3536 media_state = HEVC_ENC_MEDIA_STATE_4X_ME;
3537 downscaled_width_in_mb = priv_state->downscaled_width_4x_in_mb;
3538 downscaled_height_in_mb = priv_state->downscaled_height_4x_in_mb;
3539 break;
3540 case HEVC_HME_16X:
3541 media_state = HEVC_ENC_MEDIA_STATE_16X_ME;
3542 downscaled_width_in_mb = priv_state->downscaled_width_16x_in_mb;
3543 downscaled_height_in_mb = priv_state->downscaled_height_16x_in_mb;
3544 break;
3545 case HEVC_HME_32X:
3546 media_state = HEVC_ENC_MEDIA_STATE_32X_ME;
3547 downscaled_width_in_mb = priv_state->downscaled_width_32x_in_mb;
3548 downscaled_height_in_mb = priv_state->downscaled_height_32x_in_mb;
3549 break;
3550 default:
3551 return;
3552 }
3553
3554 if (priv_state->picture_coding_type == HEVC_SLICE_P)
3555 gpe_context = &priv_ctx->me_context.gpe_context[hme_type][HEVC_ENC_ME_P];
3556 else
3557 gpe_context = &priv_ctx->me_context.gpe_context[hme_type][HEVC_ENC_ME_B];
3558
3559 gen8_gpe_context_init(ctx, gpe_context);
3560 gen9_gpe_reset_binding_table(ctx, gpe_context);
3561 gen9_hevc_me_set_curbe(ctx, encode_state, encoder_context, hme_type, gpe_context);
3562 gen9_hevc_me_set_surfaces(ctx, encode_state, encoder_context, hme_type, gpe_context);
3563 gen8_gpe_setup_interface_data(ctx, gpe_context);
3564
3565 memset((void *)&hevc_walker_param, 0, sizeof(hevc_walker_param));
3566 hevc_walker_param.resolution_x = downscaled_width_in_mb;
3567 hevc_walker_param.resolution_y = downscaled_height_in_mb;
3568 hevc_walker_param.no_dependency = 1;
3569 gen9_hevc_init_object_walker(&hevc_walker_param, ¶m);
3570
3571 gen9_hevc_run_object_walker(ctx, encoder_context, gpe_context, ¶m,
3572 media_state);
3573 }
3574
3575 static void
gen9_hevc_hme_encode_me(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)3576 gen9_hevc_hme_encode_me(VADriverContextP ctx,
3577 struct encode_state *encode_state,
3578 struct intel_encoder_context *encoder_context)
3579 {
3580 struct encoder_vme_mfc_context *vme_context = NULL;
3581 struct generic_enc_codec_state *generic_state = NULL;
3582
3583 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
3584 generic_state = (struct generic_enc_codec_state *)vme_context->generic_enc_state;
3585
3586 if (generic_state->b16xme_enabled) {
3587 if (generic_state->b32xme_enabled)
3588 gen9_hevc_kernel_me(ctx, encode_state, encoder_context, HEVC_HME_32X);
3589
3590 gen9_hevc_kernel_me(ctx, encode_state, encoder_context, HEVC_HME_16X);
3591 }
3592
3593 gen9_hevc_kernel_me(ctx, encode_state, encoder_context, HEVC_HME_4X);
3594 }
3595
3596 // MBENC kernels setting start
3597
3598 static unsigned char
map_44_lut_value(unsigned int value,unsigned char max)3599 map_44_lut_value(unsigned int value,
3600 unsigned char max)
3601 {
3602 unsigned int max_cost = 0;
3603 int data = 0;
3604 unsigned char ret = 0;
3605
3606 if (value == 0)
3607 return 0;
3608
3609 max_cost = ((max & 15) << (max >> 4));
3610 if (value >= max_cost)
3611 return max;
3612
3613 data = (int)(log((double)value) / log(2.)) - 3;
3614 if (data < 0)
3615 data = 0;
3616
3617 ret = (unsigned char)((data << 4) +
3618 (int)((value + (data == 0 ? 0 : (1 << (data - 1)))) >> data));
3619 ret = (ret & 0xf) == 0 ? (ret | 8) : ret;
3620
3621 return ret;
3622 }
3623
3624 static void
gen9_hevc_mbenc_set_costs(struct gen9_hevc_encoder_context * priv_ctx,int slice_type,int intra_trans_type,unsigned int slice_qp,unsigned char * mode_cost,unsigned char * mv_cost,unsigned char * mode_cost_sp,unsigned int * simplest_intra_inter_threshold)3625 gen9_hevc_mbenc_set_costs(struct gen9_hevc_encoder_context *priv_ctx,
3626 int slice_type,
3627 int intra_trans_type,
3628 unsigned int slice_qp,
3629 unsigned char *mode_cost,
3630 unsigned char *mv_cost,
3631 unsigned char *mode_cost_sp,
3632 unsigned int *simplest_intra_inter_threshold)
3633 {
3634 float had_bias = intra_trans_type == HEVC_ENC_INTRA_TRANS_HADAMARD ?
3635 1.67f : 2.0f;
3636 double lambda_md, lambda_me;
3637
3638 lambda_md = priv_ctx->lambda_md_table[slice_type][slice_qp];
3639 lambda_me = priv_ctx->lambda_md_table[slice_type][slice_qp];
3640
3641 if (mode_cost) {
3642 mode_cost[0] = map_44_lut_value((unsigned int)(lambda_md * GEN9_HEVC_ENC_Mode_COST[slice_type][0] * had_bias), 0x6f);
3643 mode_cost[1] = map_44_lut_value((unsigned int)(lambda_md * GEN9_HEVC_ENC_Mode_COST[slice_type][1] * had_bias), 0x8f);
3644 mode_cost[2] = map_44_lut_value((unsigned int)(lambda_md * GEN9_HEVC_ENC_Mode_COST[slice_type][2] * had_bias), 0x8f);
3645 mode_cost[3] = map_44_lut_value((unsigned int)(lambda_md * GEN9_HEVC_ENC_Mode_COST[slice_type][3] * had_bias), 0x8f);
3646 mode_cost[4] = map_44_lut_value((unsigned int)(lambda_md * GEN9_HEVC_ENC_Mode_COST[slice_type][4] * had_bias), 0x8f);
3647 mode_cost[5] = map_44_lut_value((unsigned int)(lambda_md * GEN9_HEVC_ENC_Mode_COST[slice_type][5] * had_bias), 0x6f);
3648 mode_cost[6] = map_44_lut_value((unsigned int)(lambda_md * GEN9_HEVC_ENC_Mode_COST[slice_type][6] * had_bias), 0x6f);
3649 mode_cost[7] = map_44_lut_value((unsigned int)(lambda_md * GEN9_HEVC_ENC_Mode_COST[slice_type][7] * had_bias), 0x6f);
3650 mode_cost[8] = map_44_lut_value((unsigned int)(lambda_md * GEN9_HEVC_ENC_Mode_COST[slice_type][8] * had_bias), 0x8f);
3651 mode_cost[9] = map_44_lut_value((unsigned int)(lambda_md * GEN9_HEVC_ENC_Mode_COST[slice_type][9] * had_bias), 0x6f);
3652 mode_cost[10] = map_44_lut_value((unsigned int)(lambda_md * GEN9_HEVC_ENC_Mode_COST[slice_type][10] * had_bias), 0x6f);
3653 mode_cost[11] = map_44_lut_value((unsigned int)(lambda_md * GEN9_HEVC_ENC_Mode_COST[slice_type][11] * had_bias), 0x6f);
3654 }
3655
3656 if (mv_cost) {
3657 mv_cost[0] = map_44_lut_value((unsigned int)(lambda_me * GEN9_HEVC_ENC_MV_COST[slice_type][0] * had_bias), 0x6f);
3658 mv_cost[1] = map_44_lut_value((unsigned int)(lambda_me * GEN9_HEVC_ENC_MV_COST[slice_type][1] * had_bias), 0x6f);
3659 mv_cost[2] = map_44_lut_value((unsigned int)(lambda_me * GEN9_HEVC_ENC_MV_COST[slice_type][2] * had_bias), 0x6f);
3660 mv_cost[3] = map_44_lut_value((unsigned int)(lambda_me * GEN9_HEVC_ENC_MV_COST[slice_type][3] * had_bias), 0x6f);
3661 mv_cost[4] = map_44_lut_value((unsigned int)(lambda_me * GEN9_HEVC_ENC_MV_COST[slice_type][4] * had_bias), 0x6f);
3662 mv_cost[5] = map_44_lut_value((unsigned int)(lambda_me * GEN9_HEVC_ENC_MV_COST[slice_type][5] * had_bias), 0x6f);
3663 mv_cost[6] = map_44_lut_value((unsigned int)(lambda_me * GEN9_HEVC_ENC_MV_COST[slice_type][6] * had_bias), 0x6f);
3664 mv_cost[7] = map_44_lut_value((unsigned int)(lambda_me * GEN9_HEVC_ENC_MV_COST[slice_type][7] * had_bias), 0x6f);
3665 }
3666
3667 if (mode_cost_sp)
3668 *mode_cost_sp = map_44_lut_value((unsigned int)(lambda_md * 45 * had_bias), 0x8f);
3669
3670 if (simplest_intra_inter_threshold) {
3671 lambda_md *= had_bias;
3672 *simplest_intra_inter_threshold = 0;
3673 if (GEN9_HEVC_ENC_Mode_COST[slice_type][1] < GEN9_HEVC_ENC_Mode_COST[slice_type][3])
3674 *simplest_intra_inter_threshold = (unsigned int)(lambda_md *
3675 (GEN9_HEVC_ENC_Mode_COST[slice_type][3] - GEN9_HEVC_ENC_Mode_COST[slice_type][1]) + 0.5);
3676 }
3677 }
3678
3679 static void
gen9_hevc_set_lambda_tables(struct gen9_hevc_encoder_context * priv_ctx,int slice_type,int intra_trans_type)3680 gen9_hevc_set_lambda_tables(struct gen9_hevc_encoder_context *priv_ctx,
3681 int slice_type,
3682 int intra_trans_type)
3683 {
3684 if (slice_type != HEVC_SLICE_I) {
3685 if (priv_ctx->lambda_table_inited)
3686 return;
3687
3688 memcpy((void *)&priv_ctx->lambda_me_table[slice_type], &GEN9_HEVC_ENC_QP_LAMBDA_ME[slice_type],
3689 sizeof(GEN9_HEVC_ENC_QP_LAMBDA_ME[slice_type]));
3690 memcpy((void *)&priv_ctx->lambda_md_table[slice_type], &GEN9_HEVC_ENC_QP_LAMBDA_ME[slice_type],
3691 sizeof(GEN9_HEVC_ENC_QP_LAMBDA_ME[slice_type]));
3692 } else if (intra_trans_type != priv_ctx->lambda_intra_trans_type ||
3693 !priv_ctx->lambda_table_inited) {
3694 double temp = 0.0;
3695 double lambda = 0.0;
3696 int qp = 0;
3697
3698 for (qp = 0; qp < 52; qp++) {
3699 temp = (double)qp - 12;
3700 lambda = 0.85 * pow(2.0, temp / 3.0);
3701
3702 if ((intra_trans_type != HEVC_ENC_INTRA_TRANS_HAAR) &&
3703 (intra_trans_type != HEVC_ENC_INTRA_TRANS_HADAMARD))
3704 lambda *= 0.95;
3705
3706 priv_ctx->lambda_md_table[slice_type][qp] =
3707 priv_ctx->lambda_me_table[slice_type][qp] = sqrt(lambda);
3708 }
3709
3710 priv_ctx->lambda_intra_trans_type = intra_trans_type;
3711 }
3712 }
3713
3714 static void
gen9_hevc_lambda_tables_init(struct gen9_hevc_encoder_context * priv_ctx)3715 gen9_hevc_lambda_tables_init(struct gen9_hevc_encoder_context *priv_ctx)
3716 {
3717 gen9_hevc_set_lambda_tables(priv_ctx, HEVC_SLICE_B, HEVC_ENC_INTRA_TRANS_HAAR);
3718 gen9_hevc_set_lambda_tables(priv_ctx, HEVC_SLICE_P, HEVC_ENC_INTRA_TRANS_HAAR);
3719 gen9_hevc_set_lambda_tables(priv_ctx, HEVC_SLICE_I, HEVC_ENC_INTRA_TRANS_HAAR);
3720
3721 priv_ctx->lambda_table_inited = 1;
3722 }
3723
3724 static void
gen9_hevc_8x8_b_pak_set_curbe(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)3725 gen9_hevc_8x8_b_pak_set_curbe(VADriverContextP ctx,
3726 struct encode_state *encode_state,
3727 struct intel_encoder_context *encoder_context,
3728 struct i965_gpe_context *gpe_context)
3729 {
3730 struct i965_driver_data *i965 = i965_driver_data(ctx);
3731 struct encoder_vme_mfc_context *vme_context = NULL;
3732 struct generic_enc_codec_state *generic_state = NULL;
3733 struct gen9_hevc_encoder_state *priv_state = NULL;
3734 gen9_hevc_mbenc_b_pak_curbe_data *cmd = NULL;
3735 VAEncPictureParameterBufferHEVC *pic_param = NULL;
3736 VAEncSliceParameterBufferHEVC *slice_param = NULL;
3737 unsigned int slice_qp = 0;
3738 int bti_idx = 0;
3739
3740 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
3741 generic_state = (struct generic_enc_codec_state *)vme_context->generic_enc_state;
3742 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
3743 pic_param = (VAEncPictureParameterBufferHEVC *)encode_state->pic_param_ext->buffer;
3744 slice_param = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
3745
3746 slice_qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
3747 cmd = i965_gpe_context_map_curbe(gpe_context);
3748 if (!cmd)
3749 return;
3750
3751 memset((void *)cmd, 0, sizeof(*cmd));
3752
3753 cmd->dw0.frame_width = ALIGN(priv_state->picture_width, 16);
3754 cmd->dw0.frame_height = ALIGN(priv_state->picture_height, 16);
3755 cmd->dw1.max_vmvr = 511 * 4;
3756 cmd->dw1.qp = slice_qp;
3757 cmd->dw2.brc_enable = generic_state->brc_enabled;
3758 cmd->dw2.lcu_brc_enable = priv_state->lcu_brc_enabled;
3759 cmd->dw2.screen_content = !!pic_param->pic_fields.bits.screen_content_flag;
3760 cmd->dw2.slice_type = priv_state->picture_coding_type;
3761 cmd->dw2.roi_enable = (priv_state->num_roi > 0);
3762 cmd->dw2.fast_surveillance_flag = priv_state->picture_coding_type == HEVC_SLICE_I ?
3763 0 : priv_state->video_surveillance_flag;
3764 cmd->dw2.kbl_control_flag = (IS_KBL(i965->intel.device_info) || IS_GLK(i965->intel.device_info));
3765 cmd->dw2.enable_rolling_intra = priv_state->rolling_intra_refresh;
3766 cmd->dw2.simplest_intra_enable = (priv_state->tu_mode == HEVC_TU_BEST_SPEED);
3767 cmd->dw3.widi_intra_refresh_qp_delta = priv_state->widi_intra_refresh_qp_delta;
3768 cmd->dw3.widi_intra_refresh_mb_num = priv_state->widi_intra_insertion_location;
3769 cmd->dw3.widi_intra_refresh_unit_in_mb = priv_state->widi_intra_insertion_size;
3770
3771 cmd->dw16.bti_cu_record = bti_idx++;
3772 cmd->dw17.bti_pak_obj = bti_idx++;
3773 cmd->dw18.bti_slice_map = bti_idx++;
3774 cmd->dw19.bti_brc_input = bti_idx++;
3775 cmd->dw20.bti_lcu_qp = bti_idx++;
3776 cmd->dw21.bti_brc_data = bti_idx++;
3777 cmd->dw22.bti_mb_data = bti_idx++;
3778 cmd->dw23.bti_mvp_surface = bti_idx++;
3779 cmd->dw24.bti_debug = bti_idx++;
3780
3781 i965_gpe_context_unmap_curbe(gpe_context);
3782 }
3783
3784 static void
gen9_hevc_8x8_b_pak_set_surfaces(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)3785 gen9_hevc_8x8_b_pak_set_surfaces(VADriverContextP ctx,
3786 struct encode_state *encode_state,
3787 struct intel_encoder_context *encoder_context,
3788 struct i965_gpe_context *gpe_context)
3789 {
3790 struct encoder_vme_mfc_context *vme_context = NULL;
3791 struct gen9_hevc_encoder_context *priv_ctx = NULL;
3792 struct gen9_hevc_encoder_state *priv_state = NULL;
3793 int bti_idx = 0;
3794 int size = 0;
3795
3796 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
3797 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
3798 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
3799
3800 size = priv_state->width_in_cu * priv_state->height_in_cu *
3801 priv_state->cu_record_size;
3802 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
3803 HEVC_ENC_SURFACE_CU_RECORD, bti_idx++,
3804 0, size, priv_state->mb_data_offset, NULL, NULL);
3805
3806 size = priv_state->mb_data_offset;
3807 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
3808 HEVC_ENC_SURFACE_HCP_PAK, bti_idx++,
3809 0, size, 0, NULL, NULL);
3810
3811 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
3812 HEVC_ENC_SURFACE_SLICE_MAP, bti_idx++,
3813 0, 1, I965_SURFACEFORMAT_R8_UNORM,
3814 NULL, NULL);
3815
3816 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
3817 HEVC_ENC_SURFACE_BRC_INPUT, bti_idx++,
3818 0, 0, 0, NULL, NULL);
3819
3820 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
3821 HEVC_ENC_SURFACE_LCU_QP, bti_idx++,
3822 0, 1, I965_SURFACEFORMAT_R8_UNORM,
3823 NULL, NULL);
3824
3825 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
3826 HEVC_ENC_SURFACE_BRC_DATA, bti_idx++,
3827 0, 1, I965_SURFACEFORMAT_R8_UNORM,
3828 NULL, NULL);
3829
3830 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
3831 HEVC_ENC_SURFACE_MB_MV_INDEX, bti_idx++,
3832 0, 0, 0, NULL, NULL);
3833
3834 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
3835 HEVC_ENC_SURFACE_MVP_INDEX, bti_idx++,
3836 0, 0, 0, NULL, NULL);
3837
3838 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
3839 HEVC_ENC_SURFACE_KERNEL_DEBUG, bti_idx++,
3840 0, 0, 0, NULL, NULL);
3841 }
3842
3843 static void
gen9_hevc_8x8_b_pak(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)3844 gen9_hevc_8x8_b_pak(VADriverContextP ctx,
3845 struct encode_state *encode_state,
3846 struct intel_encoder_context *encoder_context)
3847 {
3848 struct encoder_vme_mfc_context *vme_context = NULL;
3849 struct gen9_hevc_encoder_context *priv_ctx = NULL;
3850 struct gen9_hevc_encoder_state *priv_state = NULL;
3851 struct gpe_media_object_walker_parameter param;
3852 struct hevc_enc_kernel_walker_parameter hevc_walker_param;
3853 struct i965_gpe_context *gpe_context = NULL;
3854 int media_state = HEVC_ENC_MEDIA_STATE_HEVC_B_PAK;
3855
3856 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
3857 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
3858 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
3859
3860 gpe_context = &priv_ctx->mbenc_context.gpe_contexts[HEVC_MBENC_BPAK_IDX];
3861
3862 gen8_gpe_context_init(ctx, gpe_context);
3863 gen9_gpe_reset_binding_table(ctx, gpe_context);
3864 gen9_hevc_8x8_b_pak_set_curbe(ctx, encode_state, encoder_context, gpe_context);
3865 gen9_hevc_8x8_b_pak_set_surfaces(ctx, encode_state, encoder_context, gpe_context);
3866 gen8_gpe_setup_interface_data(ctx, gpe_context);
3867
3868 memset((void *)&hevc_walker_param, 0, sizeof(hevc_walker_param));
3869 hevc_walker_param.resolution_x = ALIGN(priv_state->picture_width, 32) >> 5;
3870 hevc_walker_param.resolution_y = ALIGN(priv_state->picture_height, 32) >> 5;
3871 hevc_walker_param.no_dependency = 1;
3872 gen9_hevc_init_object_walker(&hevc_walker_param, ¶m);
3873 gen9_hevc_run_object_walker(ctx, encoder_context, gpe_context, ¶m,
3874 media_state);
3875 }
3876
3877 static const unsigned char ftq_25i[27] = {
3878 0, 0, 0, 0,
3879 1, 3, 6, 8, 11,
3880 13, 16, 19, 22, 26,
3881 30, 34, 39, 44, 50,
3882 56, 62, 69, 77, 85,
3883 94, 104, 115
3884 };
3885
3886 static void
gen9_hevc_set_forward_coeff_thd(unsigned char * pcoeff,int qp)3887 gen9_hevc_set_forward_coeff_thd(unsigned char *pcoeff,
3888 int qp)
3889 {
3890 int idx = (qp + 1) >> 1;
3891
3892 memset((void *)pcoeff, ftq_25i[idx], 7);
3893 }
3894
3895 static int
gen9_hevc_get_qp_from_ref_list(VADriverContextP ctx,VAEncSliceParameterBufferHEVC * slice_param,int list_idx,int ref_frame_idx)3896 gen9_hevc_get_qp_from_ref_list(VADriverContextP ctx,
3897 VAEncSliceParameterBufferHEVC *slice_param,
3898 int list_idx,
3899 int ref_frame_idx)
3900 {
3901 struct i965_driver_data *i965 = i965_driver_data(ctx);
3902 struct gen9_hevc_surface_priv *hevc_priv_surface = NULL;
3903 struct object_surface *obj_surface = NULL;
3904 VASurfaceID surface_id;
3905
3906 if (list_idx == 0) {
3907 if (ref_frame_idx < slice_param->num_ref_idx_l0_active_minus1 + 1)
3908 surface_id = slice_param->ref_pic_list0[ref_frame_idx].picture_id;
3909 else
3910 goto FAIL;
3911 } else {
3912 if (ref_frame_idx < slice_param->num_ref_idx_l1_active_minus1 + 1)
3913 surface_id = slice_param->ref_pic_list1[ref_frame_idx].picture_id;
3914 else
3915 goto FAIL;
3916 }
3917
3918 obj_surface = SURFACE(surface_id);
3919 if (obj_surface && obj_surface->private_data) {
3920 hevc_priv_surface = obj_surface->private_data;
3921 return hevc_priv_surface->qp_value;
3922 }
3923
3924 FAIL:
3925 return 0;
3926 }
3927
3928 static short
gen9_hevc_get_poc_diff_from_ref_list(VAEncPictureParameterBufferHEVC * pic_param,VAEncSliceParameterBufferHEVC * slice_param,int list_idx,int ref_frame_idx)3929 gen9_hevc_get_poc_diff_from_ref_list(VAEncPictureParameterBufferHEVC *pic_param,
3930 VAEncSliceParameterBufferHEVC *slice_param,
3931 int list_idx,
3932 int ref_frame_idx)
3933 {
3934 short poc_diff = 0;
3935
3936 if (list_idx == 0 &&
3937 ref_frame_idx < slice_param->num_ref_idx_l0_active_minus1 + 1)
3938 poc_diff = pic_param->decoded_curr_pic.pic_order_cnt -
3939 slice_param->ref_pic_list0[ref_frame_idx].pic_order_cnt;
3940 else if (list_idx == 1 &&
3941 ref_frame_idx < slice_param->num_ref_idx_l1_active_minus1 + 1)
3942 poc_diff = pic_param->decoded_curr_pic.pic_order_cnt -
3943 slice_param->ref_pic_list1[ref_frame_idx].pic_order_cnt;
3944
3945 return CLAMP(-128, 127, poc_diff);
3946 }
3947
3948 static void
gen9_hevc_set_control_region(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context,struct gen9_hevc_walking_pattern_parameter * param)3949 gen9_hevc_set_control_region(VADriverContextP ctx,
3950 struct encode_state *encode_state,
3951 struct intel_encoder_context *encoder_context,
3952 struct i965_gpe_context *gpe_context,
3953 struct gen9_hevc_walking_pattern_parameter *param)
3954 {
3955 struct encoder_vme_mfc_context *vme_context = NULL;
3956 struct gen9_hevc_encoder_context *priv_ctx = NULL;
3957 struct gen9_hevc_encoder_state *priv_state = NULL;
3958 VAEncSliceParameterBufferHEVC *slice_param = NULL;
3959 gen9_hevc_mbenc_control_region *p_region = NULL;
3960 unsigned int slice, num_regions, height, num_slices, num_units_in_region;
3961 unsigned int frame_width_in_units, frame_height_in_units;
3962 unsigned short region_start_table[64];
3963 unsigned int offset_to_the_region_start[16];
3964 unsigned short temp_data[32][32];
3965 int is_arbitrary_slices = 0;
3966 int slice_start_y[I965_MAX_NUM_SLICE + 1];
3967 int max_height;
3968 int k = 0, i = 0;
3969
3970 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
3971 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
3972 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
3973
3974 memset(slice_start_y, 0, sizeof(int) * (I965_MAX_NUM_SLICE + 1));
3975 memset(region_start_table, 0, sizeof(region_start_table));
3976 memset(temp_data, 0, sizeof(temp_data));
3977 memset(offset_to_the_region_start, 0, sizeof(offset_to_the_region_start));
3978
3979 if (priv_state->num_regions_in_slice < 1)
3980 priv_state->num_regions_in_slice = 1;
3981
3982 if (priv_state->num_regions_in_slice > 16)
3983 priv_state->num_regions_in_slice = 16;
3984
3985 if (priv_state->walking_pattern_26) {
3986 frame_width_in_units = ALIGN(priv_state->picture_width, 16) / 16;
3987 frame_height_in_units = ALIGN(priv_state->picture_height, 16) / 16;
3988 } else {
3989 frame_width_in_units = ALIGN(priv_state->picture_width, 32) / 32;
3990 frame_height_in_units = ALIGN(priv_state->picture_height, 32) / 32;
3991 }
3992
3993 for (slice = 0; slice < encode_state->num_slice_params_ext; slice++) {
3994 slice_param = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[slice]->buffer;
3995 if (slice_param->slice_segment_address %
3996 ALIGN(priv_state->picture_width, 32)) {
3997 is_arbitrary_slices = 1;
3998 } else {
3999 slice_start_y[slice] = slice_param->slice_segment_address /
4000 ALIGN(priv_state->picture_width, 32);
4001
4002 if (priv_state->walking_pattern_26) {
4003 slice_start_y[slice] *= 2;
4004 }
4005 }
4006 }
4007
4008 slice_start_y[encode_state->num_slice_params_ext] = frame_height_in_units;
4009
4010 region_start_table[0] = 0;
4011 region_start_table[GEN9_HEVC_ENC_REGION_START_Y_OFFSET + 0] = 0;
4012 num_regions = 1;
4013
4014 if (is_arbitrary_slices) {
4015 height = frame_height_in_units;
4016 num_slices = 1;
4017 max_height = height;
4018 if (priv_state->num_regions_in_slice > 1) {
4019 num_units_in_region =
4020 (frame_width_in_units + 2 * (frame_height_in_units - 1) + priv_state->num_regions_in_slice - 1) / priv_state->num_regions_in_slice;
4021
4022 num_regions = priv_state->num_regions_in_slice;
4023
4024 for (i = 1; i < priv_state->num_regions_in_slice; i++) {
4025 unsigned int front = i * num_units_in_region;
4026
4027 if (front < frame_width_in_units)
4028 region_start_table[i] = (unsigned int)front;
4029 else if (((front - frame_width_in_units + 1) & 1) == 0)
4030 region_start_table[i] = (unsigned int)frame_width_in_units - 1;
4031 else
4032 region_start_table[i] = (unsigned int)frame_width_in_units - 2;
4033
4034 region_start_table[GEN9_HEVC_ENC_REGION_START_Y_OFFSET + i] = (unsigned int)((front - region_start_table[i]) >> 1);
4035 }
4036 }
4037 } else {
4038 int start_y;
4039 int slice_is_merged = 0;
4040
4041 max_height = 0;
4042 num_slices = encode_state->num_slice_params_ext;
4043
4044 for (slice = 0; slice < num_slices; slice++) {
4045 int sliceHeight = slice_start_y[slice + 1] - slice_start_y[slice];
4046
4047 if (sliceHeight > max_height)
4048 max_height = sliceHeight;
4049 }
4050
4051 while (!slice_is_merged) {
4052 int newNumSlices = 1;
4053
4054 start_y = 0;
4055
4056 for (slice = 1; slice < num_slices; slice++) {
4057 if ((slice_start_y[slice + 1] - start_y) <= max_height)
4058 slice_start_y[slice] = -1;
4059 else
4060 start_y = slice_start_y[slice];
4061 }
4062
4063 for (slice = 1; slice < num_slices; slice++) {
4064 if (slice_start_y[slice] > 0) {
4065 slice_start_y[newNumSlices] = slice_start_y[slice];
4066 newNumSlices++;
4067 }
4068 }
4069
4070 num_slices = newNumSlices;
4071 slice_start_y[num_slices] = frame_height_in_units;
4072
4073 if (num_slices * priv_state->num_regions_in_slice <= GEN9_HEVC_MEDIA_WALKER_MAX_COLORS)
4074 slice_is_merged = 1;
4075 else {
4076 int num = 1;
4077
4078 max_height = frame_height_in_units;
4079
4080 for (slice = 0; slice < num_slices - 1; slice++) {
4081 if ((slice_start_y[slice + 2] - slice_start_y[slice]) <= max_height) {
4082 max_height = slice_start_y[slice + 2] - slice_start_y[slice];
4083 num = slice + 1;
4084 }
4085 }
4086
4087 for (slice = num; slice < num_slices; slice++)
4088 slice_start_y[slice] = slice_start_y[slice + 1];
4089
4090 num_slices--;
4091 }
4092 }
4093
4094 num_units_in_region = (frame_width_in_units + 2 * (max_height - 1) + priv_state->num_regions_in_slice - 1) /
4095 priv_state->num_regions_in_slice;
4096 num_regions = num_slices * priv_state->num_regions_in_slice;
4097
4098 for (slice = 0; slice < num_slices; slice++) {
4099 region_start_table[slice * priv_state->num_regions_in_slice] = 0;
4100 region_start_table[GEN9_HEVC_ENC_REGION_START_Y_OFFSET + (slice * priv_state->num_regions_in_slice)] = (unsigned int)slice_start_y[slice];
4101
4102 for (i = 1; i < priv_state->num_regions_in_slice; i++) {
4103 int front = i * num_units_in_region;
4104
4105 if ((unsigned int)front < frame_width_in_units)
4106 region_start_table[slice * priv_state->num_regions_in_slice + i] = (unsigned int)front;
4107 else if (((front - frame_width_in_units + 1) & 1) == 0)
4108 region_start_table[slice * priv_state->num_regions_in_slice + i] = (unsigned int)frame_width_in_units - 1;
4109 else
4110 region_start_table[slice * priv_state->num_regions_in_slice + i] = (unsigned int)frame_width_in_units - 2;
4111
4112 region_start_table[GEN9_HEVC_ENC_REGION_START_Y_OFFSET + (slice * priv_state->num_regions_in_slice + i)] = (unsigned int)slice_start_y[slice] +
4113 ((front - region_start_table[i]) >> 1);
4114 }
4115 }
4116 height = max_height;
4117 }
4118
4119 for (k = 0; k < num_slices; k++) {
4120 int i;
4121 int nearest_reg = 0;
4122 int min_delta = priv_state->picture_height;
4123
4124 if (priv_state->walking_pattern_26) {
4125 int cur_lcu_pel_y = region_start_table[GEN9_HEVC_ENC_REGION_START_Y_OFFSET + (k * priv_state->num_regions_in_slice)] << 4;
4126 int ts_width = priv_state->picture_width >> 4;
4127 int ts_height = height;
4128 int offset_y = -((ts_width + 1) >> 1);
4129 int offset_delta = ((ts_width + ((ts_height - 1) << 1)) + (priv_state->num_regions_in_slice - 1)) / (priv_state->num_regions_in_slice);
4130
4131 for (i = 0; i < (int)num_regions; i++) {
4132 if (region_start_table[i] == 0) {
4133 int delta = cur_lcu_pel_y - (region_start_table[GEN9_HEVC_ENC_REGION_START_Y_OFFSET + i] << 4);
4134
4135 if (delta >= 0) {
4136 if (delta < min_delta) {
4137 min_delta = delta;
4138 nearest_reg = i;
4139 }
4140 }
4141 }
4142
4143 offset_to_the_region_start[k] = 2 * region_start_table[GEN9_HEVC_ENC_REGION_START_Y_OFFSET + nearest_reg];
4144 }
4145
4146 for (i = 0; i < priv_state->num_regions_in_slice; i++) {
4147 int tmp_y = region_start_table[GEN9_HEVC_ENC_REGION_START_Y_OFFSET + (nearest_reg + priv_state->num_regions_in_slice)];
4148
4149 temp_data[k * priv_state->num_regions_in_slice + i][0] = region_start_table[nearest_reg + i];
4150 temp_data[k * priv_state->num_regions_in_slice + i][1] = region_start_table[GEN9_HEVC_ENC_REGION_START_Y_OFFSET + (nearest_reg + i)];
4151 temp_data[k * priv_state->num_regions_in_slice + i][2] = region_start_table[GEN9_HEVC_ENC_REGION_START_Y_OFFSET + nearest_reg];
4152 temp_data[k * priv_state->num_regions_in_slice + i][3] = (unsigned int)((tmp_y != 0) ? tmp_y : (priv_state->picture_height) >> 4);
4153 temp_data[k * priv_state->num_regions_in_slice + i][4] = offset_to_the_region_start[k] & 0x0FFFF;
4154 temp_data[k * priv_state->num_regions_in_slice + i][5] = 0;
4155 temp_data[k * priv_state->num_regions_in_slice + i][6] = 0;
4156 temp_data[k * priv_state->num_regions_in_slice + i][7] = (unsigned int)(offset_y + region_start_table[GEN9_HEVC_ENC_REGION_START_Y_OFFSET + nearest_reg] + ((i * offset_delta) >> 1));
4157 }
4158 } else {
4159 int cur_lcu_pel_y = region_start_table[GEN9_HEVC_ENC_REGION_START_Y_OFFSET +
4160 (k * priv_state->num_regions_in_slice)] << 5;
4161 int ts_width = (priv_state->picture_width + 16) >> 5;
4162 int ts_height = height;
4163 int offset_y = -4 * ((ts_width + 1) >> 1);
4164 int offset_delta = ((ts_width + ((ts_height - 1) << 1)) + (priv_state->num_regions_in_slice - 1)) / (priv_state->num_regions_in_slice);
4165
4166 for (i = 0; i < (int)num_regions; i++) {
4167 if (region_start_table[i] == 0) {
4168 int delta = cur_lcu_pel_y - (region_start_table[GEN9_HEVC_ENC_REGION_START_Y_OFFSET + i] << 5);
4169
4170 if (delta >= 0) {
4171 if (delta < min_delta) {
4172 min_delta = delta;
4173 nearest_reg = i;
4174 }
4175 }
4176 }
4177
4178 offset_to_the_region_start[k] = 2 * region_start_table[GEN9_HEVC_ENC_REGION_START_Y_OFFSET + nearest_reg];
4179 }
4180
4181 for (i = 0; i < priv_state->num_regions_in_slice; i++) {
4182 int tmp_y = 2 * region_start_table[GEN9_HEVC_ENC_REGION_START_Y_OFFSET + (nearest_reg + priv_state->num_regions_in_slice)];
4183
4184 temp_data[k * priv_state->num_regions_in_slice + i][0] = region_start_table[nearest_reg + i];
4185 temp_data[k * priv_state->num_regions_in_slice + i][1] = 2 * region_start_table[GEN9_HEVC_ENC_REGION_START_Y_OFFSET + (nearest_reg + i)];
4186 temp_data[k * priv_state->num_regions_in_slice + i][2] = 2 * region_start_table[GEN9_HEVC_ENC_REGION_START_Y_OFFSET + nearest_reg];
4187 temp_data[k * priv_state->num_regions_in_slice + i][3] = (unsigned int)((tmp_y != 0) ? tmp_y : (priv_state->picture_height) >> 4);
4188 temp_data[k * priv_state->num_regions_in_slice + i][4] = offset_to_the_region_start[k] & 0x0FFFF;
4189 temp_data[k * priv_state->num_regions_in_slice + i][5] = 0;
4190 temp_data[k * priv_state->num_regions_in_slice + i][6] = 0;
4191 temp_data[k * priv_state->num_regions_in_slice + i][7] = (unsigned int)(offset_y + 4 * region_start_table[GEN9_HEVC_ENC_REGION_START_Y_OFFSET + nearest_reg] + (4 * ((i * offset_delta) >> 1)));
4192 }
4193 }
4194 }
4195
4196 if (priv_state->walking_pattern_26)
4197 gen9_hevc_init_object_walker_26(priv_state, gpe_context, ¶m->gpe_param,
4198 priv_state->num_regions_in_slice, max_height,
4199 priv_state->use_hw_scoreboard,
4200 priv_state->use_hw_non_stalling_scoreborad);
4201 else
4202 gen9_hevc_init_object_walker_26z(priv_state, gpe_context, ¶m->gpe_param,
4203 priv_state->num_regions_in_slice, max_height,
4204 priv_state->use_hw_scoreboard,
4205 priv_state->use_hw_non_stalling_scoreborad);
4206
4207 p_region = (gen9_hevc_mbenc_control_region *)i965_map_gpe_resource(&priv_ctx->res_con_corrent_thread_buffer);
4208 if (!p_region)
4209 return;
4210
4211 memset((void *)p_region, 0, sizeof(*p_region) * GEN9_HEVC_ENC_CONCURRENT_SURFACE_HEIGHT);
4212
4213 for (i = 0; i < 1024 ; i += 64)
4214 memcpy(((unsigned char *)p_region) + i, (unsigned char *)temp_data[i / 64], 32);
4215
4216 param->max_height_in_region = priv_state->walking_pattern_26 ? max_height : max_height * 2;;
4217 param->num_region = num_regions;
4218 param->num_units_in_region = (frame_width_in_units + 2 * (max_height - 1) + priv_state->num_regions_in_slice - 1) /
4219 priv_state->num_regions_in_slice;
4220
4221 i965_unmap_gpe_resource(&priv_ctx->res_con_corrent_thread_buffer);
4222 }
4223
4224 static const char hevc_qpc_table[22] = {
4225 29, 30, 31, 32, 32, 33, 34, 34, 35, 35, 36, 36, 37, 37, 37, 38, 38, 38, 39, 39, 39, 39
4226 };
4227
4228 static void
gen9_hevc_8x8_b_mbenc_set_curbe(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context,struct gen9_hevc_walking_pattern_parameter * param)4229 gen9_hevc_8x8_b_mbenc_set_curbe(VADriverContextP ctx,
4230 struct encode_state *encode_state,
4231 struct intel_encoder_context *encoder_context,
4232 struct i965_gpe_context *gpe_context,
4233 struct gen9_hevc_walking_pattern_parameter *param)
4234 {
4235 struct encoder_vme_mfc_context *vme_context = NULL;
4236 struct gen9_hevc_encoder_context *priv_ctx = NULL;
4237 struct generic_enc_codec_state *generic_state = NULL;
4238 struct gen9_hevc_encoder_state *priv_state = NULL;
4239 gen9_hevc_mbenc_b_mb_enc_curbe_data *cmd = NULL;
4240 VAEncSequenceParameterBufferHEVC *seq_param = NULL;
4241 VAEncPictureParameterBufferHEVC *pic_param = NULL;
4242 VAEncSliceParameterBufferHEVC *slice_param = NULL;
4243 unsigned int slice_qp = 0, slice_type = HEVC_SLICE_I;
4244 unsigned char mode_cost[12], mv_cost[8], mode_cost_sp;
4245 unsigned char forward_trans_thd[7];
4246 unsigned int simplest_intra_inter_threshold;
4247 int transform_8x8_mode_flag = 1;
4248 int qp_bd_offset_c, q_pi, qp_c;
4249 void *default_curbe_ptr = NULL;
4250 int default_curbe_size = 0;
4251 int max_sp_len = 57;
4252 int bti_idx = 0;
4253
4254 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
4255 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
4256 generic_state = (struct generic_enc_codec_state *)vme_context->generic_enc_state;
4257 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
4258 seq_param = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
4259 pic_param = (VAEncPictureParameterBufferHEVC *)encode_state->pic_param_ext->buffer;
4260 slice_param = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
4261
4262 slice_qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
4263 slice_type = priv_state->picture_coding_type;
4264
4265 if (priv_state->tu_mode == HEVC_TU_BEST_SPEED) {
4266 gen9_hevc_set_lambda_tables(priv_ctx, slice_type,
4267 HEVC_ENC_INTRA_TRANS_HAAR);
4268
4269 max_sp_len = 25;
4270 }
4271
4272 gen9_hevc_mbenc_set_costs(priv_ctx, slice_type, HEVC_ENC_INTRA_TRANS_REGULAR, slice_qp,
4273 mode_cost, mv_cost, &mode_cost_sp,
4274 &simplest_intra_inter_threshold);
4275
4276 gen9_hevc_set_forward_coeff_thd(forward_trans_thd, slice_qp);
4277
4278 gen9_hevc_get_b_mbenc_default_curbe(priv_state->tu_mode,
4279 slice_type, &default_curbe_ptr,
4280 &default_curbe_size);
4281
4282 cmd = i965_gpe_context_map_curbe(gpe_context);
4283 if (!cmd)
4284 return;
4285
4286 memcpy((void *)cmd, default_curbe_ptr, default_curbe_size);
4287
4288 cmd->dw0.adaptive_en = 1;
4289 cmd->dw0.t_8x8_flag_for_inter_en = transform_8x8_mode_flag;
4290 cmd->dw2.pic_width = priv_state->width_in_mb;
4291 cmd->dw2.len_sp = max_sp_len;
4292 cmd->dw3.src_access = 0;
4293 cmd->dw3.ref_access = 0;
4294 cmd->dw3.ft_enable = (HEVC_ENC_FTQ_BASED_SKIP[priv_state->tu_mode] >> 1) & 0x01;
4295 cmd->dw4.pic_height_minus1 = priv_state->height_in_mb - 1;
4296 cmd->dw4.hme_enable = !!generic_state->hme_enabled;
4297 cmd->dw4.slice_type = slice_type;
4298 cmd->dw4.use_actual_ref_qp_value = 0;
4299 cmd->dw6.frame_width = priv_state->width_in_mb * 16;
4300 cmd->dw6.frame_height = priv_state->height_in_mb * 16;
4301 cmd->dw7.intra_part_mask = 3;
4302 cmd->dw8.mode0_cost = mode_cost[0];
4303 cmd->dw8.mode1_cost = mode_cost[1];
4304 cmd->dw8.mode2_cost = mode_cost[2];
4305 cmd->dw8.mode3_cost = mode_cost[3];
4306 cmd->dw9.mode4_cost = mode_cost[4];
4307 cmd->dw9.mode5_cost = mode_cost[5];
4308 cmd->dw9.mode6_cost = mode_cost[6];
4309 cmd->dw9.mode7_cost = mode_cost[7];
4310 cmd->dw10.mode8_cost = mode_cost[8];
4311 cmd->dw10.mode9_cost = mode_cost[9];
4312 cmd->dw10.ref_id_cost = mode_cost[10];
4313 cmd->dw10.chroma_intra_mode_cost = mode_cost[11];
4314 cmd->dw11.mv0_cost = mv_cost[0];
4315 cmd->dw11.mv1_cost = mv_cost[1];
4316 cmd->dw11.mv2_cost = mv_cost[2];
4317 cmd->dw11.mv3_cost = mv_cost[3];
4318 cmd->dw12.mv4_cost = mv_cost[4];
4319 cmd->dw12.mv5_cost = mv_cost[5];
4320 cmd->dw12.mv6_cost = mv_cost[6];
4321 cmd->dw12.mv7_cost = mv_cost[7];
4322
4323 cmd->dw13.qp_prime_y = slice_qp;
4324 qp_bd_offset_c = 6 * priv_state->bit_depth_chroma_minus8;
4325 q_pi = CLAMP(-qp_bd_offset_c, 51, slice_qp + pic_param->pps_cb_qp_offset);
4326 qp_c = (q_pi < 30) ? q_pi : hevc_qpc_table[q_pi - 30];
4327 cmd->dw13.qp_prime_cb = qp_c;
4328 q_pi = CLAMP(-qp_bd_offset_c, 51, slice_qp + pic_param->pps_cr_qp_offset);
4329 qp_c = (q_pi < 30) ? q_pi : hevc_qpc_table[q_pi - 30];
4330 cmd->dw13.qp_prime_cr = qp_c;
4331
4332 cmd->dw14.sic_fwd_trans_coeff_thread_0 = forward_trans_thd[0];
4333 cmd->dw14.sic_fwd_trans_coeff_thread_1 = forward_trans_thd[1];
4334 cmd->dw14.sic_fwd_trans_coeff_thread_2 = forward_trans_thd[2];
4335 cmd->dw15.sic_fwd_trans_coeff_thread_3 = forward_trans_thd[3];
4336 cmd->dw15.sic_fwd_trans_coeff_thread_4 = forward_trans_thd[4];
4337 cmd->dw15.sic_fwd_trans_coeff_thread_5 = forward_trans_thd[5];
4338 cmd->dw15.sic_fwd_trans_coeff_thread_6 = forward_trans_thd[6];
4339 cmd->dw32.skip_val =
4340 HEVC_ENC_SKIPVAL_B[cmd->dw3.block_based_skip_enable][transform_8x8_mode_flag][slice_qp];
4341
4342 if (priv_state->picture_coding_type == HEVC_SLICE_I)
4343 *(float *)&cmd->dw34.lambda_me = 0.0;
4344 else
4345 *(float *)&cmd->dw34.lambda_me = (float)priv_ctx->lambda_me_table[slice_type][slice_qp];
4346
4347 cmd->dw35.mode_cost_sp = mode_cost_sp;
4348 cmd->dw35.simp_intra_inter_threashold = simplest_intra_inter_threshold;
4349 cmd->dw36.num_refidx_l0_minus_one = slice_param->num_ref_idx_l0_active_minus1;
4350 cmd->dw36.num_refidx_l1_minus_one = slice_param->num_ref_idx_l1_active_minus1;
4351 cmd->dw36.brc_enable = !!generic_state->brc_enabled;
4352 cmd->dw36.lcu_brc_enable = !!priv_state->lcu_brc_enabled;
4353 cmd->dw36.power_saving = priv_state->power_saving;
4354 cmd->dw36.roi_enable = (priv_state->num_roi > 0);
4355 cmd->dw36.fast_surveillance_flag = priv_state->picture_coding_type == HEVC_SLICE_I ?
4356 0 : priv_state->video_surveillance_flag;
4357
4358 if (priv_state->picture_coding_type != HEVC_SLICE_I) {
4359 cmd->dw37.actual_qp_refid0_list0 = gen9_hevc_get_qp_from_ref_list(ctx, slice_param, 0, 0);
4360 cmd->dw37.actual_qp_refid1_list0 = gen9_hevc_get_qp_from_ref_list(ctx, slice_param, 0, 1);
4361 cmd->dw37.actual_qp_refid2_list0 = gen9_hevc_get_qp_from_ref_list(ctx, slice_param, 0, 2);
4362 cmd->dw37.actual_qp_refid3_list0 = gen9_hevc_get_qp_from_ref_list(ctx, slice_param, 0, 3);
4363
4364 if (priv_state->picture_coding_type == HEVC_SLICE_B) {
4365 cmd->dw39.actual_qp_refid0_list1 = gen9_hevc_get_qp_from_ref_list(ctx, slice_param, 1, 0);
4366 cmd->dw39.actual_qp_refid1_list1 = gen9_hevc_get_qp_from_ref_list(ctx, slice_param, 1, 1);
4367 }
4368 }
4369
4370 cmd->dw44.max_vmvr = 511 * 4;
4371 cmd->dw44.max_num_merge_candidates = slice_param->max_num_merge_cand;
4372
4373 if (priv_state->picture_coding_type != HEVC_SLICE_I) {
4374 cmd->dw44.max_num_ref_list0 = cmd->dw36.num_refidx_l0_minus_one + 1;
4375 cmd->dw44.max_num_ref_list1 = cmd->dw36.num_refidx_l1_minus_one + 1;
4376 cmd->dw45.temporal_mvp_enable_flag = slice_param->slice_fields.bits.slice_temporal_mvp_enabled_flag;
4377 cmd->dw45.hme_combine_len_pslice = 8;
4378 if (priv_state->picture_coding_type == HEVC_SLICE_B)
4379 cmd->dw45.hme_combine_len_bslice = 8;
4380 }
4381
4382 cmd->dw45.log2_parallel_merge_level = pic_param->log2_parallel_merge_level_minus2 + 2;
4383 cmd->dw46.log2_min_tu_size = seq_param->log2_min_transform_block_size_minus2 + 2;
4384 cmd->dw46.log2_max_tu_size = cmd->dw46.log2_min_tu_size + seq_param->log2_diff_max_min_transform_block_size;
4385 cmd->dw46.log2_min_cu_size = seq_param->log2_min_luma_coding_block_size_minus3 + 3;
4386 cmd->dw46.log2_max_cu_size = cmd->dw46.log2_min_cu_size + seq_param->log2_diff_max_min_luma_coding_block_size;
4387 cmd->dw47.num_regions_in_slice = priv_state->num_regions_in_slice;
4388 cmd->dw47.type_of_walking_pattern = priv_state->walking_pattern_26;
4389 cmd->dw47.chroma_flatness_check_flag = (priv_state->tu_mode == HEVC_TU_BEST_SPEED) ? 0 : 1;
4390 cmd->dw47.enable_intra_early_exit = (priv_state->tu_mode == HEVC_TU_RT_SPEED);
4391 cmd->dw47.skip_intra_krn_flag = (priv_state->tu_mode == HEVC_TU_BEST_SPEED);
4392 cmd->dw47.collocated_from_l0_flag = slice_param->slice_fields.bits.collocated_from_l0_flag;
4393 cmd->dw47.is_low_delay = priv_state->low_delay;
4394 cmd->dw47.screen_content_flag = !!pic_param->pic_fields.bits.screen_content_flag;
4395 cmd->dw47.multi_slice_flag = (encode_state->num_slice_params_ext > 1);
4396 cmd->dw47.arbitary_slice_flag = priv_state->arbitrary_num_mb_in_slice;
4397 cmd->dw47.num_region_minus1 = param->num_region - 1;
4398
4399 if (priv_state->picture_coding_type != HEVC_SLICE_I) {
4400 cmd->dw48.current_td_l0_0 = gen9_hevc_get_poc_diff_from_ref_list(pic_param, slice_param, 0, 0);
4401 cmd->dw48.current_td_l0_1 = gen9_hevc_get_poc_diff_from_ref_list(pic_param, slice_param, 0, 1);
4402 cmd->dw49.current_td_l0_2 = gen9_hevc_get_poc_diff_from_ref_list(pic_param, slice_param, 0, 2);
4403 cmd->dw49.current_td_l0_3 = gen9_hevc_get_poc_diff_from_ref_list(pic_param, slice_param, 0, 3);
4404
4405 if (priv_state->picture_coding_type == HEVC_SLICE_B) {
4406 cmd->dw50.current_td_l1_0 = gen9_hevc_get_poc_diff_from_ref_list(pic_param, slice_param, 1, 0);
4407 cmd->dw50.current_td_l1_1 = gen9_hevc_get_poc_diff_from_ref_list(pic_param, slice_param, 1, 1);
4408 }
4409 }
4410
4411 cmd->dw52.num_of_units_in_region = param->num_units_in_region;
4412 cmd->dw52.max_height_in_region = param->max_height_in_region;
4413
4414 if (priv_state->rolling_intra_refresh) {
4415 cmd->dw35.widi_intra_refresh_en = 1;
4416 cmd->dw35.widi_first_intra_refresh = priv_state->widi_first_intra_refresh;
4417 cmd->dw35.half_update_mixed_lcu = 0;
4418 cmd->dw35.enable_rolling_intra = 1;
4419 cmd->dw38.widi_num_frame_in_gob = priv_state->widi_frame_num_in_gob;
4420 cmd->dw38.widi_num_intra_refresh_off_frames = priv_state->widi_frame_num_without_intra_refresh;
4421 cmd->dw51.widi_intra_refresh_qp_delta = priv_state->widi_intra_refresh_qp_delta;
4422 cmd->dw51.widi_intra_refresh_mb_num = priv_state->widi_intra_insertion_location;
4423 cmd->dw51.widi_intra_refresh_unit_in_mb = priv_state->widi_intra_insertion_size;
4424 cmd->dw53.widi_intra_refresh_ref_height = 40;
4425 cmd->dw53.widi_intra_refresh_ref_width = 48;
4426
4427 priv_state->widi_first_intra_refresh = 0;
4428 priv_state->widi_frame_num_without_intra_refresh = 0;
4429 } else if (priv_state->picture_coding_type != HEVC_SLICE_I)
4430 priv_state->widi_frame_num_without_intra_refresh++;
4431
4432 cmd->dw56.bti_cu_record = bti_idx++;
4433 cmd->dw57.bti_pak_cmd = bti_idx++;
4434 cmd->dw58.bti_src_y = bti_idx++;
4435 bti_idx++;
4436 cmd->dw59.bti_intra_dist = bti_idx++;
4437 cmd->dw60.bti_min_dist = bti_idx++;
4438 cmd->dw61.bti_hme_mv_pred_fwd_bwd_surf_index = bti_idx++;
4439 cmd->dw62.bti_hme_dist_surf_index = bti_idx++;
4440 cmd->dw63.bti_slice_map = bti_idx++;
4441 cmd->dw64.bti_vme_saved_uni_sic = bti_idx++;
4442 cmd->dw65.bti_simplest_intra = bti_idx++;
4443 cmd->dw66.bti_collocated_refframe = bti_idx++;
4444 cmd->dw67.bti_reserved = bti_idx++;
4445 cmd->dw68.bti_brc_input = bti_idx++;
4446 cmd->dw69.bti_lcu_qp = bti_idx++;
4447 cmd->dw70.bti_brc_data = bti_idx++;
4448 cmd->dw71.bti_vme_inter_prediction_surf_index = bti_idx++;
4449 bti_idx += 16;
4450
4451 if (priv_state->picture_coding_type == HEVC_SLICE_P) {
4452 cmd->dw72.bti_concurrent_thread_map = bti_idx++;
4453 cmd->dw73.bti_mb_data_cur_frame = bti_idx++;
4454 cmd->dw74.bti_mvp_cur_frame = bti_idx++;
4455 cmd->dw75.bti_debug = bti_idx++;
4456 } else {
4457 cmd->dw72.bti_vme_inter_prediction_b_surf_index = bti_idx++;
4458 bti_idx += 8;
4459
4460 cmd->dw73.bti_concurrent_thread_map = bti_idx++;
4461 cmd->dw74.bti_mb_data_cur_frame = bti_idx++;
4462 cmd->dw75.bti_mvp_cur_frame = bti_idx++;
4463 cmd->dw76.bti_debug = bti_idx++;
4464 }
4465
4466 i965_gpe_context_unmap_curbe(gpe_context);
4467 }
4468
4469 static void
gen9_hevc_8x8_b_mbenc_set_surfaces(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)4470 gen9_hevc_8x8_b_mbenc_set_surfaces(VADriverContextP ctx,
4471 struct encode_state *encode_state,
4472 struct intel_encoder_context *encoder_context,
4473 struct i965_gpe_context *gpe_context)
4474 {
4475 struct i965_driver_data *i965 = i965_driver_data(ctx);
4476 struct encoder_vme_mfc_context *vme_context = NULL;
4477 struct gen9_hevc_encoder_context *priv_ctx = NULL;
4478 struct gen9_hevc_encoder_state *priv_state = NULL;
4479 VAEncSliceParameterBufferHEVC *slice_param = NULL;
4480 VAEncPictureParameterBufferHEVC *pic_param = NULL;
4481 struct gen9_hevc_surface_priv *surface_priv = NULL;
4482 struct object_surface *obj_surface = NULL;
4483 dri_bo *collocated_mv_temporal_bo = NULL;
4484 int bti_idx = 0;
4485 int size = 0;
4486 int i = 0;
4487
4488 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
4489 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
4490 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
4491 pic_param = (VAEncPictureParameterBufferHEVC *)encode_state->pic_param_ext->buffer;
4492 slice_param = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
4493
4494 if (priv_state->picture_coding_type != HEVC_SLICE_I &&
4495 slice_param->slice_fields.bits.slice_temporal_mvp_enabled_flag &&
4496 slice_param->slice_fields.bits.collocated_from_l0_flag) {
4497 if (pic_param->collocated_ref_pic_index != 0xff &&
4498 pic_param->collocated_ref_pic_index < GEN9_MAX_REF_SURFACES) {
4499 VASurfaceID idx = VA_INVALID_SURFACE;
4500
4501 idx = pic_param->reference_frames[pic_param->collocated_ref_pic_index].picture_id;
4502 obj_surface = SURFACE(idx);
4503 if (obj_surface) {
4504 surface_priv = (struct gen9_hevc_surface_priv *)obj_surface->private_data;
4505 if (surface_priv)
4506 collocated_mv_temporal_bo = surface_priv->motion_vector_temporal_bo;
4507 }
4508 }
4509 }
4510
4511 size = priv_state->width_in_cu * priv_state->height_in_cu *
4512 priv_state->cu_record_size;
4513 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
4514 HEVC_ENC_SURFACE_CU_RECORD, bti_idx++,
4515 0, size, priv_state->mb_data_offset, NULL, NULL);
4516
4517 size = priv_state->mb_data_offset;
4518 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
4519 HEVC_ENC_SURFACE_HCP_PAK, bti_idx++,
4520 0, size, 0, NULL, NULL);
4521
4522 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
4523 HEVC_ENC_SURFACE_RAW_Y_UV, bti_idx++,
4524 1, 1, I965_SURFACEFORMAT_R8_UNORM,
4525 NULL, NULL);
4526 bti_idx++;
4527
4528 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
4529 HEVC_ENC_SURFACE_INTRA_DIST, bti_idx++,
4530 0, 0, 0, NULL, NULL);
4531
4532 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
4533 HEVC_ENC_SURFACE_MIN_DIST, bti_idx++,
4534 0, 1, I965_SURFACEFORMAT_R8_UNORM,
4535 NULL, NULL);
4536
4537 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
4538 HEVC_ENC_SURFACE_HME_MVP, bti_idx++,
4539 0, 1, I965_SURFACEFORMAT_R8_UNORM,
4540 NULL, NULL);
4541
4542 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
4543 HEVC_ENC_SURFACE_HME_DIST, bti_idx++,
4544 0, 1, I965_SURFACEFORMAT_R8_UNORM,
4545 NULL, NULL);
4546
4547 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
4548 HEVC_ENC_SURFACE_SLICE_MAP, bti_idx++,
4549 0, 1, I965_SURFACEFORMAT_R8_UNORM,
4550 NULL, NULL);
4551
4552 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
4553 HEVC_ENC_SURFACE_VME_UNI_SIC_DATA, bti_idx++,
4554 0, 0, 0, NULL, NULL);
4555
4556 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
4557 HEVC_ENC_SURFACE_SIMPLIFIED_INTRA, bti_idx++,
4558 0, 1, I965_SURFACEFORMAT_R8_UNORM,
4559 NULL, NULL);
4560
4561 if (collocated_mv_temporal_bo)
4562 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
4563 HEVC_ENC_SURFACE_COL_MB_MV, bti_idx++,
4564 0, 0, 0, NULL, collocated_mv_temporal_bo);
4565 else
4566 bti_idx++;
4567
4568 bti_idx++;
4569
4570 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
4571 HEVC_ENC_SURFACE_BRC_INPUT, bti_idx++,
4572 0, 0, 0, NULL, NULL);
4573
4574 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
4575 HEVC_ENC_SURFACE_LCU_QP, bti_idx++,
4576 0, 1, I965_SURFACEFORMAT_R8_UNORM,
4577 NULL, NULL);
4578
4579 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
4580 HEVC_ENC_SURFACE_BRC_DATA, bti_idx++,
4581 0, 1, I965_SURFACEFORMAT_R8_UNORM,
4582 NULL, NULL);
4583
4584 gen9_hevc_set_gpe_adv_surface(ctx, priv_ctx, gpe_context,
4585 HEVC_ENC_SURFACE_RAW_VME, bti_idx++,
4586 NULL);
4587
4588 for (i = 0; i < 8; i++) {
4589 if (i <= slice_param->num_ref_idx_l0_active_minus1)
4590 obj_surface = SURFACE(slice_param->ref_pic_list0[i].picture_id);
4591 else
4592 obj_surface = NULL;
4593
4594 if (obj_surface) {
4595 surface_priv = (struct gen9_hevc_surface_priv *)obj_surface->private_data;
4596
4597 gen9_hevc_set_gpe_adv_surface(ctx, priv_ctx, gpe_context,
4598 HEVC_ENC_SURFACE_REF_FRAME_VME, bti_idx++,
4599 surface_priv->surface_reff);
4600 } else
4601 bti_idx++;
4602
4603 if (i <= slice_param->num_ref_idx_l1_active_minus1)
4604 obj_surface = SURFACE(slice_param->ref_pic_list1[i].picture_id);
4605 else
4606 obj_surface = NULL;
4607
4608 if (obj_surface) {
4609 surface_priv = (struct gen9_hevc_surface_priv *)obj_surface->private_data;
4610
4611 gen9_hevc_set_gpe_adv_surface(ctx, priv_ctx, gpe_context,
4612 HEVC_ENC_SURFACE_REF_FRAME_VME, bti_idx++,
4613 surface_priv->surface_reff);
4614 } else
4615 bti_idx++;
4616 }
4617
4618 if (priv_state->picture_coding_type != HEVC_SLICE_P) {
4619 gen9_hevc_set_gpe_adv_surface(ctx, priv_ctx, gpe_context,
4620 HEVC_ENC_SURFACE_RAW_VME, bti_idx++,
4621 NULL);
4622
4623 for (i = 0; i < 4; i++) {
4624 if (i <= slice_param->num_ref_idx_l1_active_minus1)
4625 obj_surface = SURFACE(slice_param->ref_pic_list1[i].picture_id);
4626 else
4627 obj_surface = NULL;
4628
4629 if (obj_surface) {
4630 surface_priv = (struct gen9_hevc_surface_priv *)obj_surface->private_data;
4631
4632 gen9_hevc_set_gpe_adv_surface(ctx, priv_ctx, gpe_context,
4633 HEVC_ENC_SURFACE_REF_FRAME_VME, bti_idx++,
4634 surface_priv->surface_reff);
4635 } else
4636 bti_idx++;
4637
4638 bti_idx++;
4639 }
4640 }
4641
4642 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
4643 HEVC_ENC_SURFACE_CONCURRENT_THREAD, bti_idx++,
4644 0, 1, I965_SURFACEFORMAT_R8_UNORM,
4645 NULL, NULL);
4646
4647 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
4648 HEVC_ENC_SURFACE_MB_MV_INDEX, bti_idx++,
4649 0, 0, 0, NULL, NULL);
4650
4651 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
4652 HEVC_ENC_SURFACE_MVP_INDEX, bti_idx++,
4653 0, 0, 0, NULL, NULL);
4654
4655 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
4656 HEVC_ENC_SURFACE_KERNEL_DEBUG, bti_idx++,
4657 0, 0, 0, NULL, NULL);
4658 }
4659
4660 static void
gen9_hevc_8x8_b_mbenc(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)4661 gen9_hevc_8x8_b_mbenc(VADriverContextP ctx,
4662 struct encode_state *encode_state,
4663 struct intel_encoder_context *encoder_context)
4664 {
4665 struct encoder_vme_mfc_context *vme_context = NULL;
4666 struct gen9_hevc_encoder_context *priv_ctx = NULL;
4667 struct gen9_hevc_encoder_state *priv_state = NULL;
4668 struct gen9_hevc_walking_pattern_parameter param;
4669 struct i965_gpe_context *gpe_context = NULL;
4670 int media_state = HEVC_ENC_MEDIA_STATE_HEVC_B_MBENC;
4671 int gpe_idx = HEVC_MBENC_BENC_IDX;
4672
4673 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
4674 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
4675 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
4676
4677 if (priv_state->picture_coding_type == HEVC_SLICE_P)
4678 gpe_idx = priv_state->rolling_intra_refresh ? HEVC_MBENC_P_WIDI_IDX : HEVC_MBENC_PENC_IDX;
4679 else if (priv_state->picture_coding_type != HEVC_SLICE_I)
4680 gpe_idx = priv_state->rolling_intra_refresh ? HEVC_MBENC_MBENC_WIDI_IDX : HEVC_MBENC_BENC_IDX;
4681
4682 gpe_context = &priv_ctx->mbenc_context.gpe_contexts[gpe_idx];
4683
4684 gen8_gpe_context_init(ctx, gpe_context);
4685 gen9_gpe_reset_binding_table(ctx, gpe_context);
4686
4687 memset((void *)¶m, 0, sizeof(param));
4688 gen9_hevc_set_control_region(ctx, encode_state, encoder_context, gpe_context, ¶m);
4689
4690 gen9_hevc_8x8_b_mbenc_set_curbe(ctx, encode_state, encoder_context, gpe_context, ¶m);
4691 gen9_hevc_8x8_b_mbenc_set_surfaces(ctx, encode_state, encoder_context, gpe_context);
4692 gen8_gpe_setup_interface_data(ctx, gpe_context);
4693
4694 param.gpe_param.color_count_minus1 = param.num_region - 1;
4695 gen9_hevc_run_object_walker(ctx, encoder_context, gpe_context, ¶m.gpe_param,
4696 media_state);
4697 }
4698
4699 static void
gen9_hevc_8x8_pu_fmode_set_curbe(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)4700 gen9_hevc_8x8_pu_fmode_set_curbe(VADriverContextP ctx,
4701 struct encode_state *encode_state,
4702 struct intel_encoder_context *encoder_context,
4703 struct i965_gpe_context *gpe_context)
4704 {
4705 struct i965_driver_data *i965 = i965_driver_data(ctx);
4706 struct encoder_vme_mfc_context *vme_context = NULL;
4707 struct gen9_hevc_encoder_context *priv_ctx = NULL;
4708 struct generic_enc_codec_state *generic_state = NULL;
4709 struct gen9_hevc_encoder_state *priv_state = NULL;
4710 gen9_hevc_mbenc_8x8_pu_fmode_curbe_data *cmd = NULL;
4711 VAEncSequenceParameterBufferHEVC *seq_param = NULL;
4712 VAEncPictureParameterBufferHEVC *pic_param = NULL;
4713 VAEncSliceParameterBufferHEVC *slice_param = NULL;
4714 unsigned int slice_qp = 0;
4715 int bti_idx = 0;
4716
4717 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
4718 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
4719 generic_state = (struct generic_enc_codec_state *)vme_context->generic_enc_state;
4720 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
4721 seq_param = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
4722 pic_param = (VAEncPictureParameterBufferHEVC *)encode_state->pic_param_ext->buffer;
4723 slice_param = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
4724
4725 slice_qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
4726
4727 cmd = i965_gpe_context_map_curbe(gpe_context);
4728 if (!cmd)
4729 return;
4730
4731 memset((void *)cmd, 0, sizeof(*cmd));
4732
4733 cmd->dw0.frame_width = ALIGN(priv_state->picture_width, 16);
4734 cmd->dw0.frame_height = ALIGN(priv_state->picture_height, 16);
4735 cmd->dw1.slice_type = priv_state->picture_coding_type;
4736 cmd->dw1.pu_type = 2;
4737 cmd->dw1.pak_reording_flag = priv_state->picture_coding_type == HEVC_SLICE_I ? 1 : 0;
4738
4739 if (seq_param->log2_min_luma_coding_block_size_minus3 + 3 +
4740 seq_param->log2_diff_max_min_luma_coding_block_size == 6)
4741 cmd->dw1.lcu_type = 0;
4742 else
4743 cmd->dw1.lcu_type = 1;
4744
4745 cmd->dw1.screen_content_flag = !!pic_param->pic_fields.bits.screen_content_flag;
4746 cmd->dw1.enable_intra_early_exit = priv_state->tu_mode == HEVC_TU_RT_SPEED ?
4747 (priv_state->picture_coding_type == HEVC_SLICE_I ? 0 : 1) : 0;
4748 cmd->dw1.enable_debug_dump = 0;
4749 cmd->dw1.brc_enable = generic_state->brc_enabled;
4750 cmd->dw1.lcu_brc_enable = priv_state->lcu_brc_enabled;
4751 cmd->dw1.roi_enable = (priv_state->num_roi > 0);
4752 cmd->dw1.fast_surveillance_flag = priv_state->picture_coding_type == HEVC_SLICE_I ?
4753 0 : priv_state->video_surveillance_flag;
4754 cmd->dw1.enable_rolling_intra = priv_state->rolling_intra_refresh;
4755 cmd->dw1.widi_intra_refresh_en = priv_state->rolling_intra_refresh;
4756 cmd->dw1.half_update_mixed_lcu = 0;
4757 cmd->dw2.luma_lambda = priv_state->fixed_point_lambda_for_luma;
4758
4759 if (priv_state->picture_coding_type != HEVC_SLICE_I) {
4760 double lambda_md;
4761 float had_bias = 2.0f;
4762
4763 lambda_md = priv_ctx->lambda_md_table[cmd->dw1.slice_type][slice_qp];
4764 lambda_md = lambda_md * had_bias;
4765 cmd->dw3.lambda_for_dist_calculation = (unsigned int)(lambda_md * (1 << 10));
4766 }
4767
4768 cmd->dw4.mode_cost_for_8x8_pu_tu8 = 0;
4769 cmd->dw5.mode_cost_for_8x8_pu_tu4 = 0;
4770 cmd->dw6.satd_16x16_pu_threshold = MAX(200 * ((int)slice_qp - 12), 0);
4771 cmd->dw6.bias_factor_toward_8x8 = pic_param->pic_fields.bits.screen_content_flag ? 1024 : 1126 + 102;
4772 cmd->dw7.qp = slice_qp;
4773 cmd->dw7.qp_for_inter = 0;
4774 cmd->dw8.simplified_flag_for_inter = 0;
4775 cmd->dw8.kbl_control_flag = (IS_KBL(i965->intel.device_info) || IS_GLK(i965->intel.device_info));
4776 cmd->dw9.widi_intra_refresh_qp_delta = priv_state->widi_intra_refresh_qp_delta;
4777 cmd->dw9.widi_intra_refresh_mb_num = priv_state->widi_intra_insertion_location;
4778 cmd->dw9.widi_intra_refresh_unit_in_mb = priv_state->widi_intra_insertion_size;
4779
4780 cmd->dw16.bti_pak_object = bti_idx++;
4781 cmd->dw17.bti_vme_8x8_mode = bti_idx++;
4782 cmd->dw18.bti_intra_mode = bti_idx++;
4783 cmd->dw19.bti_pak_command = bti_idx++;
4784 cmd->dw20.bti_slice_map = bti_idx++;
4785 cmd->dw21.bti_intra_dist = bti_idx++;
4786 cmd->dw22.bti_brc_input = bti_idx++;
4787 cmd->dw23.bti_simplest_intra = bti_idx++;
4788 cmd->dw24.bti_lcu_qp_surface = bti_idx++;
4789 cmd->dw25.bti_brc_data = bti_idx++;
4790 cmd->dw26.bti_debug = bti_idx++;
4791
4792 i965_gpe_context_unmap_curbe(gpe_context);
4793 }
4794
4795 static void
gen9_hevc_8x8_pu_fmode_set_surfaces(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)4796 gen9_hevc_8x8_pu_fmode_set_surfaces(VADriverContextP ctx,
4797 struct encode_state *encode_state,
4798 struct intel_encoder_context *encoder_context,
4799 struct i965_gpe_context *gpe_context)
4800 {
4801 struct encoder_vme_mfc_context *vme_context = NULL;
4802 struct gen9_hevc_encoder_context *priv_ctx = NULL;
4803 struct gen9_hevc_encoder_state *priv_state = NULL;
4804 int bti_idx = 0;
4805 int size = 0;
4806
4807 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
4808 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
4809 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
4810
4811 size = priv_state->width_in_cu * priv_state->height_in_cu *
4812 priv_state->cu_record_size;
4813 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
4814 HEVC_ENC_SURFACE_CU_RECORD, bti_idx++,
4815 0, size, priv_state->mb_data_offset, NULL, NULL);
4816
4817 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
4818 HEVC_ENC_SURFACE_VME_8x8, bti_idx++,
4819 0, 0, 0, NULL, NULL);
4820
4821 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
4822 HEVC_ENC_SURFACE_INTRA_MODE, bti_idx++,
4823 0, 0, 0, NULL, NULL);
4824
4825 size = priv_state->mb_data_offset;
4826 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
4827 HEVC_ENC_SURFACE_HCP_PAK, bti_idx++,
4828 0, size, 0, NULL, NULL);
4829
4830 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
4831 HEVC_ENC_SURFACE_SLICE_MAP, bti_idx++,
4832 0, 1, I965_SURFACEFORMAT_R8_UNORM,
4833 NULL, NULL);
4834
4835 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
4836 HEVC_ENC_SURFACE_INTRA_DIST, bti_idx++,
4837 0, 0, 0, NULL, NULL);
4838
4839 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
4840 HEVC_ENC_SURFACE_BRC_INPUT, bti_idx++,
4841 0, 0, 0, NULL, NULL);
4842
4843 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
4844 HEVC_ENC_SURFACE_SIMPLIFIED_INTRA, bti_idx++,
4845 0, 1, I965_SURFACEFORMAT_R8_UNORM,
4846 NULL, NULL);
4847
4848 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
4849 HEVC_ENC_SURFACE_LCU_QP, bti_idx++,
4850 0, 1, I965_SURFACEFORMAT_R8_UNORM,
4851 NULL, NULL);
4852
4853 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
4854 HEVC_ENC_SURFACE_BRC_DATA, bti_idx++,
4855 0, 1, I965_SURFACEFORMAT_R8_UNORM,
4856 NULL, NULL);
4857
4858 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
4859 HEVC_ENC_SURFACE_KERNEL_DEBUG, bti_idx++,
4860 0, 0, 0, NULL, NULL);
4861 }
4862
4863 static void
gen9_hevc_8x8_pu_fmode(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)4864 gen9_hevc_8x8_pu_fmode(VADriverContextP ctx,
4865 struct encode_state *encode_state,
4866 struct intel_encoder_context *encoder_context)
4867 {
4868 struct encoder_vme_mfc_context *vme_context = NULL;
4869 struct gen9_hevc_encoder_context *priv_ctx = NULL;
4870 struct gen9_hevc_encoder_state *priv_state = NULL;
4871 struct gpe_media_object_walker_parameter param;
4872 struct hevc_enc_kernel_walker_parameter hevc_walker_param;
4873 struct i965_gpe_context *gpe_context = NULL;
4874 int media_state = HEVC_ENC_MEDIA_STATE_8x8_PU_FMODE;
4875
4876 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
4877 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
4878 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
4879
4880 gpe_context = &priv_ctx->mbenc_context.gpe_contexts[HEVC_MBENC_8x8FMODE_IDX];
4881
4882 gen8_gpe_context_init(ctx, gpe_context);
4883 gen9_gpe_reset_binding_table(ctx, gpe_context);
4884 gen9_hevc_8x8_pu_fmode_set_curbe(ctx, encode_state, encoder_context, gpe_context);
4885 gen9_hevc_8x8_pu_fmode_set_surfaces(ctx, encode_state, encoder_context, gpe_context);
4886 gen8_gpe_setup_interface_data(ctx, gpe_context);
4887
4888 memset((void *)&hevc_walker_param, 0, sizeof(hevc_walker_param));
4889 hevc_walker_param.resolution_x = priv_state->width_in_lcu;
4890 hevc_walker_param.resolution_y = priv_state->height_in_lcu;
4891 hevc_walker_param.no_dependency = 1;
4892 gen9_hevc_init_object_walker(&hevc_walker_param, ¶m);
4893 gen9_hevc_run_object_walker(ctx, encoder_context, gpe_context, ¶m,
4894 media_state);
4895 }
4896
4897 static void
gen9_hevc_8x8_pu_mode_set_curbe(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)4898 gen9_hevc_8x8_pu_mode_set_curbe(VADriverContextP ctx,
4899 struct encode_state *encode_state,
4900 struct intel_encoder_context *encoder_context,
4901 struct i965_gpe_context *gpe_context)
4902 {
4903 struct encoder_vme_mfc_context *vme_context = NULL;
4904 struct generic_enc_codec_state *generic_state = NULL;
4905 struct gen9_hevc_encoder_state *priv_state = NULL;
4906 gen9_hevc_mbenc_8x8_pu_curbe_data *cmd = NULL;
4907 VAEncSequenceParameterBufferHEVC *seq_param = NULL;
4908 VAEncPictureParameterBufferHEVC *pic_param = NULL;
4909 VAEncSliceParameterBufferHEVC *slice_param = NULL;
4910 int bti_idx = 0;
4911
4912 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
4913 generic_state = (struct generic_enc_codec_state *)vme_context->generic_enc_state;
4914 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
4915 seq_param = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
4916 pic_param = (VAEncPictureParameterBufferHEVC *)encode_state->pic_param_ext->buffer;
4917 slice_param = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
4918
4919 cmd = i965_gpe_context_map_curbe(gpe_context);
4920 if (!cmd)
4921 return;
4922
4923 memset((void *)cmd, 0, sizeof(*cmd));
4924
4925 cmd->dw0.frame_width = ALIGN(priv_state->picture_width, 16);
4926 cmd->dw0.frame_height = ALIGN(priv_state->picture_height, 16);
4927 cmd->dw1.slice_type = priv_state->picture_coding_type;
4928 cmd->dw1.pu_type = 2;
4929 cmd->dw1.dc_filter_flag = 1;
4930 cmd->dw1.angle_refine_flag = 1;
4931 if (seq_param->log2_min_luma_coding_block_size_minus3 + 3 +
4932 seq_param->log2_diff_max_min_luma_coding_block_size == 6)
4933 cmd->dw1.lcu_type = 0;
4934 else
4935 cmd->dw1.lcu_type = 1;
4936 cmd->dw1.screen_content_flag = !!pic_param->pic_fields.bits.screen_content_flag;
4937 cmd->dw1.enable_intra_early_exit = priv_state->tu_mode == HEVC_TU_RT_SPEED ?
4938 (priv_state->picture_coding_type == HEVC_SLICE_I ? 0 : 1) : 0;
4939 cmd->dw1.enable_debug_dump = 0;
4940 cmd->dw1.brc_enable = generic_state->brc_enabled;
4941 cmd->dw1.lcu_brc_enable = priv_state->lcu_brc_enabled;
4942 cmd->dw1.roi_enable = (priv_state->num_roi > 0);
4943 cmd->dw1.fast_surveillance_flag = priv_state->picture_coding_type == HEVC_SLICE_I ?
4944 0 : priv_state->video_surveillance_flag;
4945 if (priv_state->rolling_intra_refresh) {
4946 cmd->dw1.enable_rolling_intra = 1;
4947 cmd->dw1.widi_intra_refresh_en = 1;
4948 cmd->dw1.half_update_mixed_lcu = 0;
4949
4950 cmd->dw5.widi_intra_refresh_mb_num = priv_state->widi_intra_insertion_location;
4951 cmd->dw5.widi_intra_refresh_mb_num = priv_state->widi_intra_insertion_location;
4952 cmd->dw5.widi_intra_refresh_unit_in_mb = priv_state->widi_intra_insertion_size;
4953
4954 cmd->dw1.qp_value = pic_param->pic_init_qp + slice_param->slice_qp_delta;
4955 }
4956
4957 cmd->dw2.luma_lambda = priv_state->fixed_point_lambda_for_luma;
4958 cmd->dw3.chroma_lambda = priv_state->fixed_point_lambda_for_chroma;
4959 cmd->dw4.simplified_flag_for_inter = 0;
4960 cmd->dw4.harr_trans_form_flag = priv_state->picture_coding_type == HEVC_SLICE_I ? 0 : 1;
4961
4962 cmd->dw8.bti_src_y = bti_idx++;
4963 bti_idx++;
4964 cmd->dw9.bti_slice_map = bti_idx++;
4965 cmd->dw10.bti_vme_8x8_mode = bti_idx++;
4966 cmd->dw11.bti_intra_mode = bti_idx++;
4967 cmd->dw12.bti_brc_input = bti_idx++;
4968 cmd->dw13.bti_simplest_intra = bti_idx++;
4969 cmd->dw14.bti_lcu_qp_surface = bti_idx++;
4970 cmd->dw15.bti_brc_data = bti_idx++;
4971 cmd->dw16.bti_debug = bti_idx++;
4972
4973 i965_gpe_context_unmap_curbe(gpe_context);
4974 }
4975
4976 static void
gen9_hevc_8x8_pu_mode_set_surfaces(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)4977 gen9_hevc_8x8_pu_mode_set_surfaces(VADriverContextP ctx,
4978 struct encode_state *encode_state,
4979 struct intel_encoder_context *encoder_context,
4980 struct i965_gpe_context *gpe_context)
4981 {
4982 struct encoder_vme_mfc_context *vme_context = NULL;
4983 struct gen9_hevc_encoder_context *priv_ctx = NULL;
4984 int bti_idx = 0;
4985
4986 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
4987 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
4988
4989 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
4990 HEVC_ENC_SURFACE_RAW_Y_UV, bti_idx++,
4991 1, 1, I965_SURFACEFORMAT_R8_UNORM,
4992 NULL, NULL);
4993 bti_idx++;
4994
4995 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
4996 HEVC_ENC_SURFACE_SLICE_MAP, bti_idx++,
4997 0, 1, I965_SURFACEFORMAT_R8_UNORM,
4998 NULL, NULL);
4999
5000 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
5001 HEVC_ENC_SURFACE_VME_8x8, bti_idx++,
5002 0, 0, 0, NULL, NULL);
5003
5004 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
5005 HEVC_ENC_SURFACE_INTRA_MODE, bti_idx++,
5006 0, 0, 0, NULL, NULL);
5007
5008 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
5009 HEVC_ENC_SURFACE_BRC_INPUT, bti_idx++,
5010 0, 0, 0, NULL, NULL);
5011
5012 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
5013 HEVC_ENC_SURFACE_SIMPLIFIED_INTRA, bti_idx++,
5014 0, 1, I965_SURFACEFORMAT_R8_UNORM,
5015 NULL, NULL);
5016
5017 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
5018 HEVC_ENC_SURFACE_LCU_QP, bti_idx++,
5019 0, 1, I965_SURFACEFORMAT_R8_UNORM,
5020 NULL, NULL);
5021
5022 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
5023 HEVC_ENC_SURFACE_BRC_DATA, bti_idx++,
5024 0, 1, I965_SURFACEFORMAT_R8_UNORM,
5025 NULL, NULL);
5026
5027 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
5028 HEVC_ENC_SURFACE_KERNEL_DEBUG, bti_idx++,
5029 0, 0, 0, NULL, NULL);
5030 }
5031
5032 static void
gen9_hevc_8x8_pu_mode(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)5033 gen9_hevc_8x8_pu_mode(VADriverContextP ctx,
5034 struct encode_state *encode_state,
5035 struct intel_encoder_context *encoder_context)
5036 {
5037 struct encoder_vme_mfc_context *vme_context = NULL;
5038 struct gen9_hevc_encoder_context *priv_ctx = NULL;
5039 struct gen9_hevc_encoder_state *priv_state = NULL;
5040 struct gpe_media_object_walker_parameter param;
5041 struct hevc_enc_kernel_walker_parameter hevc_walker_param;
5042 struct i965_gpe_context *gpe_context = NULL;
5043 int media_state = HEVC_ENC_MEDIA_STATE_8x8_PU;
5044
5045 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
5046 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
5047 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
5048
5049 gpe_context = &priv_ctx->mbenc_context.gpe_contexts[HEVC_MBENC_8x8PU_IDX];
5050
5051 gen8_gpe_context_init(ctx, gpe_context);
5052 gen9_gpe_reset_binding_table(ctx, gpe_context);
5053 gen9_hevc_8x8_pu_mode_set_curbe(ctx, encode_state, encoder_context, gpe_context);
5054 gen9_hevc_8x8_pu_mode_set_surfaces(ctx, encode_state, encoder_context, gpe_context);
5055 gen8_gpe_setup_interface_data(ctx, gpe_context);
5056
5057 memset((void *)&hevc_walker_param, 0, sizeof(hevc_walker_param));
5058 hevc_walker_param.resolution_x = ALIGN(priv_state->picture_width, 16) >> 3;
5059 hevc_walker_param.resolution_y = ALIGN(priv_state->picture_height, 16) >> 3;
5060 hevc_walker_param.no_dependency = 1;
5061 gen9_hevc_init_object_walker(&hevc_walker_param, ¶m);
5062 gen9_hevc_run_object_walker(ctx, encoder_context, gpe_context, ¶m,
5063 media_state);
5064 }
5065
5066 static void
gen9_hevc_16x16_pu_mode_set_curbe(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)5067 gen9_hevc_16x16_pu_mode_set_curbe(VADriverContextP ctx,
5068 struct encode_state *encode_state,
5069 struct intel_encoder_context *encoder_context,
5070 struct i965_gpe_context *gpe_context)
5071 {
5072 struct encoder_vme_mfc_context *vme_context = NULL;
5073 struct gen9_hevc_encoder_context *priv_ctx = NULL;
5074 struct generic_enc_codec_state *generic_state = NULL;
5075 struct gen9_hevc_encoder_state *priv_state = NULL;
5076 gen9_hevc_enc_16x16_pu_curbe_data *cmd = NULL;
5077 VAEncSequenceParameterBufferHEVC *seq_param = NULL;
5078 VAEncPictureParameterBufferHEVC *pic_param = NULL;
5079 VAEncSliceParameterBufferHEVC *slice_param = NULL;
5080 double squred_lambda, qp_lambda, lambda_scaling_factor;
5081 unsigned int slice_qp = 0, slice_type = HEVC_SLICE_I;
5082 unsigned int new_point_lambda_for_luma;
5083 unsigned char mode_cost[12];
5084 int bti_idx = 0;
5085
5086 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
5087 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
5088 generic_state = (struct generic_enc_codec_state *)vme_context->generic_enc_state;
5089 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
5090 seq_param = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
5091 pic_param = (VAEncPictureParameterBufferHEVC *)encode_state->pic_param_ext->buffer;
5092 slice_param = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
5093
5094 slice_qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
5095 slice_type = priv_state->picture_coding_type;
5096
5097 lambda_scaling_factor = 0.46 + slice_qp - 22;
5098 if (lambda_scaling_factor < 0)
5099 lambda_scaling_factor = 0.46;
5100 else if (lambda_scaling_factor > 15)
5101 lambda_scaling_factor = 15;
5102
5103 squred_lambda = lambda_scaling_factor * pow(2.0, ((double)slice_qp - 12.0) / 6);
5104 priv_state->fixed_point_lambda_for_luma = (unsigned int)(squred_lambda * (1 << 10));
5105
5106 lambda_scaling_factor = 1.0;
5107 qp_lambda = priv_ctx->lambda_md_table[slice_type][slice_qp];
5108 squred_lambda = qp_lambda * qp_lambda;
5109 priv_state->fixed_point_lambda_for_chroma = (unsigned int)(lambda_scaling_factor * squred_lambda * (1 << 10));
5110
5111 qp_lambda = sqrt(0.57 * pow(2.0, ((double)slice_qp - 12.0) / 3));
5112 squred_lambda = qp_lambda * qp_lambda;
5113 new_point_lambda_for_luma = (unsigned int)(squred_lambda * (1 << 10));
5114
5115 gen9_hevc_mbenc_set_costs(priv_ctx, slice_type, HEVC_ENC_INTRA_TRANS_HAAR, slice_qp,
5116 mode_cost, NULL, NULL, NULL);
5117
5118 cmd = i965_gpe_context_map_curbe(gpe_context);
5119 if (!cmd)
5120 return;
5121
5122 memset((void *)cmd, 0, sizeof(*cmd));
5123
5124 cmd->dw0.frame_width = ALIGN(priv_state->picture_width, 16);
5125 cmd->dw0.frame_height = ALIGN(priv_state->picture_height, 16);
5126 cmd->dw1.log2_min_cu_size = seq_param->log2_min_luma_coding_block_size_minus3 + 3;
5127 cmd->dw1.log2_max_cu_size = cmd->dw1.log2_min_cu_size + seq_param->log2_diff_max_min_luma_coding_block_size;
5128 cmd->dw1.log2_min_tu_size = seq_param->log2_min_transform_block_size_minus2 + 2;
5129 cmd->dw1.slice_qp = slice_qp;
5130 cmd->dw2.fixed_point_lambda_pred_mode = priv_state->fixed_point_lambda_for_chroma;
5131 cmd->dw3.lambda_scaling_factor = 1;
5132 cmd->dw3.slice_type = slice_type;
5133 cmd->dw3.enable_intra_early_exit = priv_state->tu_mode == HEVC_TU_RT_SPEED ?
5134 (priv_state->picture_coding_type == HEVC_SLICE_I ? 0 : 1) : 0;
5135 cmd->dw3.brc_enable = !!generic_state->brc_enabled;
5136 cmd->dw3.lcu_brc_enable = !!priv_state->lcu_brc_enabled;
5137 cmd->dw3.roi_enable = (priv_state->num_roi > 0);
5138 cmd->dw3.fast_surveillance_flag = priv_state->picture_coding_type == HEVC_SLICE_I ?
5139 0 : priv_state->video_surveillance_flag;
5140 cmd->dw3.enable_rolling_intra = priv_state->rolling_intra_refresh;
5141 cmd->dw3.widi_intra_refresh_en = priv_state->rolling_intra_refresh;
5142 cmd->dw3.half_update_mixed_lcu = 0;
5143 cmd->dw4.penalty_for_intra_8x8_non_dc_pred_mode = 0;
5144 cmd->dw4.intra_compute_type = 1;
5145 cmd->dw4.avc_intra_8x8_mask = 0;
5146 cmd->dw4.intra_sad_adjust = 2;
5147 cmd->dw5.fixed_point_lambda_cu_mode_for_cost_calculation = new_point_lambda_for_luma;
5148 cmd->dw6.screen_content_flag = !!pic_param->pic_fields.bits.screen_content_flag;
5149 cmd->dw7.mode_cost_intra_non_pred = mode_cost[0];
5150 cmd->dw7.mode_cost_intra_16x16 = mode_cost[1];
5151 cmd->dw7.mode_cost_intra_8x8 = mode_cost[2];
5152 cmd->dw7.mode_cost_intra_4x4 = mode_cost[3];
5153 cmd->dw8.fixed_point_lambda_cu_mode_for_luma = priv_state->fixed_point_lambda_for_luma;
5154
5155 if (priv_state->rolling_intra_refresh) {
5156 cmd->dw9.widi_intra_refresh_mb_num = priv_state->widi_intra_insertion_location;
5157 cmd->dw9.widi_intra_refresh_mb_num = priv_state->widi_intra_insertion_location;
5158 cmd->dw9.widi_intra_refresh_unit_in_mb = priv_state->widi_intra_insertion_size;
5159 }
5160
5161 cmd->dw10.simplified_flag_for_inter = 0;
5162 cmd->dw10.haar_transform_mode = priv_state->picture_coding_type == HEVC_SLICE_I ? 0 : 1;
5163
5164 cmd->dw16.bti_src_y = bti_idx++;
5165 bti_idx++;
5166 cmd->dw17.bti_sad_16x16_pu = bti_idx++;
5167 cmd->dw18.bti_pak_object = bti_idx++;
5168 cmd->dw19.bti_sad_32x32_pu_mode = bti_idx++;
5169 cmd->dw20.bti_vme_mode_8x8 = bti_idx++;
5170 cmd->dw21.bti_slice_map = bti_idx++;
5171 cmd->dw22.bti_vme_src = bti_idx++;
5172 cmd->dw23.bti_brc_input = bti_idx++;
5173 cmd->dw24.bti_simplest_intra = bti_idx++;
5174 cmd->dw25.bti_lcu_qp_surface = bti_idx++;
5175 cmd->dw26.bti_brc_data = bti_idx++;
5176 cmd->dw27.bti_debug = bti_idx++;
5177
5178 i965_gpe_context_unmap_curbe(gpe_context);
5179 }
5180
5181 static void
gen9_hevc_16x16_pu_mode_set_surfaces(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)5182 gen9_hevc_16x16_pu_mode_set_surfaces(VADriverContextP ctx,
5183 struct encode_state *encode_state,
5184 struct intel_encoder_context *encoder_context,
5185 struct i965_gpe_context *gpe_context)
5186 {
5187 struct encoder_vme_mfc_context *vme_context = NULL;
5188 struct gen9_hevc_encoder_context *priv_ctx = NULL;
5189 struct gen9_hevc_encoder_state *priv_state = NULL;
5190 int bti_idx = 0;
5191 int size = 0;
5192
5193 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
5194 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
5195 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
5196
5197 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
5198 HEVC_ENC_SURFACE_RAW_Y_UV, bti_idx++,
5199 1, 1, I965_SURFACEFORMAT_R8_UNORM,
5200 NULL, NULL);
5201 bti_idx++;
5202
5203 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
5204 HEVC_ENC_SURFACE_16x16PU_SAD, bti_idx++,
5205 0, 0, 0, NULL, NULL);
5206
5207 size = priv_state->width_in_cu * priv_state->height_in_cu *
5208 priv_state->cu_record_size;
5209 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
5210 HEVC_ENC_SURFACE_CU_RECORD, bti_idx++,
5211 0, size, priv_state->mb_data_offset, NULL, NULL);
5212
5213 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
5214 HEVC_ENC_SURFACE_32x32_PU_OUTPUT, bti_idx++,
5215 0, 0, 0, NULL, NULL);
5216
5217 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
5218 HEVC_ENC_SURFACE_VME_8x8, bti_idx++,
5219 0, 0, 0, NULL, NULL);
5220
5221 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
5222 HEVC_ENC_SURFACE_SLICE_MAP, bti_idx++,
5223 0, 1, I965_SURFACEFORMAT_R8_UNORM,
5224 NULL, NULL);
5225
5226 gen9_hevc_set_gpe_adv_surface(ctx, priv_ctx, gpe_context,
5227 HEVC_ENC_SURFACE_RAW_VME, bti_idx++,
5228 NULL);
5229
5230 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
5231 HEVC_ENC_SURFACE_BRC_INPUT, bti_idx++,
5232 0, 0, 0, NULL, NULL);
5233
5234 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
5235 HEVC_ENC_SURFACE_SIMPLIFIED_INTRA, bti_idx++,
5236 0, 1, I965_SURFACEFORMAT_R8_UNORM,
5237 NULL, NULL);
5238
5239 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
5240 HEVC_ENC_SURFACE_LCU_QP, bti_idx++,
5241 0, 1, I965_SURFACEFORMAT_R8_UNORM,
5242 NULL, NULL);
5243
5244 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
5245 HEVC_ENC_SURFACE_BRC_DATA, bti_idx++,
5246 0, 1, I965_SURFACEFORMAT_R8_UNORM,
5247 NULL, NULL);
5248
5249 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
5250 HEVC_ENC_SURFACE_KERNEL_DEBUG, bti_idx++,
5251 0, 0, 0, NULL, NULL);
5252 }
5253
5254 static void
gen9_hevc_16x16_pu_mode(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)5255 gen9_hevc_16x16_pu_mode(VADriverContextP ctx,
5256 struct encode_state *encode_state,
5257 struct intel_encoder_context *encoder_context)
5258 {
5259 struct encoder_vme_mfc_context *vme_context = NULL;
5260 struct gen9_hevc_encoder_context *priv_ctx = NULL;
5261 struct gen9_hevc_encoder_state *priv_state = NULL;
5262 struct gpe_media_object_walker_parameter param;
5263 struct hevc_enc_kernel_walker_parameter hevc_walker_param;
5264 struct i965_gpe_context *gpe_context = NULL;
5265 int media_state = HEVC_ENC_MEDIA_STATE_16x16_PU_MODE_DECISION;
5266
5267 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
5268 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
5269 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
5270
5271 gpe_context = &priv_ctx->mbenc_context.gpe_contexts[HEVC_MBENC_16x16MD_IDX];
5272
5273 gen8_gpe_context_init(ctx, gpe_context);
5274 gen9_gpe_reset_binding_table(ctx, gpe_context);
5275 gen9_hevc_16x16_pu_mode_set_curbe(ctx, encode_state, encoder_context, gpe_context);
5276 gen9_hevc_16x16_pu_mode_set_surfaces(ctx, encode_state, encoder_context, gpe_context);
5277 gen8_gpe_setup_interface_data(ctx, gpe_context);
5278
5279 memset((void *)&hevc_walker_param, 0, sizeof(hevc_walker_param));
5280 hevc_walker_param.resolution_x = ALIGN(priv_state->picture_width, 32) >> 5;
5281 hevc_walker_param.resolution_y = ALIGN(priv_state->picture_height, 32) >> 5;
5282 hevc_walker_param.no_dependency = 1;
5283 gen9_hevc_init_object_walker(&hevc_walker_param, ¶m);
5284 gen9_hevc_run_object_walker(ctx, encoder_context, gpe_context, ¶m,
5285 media_state);
5286 }
5287
5288 static void
gen9_hevc_16x16_sad_pu_comp_set_curbe(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)5289 gen9_hevc_16x16_sad_pu_comp_set_curbe(VADriverContextP ctx,
5290 struct encode_state *encode_state,
5291 struct intel_encoder_context *encoder_context,
5292 struct i965_gpe_context *gpe_context)
5293 {
5294 struct encoder_vme_mfc_context *vme_context = NULL;
5295 struct gen9_hevc_encoder_state *priv_state = NULL;
5296 gen9_hevc_mbenc_16x16_sad_curbe_data *cmd = NULL;
5297 VAEncSequenceParameterBufferHEVC *seq_param = NULL;
5298 int bti_idx = 0;
5299
5300 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
5301 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
5302 seq_param = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
5303
5304 cmd = i965_gpe_context_map_curbe(gpe_context);
5305 if (!cmd)
5306 return;
5307
5308 memset((void *)cmd, 0, sizeof(*cmd));
5309
5310 cmd->dw0.frame_width = ALIGN(priv_state->picture_width, 16);
5311 cmd->dw0.frame_height = ALIGN(priv_state->picture_height, 16);
5312 cmd->dw1.log2_min_cu_size = seq_param->log2_min_luma_coding_block_size_minus3 + 3;
5313 cmd->dw1.log2_max_cu_size = cmd->dw1.log2_min_cu_size + seq_param->log2_diff_max_min_luma_coding_block_size;
5314 cmd->dw1.log2_min_tu_size = seq_param->log2_min_transform_block_size_minus2 + 2;
5315 cmd->dw1.enable_intra_early_exit = priv_state->tu_mode == HEVC_TU_RT_SPEED ?
5316 (priv_state->picture_coding_type == HEVC_SLICE_I ? 0 : 1) : 0;
5317 cmd->dw2.sim_flag_for_inter = 0;
5318 cmd->dw2.slice_type = priv_state->picture_coding_type;
5319 cmd->dw2.fast_surveillance_flag = priv_state->picture_coding_type == HEVC_SLICE_I ?
5320 0 : priv_state->video_surveillance_flag;
5321
5322 cmd->dw8.bti_src_y = bti_idx++;
5323 bti_idx++;
5324 cmd->dw9.bti_sad_16x16_pu_output = bti_idx++;
5325 cmd->dw10.bti_32x32_pu_mode_decision = bti_idx++;
5326 cmd->dw11.bti_slice_map = bti_idx++;
5327 cmd->dw12.bti_simplest_intra = bti_idx++;
5328 cmd->dw13.bti_debug = bti_idx++;
5329
5330 i965_gpe_context_unmap_curbe(gpe_context);
5331 }
5332
5333 static void
gen9_hevc_16x16_sad_pu_comp_set_surfaces(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)5334 gen9_hevc_16x16_sad_pu_comp_set_surfaces(VADriverContextP ctx,
5335 struct encode_state *encode_state,
5336 struct intel_encoder_context *encoder_context,
5337 struct i965_gpe_context *gpe_context)
5338 {
5339 struct encoder_vme_mfc_context *vme_context = NULL;
5340 struct gen9_hevc_encoder_context *priv_ctx = NULL;
5341 int bti_idx = 0;
5342
5343 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
5344 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
5345
5346 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
5347 HEVC_ENC_SURFACE_RAW_Y_UV, bti_idx++,
5348 1, 1, I965_SURFACEFORMAT_R8_UNORM,
5349 NULL, NULL);
5350 bti_idx++;
5351
5352 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
5353 HEVC_ENC_SURFACE_16x16PU_SAD, bti_idx++,
5354 0, 0, 0, NULL, NULL);
5355
5356 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
5357 HEVC_ENC_SURFACE_32x32_PU_OUTPUT, bti_idx++,
5358 0, 0, 0, NULL, NULL);
5359
5360 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
5361 HEVC_ENC_SURFACE_SLICE_MAP, bti_idx++,
5362 0, 1, I965_SURFACEFORMAT_R8_UNORM,
5363 NULL, NULL);
5364
5365 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
5366 HEVC_ENC_SURFACE_SIMPLIFIED_INTRA, bti_idx++,
5367 0, 1, I965_SURFACEFORMAT_R8_UNORM,
5368 NULL, NULL);
5369
5370 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
5371 HEVC_ENC_SURFACE_KERNEL_DEBUG, bti_idx++,
5372 0, 0, 0, NULL, NULL);
5373 }
5374
5375 static void
gen9_hevc_16x16_sad_pu_computation(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)5376 gen9_hevc_16x16_sad_pu_computation(VADriverContextP ctx,
5377 struct encode_state *encode_state,
5378 struct intel_encoder_context *encoder_context)
5379 {
5380 struct encoder_vme_mfc_context *vme_context = NULL;
5381 struct gen9_hevc_encoder_context *priv_ctx = NULL;
5382 struct gen9_hevc_encoder_state *priv_state = NULL;
5383 struct gpe_media_object_walker_parameter param;
5384 struct hevc_enc_kernel_walker_parameter hevc_walker_param;
5385 struct i965_gpe_context *gpe_context = NULL;
5386 int media_state = HEVC_ENC_MEDIA_STATE_16x16_PU_SAD;
5387
5388 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
5389 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
5390 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
5391
5392 gpe_context = &priv_ctx->mbenc_context.gpe_contexts[HEVC_MBENC_16x16SAD_IDX];
5393
5394 gen8_gpe_context_init(ctx, gpe_context);
5395 gen9_gpe_reset_binding_table(ctx, gpe_context);
5396 gen9_hevc_16x16_sad_pu_comp_set_curbe(ctx, encode_state, encoder_context, gpe_context);
5397 gen9_hevc_16x16_sad_pu_comp_set_surfaces(ctx, encode_state, encoder_context, gpe_context);
5398 gen8_gpe_setup_interface_data(ctx, gpe_context);
5399
5400 memset((void *)&hevc_walker_param, 0, sizeof(hevc_walker_param));
5401 hevc_walker_param.resolution_x = ALIGN(priv_state->picture_width, 16) >> 4;
5402 hevc_walker_param.resolution_y = ALIGN(priv_state->picture_height, 16) >> 4;
5403 hevc_walker_param.no_dependency = 1;
5404 gen9_hevc_init_object_walker(&hevc_walker_param, ¶m);
5405 gen9_hevc_run_object_walker(ctx, encoder_context, gpe_context, ¶m,
5406 media_state);
5407 }
5408
5409 static void
gen9_hevc_32x32_b_intra_set_curbe(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)5410 gen9_hevc_32x32_b_intra_set_curbe(VADriverContextP ctx,
5411 struct encode_state *encode_state,
5412 struct intel_encoder_context *encoder_context,
5413 struct i965_gpe_context *gpe_context)
5414 {
5415 struct encoder_vme_mfc_context *vme_context = NULL;
5416 struct generic_enc_codec_state *generic_state = NULL;
5417 struct gen9_hevc_encoder_state *priv_state = NULL;
5418 gen9_hevc_mbenc_b_32x32_pu_intra_curbe_data *cmd = NULL;
5419 VAEncSequenceParameterBufferHEVC *seq_param = NULL;
5420 int bti_idx = 0;
5421
5422 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
5423 generic_state = (struct generic_enc_codec_state *)vme_context->generic_enc_state;
5424 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
5425 seq_param = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
5426
5427 cmd = i965_gpe_context_map_curbe(gpe_context);
5428 if (!cmd)
5429 return;
5430
5431 memset((void *)cmd, 0, sizeof(*cmd));
5432
5433 cmd->dw0.frame_width = ALIGN(priv_state->picture_width, 16);
5434 cmd->dw0.frame_height = ALIGN(priv_state->picture_height, 16);
5435 cmd->dw1.enable_debug_dump = 0;
5436 cmd->dw1.enable_intra_early_exit = priv_state->tu_mode == HEVC_TU_RT_SPEED ? 1 : 0;
5437 cmd->dw1.flags = 0;
5438 cmd->dw1.log2_min_tu_size = seq_param->log2_min_transform_block_size_minus2 + 2;
5439 cmd->dw1.slice_type = priv_state->picture_coding_type;
5440 cmd->dw1.hme_enable = generic_state->hme_enabled;
5441 cmd->dw1.fast_surveillance_flag = priv_state->picture_coding_type == HEVC_SLICE_I ?
5442 0 : priv_state->video_surveillance_flag;
5443
5444 cmd->dw2.qp_multiplier = 100;
5445 cmd->dw2.qp_value = 0;
5446
5447 cmd->dw8.bti_per_32x32_pu_intra_checck = bti_idx++;
5448 cmd->dw9.bti_src_y = bti_idx++;
5449 bti_idx++;
5450 cmd->dw10.bti_src_y2x = bti_idx++;
5451 cmd->dw11.bti_slice_map = bti_idx++;
5452 cmd->dw12.bti_vme_y2x = bti_idx++;
5453 cmd->dw13.bti_simplest_intra = bti_idx++;
5454 cmd->dw14.bti_hme_mv_pred = bti_idx++;
5455 cmd->dw15.bti_hme_dist = bti_idx++;
5456 cmd->dw16.bti_lcu_skip = bti_idx++;
5457 cmd->dw17.bti_debug = bti_idx++;
5458
5459 i965_gpe_context_unmap_curbe(gpe_context);
5460 }
5461
5462 static void
gen9_hevc_32x32_b_intra_set_surfaces(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)5463 gen9_hevc_32x32_b_intra_set_surfaces(VADriverContextP ctx,
5464 struct encode_state *encode_state,
5465 struct intel_encoder_context *encoder_context,
5466 struct i965_gpe_context *gpe_context)
5467 {
5468 struct encoder_vme_mfc_context *vme_context = NULL;
5469 struct gen9_hevc_encoder_context *priv_ctx = NULL;
5470 int bti_idx = 0;
5471
5472 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
5473 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
5474
5475 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
5476 HEVC_ENC_SURFACE_32x32_PU_OUTPUT, bti_idx++,
5477 0, 0, 0, NULL, NULL);
5478
5479 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
5480 HEVC_ENC_SURFACE_RAW_Y_UV, bti_idx++,
5481 1, 1, I965_SURFACEFORMAT_R8_UNORM,
5482 NULL, NULL);
5483 bti_idx++;
5484
5485 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
5486 HEVC_ENC_SURFACE_Y_2X, bti_idx++,
5487 0, 1, I965_SURFACEFORMAT_R8_UNORM,
5488 NULL, NULL);
5489
5490 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
5491 HEVC_ENC_SURFACE_SLICE_MAP, bti_idx++,
5492 0, 1, I965_SURFACEFORMAT_R8_UNORM,
5493 NULL, NULL);
5494
5495 gen9_hevc_set_gpe_adv_surface(ctx, priv_ctx, gpe_context,
5496 HEVC_ENC_SURFACE_Y_2X_VME, bti_idx++,
5497 NULL);
5498
5499 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
5500 HEVC_ENC_SURFACE_SIMPLIFIED_INTRA, bti_idx++,
5501 0, 1, I965_SURFACEFORMAT_R8_UNORM,
5502 NULL, NULL);
5503
5504 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
5505 HEVC_ENC_SURFACE_HME_MVP, bti_idx++,
5506 0, 1, I965_SURFACEFORMAT_R8_UNORM,
5507 NULL, NULL);
5508
5509 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
5510 HEVC_ENC_SURFACE_HME_DIST, bti_idx++,
5511 0, 1, I965_SURFACEFORMAT_R8_UNORM,
5512 NULL, NULL);
5513
5514 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
5515 HEVC_ENC_SURFACE_LCU_QP, bti_idx++,
5516 0, 1, I965_SURFACEFORMAT_R8_UNORM,
5517 NULL, NULL);
5518
5519 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
5520 HEVC_ENC_SURFACE_KERNEL_DEBUG, bti_idx,
5521 0, 0, 0, NULL, NULL);
5522 }
5523
5524 static void
gen9_hevc_32x32_b_intra(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)5525 gen9_hevc_32x32_b_intra(VADriverContextP ctx,
5526 struct encode_state *encode_state,
5527 struct intel_encoder_context *encoder_context)
5528 {
5529 struct encoder_vme_mfc_context *vme_context = NULL;
5530 struct gen9_hevc_encoder_context *priv_ctx = NULL;
5531 struct gen9_hevc_encoder_state *priv_state = NULL;
5532 struct gpe_media_object_walker_parameter param;
5533 struct hevc_enc_kernel_walker_parameter hevc_walker_param;
5534 struct i965_gpe_context *gpe_context = NULL;
5535 int media_state = HEVC_ENC_MEDIA_STATE_32x32_B_INTRA_CHECK;
5536
5537 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
5538 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
5539 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
5540
5541 gpe_context = &priv_ctx->mbenc_context.gpe_contexts[HEVC_MBENC_32x32INTRACHECK_IDX];
5542
5543 gen8_gpe_context_init(ctx, gpe_context);
5544 gen9_gpe_reset_binding_table(ctx, gpe_context);
5545 gen9_hevc_32x32_b_intra_set_curbe(ctx, encode_state, encoder_context, gpe_context);
5546 gen9_hevc_32x32_b_intra_set_surfaces(ctx, encode_state, encoder_context, gpe_context);
5547 gen8_gpe_setup_interface_data(ctx, gpe_context);
5548
5549 memset((void *)&hevc_walker_param, 0, sizeof(hevc_walker_param));
5550 hevc_walker_param.resolution_x = ALIGN(priv_state->picture_width, 32) >> 5;
5551 hevc_walker_param.resolution_y = ALIGN(priv_state->picture_height, 32) >> 5;
5552 hevc_walker_param.no_dependency = 1;
5553 gen9_hevc_init_object_walker(&hevc_walker_param, ¶m);
5554 gen9_hevc_run_object_walker(ctx, encoder_context, gpe_context, ¶m,
5555 media_state);
5556 }
5557
5558 static void
gen9_hevc_32x32_pu_mode_set_curbe(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)5559 gen9_hevc_32x32_pu_mode_set_curbe(VADriverContextP ctx,
5560 struct encode_state *encode_state,
5561 struct intel_encoder_context *encoder_context,
5562 struct i965_gpe_context *gpe_context)
5563 {
5564 struct encoder_vme_mfc_context *vme_context = NULL;
5565 struct gen9_hevc_encoder_context *priv_ctx = NULL;
5566 struct generic_enc_codec_state *generic_state = NULL;
5567 struct gen9_hevc_encoder_state *priv_state = NULL;
5568 VAEncPictureParameterBufferHEVC *pic_param = NULL;
5569 VAEncSliceParameterBufferHEVC *slice_param = NULL;
5570 gen9_hevc_mbenc_32x32_pu_mode_curbe_data *cmd = NULL;
5571 double lambda_scaling_factor = 1.0, qp_lambda = 0.0, squared_qp_lambda = 0.0;
5572 unsigned int slice_qp = 0, fixed_point_lambda = 0;
5573 int bti_idx = 0;
5574
5575 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
5576 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
5577 generic_state = (struct generic_enc_codec_state *)vme_context->generic_enc_state;
5578 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
5579 pic_param = (VAEncPictureParameterBufferHEVC *)encode_state->pic_param_ext->buffer;
5580 slice_param = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
5581
5582 slice_qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
5583 gen9_hevc_set_lambda_tables(priv_ctx, HEVC_SLICE_I, HEVC_ENC_INTRA_TRANS_HAAR);
5584 lambda_scaling_factor = 1.0;
5585 qp_lambda = priv_ctx->lambda_md_table[HEVC_SLICE_I][slice_qp];
5586 squared_qp_lambda = qp_lambda * qp_lambda;
5587 fixed_point_lambda = (unsigned int)(lambda_scaling_factor * squared_qp_lambda * (1 << 10));
5588
5589 cmd = i965_gpe_context_map_curbe(gpe_context);
5590 if (!cmd)
5591 return;
5592
5593 memset((void *)cmd, 0, sizeof(*cmd));
5594
5595 cmd->dw0.frame_width = ALIGN(priv_state->picture_width, 16);
5596 cmd->dw0.frame_height = ALIGN(priv_state->picture_height, 16);
5597 cmd->dw1.enable_debug_dump = 0;
5598 cmd->dw1.lcu_type = priv_state->lcu_size == 64 ? 0 : 1;
5599 cmd->dw1.pu_type = 0;
5600 cmd->dw1.brc_enable = !!generic_state->brc_enabled;
5601 cmd->dw1.lcu_brc_enable = priv_state->lcu_brc_enabled;
5602 cmd->dw1.slice_type = priv_state->picture_coding_type;
5603 cmd->dw1.fast_surveillance_flag = priv_state->picture_coding_type == HEVC_SLICE_I ?
5604 0 : priv_state->video_surveillance_flag;
5605 cmd->dw1.roi_enable = (priv_state->num_roi > 0);
5606
5607 cmd->dw2.lambda = fixed_point_lambda;
5608 cmd->dw3.mode_cost_32x32 = 0;
5609 cmd->dw4.early_exit = (unsigned int) - 1;
5610
5611 cmd->dw8.bti_32x32_pu_output = bti_idx++;
5612 cmd->dw9.bti_src_y = bti_idx++;
5613 bti_idx++;
5614 cmd->dw10.bti_src_y2x = bti_idx++;
5615 cmd->dw11.bti_slice_map = bti_idx++;
5616 cmd->dw12.bti_src_y2x_vme = bti_idx++;
5617 cmd->dw13.bti_brc_input = bti_idx++;
5618 cmd->dw14.bti_lcu_qp_surface = bti_idx++;
5619 cmd->dw15.bti_brc_data = bti_idx++;
5620 cmd->dw16.bti_kernel_debug = bti_idx++;
5621
5622 i965_gpe_context_unmap_curbe(gpe_context);
5623 }
5624
5625 static void
gen9_hevc_32x32_pu_mode_set_surfaces(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)5626 gen9_hevc_32x32_pu_mode_set_surfaces(VADriverContextP ctx,
5627 struct encode_state *encode_state,
5628 struct intel_encoder_context *encoder_context,
5629 struct i965_gpe_context *gpe_context)
5630 {
5631 struct encoder_vme_mfc_context *vme_context = NULL;
5632 struct gen9_hevc_encoder_context *priv_ctx = NULL;
5633 int bti_idx = 0;
5634
5635 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
5636 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
5637
5638 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
5639 HEVC_ENC_SURFACE_32x32_PU_OUTPUT, bti_idx++,
5640 0, 0, 0, NULL, NULL);
5641
5642 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
5643 HEVC_ENC_SURFACE_RAW_Y, bti_idx++,
5644 1, 1, I965_SURFACEFORMAT_R8_UNORM,
5645 NULL, NULL);
5646 bti_idx++;
5647
5648 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
5649 HEVC_ENC_SURFACE_Y_2X, bti_idx++,
5650 0, 1, I965_SURFACEFORMAT_R8_UNORM,
5651 NULL, NULL);
5652
5653 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
5654 HEVC_ENC_SURFACE_SLICE_MAP, bti_idx++,
5655 0, 1, I965_SURFACEFORMAT_R8_UNORM,
5656 NULL, NULL);
5657
5658 gen9_hevc_set_gpe_adv_surface(ctx, priv_ctx, gpe_context,
5659 HEVC_ENC_SURFACE_Y_2X_VME, bti_idx++,
5660 NULL);
5661
5662 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
5663 HEVC_ENC_SURFACE_BRC_INPUT, bti_idx++,
5664 0, 0, 0, NULL, NULL);
5665
5666 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
5667 HEVC_ENC_SURFACE_LCU_QP, bti_idx++,
5668 0, 1, I965_SURFACEFORMAT_R8_UNORM,
5669 NULL, NULL);
5670
5671 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
5672 HEVC_ENC_SURFACE_BRC_DATA, bti_idx++,
5673 0, 1, I965_SURFACEFORMAT_R8_UNORM,
5674 NULL, NULL);
5675
5676 gen9_hevc_set_gpe_1d_surface(ctx, priv_ctx, gpe_context,
5677 HEVC_ENC_SURFACE_KERNEL_DEBUG, bti_idx,
5678 0, 0, 0, NULL, NULL);
5679 }
5680
5681 static void
gen9_hevc_32x32_pu_mode(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)5682 gen9_hevc_32x32_pu_mode(VADriverContextP ctx,
5683 struct encode_state *encode_state,
5684 struct intel_encoder_context *encoder_context)
5685 {
5686 struct encoder_vme_mfc_context *vme_context = NULL;
5687 struct gen9_hevc_encoder_context *priv_ctx = NULL;
5688 struct gen9_hevc_encoder_state *priv_state = NULL;
5689 struct gpe_media_object_walker_parameter param;
5690 struct hevc_enc_kernel_walker_parameter hevc_walker_param;
5691 struct i965_gpe_context *gpe_context = NULL;
5692 int media_state = HEVC_ENC_MEDIA_STATE_32x32_PU_MODE_DECISION;
5693
5694 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
5695 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
5696 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
5697
5698 gpe_context = &priv_ctx->mbenc_context.gpe_contexts[HEVC_MBENC_32x32MD_IDX];
5699
5700 gen8_gpe_context_init(ctx, gpe_context);
5701 gen9_gpe_reset_binding_table(ctx, gpe_context);
5702 gen9_hevc_32x32_pu_mode_set_curbe(ctx, encode_state, encoder_context, gpe_context);
5703 gen9_hevc_32x32_pu_mode_set_surfaces(ctx, encode_state, encoder_context, gpe_context);
5704 gen8_gpe_setup_interface_data(ctx, gpe_context);
5705
5706 memset((void *)&hevc_walker_param, 0, sizeof(hevc_walker_param));
5707 hevc_walker_param.resolution_x = ALIGN(priv_state->picture_width, 32) >> 5;
5708 hevc_walker_param.resolution_y = ALIGN(priv_state->picture_height, 32) >> 5;
5709 hevc_walker_param.no_dependency = 1;
5710 gen9_hevc_init_object_walker(&hevc_walker_param, ¶m);
5711 gen9_hevc_run_object_walker(ctx, encoder_context, gpe_context, ¶m,
5712 media_state);
5713 }
5714
5715 static void
gen9_hevc_2x_scaling_set_curbe(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)5716 gen9_hevc_2x_scaling_set_curbe(VADriverContextP ctx,
5717 struct encode_state *encode_state,
5718 struct intel_encoder_context *encoder_context,
5719 struct i965_gpe_context *gpe_context)
5720 {
5721 struct encoder_vme_mfc_context *vme_context = NULL;
5722 struct gen9_hevc_encoder_state *priv_state = NULL;
5723 gen9_hevc_mbenc_downscaling2x_curbe_data *cmd = NULL;
5724 int bti_idx = 0;
5725
5726 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
5727 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
5728
5729 cmd = i965_gpe_context_map_curbe(gpe_context);
5730 if (!cmd)
5731 return;
5732
5733 memset((void *)cmd, 0, sizeof(gen9_hevc_mbenc_downscaling2x_curbe_data));
5734
5735 cmd->dw0.pic_width = ALIGN(priv_state->picture_width, 16);
5736 cmd->dw0.pic_height = ALIGN(priv_state->picture_height, 16);
5737
5738 cmd->dw8.bti_src_y = bti_idx++;
5739 cmd->dw9.bit_dst_y = bti_idx;
5740
5741 i965_gpe_context_unmap_curbe(gpe_context);
5742 }
5743
5744 static void
gen9_hevc_2x_scaling_set_surfaces(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct i965_gpe_context * gpe_context)5745 gen9_hevc_2x_scaling_set_surfaces(VADriverContextP ctx,
5746 struct encode_state *encode_state,
5747 struct intel_encoder_context *encoder_context,
5748 struct i965_gpe_context *gpe_context)
5749 {
5750 struct encoder_vme_mfc_context *vme_context = NULL;
5751 struct gen9_hevc_encoder_context *priv_ctx = NULL;
5752 int bti_idx = 0;
5753
5754 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
5755 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
5756
5757 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
5758 HEVC_ENC_SURFACE_RAW_Y, bti_idx++,
5759 0, 1, I965_SURFACEFORMAT_R16_UNORM,
5760 NULL, NULL);
5761
5762 gen9_hevc_set_gpe_2d_surface(ctx, priv_ctx, gpe_context,
5763 HEVC_ENC_SURFACE_Y_2X, bti_idx,
5764 0, 1, I965_SURFACEFORMAT_R16_UNORM,
5765 NULL, NULL);
5766 }
5767
5768 static void
gen9_hevc_2x_scaling(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)5769 gen9_hevc_2x_scaling(VADriverContextP ctx,
5770 struct encode_state *encode_state,
5771 struct intel_encoder_context *encoder_context)
5772 {
5773 struct encoder_vme_mfc_context *vme_context = NULL;
5774 struct gen9_hevc_encoder_context *priv_ctx = NULL;
5775 struct gen9_hevc_encoder_state *priv_state = NULL;
5776 struct gpe_media_object_walker_parameter param;
5777 struct hevc_enc_kernel_walker_parameter hevc_walker_param;
5778 struct i965_gpe_context *gpe_context = NULL;
5779 int media_state = HEVC_ENC_MEDIA_STATE_2X_SCALING;
5780
5781 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
5782 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
5783 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
5784
5785 gpe_context = &priv_ctx->mbenc_context.gpe_contexts[HEVC_MBENC_2xSCALING_IDX];
5786
5787 gen8_gpe_context_init(ctx, gpe_context);
5788 gen9_gpe_reset_binding_table(ctx, gpe_context);
5789 gen9_hevc_2x_scaling_set_curbe(ctx, encode_state, encoder_context, gpe_context);
5790 gen9_hevc_2x_scaling_set_surfaces(ctx, encode_state, encoder_context, gpe_context);
5791 gen8_gpe_setup_interface_data(ctx, gpe_context);
5792
5793 memset((void *)&hevc_walker_param, 0, sizeof(hevc_walker_param));
5794 hevc_walker_param.resolution_x = ALIGN(priv_state->picture_width, 32) >> 5;
5795 hevc_walker_param.resolution_y = ALIGN(priv_state->picture_height, 32) >> 5;
5796 hevc_walker_param.no_dependency = 1;
5797 gen9_hevc_init_object_walker(&hevc_walker_param, ¶m);
5798
5799 gen9_hevc_run_object_walker(ctx, encoder_context, gpe_context, ¶m,
5800 media_state);
5801 }
5802
5803 static void
gen9_hevc_mbenc(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)5804 gen9_hevc_mbenc(VADriverContextP ctx,
5805 struct encode_state *encode_state,
5806 struct intel_encoder_context *encoder_context)
5807 {
5808 struct encoder_vme_mfc_context *vme_context = NULL;
5809 struct gen9_hevc_encoder_state *priv_state = NULL;
5810 int fast_encoding = 0;
5811
5812 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
5813 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
5814 fast_encoding = (priv_state->tu_mode == HEVC_TU_BEST_SPEED);
5815
5816 if (!fast_encoding) {
5817 if (!priv_state->bit_depth_luma_minus8)
5818 gen9_hevc_2x_scaling(ctx, encode_state, encoder_context);
5819
5820 if (priv_state->picture_coding_type == HEVC_SLICE_I)
5821 gen9_hevc_32x32_pu_mode(ctx, encode_state, encoder_context);
5822 else
5823 gen9_hevc_32x32_b_intra(ctx, encode_state, encoder_context);
5824
5825 gen9_hevc_16x16_sad_pu_computation(ctx, encode_state, encoder_context);
5826 gen9_hevc_16x16_pu_mode(ctx, encode_state, encoder_context);
5827 gen9_hevc_8x8_pu_mode(ctx, encode_state, encoder_context);
5828 gen9_hevc_8x8_pu_fmode(ctx, encode_state, encoder_context);
5829 }
5830
5831 if (priv_state->picture_coding_type != HEVC_SLICE_I ||
5832 fast_encoding) {
5833 gen9_hevc_8x8_b_mbenc(ctx, encode_state, encoder_context);
5834 gen9_hevc_8x8_b_pak(ctx, encode_state, encoder_context);
5835 }
5836 }
5837
5838 static VAStatus
gen9_hevc_vme_gpe_init(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)5839 gen9_hevc_vme_gpe_init(VADriverContextP ctx,
5840 struct encode_state *encode_state,
5841 struct intel_encoder_context *encoder_context)
5842 {
5843 struct encoder_vme_mfc_context *vme_context = NULL;
5844 struct gen9_hevc_encoder_context *priv_ctx = NULL;
5845 struct gen9_hevc_encoder_state *priv_state = NULL;
5846 VAEncSliceParameterBufferHEVC *slice_param = NULL;
5847 int i = 0, j = 0;
5848
5849 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
5850 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
5851 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
5852
5853 i965_zero_gpe_resource(&priv_ctx->res_mb_code_surface);
5854
5855 i965_zero_gpe_resource(&priv_ctx->res_slice_map_buffer);
5856 if (encode_state->num_slice_params_ext > 1) {
5857 struct gen9_hevc_slice_map *pslice_map = NULL;
5858 int width = priv_state->width_in_lcu;
5859 int pitch = ALIGN(priv_state->frame_width_in_max_lcu >> 3, 64);
5860 void *ptr_start = NULL;
5861 int lcu_count = 0;
5862
5863 ptr_start = (void *)i965_map_gpe_resource(&priv_ctx->res_slice_map_buffer);
5864
5865 if (!ptr_start)
5866 return VA_STATUS_ERROR_UNKNOWN;
5867
5868 pslice_map = (struct gen9_hevc_slice_map *)ptr_start;
5869 for (i = 0; i < encode_state->num_slice_params_ext; i++) {
5870 slice_param = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[i]->buffer;
5871
5872 for (j = 0; j < slice_param->num_ctu_in_slice; j++) {
5873 pslice_map[lcu_count++].slice_id = i;
5874
5875 if (lcu_count >= width) {
5876 lcu_count = 0;
5877 ptr_start += pitch;
5878
5879 pslice_map = (struct gen9_hevc_slice_map *)ptr_start;
5880 }
5881 }
5882 }
5883
5884 i965_unmap_gpe_resource(&priv_ctx->res_slice_map_buffer);
5885 }
5886
5887 return VA_STATUS_SUCCESS;
5888 }
5889
5890 static VAStatus
gen9_hevc_vme_gpe_run(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)5891 gen9_hevc_vme_gpe_run(VADriverContextP ctx,
5892 struct encode_state *encode_state,
5893 struct intel_encoder_context *encoder_context)
5894 {
5895 struct encoder_vme_mfc_context *vme_context = NULL;
5896 struct generic_enc_codec_state *generic_state = NULL;
5897 struct gen9_hevc_encoder_state *priv_state = NULL;
5898
5899 vme_context = encoder_context->vme_context;
5900 generic_state = vme_context->generic_enc_state;
5901 priv_state = vme_context->private_enc_state;
5902
5903 if (generic_state->brc_enabled &&
5904 (generic_state->brc_need_reset || !generic_state->brc_inited)) {
5905 gen9_hevc_brc_init_reset(ctx, encode_state, encoder_context,
5906 generic_state->brc_inited ? 1 : 0);
5907 generic_state->brc_need_reset = 0;
5908 generic_state->brc_inited = 1;
5909 }
5910
5911 if (generic_state->hme_supported || generic_state->brc_enabled) {
5912 gen9_hevc_hme_scaling(ctx, encode_state, encoder_context);
5913
5914 if (generic_state->brc_enabled)
5915 gen9_hevc_brc_intra_dist(ctx, encode_state, encoder_context);
5916
5917 if (generic_state->hme_enabled)
5918 gen9_hevc_hme_encode_me(ctx, encode_state, encoder_context);
5919
5920 if (generic_state->brc_enabled)
5921 gen9_hevc_brc_update(ctx, encode_state, encoder_context);
5922 }
5923
5924 if (priv_state->num_roi && !generic_state->brc_enabled)
5925 gen9_hevc_brc_update_lcu_based(ctx, encode_state, encoder_context);
5926
5927 if (priv_state->bit_depth_luma_minus8)
5928 gen9_hevc_ref_frame_depth_conversion(ctx, encode_state, encoder_context);
5929
5930 gen9_hevc_mbenc(ctx, encode_state, encoder_context);
5931
5932 return VA_STATUS_SUCCESS;
5933 }
5934
5935 static VAStatus
gen9_hevc_vme_pipeline(VADriverContextP ctx,VAProfile profile,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)5936 gen9_hevc_vme_pipeline(VADriverContextP ctx,
5937 VAProfile profile,
5938 struct encode_state *encode_state,
5939 struct intel_encoder_context *encoder_context)
5940 {
5941 VAStatus va_status = VA_STATUS_SUCCESS;
5942
5943 va_status = gen9_hevc_enc_init_parameters(ctx, encode_state, encoder_context);
5944 if (va_status != VA_STATUS_SUCCESS)
5945 goto EXIT;
5946
5947 va_status = gen9_hevc_vme_gpe_init(ctx, encode_state, encoder_context);
5948 if (va_status != VA_STATUS_SUCCESS)
5949 goto EXIT;
5950
5951 va_status = gen9_hevc_vme_gpe_run(ctx, encode_state, encoder_context);
5952
5953 EXIT:
5954 return va_status;
5955 }
5956
5957 static void
gen9_hevc_vme_scaling_context_init(VADriverContextP ctx,struct intel_encoder_context * encoder_context)5958 gen9_hevc_vme_scaling_context_init(VADriverContextP ctx,
5959 struct intel_encoder_context *encoder_context)
5960 {
5961 struct encoder_vme_mfc_context *vme_context = NULL;
5962 struct gen9_hevc_encoder_context *priv_ctx = NULL;
5963 struct gen9_hevc_encoder_state *priv_state = NULL;
5964 struct i965_gpe_context *gpe_context = NULL;
5965 struct i965_kernel kernel_info;
5966 struct gen9_hevc_scaling_context *scaling_ctx = NULL;
5967 GEN9_ENC_OPERATION kernel_idx;
5968 int curbe_size = 0;
5969 int i = 0;
5970
5971 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
5972 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
5973 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
5974
5975 scaling_ctx = &priv_ctx->scaling_context;
5976
5977 for (i = 0; i < NUM_HEVC_ENC_SCALING; i++) {
5978 if (i == HEVC_ENC_SCALING_4X ||
5979 i == HEVC_ENC_SCALING_16X) {
5980 curbe_size = sizeof(gen9_hevc_scaling4x_curbe_data);
5981 kernel_idx = GEN9_ENC_SCALING4X;
5982 } else if (i == HEVC_ENC_SCALING_32X) {
5983 curbe_size = sizeof(gen9_hevc_scaling2x_curbe_data);
5984 kernel_idx = GEN9_ENC_SCALING2X;
5985 }
5986
5987 gpe_context = &scaling_ctx->gpe_contexts[i];
5988
5989 gen9_hevc_vme_init_gpe_context(ctx, gpe_context,
5990 curbe_size,
5991 curbe_size);
5992 gen9_hevc_vme_init_scoreboard(gpe_context,
5993 0xFF,
5994 priv_state->use_hw_scoreboard,
5995 priv_state->use_hw_non_stalling_scoreborad);
5996
5997 memset(&kernel_info, 0, sizeof(kernel_info));
5998 gen9_hevc_get_kernel_header_and_size((void *)hevc_enc_kernel_ptr,
5999 hevc_enc_kernel_size,
6000 kernel_idx,
6001 0,
6002 &kernel_info);
6003 gen8_gpe_load_kernels(ctx,
6004 gpe_context,
6005 &kernel_info,
6006 1);
6007 }
6008 }
6009
6010 static void
gen9_hevc_vme_me_context_init(VADriverContextP ctx,struct intel_encoder_context * encoder_context)6011 gen9_hevc_vme_me_context_init(VADriverContextP ctx,
6012 struct intel_encoder_context *encoder_context)
6013 {
6014 struct encoder_vme_mfc_context *vme_context = NULL;
6015 struct gen9_hevc_encoder_context *priv_ctx = NULL;
6016 struct gen9_hevc_encoder_state *priv_state = NULL;
6017 struct i965_gpe_context *gpe_context = NULL;
6018 struct i965_kernel kernel_info;
6019 struct gen9_hevc_me_context *me_ctx = NULL;
6020 int i = 0, j = 0;
6021
6022 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
6023 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
6024 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
6025
6026 me_ctx = &priv_ctx->me_context;
6027
6028 for (i = 0; i < NUM_HEVC_ENC_ME; i++) {
6029 for (j = 0; j < NUM_HEVC_ENC_ME_TYPES; j++) {
6030 gpe_context = &me_ctx->gpe_context[j][i];
6031
6032 gen9_hevc_vme_init_gpe_context(ctx, gpe_context,
6033 sizeof(gen9_hevc_me_curbe_data),
6034 0);
6035 gen9_hevc_vme_init_scoreboard(gpe_context,
6036 0xFF,
6037 priv_state->use_hw_scoreboard,
6038 priv_state->use_hw_non_stalling_scoreborad);
6039
6040 memset(&kernel_info, 0, sizeof(kernel_info));
6041 gen9_hevc_get_kernel_header_and_size((void *)hevc_enc_kernel_ptr,
6042 hevc_enc_kernel_size,
6043 GEN9_ENC_ME,
6044 i,
6045 &kernel_info);
6046 gen8_gpe_load_kernels(ctx,
6047 gpe_context,
6048 &kernel_info,
6049 1);
6050 }
6051 }
6052 }
6053
6054 static void
gen9_hevc_vme_mbenc_context_init(VADriverContextP ctx,struct intel_encoder_context * encoder_context)6055 gen9_hevc_vme_mbenc_context_init(VADriverContextP ctx,
6056 struct intel_encoder_context *encoder_context)
6057 {
6058 struct encoder_vme_mfc_context *vme_context = NULL;
6059 struct gen9_hevc_encoder_context *priv_ctx = NULL;
6060 struct gen9_hevc_encoder_state *priv_state = NULL;
6061 struct i965_gpe_context *gpe_context = NULL;
6062 struct i965_kernel kernel_info;
6063 struct gen9_hevc_mbenc_context *mbenc_ctx = NULL;
6064 int i = 0;
6065
6066 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
6067 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
6068 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
6069
6070 mbenc_ctx = &priv_ctx->mbenc_context;
6071
6072 mbenc_ctx->kernel_num = GEN8_HEVC_ENC_MBENC_TOTAL_NUM;
6073
6074 for (i = 0; i < mbenc_ctx->kernel_num; i++) {
6075 gpe_context = &mbenc_ctx->gpe_contexts[i];
6076
6077 gen9_hevc_vme_init_gpe_context(ctx, gpe_context,
6078 hevc_mbenc_curbe_size[i],
6079 0);
6080 gen9_hevc_vme_init_scoreboard(gpe_context,
6081 0xFF,
6082 priv_state->use_hw_scoreboard,
6083 priv_state->use_hw_non_stalling_scoreborad);
6084
6085 memset(&kernel_info, 0, sizeof(kernel_info));
6086 gen9_hevc_get_kernel_header_and_size((void *)hevc_enc_kernel_ptr,
6087 hevc_enc_kernel_size,
6088 GEN9_ENC_MBENC,
6089 i,
6090 &kernel_info);
6091 gen8_gpe_load_kernels(ctx,
6092 gpe_context,
6093 &kernel_info,
6094 1);
6095 }
6096 }
6097
6098 static void
gen9_hevc_vme_brc_context_init(VADriverContextP ctx,struct intel_encoder_context * encoder_context)6099 gen9_hevc_vme_brc_context_init(VADriverContextP ctx,
6100 struct intel_encoder_context *encoder_context)
6101 {
6102 struct encoder_vme_mfc_context *vme_context = NULL;
6103 struct gen9_hevc_encoder_context *priv_ctx = NULL;
6104 struct gen9_hevc_encoder_state *priv_state = NULL;
6105 struct i965_gpe_context *gpe_context = NULL;
6106 struct i965_kernel kernel_info;
6107 struct gen9_hevc_brc_context *brc_ctx = NULL;
6108 int i = 0;
6109
6110 vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
6111 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
6112 priv_state = (struct gen9_hevc_encoder_state *)vme_context->private_enc_state;
6113
6114 brc_ctx = &priv_ctx->brc_context;
6115
6116 for (i = 0; i < GEN9_HEVC_ENC_BRC_NUM; i++) {
6117 gpe_context = &brc_ctx->gpe_contexts[i];
6118
6119 gen9_hevc_vme_init_gpe_context(ctx, gpe_context,
6120 hevc_brc_curbe_size[i],
6121 0);
6122 gen9_hevc_vme_init_scoreboard(gpe_context,
6123 0xFF,
6124 priv_state->use_hw_scoreboard,
6125 priv_state->use_hw_non_stalling_scoreborad);
6126
6127 memset(&kernel_info, 0, sizeof(kernel_info));
6128 gen9_hevc_get_kernel_header_and_size((void *)hevc_enc_kernel_ptr,
6129 hevc_enc_kernel_size,
6130 GEN9_ENC_BRC,
6131 i,
6132 &kernel_info);
6133 gen8_gpe_load_kernels(ctx,
6134 gpe_context,
6135 &kernel_info,
6136 1);
6137 }
6138 }
6139
6140 static void
gen9_hevc_vme_scaling_context_destroy(struct gen9_hevc_scaling_context * scaling_context)6141 gen9_hevc_vme_scaling_context_destroy(struct gen9_hevc_scaling_context *scaling_context)
6142 {
6143 int i;
6144
6145 for (i = 0; i < NUM_HEVC_ENC_SCALING; i++)
6146 gen8_gpe_context_destroy(&scaling_context->gpe_contexts[i]);
6147 }
6148
6149 static void
gen9_hevc_vme_me_context_destroy(struct gen9_hevc_me_context * me_context)6150 gen9_hevc_vme_me_context_destroy(struct gen9_hevc_me_context *me_context)
6151 {
6152 int i, j;
6153
6154 for (i = 0; i < NUM_HEVC_ENC_ME; i++)
6155 for (j = 0; j < NUM_HEVC_ENC_ME_TYPES; j++)
6156 gen8_gpe_context_destroy(&me_context->gpe_context[j][i]);
6157 }
6158
6159 static void
gen9_hevc_vme_mbenc_context_destroy(struct gen9_hevc_mbenc_context * mbenc_context)6160 gen9_hevc_vme_mbenc_context_destroy(struct gen9_hevc_mbenc_context *mbenc_context)
6161 {
6162 int i;
6163
6164 for (i = 0; i < mbenc_context->kernel_num; i++)
6165 gen8_gpe_context_destroy(&mbenc_context->gpe_contexts[i]);
6166 }
6167
6168 static void
gen9_hevc_vme_brc_context_destroy(struct gen9_hevc_brc_context * brc_context)6169 gen9_hevc_vme_brc_context_destroy(struct gen9_hevc_brc_context *brc_context)
6170 {
6171 int i;
6172
6173 for (i = 0; i < GEN9_HEVC_ENC_BRC_NUM; i++)
6174 gen8_gpe_context_destroy(&brc_context->gpe_contexts[i]);
6175 }
6176
6177 static void
gen9_hevc_vme_kernels_context_init(VADriverContextP ctx,struct intel_encoder_context * encoder_context)6178 gen9_hevc_vme_kernels_context_init(VADriverContextP ctx,
6179 struct intel_encoder_context *encoder_context)
6180 {
6181 gen9_hevc_vme_scaling_context_init(ctx, encoder_context);
6182 gen9_hevc_vme_me_context_init(ctx, encoder_context);
6183 gen9_hevc_vme_mbenc_context_init(ctx, encoder_context);
6184 gen9_hevc_vme_brc_context_init(ctx, encoder_context);
6185 }
6186
6187 static void
gen9_hevc_vme_kernels_context_destroy(struct encoder_vme_mfc_context * vme_context)6188 gen9_hevc_vme_kernels_context_destroy(struct encoder_vme_mfc_context *vme_context)
6189 {
6190 struct gen9_hevc_encoder_context *priv_ctx = NULL;
6191
6192 priv_ctx = (struct gen9_hevc_encoder_context *)vme_context->private_enc_ctx;
6193
6194 gen9_hevc_vme_scaling_context_destroy(&priv_ctx->scaling_context);
6195 gen9_hevc_vme_me_context_destroy(&priv_ctx->me_context);
6196 gen9_hevc_vme_mbenc_context_destroy(&priv_ctx->mbenc_context);
6197 gen9_hevc_vme_brc_context_destroy(&priv_ctx->brc_context);
6198 }
6199
6200 static void
gen9_hevc_vme_context_destroy(void * context)6201 gen9_hevc_vme_context_destroy(void *context)
6202 {
6203 struct encoder_vme_mfc_context *vme_context = (struct encoder_vme_mfc_context *)context;
6204
6205 if (!vme_context)
6206 return;
6207
6208 gen9_hevc_enc_free_resources(vme_context);
6209
6210 gen9_hevc_vme_kernels_context_destroy(vme_context);
6211
6212 if (vme_context->private_enc_ctx) free(vme_context->private_enc_ctx);
6213 if (vme_context->generic_enc_state) free(vme_context->generic_enc_state);
6214 if (vme_context->private_enc_state) free(vme_context->private_enc_state);
6215
6216 free(vme_context);
6217 }
6218
6219 #define PAK_IMPLEMENTATION_START
6220
6221 static void
gen9_hevc_pak_pipe_mode_select(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)6222 gen9_hevc_pak_pipe_mode_select(VADriverContextP ctx,
6223 struct encode_state *encode_state,
6224 struct intel_encoder_context *encoder_context)
6225 {
6226 struct intel_batchbuffer *batch = encoder_context->base.batch;
6227
6228 BEGIN_BCS_BATCH(batch, 6);
6229
6230 OUT_BCS_BATCH(batch, HCP_PIPE_MODE_SELECT | (6 - 2));
6231 OUT_BCS_BATCH(batch,
6232 (0 << 5) |
6233 (0 << 3) |
6234 HCP_CODEC_SELECT_ENCODE);
6235 OUT_BCS_BATCH(batch, 0);
6236 OUT_BCS_BATCH(batch, 0);
6237 OUT_BCS_BATCH(batch, 0);
6238 OUT_BCS_BATCH(batch, 0);
6239
6240 ADVANCE_BCS_BATCH(batch);
6241 }
6242
6243 static void
gen9_hevc_pak_add_surface_state(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,struct object_surface * obj_surface,enum GEN9_HEVC_ENC_SURFACE_TYPE type)6244 gen9_hevc_pak_add_surface_state(VADriverContextP ctx,
6245 struct encode_state *encode_state,
6246 struct intel_encoder_context *encoder_context,
6247 struct object_surface *obj_surface,
6248 enum GEN9_HEVC_ENC_SURFACE_TYPE type)
6249 {
6250 struct intel_batchbuffer *batch = encoder_context->base.batch;
6251
6252 BEGIN_BCS_BATCH(batch, 3);
6253
6254 OUT_BCS_BATCH(batch, HCP_SURFACE_STATE | (3 - 2));
6255 OUT_BCS_BATCH(batch,
6256 (type << 28) |
6257 (obj_surface->width - 1));
6258 OUT_BCS_BATCH(batch,
6259 (((obj_surface->fourcc == VA_FOURCC_P010) ?
6260 SURFACE_FORMAT_P010 :
6261 SURFACE_FORMAT_PLANAR_420_8) << 28) |
6262 (obj_surface->y_cb_offset));
6263
6264 ADVANCE_BCS_BATCH(batch);
6265 }
6266
6267 #define OUT_BUFFER(buf_bo, is_target, ma) \
6268 do { \
6269 if (buf_bo) { \
6270 OUT_RELOC64(batch, \
6271 buf_bo, \
6272 I915_GEM_DOMAIN_RENDER, \
6273 is_target ? I915_GEM_DOMAIN_RENDER : 0, \
6274 0); \
6275 } else { \
6276 OUT_BCS_BATCH(batch, 0); \
6277 OUT_BCS_BATCH(batch, 0); \
6278 } \
6279 if (ma) \
6280 OUT_BCS_BATCH(batch, priv_ctx->mocs); \
6281 } while (0);
6282
6283 #define OUT_BUFFER_MA_TARGET(buf_bo) OUT_BUFFER(buf_bo, 1, 1)
6284 #define OUT_BUFFER_MA_REFERENCE(buf_bo) OUT_BUFFER(buf_bo, 0, 1)
6285 #define OUT_BUFFER_NMA_REFERENCE(buf_bo) OUT_BUFFER(buf_bo, 0, 0)
6286
6287 static void
gen9_hevc_pak_add_pipe_buf_addr_state(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)6288 gen9_hevc_pak_add_pipe_buf_addr_state(VADriverContextP ctx,
6289 struct encode_state *encode_state,
6290 struct intel_encoder_context *encoder_context)
6291 {
6292 struct i965_driver_data *i965 = i965_driver_data(ctx);
6293 struct intel_batchbuffer *batch = encoder_context->base.batch;
6294 struct encoder_vme_mfc_context *pak_context = NULL;
6295 struct gen9_hevc_encoder_context *priv_ctx = NULL;
6296 dri_bo *bo = NULL;
6297 int i = 0;
6298
6299 pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
6300 priv_ctx = (struct gen9_hevc_encoder_context *)pak_context->private_enc_ctx;
6301
6302 if (IS_KBL(i965->intel.device_info) || IS_GLK(i965->intel.device_info)) {
6303 BEGIN_BCS_BATCH(batch, 104);
6304
6305 OUT_BCS_BATCH(batch, HCP_PIPE_BUF_ADDR_STATE | (104 - 2));
6306 } else {
6307 BEGIN_BCS_BATCH(batch, 95);
6308
6309 OUT_BCS_BATCH(batch, HCP_PIPE_BUF_ADDR_STATE | (95 - 2));
6310 }
6311
6312 OUT_BUFFER_MA_TARGET(priv_ctx->reconstructed_object.obj_surface->bo);
6313 OUT_BUFFER_MA_TARGET(priv_ctx->deblocking_filter_line_buffer.bo);
6314 OUT_BUFFER_MA_TARGET(priv_ctx->deblocking_filter_tile_line_buffer.bo);
6315 OUT_BUFFER_MA_TARGET(priv_ctx->deblocking_filter_tile_column_buffer.bo);
6316 OUT_BUFFER_MA_TARGET(priv_ctx->metadata_line_buffer.bo);
6317 OUT_BUFFER_MA_TARGET(priv_ctx->metadata_tile_line_buffer.bo);
6318 OUT_BUFFER_MA_TARGET(priv_ctx->metadata_tile_column_buffer.bo);
6319 OUT_BUFFER_MA_TARGET(priv_ctx->sao_line_buffer.bo);
6320 OUT_BUFFER_MA_TARGET(priv_ctx->sao_tile_line_buffer.bo);
6321 OUT_BUFFER_MA_TARGET(priv_ctx->sao_tile_column_buffer.bo);
6322 OUT_BUFFER_MA_TARGET(priv_ctx->
6323 mv_temporal_buffer[GEN9_MAX_MV_TEMPORAL_BUFFERS - 1].bo);
6324 OUT_BUFFER_MA_TARGET(NULL);
6325
6326 for (i = 0; i < GEN9_MAX_REF_SURFACES; i++) {
6327 if (priv_ctx->reference_surfaces[i].obj_surface_bo) {
6328 bo = priv_ctx->reference_surfaces[i].obj_surface_bo;
6329
6330 OUT_BUFFER_NMA_REFERENCE(bo);
6331 } else
6332 OUT_BUFFER_NMA_REFERENCE(NULL);
6333 }
6334 OUT_BCS_BATCH(batch, priv_ctx->mocs);
6335
6336 OUT_BUFFER_MA_TARGET(priv_ctx->
6337 uncompressed_picture_source.obj_surface->bo);
6338 OUT_BUFFER_MA_TARGET(NULL);
6339 OUT_BUFFER_MA_TARGET(NULL);
6340 OUT_BUFFER_MA_TARGET(NULL);
6341
6342 for (i = 0; i < GEN9_MAX_MV_TEMPORAL_BUFFERS - 1; i++) {
6343 bo = priv_ctx->mv_temporal_buffer[i].bo;
6344
6345 if (bo) {
6346 OUT_BUFFER_NMA_REFERENCE(bo);
6347 } else
6348 OUT_BUFFER_NMA_REFERENCE(NULL);
6349 }
6350 OUT_BCS_BATCH(batch, priv_ctx->mocs);
6351
6352 OUT_BUFFER_MA_TARGET(NULL);
6353 OUT_BUFFER_MA_TARGET(NULL);
6354 OUT_BUFFER_MA_TARGET(NULL);
6355 OUT_BUFFER_MA_TARGET(NULL);
6356
6357 if (IS_KBL(i965->intel.device_info) || IS_GLK(i965->intel.device_info)) {
6358 for (i = 0; i < 9; i++)
6359 OUT_BCS_BATCH(batch, 0);
6360 }
6361
6362 ADVANCE_BCS_BATCH(batch);
6363 }
6364
6365 static void
gen9_hevc_pak_add_ind_obj_base_addr_state(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)6366 gen9_hevc_pak_add_ind_obj_base_addr_state(VADriverContextP ctx,
6367 struct encode_state *encode_state,
6368 struct intel_encoder_context *encoder_context)
6369 {
6370 struct intel_batchbuffer *batch = encoder_context->base.batch;
6371 struct encoder_vme_mfc_context *pak_context = NULL;
6372 struct gen9_hevc_encoder_context *priv_ctx = NULL;
6373 struct gen9_hevc_encoder_state *priv_state = NULL;
6374
6375 pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
6376 priv_ctx = (struct gen9_hevc_encoder_context *)pak_context->private_enc_ctx;
6377 priv_state = (struct gen9_hevc_encoder_state *)pak_context->private_enc_state;
6378
6379 BEGIN_BCS_BATCH(batch, 14);
6380
6381 OUT_BCS_BATCH(batch, HCP_IND_OBJ_BASE_ADDR_STATE | (14 - 2));
6382 OUT_BUFFER_MA_REFERENCE(NULL);
6383 OUT_BUFFER_NMA_REFERENCE(NULL);
6384
6385 OUT_RELOC64(batch,
6386 priv_ctx->res_mb_code_surface.bo,
6387 I915_GEM_DOMAIN_INSTRUCTION, 0,
6388 priv_state->mb_data_offset);
6389 OUT_BCS_BATCH(batch, priv_ctx->mocs);
6390
6391 OUT_RELOC64(batch,
6392 priv_ctx->indirect_pak_bse_object.bo,
6393 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
6394 priv_ctx->indirect_pak_bse_object.offset);
6395 OUT_BCS_BATCH(batch, priv_ctx->mocs);
6396
6397 OUT_RELOC64(batch,
6398 priv_ctx->indirect_pak_bse_object.bo,
6399 I915_GEM_DOMAIN_RENDER, 0,
6400 priv_ctx->indirect_pak_bse_object.end_offset);
6401
6402 ADVANCE_BCS_BATCH(batch);
6403 }
6404
6405 static void
gen9_hevc_pak_set_qm(VADriverContextP ctx,int size_id,int color_component,int pred_type,int dc,unsigned int * qm,int qm_length,struct intel_encoder_context * encoder_context)6406 gen9_hevc_pak_set_qm(VADriverContextP ctx,
6407 int size_id,
6408 int color_component,
6409 int pred_type,
6410 int dc,
6411 unsigned int *qm,
6412 int qm_length,
6413 struct intel_encoder_context *encoder_context)
6414 {
6415 struct intel_batchbuffer *batch = encoder_context->base.batch;
6416 unsigned int qm_buffer[16];
6417
6418 memset(qm_buffer, 0, sizeof(qm_buffer));
6419 memcpy(qm_buffer, qm, qm_length * 4);
6420
6421 BEGIN_BCS_BATCH(batch, 18);
6422
6423 OUT_BCS_BATCH(batch, HCP_QM_STATE | (18 - 2));
6424 OUT_BCS_BATCH(batch,
6425 dc << 5 |
6426 color_component << 3 |
6427 size_id << 1 |
6428 pred_type);
6429 intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
6430
6431 ADVANCE_BCS_BATCH(batch);
6432 }
6433
6434 static unsigned int qm_default[16] = {
6435 0x10101010, 0x10101010, 0x10101010, 0x10101010,
6436 0x10101010, 0x10101010, 0x10101010, 0x10101010,
6437 0x10101010, 0x10101010, 0x10101010, 0x10101010,
6438 0x10101010, 0x10101010, 0x10101010, 0x10101010
6439 };
6440
6441 static void
gen9_hevc_pak_add_qm_state(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)6442 gen9_hevc_pak_add_qm_state(VADriverContextP ctx,
6443 struct encode_state *encode_state,
6444 struct intel_encoder_context *encoder_context)
6445 {
6446 int i;
6447
6448 for (i = 0; i < 6; i++)
6449 gen9_hevc_pak_set_qm(ctx,
6450 0, i % 3, i / 3, 0,
6451 qm_default, 4,
6452 encoder_context);
6453
6454 for (i = 0; i < 6; i++)
6455 gen9_hevc_pak_set_qm(ctx,
6456 1, i % 3, i / 3, 0,
6457 qm_default, 16,
6458 encoder_context);
6459
6460 for (i = 0; i < 6; i++)
6461 gen9_hevc_pak_set_qm(ctx,
6462 2, i % 3, i / 3, 16,
6463 qm_default, 16,
6464 encoder_context);
6465
6466 for (i = 0; i < 2; i++)
6467 gen9_hevc_pak_set_qm(ctx,
6468 3, 0, i % 2, 16,
6469 qm_default, 16,
6470 encoder_context);
6471 }
6472
6473 static void
gen9_hevc_pak_set_fqm(VADriverContextP ctx,int size_id,int color_component,int pred_type,int dc,unsigned int * fqm,int fqm_length,struct intel_encoder_context * encoder_context)6474 gen9_hevc_pak_set_fqm(VADriverContextP ctx,
6475 int size_id,
6476 int color_component,
6477 int pred_type,
6478 int dc,
6479 unsigned int *fqm,
6480 int fqm_length,
6481 struct intel_encoder_context *encoder_context)
6482 {
6483 struct intel_batchbuffer *batch = encoder_context->base.batch;
6484 unsigned int fqm_buffer[32];
6485
6486 memset(fqm_buffer, 0, sizeof(fqm_buffer));
6487 memcpy(fqm_buffer, fqm, fqm_length * 4);
6488
6489 BEGIN_BCS_BATCH(batch, 34);
6490
6491 OUT_BCS_BATCH(batch, HCP_FQM_STATE | (34 - 2));
6492 OUT_BCS_BATCH(batch,
6493 dc << 16 |
6494 color_component << 3 |
6495 size_id << 1 |
6496 pred_type);
6497 intel_batchbuffer_data(batch, fqm_buffer, 32 * 4);
6498
6499 ADVANCE_BCS_BATCH(batch);
6500 }
6501
6502 static unsigned int fm_default[32] = {
6503 0x10001000, 0x10001000, 0x10001000, 0x10001000,
6504 0x10001000, 0x10001000, 0x10001000, 0x10001000,
6505 0x10001000, 0x10001000, 0x10001000, 0x10001000,
6506 0x10001000, 0x10001000, 0x10001000, 0x10001000,
6507 0x10001000, 0x10001000, 0x10001000, 0x10001000,
6508 0x10001000, 0x10001000, 0x10001000, 0x10001000,
6509 0x10001000, 0x10001000, 0x10001000, 0x10001000,
6510 0x10001000, 0x10001000, 0x10001000, 0x10001000
6511 };
6512
6513 static void
gen9_hevc_pak_add_fm_state(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)6514 gen9_hevc_pak_add_fm_state(VADriverContextP ctx,
6515 struct encode_state *encode_state,
6516 struct intel_encoder_context *encoder_context)
6517 {
6518 gen9_hevc_pak_set_fqm(ctx,
6519 0, 0, 0, 0,
6520 fm_default, 8,
6521 encoder_context);
6522 gen9_hevc_pak_set_fqm(ctx,
6523 0, 0, 1, 0,
6524 fm_default, 8,
6525 encoder_context);
6526 gen9_hevc_pak_set_fqm(ctx,
6527 1, 0, 0, 0,
6528 fm_default, 32,
6529 encoder_context);
6530 gen9_hevc_pak_set_fqm(ctx,
6531 1, 0, 1, 0,
6532 fm_default, 32,
6533 encoder_context);
6534 gen9_hevc_pak_set_fqm(ctx,
6535 2, 0, 0, 0x1000,
6536 fm_default, 0,
6537 encoder_context);
6538 gen9_hevc_pak_set_fqm(ctx,
6539 2, 0, 1, 0x1000,
6540 fm_default, 0,
6541 encoder_context);
6542 gen9_hevc_pak_set_fqm(ctx,
6543 3, 0, 0, 0x1000,
6544 fm_default, 0,
6545 encoder_context);
6546 gen9_hevc_pak_set_fqm(ctx,
6547 3, 0, 1, 0x1000,
6548 fm_default, 0,
6549 encoder_context);
6550 }
6551
6552 static void
gen9_hevc_set_reflist(VADriverContextP ctx,struct gen9_hevc_encoder_context * priv_ctx,VAEncPictureParameterBufferHEVC * pic_param,VAEncSliceParameterBufferHEVC * slice_param,int list_idx,struct intel_batchbuffer * batch)6553 gen9_hevc_set_reflist(VADriverContextP ctx,
6554 struct gen9_hevc_encoder_context *priv_ctx,
6555 VAEncPictureParameterBufferHEVC *pic_param,
6556 VAEncSliceParameterBufferHEVC *slice_param,
6557 int list_idx,
6558 struct intel_batchbuffer *batch)
6559 {
6560 struct i965_driver_data *i965 = i965_driver_data(ctx);
6561 int num_ref_minus1 = (list_idx ?
6562 slice_param->num_ref_idx_l1_active_minus1 :
6563 slice_param->num_ref_idx_l0_active_minus1);
6564 VAPictureHEVC *ref_list = (list_idx ?
6565 slice_param->ref_pic_list1 :
6566 slice_param->ref_pic_list0);
6567 VAPictureHEVC *curr_pic = &pic_param->decoded_curr_pic;
6568 struct object_surface *obj_surface = NULL;
6569 int frame_idx;
6570 int i = 0, j = 0;
6571
6572 BEGIN_BCS_BATCH(batch, 18);
6573
6574 OUT_BCS_BATCH(batch, HCP_REF_IDX_STATE | (18 - 2));
6575 OUT_BCS_BATCH(batch,
6576 num_ref_minus1 << 1 |
6577 list_idx);
6578
6579 for (i = 0; i < 16; i++) {
6580 frame_idx = -1;
6581 if (i < 15)
6582 obj_surface = SURFACE(ref_list[i].picture_id);
6583 else
6584 obj_surface = NULL;
6585
6586 if (i < MIN((num_ref_minus1 + 1), GEN9_MAX_REF_SURFACES) && obj_surface) {
6587 for (j = 0; j < GEN9_MAX_REF_SURFACES; j++) {
6588 if (obj_surface == priv_ctx->reference_surfaces[j].obj_surface) {
6589 frame_idx = j;
6590 break;
6591 }
6592 }
6593 }
6594
6595 if (i < MIN((num_ref_minus1 + 1), GEN9_MAX_REF_SURFACES) &&
6596 frame_idx >= 0) {
6597 OUT_BCS_BATCH(batch,
6598 1 << 15 |
6599 0 << 14 |
6600 !!(ref_list[i].flags & VA_PICTURE_HEVC_LONG_TERM_REFERENCE) << 13 |
6601 0 << 12 |
6602 0 << 11 |
6603 frame_idx << 8 |
6604 (CLAMP(-128, 127, curr_pic->pic_order_cnt -
6605 ref_list[i].pic_order_cnt) & 0xff));
6606 } else {
6607 OUT_BCS_BATCH(batch, 0);
6608 }
6609 }
6610
6611 ADVANCE_BCS_BATCH(batch);
6612 }
6613
6614 static void
gen9_hevc_pak_add_slice_state(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,int slice_idx,struct intel_batchbuffer * batch)6615 gen9_hevc_pak_add_slice_state(VADriverContextP ctx,
6616 struct encode_state *encode_state,
6617 struct intel_encoder_context *encoder_context,
6618 int slice_idx,
6619 struct intel_batchbuffer *batch)
6620 {
6621 struct i965_driver_data *i965 = i965_driver_data(ctx);
6622 struct encoder_vme_mfc_context *pak_context = NULL;
6623 struct gen9_hevc_encoder_state *priv_state = NULL;
6624 VAEncPictureParameterBufferHEVC *pic_param = NULL;
6625 VAEncSliceParameterBufferHEVC *slice_param = NULL;
6626 int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos;
6627 int slice_type = 0, slice_end = 0, last_slice = 0;
6628 int collocated_ref_idx = 0;
6629
6630 pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
6631 priv_state = (struct gen9_hevc_encoder_state *)pak_context->private_enc_state;
6632 pic_param = (VAEncPictureParameterBufferHEVC *)encode_state->pic_param_ext->buffer;
6633 slice_param = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[slice_idx]->buffer;
6634
6635 slice_type = slice_param->slice_type;
6636 slice_end = slice_param->slice_segment_address + slice_param->num_ctu_in_slice;
6637 slice_hor_pos = slice_param->slice_segment_address % priv_state->width_in_lcu;
6638 slice_ver_pos = slice_param->slice_segment_address / priv_state->width_in_lcu;
6639 next_slice_hor_pos = slice_end % priv_state->width_in_lcu;
6640 next_slice_ver_pos = slice_end / priv_state->width_in_lcu;
6641
6642 if (slice_end >= priv_state->width_in_lcu * priv_state->height_in_lcu ||
6643 slice_idx == encode_state->num_slice_params_ext - 1)
6644 last_slice = 1;
6645
6646 if (priv_state->picture_coding_type != HEVC_SLICE_I &&
6647 slice_param->slice_fields.bits.slice_temporal_mvp_enabled_flag &&
6648 slice_param->slice_fields.bits.collocated_from_l0_flag)
6649 collocated_ref_idx = pic_param->collocated_ref_pic_index;
6650
6651 if (IS_KBL(i965->intel.device_info) || IS_GLK(i965->intel.device_info)) {
6652 BEGIN_BCS_BATCH(batch, 11);
6653
6654 OUT_BCS_BATCH(batch, HCP_SLICE_STATE | (11 - 2));
6655 } else {
6656 BEGIN_BCS_BATCH(batch, 9);
6657
6658 OUT_BCS_BATCH(batch, HCP_SLICE_STATE | (9 - 2));
6659 }
6660
6661 OUT_BCS_BATCH(batch,
6662 slice_ver_pos << 16 |
6663 slice_hor_pos);
6664 OUT_BCS_BATCH(batch,
6665 next_slice_ver_pos << 16 |
6666 next_slice_hor_pos);
6667 OUT_BCS_BATCH(batch,
6668 (slice_param->slice_cr_qp_offset & 0x1f) << 17 |
6669 (slice_param->slice_cb_qp_offset & 0x1f) << 12 |
6670 (pic_param->pic_init_qp + slice_param->slice_qp_delta) << 6 |
6671 slice_param->slice_fields.bits.slice_temporal_mvp_enabled_flag << 5 |
6672 slice_param->slice_fields.bits.dependent_slice_segment_flag << 4 |
6673 last_slice << 2 |
6674 slice_type);
6675 OUT_BCS_BATCH(batch,
6676 collocated_ref_idx << 26 |
6677 (slice_param->max_num_merge_cand - 1) << 23 |
6678 slice_param->slice_fields.bits.cabac_init_flag << 22 |
6679 slice_param->luma_log2_weight_denom << 19 |
6680 (slice_param->luma_log2_weight_denom + slice_param->delta_chroma_log2_weight_denom) << 16 |
6681 slice_param->slice_fields.bits.collocated_from_l0_flag << 15 |
6682 priv_state->low_delay << 14 |
6683 slice_param->slice_fields.bits.mvd_l1_zero_flag << 13 |
6684 slice_param->slice_fields.bits.slice_sao_luma_flag << 12 |
6685 slice_param->slice_fields.bits.slice_sao_chroma_flag << 11 |
6686 slice_param->slice_fields.bits.slice_loop_filter_across_slices_enabled_flag << 10 |
6687 (slice_param->slice_beta_offset_div2 & 0xf) << 5 |
6688 (slice_param->slice_tc_offset_div2 & 0xf) << 1 |
6689 slice_param->slice_fields.bits.slice_deblocking_filter_disabled_flag);
6690 OUT_BCS_BATCH(batch, 0);
6691
6692 if (!pic_param->pic_fields.bits.reference_pic_flag &&
6693 priv_state->picture_coding_type != HEVC_SLICE_I)
6694 OUT_BCS_BATCH(batch, 0 << 26 |
6695 8 << 20);
6696 else
6697 OUT_BCS_BATCH(batch, 5 << 26 |
6698 11 << 20);
6699
6700 OUT_BCS_BATCH(batch,
6701 1 << 10 |
6702 1 << 9 |
6703 1 << 2 |
6704 1 << 1 |
6705 0);
6706 OUT_BCS_BATCH(batch, 0);
6707
6708 if (IS_KBL(i965->intel.device_info) || IS_GLK(i965->intel.device_info)) {
6709 OUT_BCS_BATCH(batch, 0);
6710 OUT_BCS_BATCH(batch, 0);
6711 }
6712
6713 ADVANCE_BCS_BATCH(batch);
6714 }
6715
6716 static int
gen9_hevc_find_skipemulcnt(unsigned char * buf,unsigned int bits_length)6717 gen9_hevc_find_skipemulcnt(unsigned char *buf, unsigned int bits_length)
6718 {
6719 int skip_cnt = 0, i = 0;
6720
6721 if ((bits_length >> 3) < 6)
6722 return 0;
6723
6724 for (i = 0; i < 3; i++)
6725 if (buf[i] != 0)
6726 break;
6727
6728 if (i > 1) {
6729 if (buf[i] == 1)
6730 skip_cnt = i + 3;
6731 }
6732
6733 return skip_cnt;
6734 }
6735
6736 static void
gen9_hevc_pak_insert_object(unsigned int * data_buffer,unsigned int data_size,unsigned char emulation_flag,int is_last_header,int is_end_of_slice,int skip_emul_byte_cnt,struct intel_batchbuffer * batch)6737 gen9_hevc_pak_insert_object(unsigned int *data_buffer,
6738 unsigned int data_size,
6739 unsigned char emulation_flag,
6740 int is_last_header,
6741 int is_end_of_slice,
6742 int skip_emul_byte_cnt,
6743 struct intel_batchbuffer *batch)
6744 {
6745 int length_in_dws = ALIGN(data_size, 32) >> 5;
6746 int data_bits_in_last_dw = data_size & 0x1f;
6747 int skip_cnt = skip_emul_byte_cnt;
6748
6749 if (data_bits_in_last_dw == 0)
6750 data_bits_in_last_dw = 32;
6751
6752 if (emulation_flag) {
6753 if (!skip_cnt)
6754 skip_cnt = gen9_hevc_find_skipemulcnt((unsigned char *)data_buffer,
6755 data_size);
6756 }
6757
6758 BEGIN_BCS_BATCH(batch, length_in_dws + 2);
6759
6760 OUT_BCS_BATCH(batch, HCP_INSERT_PAK_OBJECT | (length_in_dws + 2 - 2));
6761 OUT_BCS_BATCH(batch,
6762 (0 << 31) |
6763 (0 << 16) |
6764 (0 << 15) |
6765 (data_bits_in_last_dw << 8) |
6766 (skip_cnt << 4) |
6767 ((!!emulation_flag) << 3) |
6768 ((!!is_last_header) << 2) |
6769 ((!!is_end_of_slice) << 1) |
6770 (0 << 0));
6771 intel_batchbuffer_data(batch, data_buffer, length_in_dws * 4);
6772
6773 ADVANCE_BCS_BATCH(batch);
6774 }
6775
6776 static void
gen9_hevc_pak_add_refs(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,int slice_idx,struct intel_batchbuffer * batch)6777 gen9_hevc_pak_add_refs(VADriverContextP ctx,
6778 struct encode_state *encode_state,
6779 struct intel_encoder_context *encoder_context,
6780 int slice_idx,
6781 struct intel_batchbuffer *batch)
6782 {
6783 struct encoder_vme_mfc_context *pak_context = NULL;
6784 struct gen9_hevc_encoder_context *priv_ctx = NULL;
6785 VAEncPictureParameterBufferHEVC *pic_param = NULL;
6786 VAEncSliceParameterBufferHEVC *slice_param = NULL;
6787
6788 pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
6789 priv_ctx = (struct gen9_hevc_encoder_context *)pak_context->private_enc_ctx;
6790 pic_param = (VAEncPictureParameterBufferHEVC *)encode_state->pic_param_ext->buffer;
6791 slice_param = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[slice_idx]->buffer;
6792
6793 if (slice_param->slice_type == HEVC_SLICE_I)
6794 return;
6795
6796 gen9_hevc_set_reflist(ctx, priv_ctx, pic_param, slice_param, 0, batch);
6797
6798 if (slice_param->slice_type == HEVC_SLICE_P)
6799 return;
6800
6801 gen9_hevc_set_reflist(ctx, priv_ctx, pic_param, slice_param, 1, batch);
6802 }
6803
6804 static void
gen9_hevc_pak_insert_packed_data(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,int slice_idx,struct intel_batchbuffer * batch)6805 gen9_hevc_pak_insert_packed_data(VADriverContextP ctx,
6806 struct encode_state *encode_state,
6807 struct intel_encoder_context *encoder_context,
6808 int slice_idx,
6809 struct intel_batchbuffer *batch)
6810 {
6811 VAEncPackedHeaderParameterBuffer *param = NULL;
6812 unsigned int *header_data = NULL;
6813 unsigned int length_in_bits = 0;
6814 int packed_type = 0;
6815 int idx = 0, idx_offset = 0;
6816 int i = 0;
6817
6818 for (i = 0; i < 4; i++) {
6819 idx_offset = 0;
6820 switch (i) {
6821 case 0:
6822 packed_type = VAEncPackedHeaderHEVC_VPS;
6823 break;
6824 case 1:
6825 packed_type = VAEncPackedHeaderHEVC_VPS;
6826 idx_offset = 1;
6827 break;
6828 case 2:
6829 packed_type = VAEncPackedHeaderHEVC_PPS;
6830 break;
6831 case 3:
6832 packed_type = VAEncPackedHeaderHEVC_SEI;
6833 break;
6834 default:
6835 break;
6836 }
6837
6838 idx = va_enc_packed_type_to_idx(packed_type) + idx_offset;
6839 if (encode_state->packed_header_data[idx]) {
6840 param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer;
6841 header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer;
6842 length_in_bits = param->bit_length;
6843
6844 gen9_hevc_pak_insert_object(header_data, length_in_bits,
6845 !param->has_emulation_bytes, 0, 0, 0,
6846 batch);
6847 }
6848 }
6849 }
6850
6851 static void
gen9_hevc_pak_insert_slice_header(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,int slice_idx,struct intel_batchbuffer * batch)6852 gen9_hevc_pak_insert_slice_header(VADriverContextP ctx,
6853 struct encode_state *encode_state,
6854 struct intel_encoder_context *encoder_context,
6855 int slice_idx,
6856 struct intel_batchbuffer *batch)
6857 {
6858 VAEncPackedHeaderParameterBuffer *param = NULL;
6859 unsigned int *header_data = NULL;
6860 unsigned int length_in_bits = 0;
6861 int count = 0, start_index = -1;
6862 int i = 0;
6863
6864 count = encode_state->slice_rawdata_count[slice_idx];
6865 start_index = encode_state->slice_rawdata_index[slice_idx] &
6866 SLICE_PACKED_DATA_INDEX_MASK;
6867
6868 for (i = 0; i < count; i++) {
6869 param = (VAEncPackedHeaderParameterBuffer *)
6870 (encode_state->packed_header_params_ext[start_index + i]->buffer);
6871
6872 if (param->type == VAEncPackedHeaderSlice)
6873 continue;
6874
6875 header_data = (unsigned int *)encode_state->packed_header_data_ext[start_index]->buffer;
6876 length_in_bits = param->bit_length;
6877 gen9_hevc_pak_insert_object(header_data, length_in_bits,
6878 !param->has_emulation_bytes, 0, 0, 0,
6879 batch);
6880 }
6881
6882 start_index = -1;
6883 if (encode_state->slice_header_index[slice_idx] & SLICE_PACKED_DATA_INDEX_TYPE)
6884 start_index = encode_state->slice_header_index[slice_idx] &
6885 SLICE_PACKED_DATA_INDEX_MASK;
6886 if (start_index == -1) {
6887 VAEncSequenceParameterBufferHEVC *seq_param = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
6888 VAEncPictureParameterBufferHEVC *pic_param = (VAEncPictureParameterBufferHEVC *)encode_state->pic_param_ext->buffer;
6889 VAEncSliceParameterBufferHEVC *slice_param = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[slice_idx]->buffer;
6890 unsigned char *slice_header = NULL;
6891 int slice_header_bits = 0;
6892
6893 slice_header_bits = build_hevc_slice_header(seq_param,
6894 pic_param,
6895 slice_param,
6896 &slice_header,
6897 0);
6898
6899 gen9_hevc_pak_insert_object((unsigned int *)slice_header, slice_header_bits,
6900 1, 1, 0, 5,
6901 batch);
6902
6903 free(slice_header);
6904 } else {
6905 param = (VAEncPackedHeaderParameterBuffer *)
6906 (encode_state->packed_header_params_ext[start_index]->buffer);
6907 header_data = (unsigned int *)encode_state->packed_header_data_ext[start_index]->buffer;
6908 length_in_bits = param->bit_length;
6909
6910 gen9_hevc_pak_insert_object(header_data, length_in_bits,
6911 !param->has_emulation_bytes, 1, 0, 0,
6912 batch);
6913 }
6914 }
6915
6916 static VAStatus
gen9_hevc_pak_slice_level(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context,int slice_idx)6917 gen9_hevc_pak_slice_level(VADriverContextP ctx,
6918 struct encode_state *encode_state,
6919 struct intel_encoder_context *encoder_context,
6920 int slice_idx)
6921 {
6922 struct intel_batchbuffer *batch = encoder_context->base.batch;
6923 struct encoder_vme_mfc_context *pak_context = NULL;
6924 struct gen9_hevc_encoder_context *priv_ctx = NULL;
6925 struct generic_enc_codec_state *generic_state = NULL;
6926 struct gen9_hevc_encoder_state *priv_state = NULL;
6927 VAEncSliceParameterBufferHEVC *slice_param = NULL;
6928 struct intel_batchbuffer *slice_batch = NULL;
6929 struct gpe_mi_batch_buffer_start_parameter second_level_batch;
6930 VAStatus va_status = VA_STATUS_SUCCESS;
6931 int slice_offset = 0;
6932
6933 pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
6934 priv_ctx = (struct gen9_hevc_encoder_context *)pak_context->private_enc_ctx;
6935 generic_state = (struct generic_enc_codec_state *)pak_context->generic_enc_state;
6936 priv_state = (struct gen9_hevc_encoder_state *)pak_context->private_enc_state;
6937 slice_param = (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[slice_idx]->buffer;
6938
6939 slice_batch = priv_ctx->res_pak_slice_batch_buffer;
6940
6941 if (generic_state->curr_pak_pass == 0) {
6942 slice_offset = intel_batchbuffer_used_size(slice_batch);
6943 priv_state->slice_batch_offset[slice_idx] = slice_offset;
6944
6945 if (slice_idx < encode_state->num_slice_params_ext - 1)
6946 priv_state->slice_start_lcu[slice_idx + 1] =
6947 priv_state->slice_start_lcu[slice_idx] +
6948 slice_param->num_ctu_in_slice;
6949
6950 gen9_hevc_pak_add_refs(ctx, encode_state, encoder_context,
6951 slice_idx, slice_batch);
6952 gen9_hevc_pak_add_slice_state(ctx, encode_state, encoder_context,
6953 slice_idx, slice_batch);
6954
6955 if (slice_idx == 0)
6956 gen9_hevc_pak_insert_packed_data(ctx, encode_state, encoder_context,
6957 slice_idx, slice_batch);
6958
6959 gen9_hevc_pak_insert_slice_header(ctx, encode_state, encoder_context,
6960 slice_idx, slice_batch);
6961
6962 BEGIN_BCS_BATCH(slice_batch, 2);
6963 OUT_BCS_BATCH(slice_batch, 0);
6964 OUT_BCS_BATCH(slice_batch, MI_BATCH_BUFFER_END);
6965 ADVANCE_BCS_BATCH(slice_batch);
6966 } else
6967 slice_offset = priv_state->slice_batch_offset[slice_idx];
6968
6969 memset(&second_level_batch, 0, sizeof(second_level_batch));
6970 second_level_batch.offset = slice_offset;
6971 second_level_batch.is_second_level = 1;
6972 second_level_batch.bo = slice_batch->buffer;
6973 gen8_gpe_mi_batch_buffer_start(ctx, batch, &second_level_batch);
6974
6975 memset(&second_level_batch, 0, sizeof(second_level_batch));
6976 second_level_batch.offset = priv_state->slice_start_lcu[slice_idx] *
6977 priv_state->pak_obj_size;
6978 second_level_batch.is_second_level = 1;
6979 second_level_batch.bo = priv_ctx->res_mb_code_surface.bo;
6980 gen8_gpe_mi_batch_buffer_start(ctx, batch, &second_level_batch);
6981
6982 return va_status;
6983 }
6984
6985 static VAStatus
gen9_hevc_pak_pipeline_prepare(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)6986 gen9_hevc_pak_pipeline_prepare(VADriverContextP ctx,
6987 struct encode_state *encode_state,
6988 struct intel_encoder_context *encoder_context)
6989 {
6990 struct i965_driver_data *i965 = i965_driver_data(ctx);
6991 struct encoder_vme_mfc_context *pak_context = NULL;
6992 struct gen9_hevc_encoder_context *priv_ctx = NULL;
6993 struct gen9_hevc_encoder_state *priv_state = NULL;
6994 struct gen9_hevc_surface_priv *surface_priv;
6995 VAEncPictureParameterBufferHEVC *pic_param = NULL;
6996 struct i965_coded_buffer_segment *coded_buffer_segment = NULL;
6997 struct object_surface *obj_surface = NULL;
6998 struct object_buffer *obj_buffer = NULL;
6999 dri_bo *bo = NULL;
7000 int i = 0;
7001
7002 pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
7003 priv_ctx = (struct gen9_hevc_encoder_context *)pak_context->private_enc_ctx;
7004 priv_state = (struct gen9_hevc_encoder_state *)pak_context->private_enc_state;
7005 pic_param = (VAEncPictureParameterBufferHEVC *)encode_state->pic_param_ext->buffer;
7006
7007 dri_bo_unreference(priv_ctx->uncompressed_picture_source.obj_surface_bo);
7008 priv_ctx->uncompressed_picture_source.obj_surface = encode_state->input_yuv_object;
7009 priv_ctx->uncompressed_picture_source.surface_id = encoder_context->input_yuv_surface;
7010 priv_ctx->uncompressed_picture_source.obj_surface_bo = encode_state->input_yuv_object->bo;
7011 dri_bo_reference(priv_ctx->uncompressed_picture_source.obj_surface_bo);
7012
7013 dri_bo_unreference(priv_ctx->reconstructed_object.obj_surface_bo);
7014 priv_ctx->reconstructed_object.obj_surface = encode_state->reconstructed_object;
7015 priv_ctx->reconstructed_object.surface_id = pic_param->decoded_curr_pic.picture_id;
7016 priv_ctx->reconstructed_object.obj_surface_bo = encode_state->reconstructed_object->bo;
7017 dri_bo_reference(priv_ctx->reconstructed_object.obj_surface_bo);
7018
7019 surface_priv = (struct gen9_hevc_surface_priv *)encode_state->reconstructed_object->private_data;
7020 if (surface_priv) {
7021 if (priv_ctx->mv_temporal_buffer[GEN9_MAX_MV_TEMPORAL_BUFFERS - 1].bo)
7022 dri_bo_unreference(priv_ctx->mv_temporal_buffer[GEN9_MAX_MV_TEMPORAL_BUFFERS - 1].bo);
7023 priv_ctx->mv_temporal_buffer[GEN9_MAX_MV_TEMPORAL_BUFFERS - 1].bo =
7024 surface_priv->motion_vector_temporal_bo;
7025 dri_bo_reference(surface_priv->motion_vector_temporal_bo);
7026 }
7027
7028 if (priv_state->picture_coding_type != HEVC_SLICE_I) {
7029 for (i = 0; i < GEN9_MAX_REF_SURFACES; i++) {
7030 obj_surface = encode_state->reference_objects[i];
7031 if (obj_surface && obj_surface->bo) {
7032 dri_bo_unreference(priv_ctx->reference_surfaces[i].obj_surface_bo);
7033 priv_ctx->reference_surfaces[i].obj_surface = obj_surface;
7034 priv_ctx->reference_surfaces[i].surface_id = pic_param->reference_frames[i].picture_id;
7035 priv_ctx->reference_surfaces[i].obj_surface_bo = obj_surface->bo;
7036 dri_bo_reference(priv_ctx->reference_surfaces[i].obj_surface_bo);
7037
7038 surface_priv = (struct gen9_hevc_surface_priv *) obj_surface->private_data;
7039 if (surface_priv) {
7040 if (priv_ctx->mv_temporal_buffer[i].bo)
7041 dri_bo_unreference(priv_ctx->mv_temporal_buffer[i].bo);
7042 priv_ctx->mv_temporal_buffer[i].bo = surface_priv->motion_vector_temporal_bo;
7043 dri_bo_reference(surface_priv->motion_vector_temporal_bo);
7044 }
7045 } else {
7046 break;
7047 }
7048 }
7049 }
7050
7051 obj_buffer = encode_state->coded_buf_object;
7052 bo = obj_buffer->buffer_store->bo;
7053
7054 if (priv_ctx->indirect_pak_bse_object.bo)
7055 dri_bo_unreference(priv_ctx->indirect_pak_bse_object.bo);
7056 priv_ctx->indirect_pak_bse_object.offset = I965_CODEDBUFFER_HEADER_SIZE;
7057 priv_ctx->indirect_pak_bse_object.end_offset = ALIGN((obj_buffer->size_element - 0x1000), 0x1000);
7058 priv_ctx->indirect_pak_bse_object.bo = bo;
7059 dri_bo_reference(priv_ctx->indirect_pak_bse_object.bo);
7060
7061 dri_bo_map(bo, 1);
7062
7063 if (!bo->virtual)
7064 return VA_STATUS_ERROR_INVALID_VALUE;
7065
7066 coded_buffer_segment = (struct i965_coded_buffer_segment *)bo->virtual;
7067 coded_buffer_segment->mapped = 0;
7068 coded_buffer_segment->codec = encoder_context->codec;
7069 coded_buffer_segment->status_support = 1;
7070
7071 dri_bo_unmap(bo);
7072
7073 if (priv_ctx->res_pak_slice_batch_buffer)
7074 intel_batchbuffer_free(priv_ctx->res_pak_slice_batch_buffer);
7075
7076 priv_ctx->res_pak_slice_batch_buffer =
7077 intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD,
7078 GEN9_HEVC_ENC_PAK_SLICE_STATE_SIZE *
7079 encode_state->num_slice_params_ext);
7080 if (!priv_ctx->res_pak_slice_batch_buffer)
7081 return VA_STATUS_ERROR_ALLOCATION_FAILED;
7082
7083 for (i = 0; i < I965_MAX_NUM_SLICE; i++) {
7084 priv_state->slice_batch_offset[i] = 0;
7085 priv_state->slice_start_lcu[i] = 0;
7086 }
7087
7088 return VA_STATUS_SUCCESS;
7089 }
7090
7091 static VAStatus
gen9_hevc_pak_picture_level(VADriverContextP ctx,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)7092 gen9_hevc_pak_picture_level(VADriverContextP ctx,
7093 struct encode_state *encode_state,
7094 struct intel_encoder_context *encoder_context)
7095 {
7096 struct intel_batchbuffer *batch = encoder_context->base.batch;
7097 struct encoder_vme_mfc_context *pak_context = NULL;
7098 struct gen9_hevc_encoder_context *priv_ctx = NULL;
7099 struct generic_enc_codec_state *generic_state = NULL;
7100 struct gen9_hevc_encoder_state *priv_state = NULL;
7101 struct gpe_mi_batch_buffer_start_parameter second_level_batch;
7102 struct hevc_encode_status_buffer *status_buffer = NULL;
7103 VAStatus va_status = VA_STATUS_SUCCESS;
7104 int i = 0;
7105
7106 pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
7107 priv_ctx = (struct gen9_hevc_encoder_context *)pak_context->private_enc_ctx;
7108 generic_state = (struct generic_enc_codec_state *)pak_context->generic_enc_state;
7109 priv_state = (struct gen9_hevc_encoder_state *)pak_context->private_enc_state;
7110 status_buffer = &priv_state->status_buffer;
7111
7112 if (generic_state->brc_enabled &&
7113 generic_state->curr_pak_pass) {
7114 gen9_hevc_conditional_end(ctx,
7115 batch, status_buffer->bo,
7116 status_buffer->status_image_mask_offset,
7117 0);
7118
7119 gen9_hevc_load_reg_mem(ctx,
7120 batch, status_buffer->bo,
7121 status_buffer->status_image_ctrl_offset,
7122 status_buffer->mmio_image_ctrl_offset);
7123
7124 gen9_hevc_store_reg_mem(ctx, batch, priv_ctx->res_brc_pak_statistic_buffer.bo,
7125 offsetof(GEN9_HEVC_PAK_STATES, HEVC_ENC_IMAGE_STATUS_CONTROL_FOR_LAST_PASS),
7126 status_buffer->mmio_image_ctrl_offset);
7127
7128 gen9_hevc_store_reg_mem(ctx, batch, status_buffer->bo,
7129 status_buffer->status_image_ctrl_last_pass_offset,
7130 status_buffer->mmio_image_ctrl_offset);
7131 }
7132
7133 gen9_hevc_pak_pipe_mode_select(ctx, encode_state, encoder_context);
7134 gen9_hevc_pak_add_surface_state(ctx, encode_state, encoder_context,
7135 encode_state->input_yuv_object,
7136 GEN9_HEVC_ENC_SURFACE_SOURCE);
7137 gen9_hevc_pak_add_surface_state(ctx, encode_state, encoder_context,
7138 encode_state->reconstructed_object,
7139 GEN9_HEVC_ENC_SURFACE_RECON);
7140 gen9_hevc_pak_add_pipe_buf_addr_state(ctx, encode_state, encoder_context);
7141 gen9_hevc_pak_add_ind_obj_base_addr_state(ctx, encode_state, encoder_context);
7142 gen9_hevc_pak_add_qm_state(ctx, encode_state, encoder_context);
7143 gen9_hevc_pak_add_fm_state(ctx, encode_state, encoder_context);
7144
7145 if (generic_state->brc_enabled) {
7146 memset(&second_level_batch, 0, sizeof(second_level_batch));
7147
7148 second_level_batch.offset = generic_state->curr_pak_pass * priv_state->pic_state_size;
7149 second_level_batch.bo = priv_ctx->res_brc_pic_states_write_buffer.bo;
7150 second_level_batch.is_second_level = 1;
7151 gen8_gpe_mi_batch_buffer_start(ctx, batch, &second_level_batch);
7152 } else
7153 gen9_hevc_add_pic_state(ctx, encode_state, encoder_context, NULL, 0, 0);
7154
7155 for (i = 0; i < encode_state->num_slice_params_ext; i++) {
7156 va_status = gen9_hevc_pak_slice_level(ctx, encode_state, encoder_context, i);
7157 if (va_status != VA_STATUS_SUCCESS)
7158 goto EXIT;
7159 }
7160
7161 EXIT:
7162 return va_status;
7163 }
7164
7165 static void
gen9_hevc_pak_read_status(VADriverContextP ctx,struct intel_encoder_context * encoder_context)7166 gen9_hevc_pak_read_status(VADriverContextP ctx,
7167 struct intel_encoder_context *encoder_context)
7168 {
7169 struct intel_batchbuffer *batch = encoder_context->base.batch;
7170 struct encoder_vme_mfc_context *pak_context = NULL;
7171 struct gen9_hevc_encoder_context *priv_ctx = NULL;
7172 struct generic_enc_codec_state *generic_state = NULL;
7173 struct gen9_hevc_encoder_state *priv_state = NULL;
7174 struct gpe_mi_flush_dw_parameter mi_flush_dw_param;
7175 struct hevc_encode_status_buffer *status_buffer = NULL;
7176
7177 pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
7178 priv_ctx = (struct gen9_hevc_encoder_context *)pak_context->private_enc_ctx;
7179 generic_state = (struct generic_enc_codec_state *)pak_context->generic_enc_state;
7180 priv_state = (struct gen9_hevc_encoder_state *)pak_context->private_enc_state;
7181
7182 status_buffer = &priv_state->status_buffer;
7183
7184 memset(&mi_flush_dw_param, 0, sizeof(mi_flush_dw_param));
7185 gen8_gpe_mi_flush_dw(ctx, batch, &mi_flush_dw_param);
7186
7187 gen9_hevc_store_reg_mem(ctx, batch, status_buffer->bo,
7188 status_buffer->status_bs_byte_count_offset,
7189 status_buffer->mmio_bs_frame_offset);
7190
7191 gen9_hevc_store_reg_mem(ctx, batch, status_buffer->bo,
7192 status_buffer->status_image_mask_offset,
7193 status_buffer->mmio_image_mask_offset);
7194
7195 gen9_hevc_store_reg_mem(ctx, batch, status_buffer->bo,
7196 status_buffer->status_image_ctrl_offset,
7197 status_buffer->mmio_image_ctrl_offset);
7198
7199 if (generic_state->brc_enabled) {
7200 gen9_hevc_store_reg_mem(ctx, batch, priv_ctx->res_brc_pak_statistic_buffer.bo,
7201 offsetof(GEN9_HEVC_PAK_STATES, HEVC_ENC_BYTECOUNT_FRAME),
7202 status_buffer->mmio_bs_frame_offset);
7203 gen9_hevc_store_reg_mem(ctx, batch, priv_ctx->res_brc_pak_statistic_buffer.bo,
7204 offsetof(GEN9_HEVC_PAK_STATES, HEVC_ENC_BYTECOUNT_FRAME_NOHEADER),
7205 status_buffer->mmio_bs_frame_no_header_offset);
7206 gen9_hevc_store_reg_mem(ctx, batch, priv_ctx->res_brc_pak_statistic_buffer.bo,
7207 offsetof(GEN9_HEVC_PAK_STATES, HEVC_ENC_IMAGE_STATUS_CONTROL),
7208 status_buffer->mmio_image_ctrl_offset);
7209 }
7210
7211 gen8_gpe_mi_flush_dw(ctx, batch, &mi_flush_dw_param);
7212 }
7213
7214 static VAStatus
gen9_hevc_pak_pipeline(VADriverContextP ctx,VAProfile profile,struct encode_state * encode_state,struct intel_encoder_context * encoder_context)7215 gen9_hevc_pak_pipeline(VADriverContextP ctx,
7216 VAProfile profile,
7217 struct encode_state *encode_state,
7218 struct intel_encoder_context *encoder_context)
7219 {
7220 struct i965_driver_data *i965 = i965_driver_data(ctx);
7221 struct intel_batchbuffer *batch = encoder_context->base.batch;
7222 struct encoder_vme_mfc_context *pak_context = encoder_context->vme_context;
7223 struct gen9_hevc_encoder_context *priv_ctx = NULL;
7224 struct generic_enc_codec_state *generic_state = NULL;
7225 struct gen9_hevc_encoder_state *priv_state = NULL;
7226 VAStatus va_status = VA_STATUS_SUCCESS;
7227
7228 if (!pak_context || !pak_context->generic_enc_state || !batch) {
7229 va_status = VA_STATUS_ERROR_INVALID_CONTEXT;
7230 goto EXIT;
7231 }
7232
7233 va_status = gen9_hevc_pak_pipeline_prepare(ctx, encode_state, encoder_context);
7234 if (va_status != VA_STATUS_SUCCESS)
7235 goto EXIT;
7236
7237 if (i965->intel.has_bsd2)
7238 intel_batchbuffer_start_atomic_bcs_override(batch, 0x1000, BSD_RING0);
7239 else
7240 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
7241
7242 intel_batchbuffer_emit_mi_flush(batch);
7243
7244 generic_state = (struct generic_enc_codec_state *)pak_context->generic_enc_state;
7245 priv_state = (struct gen9_hevc_encoder_state *)pak_context->private_enc_state;
7246 priv_ctx = (struct gen9_hevc_encoder_context *)pak_context->private_enc_ctx;
7247
7248 for (generic_state->curr_pak_pass = 0;
7249 generic_state->curr_pak_pass < generic_state->num_pak_passes;
7250 generic_state->curr_pak_pass++) {
7251 va_status = gen9_hevc_pak_picture_level(ctx, encode_state, encoder_context);
7252 if (va_status != VA_STATUS_SUCCESS)
7253 goto EXIT;
7254
7255 gen9_hevc_pak_read_status(ctx, encoder_context);
7256 }
7257
7258 if (priv_ctx->res_pak_slice_batch_buffer) {
7259 intel_batchbuffer_free(priv_ctx->res_pak_slice_batch_buffer);
7260
7261 priv_ctx->res_pak_slice_batch_buffer = NULL;
7262 }
7263
7264 intel_batchbuffer_end_atomic(batch);
7265
7266 intel_batchbuffer_flush(batch);
7267
7268 priv_state->frame_number++;
7269
7270 EXIT:
7271 return va_status;
7272 }
7273
7274 static void
gen9_hevc_pak_context_destroy(void * context)7275 gen9_hevc_pak_context_destroy(void *context)
7276 {
7277 struct encoder_vme_mfc_context *pak_context = (struct encoder_vme_mfc_context *)context;
7278 struct gen9_hevc_encoder_context *priv_ctx = NULL;
7279 int i = 0;
7280
7281 priv_ctx = (struct gen9_hevc_encoder_context *)pak_context->private_enc_ctx;
7282
7283 if (priv_ctx->res_pak_slice_batch_buffer) {
7284 intel_batchbuffer_free(priv_ctx->res_pak_slice_batch_buffer);
7285 priv_ctx->res_pak_slice_batch_buffer = NULL;
7286 }
7287
7288 dri_bo_unreference(priv_ctx->indirect_pak_bse_object.bo);
7289 priv_ctx->indirect_pak_bse_object.bo = NULL;
7290
7291 dri_bo_unreference(priv_ctx->uncompressed_picture_source.obj_surface_bo);
7292 priv_ctx->uncompressed_picture_source.obj_surface_bo = NULL;
7293 dri_bo_unreference(priv_ctx->reconstructed_object.obj_surface_bo);
7294 priv_ctx->reconstructed_object.obj_surface_bo = NULL;
7295
7296 for (i = 0; i < GEN9_MAX_REF_SURFACES; i++) {
7297 dri_bo_unreference(priv_ctx->reference_surfaces[i].obj_surface_bo);
7298 priv_ctx->reference_surfaces[i].obj_surface_bo = NULL;
7299 }
7300 }
7301
7302 #define STATUS_IMPLEMENTATION_START
7303
7304 static void
gen9_hevc_status_buffer_init(struct hevc_encode_status_buffer * status_buffer)7305 gen9_hevc_status_buffer_init(struct hevc_encode_status_buffer *status_buffer)
7306 {
7307 uint32_t base_offset = offsetof(struct i965_coded_buffer_segment, codec_private_data);
7308
7309 status_buffer->mmio_bs_frame_offset = MMIO_HCP_ENC_BITSTREAM_BYTECOUNT_FRAME_OFFSET;
7310 status_buffer->mmio_bs_frame_no_header_offset = MMIO_HCP_ENC_BITSTREAM_BYTECOUNT_FRAME_NO_HEADER_OFFSET;
7311 status_buffer->mmio_image_mask_offset = MMIO_HCP_ENC_IMAGE_STATUS_MASK_OFFSET;
7312 status_buffer->mmio_image_ctrl_offset = MMIO_HCP_ENC_IMAGE_STATUS_CTRL_OFFSET;
7313
7314 status_buffer->status_image_mask_offset = base_offset +
7315 offsetof(struct hevc_encode_status, image_status_mask);
7316 status_buffer->status_image_ctrl_offset = base_offset +
7317 offsetof(struct hevc_encode_status, image_status_ctrl);
7318 status_buffer->status_image_ctrl_last_pass_offset = base_offset +
7319 offsetof(struct hevc_encode_status, image_status_ctrl_last_pass);
7320 status_buffer->status_bs_byte_count_offset = base_offset +
7321 offsetof(struct hevc_encode_status, bs_byte_count);
7322 status_buffer->status_media_state_offset = base_offset +
7323 offsetof(struct hevc_encode_status, media_state);
7324 status_buffer->status_pass_num_offset = base_offset +
7325 offsetof(struct hevc_encode_status, pass_num);
7326 }
7327
7328 static VAStatus
gen9_hevc_get_coded_status(VADriverContextP ctx,struct intel_encoder_context * encoder_context,struct i965_coded_buffer_segment * coded_buf_seg)7329 gen9_hevc_get_coded_status(VADriverContextP ctx,
7330 struct intel_encoder_context *encoder_context,
7331 struct i965_coded_buffer_segment *coded_buf_seg)
7332 {
7333 struct hevc_encode_status *encode_status;
7334 struct hevc_enc_image_status_ctrl *image_status_ctrl, *image_status_ctrl_last_pass;
7335
7336 if (!encoder_context || !coded_buf_seg)
7337 return VA_STATUS_ERROR_INVALID_BUFFER;
7338
7339 encode_status = (struct hevc_encode_status *)coded_buf_seg->codec_private_data;
7340
7341 coded_buf_seg->base.size = encode_status->bs_byte_count;
7342
7343 image_status_ctrl = (struct hevc_enc_image_status_ctrl *)&encode_status->image_status_ctrl;
7344 image_status_ctrl_last_pass = (struct hevc_enc_image_status_ctrl *)&encode_status->image_status_ctrl_last_pass;
7345
7346 if (image_status_ctrl->total_pass && image_status_ctrl->cumulative_frame_delta_qp == 0)
7347 image_status_ctrl->cumulative_frame_delta_qp = image_status_ctrl_last_pass->cumulative_frame_delta_qp;
7348
7349 image_status_ctrl_last_pass->cumulative_frame_delta_qp = 0;
7350
7351 return VA_STATUS_SUCCESS;
7352 }
7353
7354 // External initial APIs
7355
7356 Bool
gen9_hevc_vme_context_init(VADriverContextP ctx,struct intel_encoder_context * encoder_context)7357 gen9_hevc_vme_context_init(VADriverContextP ctx,
7358 struct intel_encoder_context *encoder_context)
7359 {
7360 struct i965_driver_data *i965 = i965_driver_data(ctx);
7361 struct encoder_vme_mfc_context *vme_context = NULL;
7362 struct gen9_hevc_encoder_context *priv_ctx = NULL;
7363 struct generic_enc_codec_state *generic_state = NULL;
7364 struct gen9_hevc_encoder_state *priv_state = NULL;
7365
7366 hevc_enc_kernel_ptr = (void *)gen9_hevc_encoder_kernels;
7367 hevc_enc_kernel_size = sizeof(gen9_hevc_encoder_kernels);
7368
7369 vme_context = calloc(1, sizeof(*vme_context));
7370 priv_ctx = calloc(1, sizeof(*priv_ctx));
7371 generic_state = calloc(1, sizeof(*generic_state));
7372 priv_state = calloc(1, sizeof(*priv_state));
7373
7374 if (!vme_context || !generic_state ||
7375 !priv_ctx || !priv_state) {
7376 if (vme_context) free(vme_context);
7377 if (generic_state) free(generic_state);
7378 if (priv_ctx) free(priv_ctx);
7379 if (priv_state) free(priv_state);
7380
7381 return false;
7382 }
7383
7384 encoder_context->vme_context = (void *)vme_context;
7385 vme_context->private_enc_ctx = (void *)priv_ctx;
7386 vme_context->generic_enc_state = (void *)generic_state;
7387 vme_context->private_enc_state = (void *)priv_state;
7388
7389 priv_ctx->ctx = ctx;
7390 priv_ctx->mocs = i965->intel.mocs_state;
7391
7392 generic_state->num_pak_passes = 1;
7393 generic_state->brc_enabled = 0;
7394
7395 priv_state->tu_mode = HEVC_TU_RT_SPEED;
7396 priv_state->use_hw_scoreboard = 1;
7397 priv_state->use_hw_non_stalling_scoreborad = 1;
7398 priv_state->rolling_intra_refresh = 0;
7399 priv_state->flatness_check_supported = 0;
7400 priv_state->walking_pattern_26 = 0;
7401 priv_state->num_regions_in_slice = 4;
7402 priv_state->frames_per_100s = 30000;
7403 priv_state->user_max_frame_size = 0;
7404 priv_state->brc_method = HEVC_BRC_CQP;
7405 priv_state->lcu_brc_enabled = 0;
7406 priv_state->parallel_brc = 0;
7407 priv_state->pak_obj_size = ((IS_KBL(i965->intel.device_info) || IS_GLK(i965->intel.device_info)) ?
7408 GEN95_HEVC_ENC_PAK_OBJ_SIZE :
7409 GEN9_HEVC_ENC_PAK_OBJ_SIZE) *
7410 4;
7411 priv_state->cu_record_size = GEN9_HEVC_ENC_PAK_CU_RECORD_SIZE * 4;
7412 priv_state->pic_state_size = GEN9_HEVC_ENC_BRC_PIC_STATE_SIZE;
7413
7414 gen9_hevc_status_buffer_init(&priv_state->status_buffer);
7415 gen9_hevc_vme_kernels_context_init(ctx, encoder_context);
7416 gen9_hevc_lambda_tables_init(priv_ctx);
7417
7418 encoder_context->vme_pipeline = gen9_hevc_vme_pipeline;
7419 encoder_context->vme_context_destroy = gen9_hevc_vme_context_destroy;
7420 return true;
7421 }
7422
7423 Bool
gen9_hevc_pak_context_init(VADriverContextP ctx,struct intel_encoder_context * encoder_context)7424 gen9_hevc_pak_context_init(VADriverContextP ctx,
7425 struct intel_encoder_context *encoder_context)
7426 {
7427 struct encoder_vme_mfc_context *pak_context = encoder_context->vme_context;
7428
7429 if (!pak_context)
7430 return false;
7431
7432 encoder_context->mfc_context = pak_context;
7433 encoder_context->mfc_context_destroy = gen9_hevc_pak_context_destroy;
7434 encoder_context->mfc_pipeline = gen9_hevc_pak_pipeline;
7435 encoder_context->mfc_brc_prepare = gen9_hevc_brc_prepare;
7436 encoder_context->get_status = gen9_hevc_get_coded_status;
7437 return true;
7438 }
7439