1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Midhunchandra Kodiyath <midhunchandra.kodiyath@intel.com> 26 * 27 */ 28 29 #ifndef _MEDIA__DRIVER_H 30 #define _MEDIA__DRIVER_H 31 #include <va/va_backend.h> 32 #include "media_drv_util.h" 33 #include "media_drv_defines.h" 34 #include "media_drv_init.h" 35 #include "va_backend_compat.h" 36 37 38 #define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* Desktop */ 39 #define PCI_CHIP_IVYBRIDGE_GT2 0x0162 40 #define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* Mobile */ 41 #define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166 42 #define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a /* Server */ 43 #define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a 44 #define PCI_CHIP_BAYTRAIL_M_1 0x0F31 45 #define PCI_CHIP_BAYTRAIL_M_2 0x0F32 46 #define PCI_CHIP_BAYTRAIL_M_3 0x0F33 47 #define PCI_CHIP_BAYTRAIL_M_4 0x0157 48 #define PCI_CHIP_BAYTRAIL_D 0x0155 49 50 51 #define CONFIG_ID_OFFSET 0x01000000 52 #define CONTEXT_ID_OFFSET 0x02000000 53 #define SURFACE_ID_OFFSET 0x04000000 54 #define BUFFER_ID_OFFSET 0x08000000 55 #define IMAGE_ID_OFFSET 0x0a000000 56 #define SUBPIC_ID_OFFSET 0x10000000 57 #define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */ 58 #define PCI_CHIP_HASWELL_GT2 0x0412 59 #define PCI_CHIP_HASWELL_GT3 0x0422 60 #define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */ 61 #define PCI_CHIP_HASWELL_M_GT2 0x0416 62 #define PCI_CHIP_HASWELL_M_GT3 0x0426 63 #define PCI_CHIP_HASWELL_S_GT1 0x040a /* Server */ 64 #define PCI_CHIP_HASWELL_S_GT2 0x041a 65 #define PCI_CHIP_HASWELL_S_GT3 0x042a 66 #define PCI_CHIP_HASWELL_B_GT1 0x040b /* Reserved */ 67 #define PCI_CHIP_HASWELL_B_GT2 0x041b 68 #define PCI_CHIP_HASWELL_B_GT3 0x042b 69 #define PCI_CHIP_HASWELL_E_GT1 0x040e /* Reserved */ 70 #define PCI_CHIP_HASWELL_E_GT2 0x041e 71 #define PCI_CHIP_HASWELL_E_GT3 0x042e 72 73 #define PCI_CHIP_HASWELL_SDV_GT1 0x0c02 /* Desktop */ 74 #define PCI_CHIP_HASWELL_SDV_GT2 0x0c12 75 #define PCI_CHIP_HASWELL_SDV_GT3 0x0c22 76 #define PCI_CHIP_HASWELL_SDV_M_GT1 0x0c06 /* Mobile */ 77 #define PCI_CHIP_HASWELL_SDV_M_GT2 0x0c16 78 #define PCI_CHIP_HASWELL_SDV_M_GT3 0x0c26 79 #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0c0a /* Server */ 80 #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0c1a 81 #define PCI_CHIP_HASWELL_SDV_S_GT3 0x0c2a 82 #define PCI_CHIP_HASWELL_SDV_B_GT1 0x0c0b /* Reserved */ 83 #define PCI_CHIP_HASWELL_SDV_B_GT2 0x0c1b 84 #define PCI_CHIP_HASWELL_SDV_B_GT3 0x0c2b 85 #define PCI_CHIP_HASWELL_SDV_E_GT1 0x0c0e /* Reserved */ 86 #define PCI_CHIP_HASWELL_SDV_E_GT2 0x0c1e 87 #define PCI_CHIP_HASWELL_SDV_E_GT3 0x0c2e 88 89 #define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */ 90 #define PCI_CHIP_HASWELL_ULT_GT2 0x0A12 91 #define PCI_CHIP_HASWELL_ULT_GT3 0x0A22 92 #define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */ 93 #define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16 94 #define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26 95 #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */ 96 #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A 97 #define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A 98 #define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B /* Reserved */ 99 #define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B 100 #define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B 101 #define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E /* Reserved */ 102 #define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E 103 #define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E 104 105 #define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */ 106 #define PCI_CHIP_HASWELL_CRW_GT2 0x0D12 107 #define PCI_CHIP_HASWELL_CRW_GT3 0x0D22 108 #define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */ 109 #define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16 110 #define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26 111 #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */ 112 #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A 113 #define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A 114 #define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B /* Reserved */ 115 #define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B 116 #define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B 117 #define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E /* Reserved */ 118 #define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E 119 #define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E 120 121 #define PCI_CHIP_SKYLAKE_GT1_DESK 0x0901 122 #define PCI_CHIP_SKYLAKE_GT2_DESK 0x0902 123 #define PCI_CHIP_SKYLAKE_GT4_DT 0x1932 124 #define PCI_CHIP_SKYLAKE_GT2_DT 0x1912 125 #define PCI_CHIP_SKYLAKE_GT1_5_DT 0x1917 126 #define PCI_CHIP_SKYLAKE_GT1_DT 0x1902 127 #define PCI_CHIP_SKYLAKE_GT3_DESK 0x0903 128 #define PCI_CHIP_SKYLAKE_GT4_DESK 0x0904 129 #define PCI_CHIP_SKYLAKE_GT2_ULT 0x1916 130 #define PCI_CHIP_SKYLAKE_GT2F_ULT 0x1921 131 #define PCI_CHIP_SKYLAKE_GT2_ULX 0x191E 132 #define PCI_CHIP_SKYLAKE_GT1_ULT 0x1906 133 #define PCI_CHIP_SKYLAKE_GT1_ULX 0x190E 134 #define PCI_CHIP_SKYLAKE_GT1_5_ULT 0x1913 135 #define PCI_CHIP_SKYLAKE_GT1_5_ULX 0x1915 136 #define PCI_CHIP_SKYLAKE_GT3_ULT 0x1926 137 #define PCI_CHIP_SKYLAKE_GT1_HALO_MOBL 0x190B 138 #define PCI_CHIP_SKYLAKE_GT2_HALO_MOBL 0x191B 139 #define PCI_CHIP_SKYLAKE_GT3_HALO_MOBL 0x192B 140 #define PCI_CHIP_SKYLAKE_GT4_HALO_MOBL 0x193B 141 #define PCI_CHIP_SKYLAKE_GT1_SERV 0x190A 142 #define PCI_CHIP_SKYLAKE_GT2_SERV 0x191A 143 #define PCI_CHIP_SKYLAKE_GT3_SERV 0x192A 144 #define PCI_CHIP_SKYLAKE_GT4_SERV 0x193A 145 #define PCI_CHIP_SKYLAKE_GT2_WRK 0x191D 146 #define PCI_CHIP_SKYLAKE_GT4_WRK 0x193D 147 148 #define IS_BAYTRAIL_M1(devid) (devid == PCI_CHIP_BAYTRAIL_M_1) 149 #define IS_BAYTRAIL_M2(devid) (devid == PCI_CHIP_BAYTRAIL_M_2) 150 #define IS_BAYTRAIL_M3(devid) (devid == PCI_CHIP_BAYTRAIL_M_3) 151 #define IS_BAYTRAIL_D(devid) (devid == PCI_CHIP_BAYTRAIL_D) 152 #define IS_BAYTRAIL(devid) (IS_BAYTRAIL_M1(devid) || \ 153 IS_BAYTRAIL_M2(devid) || \ 154 IS_BAYTRAIL_M3(devid) || \ 155 IS_BAYTRAIL_D(devid) ) 156 157 #define IS_IVB_GT1(devid) (devid == PCI_CHIP_IVYBRIDGE_GT1 || \ 158 devid == PCI_CHIP_IVYBRIDGE_M_GT1 || \ 159 devid == PCI_CHIP_IVYBRIDGE_S_GT1) 160 161 #define IS_IVB_GT2(devid) (devid == PCI_CHIP_IVYBRIDGE_GT2 || \ 162 devid == PCI_CHIP_IVYBRIDGE_M_GT2 || \ 163 devid == PCI_CHIP_IVYBRIDGE_S_GT2) 164 165 #define IS_IVYBRIDGE(devid) (IS_IVB_GT1(devid) || \ 166 IS_IVB_GT2(devid) || \ 167 IS_BAYTRAIL(devid) ) 168 169 #define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \ 170 devid == PCI_CHIP_HASWELL_M_GT1 || \ 171 devid == PCI_CHIP_HASWELL_S_GT1 || \ 172 devid == PCI_CHIP_HASWELL_B_GT1 || \ 173 devid == PCI_CHIP_HASWELL_E_GT1 || \ 174 devid == PCI_CHIP_HASWELL_SDV_GT1 || \ 175 devid == PCI_CHIP_HASWELL_SDV_M_GT1 || \ 176 devid == PCI_CHIP_HASWELL_SDV_S_GT1 || \ 177 devid == PCI_CHIP_HASWELL_SDV_B_GT1 || \ 178 devid == PCI_CHIP_HASWELL_SDV_E_GT1 || \ 179 devid == PCI_CHIP_HASWELL_CRW_GT1 || \ 180 devid == PCI_CHIP_HASWELL_CRW_M_GT1 || \ 181 devid == PCI_CHIP_HASWELL_CRW_S_GT1 || \ 182 devid == PCI_CHIP_HASWELL_CRW_B_GT1 || \ 183 devid == PCI_CHIP_HASWELL_CRW_E_GT1 || \ 184 devid == PCI_CHIP_HASWELL_ULT_GT1 || \ 185 devid == PCI_CHIP_HASWELL_ULT_M_GT1 || \ 186 devid == PCI_CHIP_HASWELL_ULT_S_GT1 || \ 187 devid == PCI_CHIP_HASWELL_ULT_B_GT1 || \ 188 devid == PCI_CHIP_HASWELL_ULT_E_GT1) 189 190 191 #define IS_HSW_GT2(devid) (devid == PCI_CHIP_HASWELL_GT2|| \ 192 devid == PCI_CHIP_HASWELL_M_GT2|| \ 193 devid == PCI_CHIP_HASWELL_S_GT2|| \ 194 devid == PCI_CHIP_HASWELL_B_GT2 || \ 195 devid == PCI_CHIP_HASWELL_E_GT2 || \ 196 devid == PCI_CHIP_HASWELL_SDV_GT2|| \ 197 devid == PCI_CHIP_HASWELL_SDV_M_GT2|| \ 198 devid == PCI_CHIP_HASWELL_SDV_S_GT2|| \ 199 devid == PCI_CHIP_HASWELL_SDV_B_GT2 || \ 200 devid == PCI_CHIP_HASWELL_SDV_E_GT2 || \ 201 devid == PCI_CHIP_HASWELL_CRW_GT2|| \ 202 devid == PCI_CHIP_HASWELL_CRW_M_GT2|| \ 203 devid == PCI_CHIP_HASWELL_CRW_S_GT2|| \ 204 devid == PCI_CHIP_HASWELL_CRW_B_GT2|| \ 205 devid == PCI_CHIP_HASWELL_CRW_E_GT2|| \ 206 devid == PCI_CHIP_HASWELL_ULT_GT2|| \ 207 devid == PCI_CHIP_HASWELL_ULT_M_GT2|| \ 208 devid == PCI_CHIP_HASWELL_ULT_S_GT2|| \ 209 devid == PCI_CHIP_HASWELL_ULT_B_GT2 || \ 210 devid == PCI_CHIP_HASWELL_ULT_E_GT2) 211 212 #define VA_INTEL_HYBRID_PRE_DUMP (1 << 2) 213 #define VA_INTEL_HYBRID_POST_DUMP (1 << 3) 214 215 #define IS_HSW_GT3(devid) (devid == PCI_CHIP_HASWELL_GT3 || \ 216 devid == PCI_CHIP_HASWELL_M_GT3 || \ 217 devid == PCI_CHIP_HASWELL_S_GT3 || \ 218 devid == PCI_CHIP_HASWELL_B_GT3 || \ 219 devid == PCI_CHIP_HASWELL_E_GT3 || \ 220 devid == PCI_CHIP_HASWELL_SDV_GT3 || \ 221 devid == PCI_CHIP_HASWELL_SDV_M_GT3 || \ 222 devid == PCI_CHIP_HASWELL_SDV_S_GT3 || \ 223 devid == PCI_CHIP_HASWELL_SDV_B_GT3 || \ 224 devid == PCI_CHIP_HASWELL_SDV_E_GT3 || \ 225 devid == PCI_CHIP_HASWELL_CRW_GT3 || \ 226 devid == PCI_CHIP_HASWELL_CRW_M_GT3 || \ 227 devid == PCI_CHIP_HASWELL_CRW_S_GT3 || \ 228 devid == PCI_CHIP_HASWELL_CRW_B_GT3 || \ 229 devid == PCI_CHIP_HASWELL_CRW_E_GT3 || \ 230 devid == PCI_CHIP_HASWELL_ULT_GT3 || \ 231 devid == PCI_CHIP_HASWELL_ULT_M_GT3 || \ 232 devid == PCI_CHIP_HASWELL_ULT_S_GT3 || \ 233 devid == PCI_CHIP_HASWELL_ULT_B_GT3 || \ 234 devid == PCI_CHIP_HASWELL_ULT_E_GT3) 235 236 #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \ 237 IS_HSW_GT2(devid) || \ 238 IS_HSW_GT3(devid)) 239 240 #define IS_GEN75(devid) (IS_HASWELL(devid)) 241 242 #define IS_GEN7(devid) (IS_IVYBRIDGE(devid)) 243 244 #define IS_BROADWELL(devid) (devid == 0x1602 || \ 245 devid == 0x1606 || \ 246 devid == 0x160A || \ 247 devid == 0x160B || \ 248 devid == 0x160D || \ 249 devid == 0x160E || \ 250 devid == 0x1612 || \ 251 devid == 0x1616 || \ 252 devid == 0x161A || \ 253 devid == 0x161B || \ 254 devid == 0x161D || \ 255 devid == 0x161E || \ 256 devid == 0x1622 || \ 257 devid == 0x1626 || \ 258 devid == 0x162A || \ 259 devid == 0x162B || \ 260 devid == 0x162D || \ 261 devid == 0x162E ) 262 263 #define IS_GEN8(devid) (IS_BROADWELL(devid)) 264 265 #define PCI_CHIP_CHV_0 0x22B0 266 #define PCI_CHIP_CHV_1 0x22B1 267 #define PCI_CHIP_CHV_2 0x22B2 268 #define PCI_CHIP_CHV_3 0x22B3 269 270 271 #define IS_CHERRYVIEW(devid) (devid == PCI_CHIP_CHV_0 || \ 272 devid == PCI_CHIP_CHV_1 || \ 273 devid == PCI_CHIP_CHV_2 || \ 274 devid == PCI_CHIP_CHV_3) 275 276 #define IS_SKL_GT1(devid) (devid == PCI_CHIP_SKYLAKE_GT1_DESK || \ 277 devid == PCI_CHIP_SKYLAKE_GT1_DT || \ 278 devid == PCI_CHIP_SKYLAKE_GT1_ULT || \ 279 devid == PCI_CHIP_SKYLAKE_GT1_ULX || \ 280 devid == PCI_CHIP_SKYLAKE_GT1_HALO_MOBL || \ 281 devid == PCI_CHIP_SKYLAKE_GT1_SERV) 282 283 #define IS_SKL_GT1_5(devid) (devid == PCI_CHIP_SKYLAKE_GT1_5_DT || \ 284 devid == PCI_CHIP_SKYLAKE_GT1_5_ULT || \ 285 devid == PCI_CHIP_SKYLAKE_GT1_5_ULX) 286 287 #define IS_SKL_GT2(devid) (devid == PCI_CHIP_SKYLAKE_GT2_DESK || \ 288 devid == PCI_CHIP_SKYLAKE_GT2_DT || \ 289 devid == PCI_CHIP_SKYLAKE_GT2_ULT || \ 290 devid == PCI_CHIP_SKYLAKE_GT2F_ULT || \ 291 devid == PCI_CHIP_SKYLAKE_GT2_ULX || \ 292 devid == PCI_CHIP_SKYLAKE_GT2_HALO_MOBL || \ 293 devid == PCI_CHIP_SKYLAKE_GT2_SERV || \ 294 devid == PCI_CHIP_SKYLAKE_GT2_WRK) 295 296 #define IS_SKL_GT3(devid) (devid == PCI_CHIP_SKYLAKE_GT3_DESK || \ 297 devid == PCI_CHIP_SKYLAKE_GT3_ULT || \ 298 devid == PCI_CHIP_SKYLAKE_GT3_HALO_MOBL || \ 299 devid == PCI_CHIP_SKYLAKE_GT3_SERV) 300 301 #define IS_SKL_GT4(devid) (devid == PCI_CHIP_SKYLAKE_GT4_DT || \ 302 devid == PCI_CHIP_SKYLAKE_GT4_DESK || \ 303 devid == PCI_CHIP_SKYLAKE_GT4_HALO_MOBL || \ 304 devid == PCI_CHIP_SKYLAKE_GT4_SERV || \ 305 devid == PCI_CHIP_SKYLAKE_GT4_WRK) 306 307 308 #define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \ 309 IS_SKL_GT1_5(devid) || \ 310 IS_SKL_GT2(devid) || \ 311 IS_SKL_GT3(devid) || \ 312 IS_SKL_GT4(devid)) 313 314 #define IS_GEN9(devid) (IS_SKYLAKE(devid)) 315 316 struct region 317 { 318 INT x; 319 INT y; 320 UINT width; 321 UINT height; 322 UINT cpp; 323 UINT pitch; 324 UINT tiling; 325 UINT swizzle; 326 dri_bo *bo; 327 }; 328 329 VOID media_driver_terminate (VADriverContextP ctx); 330 VOID media_driver_data_terminate (VADriverContextP ctx); 331 332 BOOL media_driver_init (VADriverContextP ctx); 333 334 BOOL media_driver_data_init (VADriverContextP ctx); 335 VOID media_destroy_config (struct object_heap *heap, struct object_base *obj); 336 VOID 337 media_destroy_context (struct object_heap *heap, struct object_base *obj); 338 VOID media_destroy_buffer (struct object_heap *heap, struct object_base *obj); 339 VOID media_release_buffer_store (struct buffer_store **ptr); 340 341 void media_destroy_subpic (struct object_heap *heap, struct object_base *obj); 342 343 #ifdef __cplusplus 344 extern "C" { 345 #endif 346 347 extern uint32_t g_intel_debug_option_flags; 348 349 #ifdef __cplusplus 350 } 351 #endif 352 353 #define MEDIA_MAX_SURFACE_ATTRIBUTES 10 354 355 #endif 356