1 /* 2 * Copyright (c) 2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file cm_def.h 24 //! \brief Contains CM definitions 25 //! 26 27 #ifndef MEDIADRIVER_AGNOSTIC_COMMON_CM_CMDEF_H_ 28 #define MEDIADRIVER_AGNOSTIC_COMMON_CM_CMDEF_H_ 29 30 #include "cm_def_os.h" 31 #include "cm_common.h" 32 33 //! Map CM_SURFACE_FORMAT to MOS_FORMAT 34 #define CM_SURFACE_FORMAT MOS_FORMAT 35 #define CM_SURFACE_FORMAT_INVALID Format_Invalid 36 #define CM_SURFACE_FORMAT_A8R8G8B8 Format_A8R8G8B8 37 #define CM_SURFACE_FORMAT_X8R8G8B8 Format_X8R8G8B8 38 #define CM_SURFACE_FORMAT_A8B8G8R8 Format_A8B8G8R8 39 #define CM_SURFACE_FORMAT_A8 Format_A8 40 #define CM_SURFACE_FORMAT_P8 Format_P8 41 #define CM_SURFACE_FORMAT_R32F Format_R32F 42 #define CM_SURFACE_FORMAT_NV12 Format_NV12 43 #define CM_SURFACE_FORMAT_P016 Format_P016 44 #define CM_SURFACE_FORMAT_P010 Format_P010 45 #define CM_SURFACE_FORMAT_P208 Format_P208 46 #define CM_SURFACE_FORMAT_V8U8 Format_V8U8 47 #define CM_SURFACE_FORMAT_A8L8 Format_A8L8 48 #define CM_SURFACE_FORMAT_D16 Format_D16 49 #define CM_SURFACE_FORMAT_A16B16G16R16F Format_A16B16G16R16F 50 #define CM_SURFACE_FORMAT_R10G10B10A2 Format_R10G10B10A2 51 #define CM_SURFACE_FORMAT_A16B16G16R16 Format_A16B16G16R16 52 #define CM_SURFACE_FORMAT_IRW0 Format_IRW0 53 #define CM_SURFACE_FORMAT_IRW1 Format_IRW1 54 #define CM_SURFACE_FORMAT_IRW2 Format_IRW2 55 #define CM_SURFACE_FORMAT_IRW3 Format_IRW3 56 #define CM_SURFACE_FORMAT_R32_SINT Format_R32S 57 #define CM_SURFACE_FORMAT_R16_FLOAT Format_R16F 58 #define CM_SURFACE_FORMAT_A8P8 Format_A8P8 59 #define CM_SURFACE_FORMAT_I420 Format_I420 60 #define CM_SURFACE_FORMAT_IMC3 Format_IMC3 61 #define CM_SURFACE_FORMAT_IA44 Format_IA44 62 #define CM_SURFACE_FORMAT_AI44 Format_AI44 63 #define CM_SURFACE_FORMAT_Y410 Format_Y410 64 #define CM_SURFACE_FORMAT_Y416 Format_Y416 65 #define CM_SURFACE_FORMAT_Y210 Format_Y210 66 #define CM_SURFACE_FORMAT_Y216 Format_Y216 67 #define CM_SURFACE_FORMAT_AYUV Format_AYUV 68 #define CM_SURFACE_FORMAT_YV12 Format_YV12 69 #define CM_SURFACE_FORMAT_400P Format_400P 70 #define CM_SURFACE_FORMAT_411P Format_411P 71 #define CM_SURFACE_FORMAT_411R Format_411R 72 #define CM_SURFACE_FORMAT_422H Format_422H 73 #define CM_SURFACE_FORMAT_422V Format_422V 74 #define CM_SURFACE_FORMAT_444P Format_444P 75 #define CM_SURFACE_FORMAT_RGBP Format_RGBP 76 #define CM_SURFACE_FORMAT_BGRP Format_BGRP 77 #define CM_SURFACE_FORMAT_R8_UINT Format_R8U 78 #define CM_SURFACE_FORMAT_R32_UINT Format_R32U 79 #define CM_SURFACE_FORMAT_R16_SINT Format_R16S 80 #define CM_SURFACE_FORMAT_R16_UNORM Format_R16UN 81 #define CM_SURFACE_FORMAT_R8G8_UNORM Format_R8G8UN 82 #define CM_SURFACE_FORMAT_R16_UINT Format_R16U 83 #define CM_SURFACE_FORMAT_R16_TYPELESS Format_R16 84 #define CM_SURFACE_FORMAT_R16G16_UNORM Format_R16G16UN 85 #define CM_SURFACE_FORMAT_L16 Format_L16 86 #define CM_SURFACE_FORMAT_YUY2 Format_YUY2 87 #define CM_SURFACE_FORMAT_L8 Format_L8 88 #define CM_SURFACE_FORMAT_UYVY Format_UYVY 89 #define CM_SURFACE_FORMAT_VYUY Format_VYUY 90 #define CM_SURFACE_FORMAT_R8G8_SNORM Format_R8G8SN 91 #define CM_SURFACE_FORMAT_Y16_SNORM Format_Y16S 92 #define CM_SURFACE_FORMAT_Y16_UNORM Format_Y16U 93 #define CM_SURFACE_FORMAT_Y8_UNORM Format_Y8 94 #define CM_SURFACE_FORMAT_BUFFER_2D Format_Buffer_2D 95 #define CM_SURFACE_FORMAT_D32F Format_D32F 96 #define CM_SURFACE_FORMAT_D24_UNORM_S8_UINT Format_D24S8UN 97 #define CM_SURFACE_FORMAT_D32F_S8X24_UINT Format_D32S8X24_FLOAT 98 #define CM_SURFACE_FORMAT_R16G16_SINT Format_R16G16S 99 #define CM_SURFACE_FORMAT_R24G8_TYPELESS Format_R24G8 100 #define CM_SURFACE_FORMAT_R32_TYPELESS Format_R32 101 #define CM_SURFACE_FORMAT_R32G8X24_TYPELESS Format_R32G8X24 102 #define CM_SURFACE_FORMAT_R8_UNORM Format_R8UN 103 #define CM_SURFACE_FORMAT_R32G32B32A32F Format_R32G32B32A32F 104 105 typedef unsigned char byte; 106 107 #define CM_RT_API 108 #define CMRT_UMD_API 109 110 #define CISA_MAGIC_NUMBER 0x41534943 //"CISA" 111 #define CM_MIN_SURF_WIDTH 1 112 #define CM_MIN_SURF_HEIGHT 1 113 #define CM_MIN_SURF_DEPTH 2 114 115 #define CM_MAX_1D_SURF_WIDTH 0x80000000 // 2^31, 2 GB 116 117 #define CM_PAGE_ALIGNMENT 0x1000 118 #define CM_PAGE_ALIGNMENT_MASK 0x0FFF 119 120 #define CM_MAX_3D_SURF_WIDTH 2048 121 #define CM_MAX_3D_SURF_HEIGHT 2048 122 #define CM_MAX_3D_SURF_DEPTH 2048 123 124 #define CM_INIT_PROGRAM_COUNT 16 125 #define CM_INIT_KERNEL_COUNT 64 126 #define CM_INIT_SAMPLER_COUNT 32 127 #define CM_INIT_TASK_COUNT 16 128 #define CM_INIT_THREADGROUPSPACE_COUNT 8 129 #define CM_INIT_SAMPLER_8X8_STATE_COUNT 8 130 #define CM_INIT_EVENT_COUNT 128 131 #define CM_INIT_THREADSPACE_COUNT 8 132 #define CM_INIT_VEBOX_COUNT 16 133 134 #define CM_NO_EVENT ((CmEvent *)(-1)) // Magic Number for invisible event. 135 136 #define _NAME(...) #__VA_ARGS__ 137 // hard ceiling 138 #define CM_MAX_OPTION_SIZE_IN_BYTE 512 139 #define CM_MAX_KERNEL_NAME_SIZE_IN_BYTE 256 140 #define CM_MAX_ISA_FILE_NAME_SIZE_IN_BYTE 256 141 #define CM_MAX_KERNEL_STRING_IN_BYTE 512 142 143 //Time in seconds before kernel should timeout 144 #define CM_MAX_TIMEOUT 2 145 //Time in milliseconds before kernel should timeout 146 #define CM_MAX_TIMEOUT_MS CM_MAX_TIMEOUT*1000 147 148 #define CM_INVALID_KERNEL_INDEX 0xFFFFFFFF 149 150 #define CM_VME_FORWARD_ARRAY_LENGTH 16 151 #define CM_VME_BACKWARD_ARRAY_LENGTH 16 152 153 #define CM_INVALID_VME_SURFACE 0xFFFFFFFF 154 155 #define CM_INVALID_GLOBAL_SURFACE 0xFFFFFFFF 156 157 //GT-PIN 158 #define CM_MAX_ENTRY_FOR_A_SURFACE 6 //maxium planes(3)*dual state(2) 159 #define CM_GTPIN_BUFFER_NUM 3 160 161 #define CM_INIT_KERNEL_PER_PROGRAM 64 // 162 163 #define CM_MAX_SURFACE3D_FORMAT_COUNT 3 164 165 #define CM_RT_PLATFORM "CM_RT_PLATFORM" 166 #define INCLUDE_GTENVVAR_NAME "CM_DYNGT_INCLUDE" 167 #define CM_RT_SKU "CM_RT_SKU" 168 #define CM_RT_MAX_THREADS "CM_RT_MAX_THREADS" 169 #define CM_RT_AUB_PARAM "CM_RT_AUB_PARAM" 170 #define CM_RT_MUL_FRAME_FILE_BEGIN 0 171 #define CM_RT_MUL_FRAME_FILE_MIDDLE 1 172 #define CM_RT_MUL_FRAME_FILE_END 2 173 174 #define CM_RT_USER_FEATURE_FORCE_COHERENT_STATELESSBTI "ForceCoherentStatelessBTI" 175 176 // need to sync with driver code 177 #define CM_HAL_LOCKFLAG_READONLY 0x00000001 178 #define CM_HAL_LOCKFLAG_WRITEONLY 0x00000002 179 180 #define CM_MAX_DEPENDENCY_COUNT 8 181 #define CM_MAX_THREADSPACE_WIDTH_FOR_MW 511 182 #define CM_MAX_THREADSPACE_HEIGHT_FOR_MW 511 183 #define CM_MAX_THREADSPACE_WIDTH_SKLUP_FOR_MW 2047 184 #define CM_MAX_THREADSPACE_HEIGHT_SKLUP_FOR_MW 2047 185 186 #define MAX_SLM_SIZE_PER_GROUP_IN_1K 64 // 64KB PER Group on Gen7+ 187 #define CM_MAX_THREAD_GROUP 64 188 189 #define COMMON_ISA_NUM_PREDEFINED_SURF_VER_2 1 190 #define COMMON_ISA_NUM_PREDEFINED_SURF_VER_2_1 5 191 #define COMMON_ISA_NUM_PREDEFINED_SURF_VER_3_1 6 192 193 #define CM_FLAG_CURBE_ENABLED 0x00000001 //bit 0 194 #define CM_FLAG_NONSTALLING_SCOREBOARD_ENABLED 0x00000002 //bit 1 195 196 #define GT_PIN_MSG_SIZE 1024 197 198 #define CM_GLOBAL_SURFACE_NUMBER 4 199 #define CM_GTPIN_SURFACE_NUMBER 3 200 201 #define GT_RESERVED_INDEX_START 250 202 #define GT_RESERVED_INDEX_START_GEN9_PLUS 240 203 #define CM_GLOBAL_SURFACE_INDEX_START 243 204 #define CM_GLOBAL_SURFACE_INDEX_START_GEN9_PLUS 1 205 #define CM_NULL_SURFACE_BINDING_INDEX 0 //Reserve 0 for NULL surface 206 207 #define GTPIN_BINDING_TABLE_INDEX_BUFF0_GEN9_PLUS (CM_GLOBAL_SURFACE_INDEX_START_GEN9_PLUS + CM_GLOBAL_SURFACE_NUMBER) 208 #define GTPIN_BINDING_TABLE_INDEX_BUFF1_GEN9_PLUS (GTPIN_BINDING_TABLE_INDEX_BUFF0_GEN9_PLUS + 1) 209 #define GTPIN_BINDING_TABLE_INDEX_BUFF2_GEN9_PLUS (GTPIN_BINDING_TABLE_INDEX_BUFF0_GEN9_PLUS + 2) 210 211 #define CM_NULL_SURFACE 0xFFFF 212 213 #define R64_OFFSET 32*64 214 #define CM_MOVE_INSTRUCTION_SIZE 16 // 16 bytes per move instruction 215 216 #define CM_SAMPLER_MAX_BINDING_INDEX 15 217 218 // For EnqueueWithHints using media objects 219 // hard code add instruction to adjust y coordinate 220 // just need to replace DW3 with constant value 221 // add (1) r0.3<1>:uw r0.3<0;1,0>:uw 0x0:w 222 #define CM_BDW_ADJUST_Y_SCOREBOARD_DW0 0x00000040 223 #define CM_BDW_ADJUST_Y_SCOREBOARD_DW1 0x20061248 224 #define CM_BDW_ADJUST_Y_SCOREBOARD_DW2 0x1e000006 225 226 #define CM_MINIMUM_NUM_KERNELS_ENQWHINTS 2 227 228 #define CM_DEFAULT_PRINT_BUFFER_SIZE (1*1024*1024) // 1M print buffer size 229 #define PRINT_BUFFER_HEADER_SIZE 32 230 #define CM_PRINTF_STATIC_BUFFER_ID 1 231 232 #define CM_INVALID_COLOR_COUNT 0 233 234 #define CM_INIT_GPUCOPY_KERNL_COUNT 16 235 236 #define CM_NUM_VME_HEVC_REFS 4 237 238 #define PLATFORM_INTEL_UNKNOWN 0 239 240 #define PLATFORM_INTEL_GT_UNKNOWN 0 241 #define PLATFORM_INTEL_GT1 1 242 #define PLATFORM_INTEL_GT2 2 243 #define PLATFORM_INTEL_GT3 3 244 #define PLATFORM_INTEL_GT4 4 245 #define PLATFORM_INTEL_GT1_5 10 246 247 #define BDW_GT1_MAX_NUM_SLICES (1) 248 #define BDW_GT1_MAX_NUM_SUBSLICES (2) 249 #define BDW_GT1_5_MAX_NUM_SLICES (1) 250 #define BDW_GT1_5_MAX_NUM_SUBSLICES (3) 251 #define BDW_GT2_MAX_NUM_SLICES (1) 252 #define BDW_GT2_MAX_NUM_SUBSLICES (3) 253 #define BDW_GT3_MAX_NUM_SLICES (2) 254 #define BDW_GT3_MAX_NUM_SUBSLICES (6) 255 256 #define SKL_GT1_MAX_NUM_SLICES (1) 257 #define SKL_GT1_MAX_NUM_SUBSLICES (2) 258 #define SKL_GT1_5_MAX_NUM_SLICES (1) 259 #define SKL_GT1_5_MAX_NUM_SUBSLICES (3) 260 #define SKL_GT2_MAX_NUM_SLICES (1) 261 #define SKL_GT2_MAX_NUM_SUBSLICES (3) 262 #define SKL_GT3_MAX_NUM_SLICES (2) 263 #define SKL_GT3_MAX_NUM_SUBSLICES (6) 264 #define SKL_GT4_MAX_NUM_SLICES (3) 265 #define SKL_GT4_MAX_NUM_SUBSLICES (9) 266 267 #define CNL_GT1_4X8_MAX_NUM_SLICES (2) 268 #define CNL_GT1_4X8_MAX_NUM_SUBSLICES (4) 269 #define CNL_GT2_7X8_MAX_NUM_SLICES (3) 270 #define CNL_GT2_7X8_MAX_NUM_SUBSLICES (7) 271 #define CNL_GT3_9X8_MAX_NUM_SLICES (4) 272 #define CNL_GT3_9_8MAX_NUM_SUBSLICES (9) 273 274 typedef enum _CM_DEVICE_CAP_NAME 275 { 276 CAP_KERNEL_COUNT_PER_TASK, 277 CAP_KERNEL_BINARY_SIZE, 278 CAP_SAMPLER_COUNT , 279 CAP_SAMPLER_COUNT_PER_KERNEL, 280 CAP_BUFFER_COUNT , 281 CAP_SURFACE2D_COUNT, 282 CAP_SURFACE3D_COUNT, 283 CAP_SURFACE_COUNT_PER_KERNEL, 284 CAP_ARG_COUNT_PER_KERNEL, 285 CAP_ARG_SIZE_PER_KERNEL , 286 CAP_USER_DEFINED_THREAD_COUNT_PER_TASK, 287 CAP_HW_THREAD_COUNT, 288 CAP_SURFACE2D_FORMAT_COUNT, 289 CAP_SURFACE2D_FORMATS, 290 CAP_SURFACE3D_FORMAT_COUNT, 291 CAP_SURFACE3D_FORMATS, 292 CAP_VME_STATE_COUNT, 293 CAP_GPU_PLATFORM, 294 CAP_GT_PLATFORM, 295 CAP_MIN_FREQUENCY, 296 CAP_MAX_FREQUENCY, 297 CAP_L3_CONFIG, 298 CAP_GPU_CURRENT_FREQUENCY, 299 CAP_USER_DEFINED_THREAD_COUNT_PER_TASK_NO_THREAD_ARG, 300 CAP_USER_DEFINED_THREAD_COUNT_PER_MEDIA_WALKER, 301 CAP_USER_DEFINED_THREAD_COUNT_PER_THREAD_GROUP, 302 CAP_SURFACE2DUP_COUNT, 303 CAP_PLATFORM_INFO, 304 CAP_MAX_BUFFER_SIZE 305 } CM_DEVICE_CAP_NAME; 306 307 // BDW stepping sequence: // A0 308 // HSW stepping sequence: // A0, A1, B0, C0, D0 309 #define HW_GT_STEPPING_A0 "A0" 310 #define HW_GT_STEPPING_A1 "A1" 311 #define HW_GT_STEPPING_B0 "B0" 312 #define HW_GT_STEPPING_C0 "C0" 313 #define HW_GT_STEPPING_D0 "D0" 314 315 /**************** L3/Cache ***************/ 316 typedef enum _MEMORY_OBJECT_CONTROL{ 317 // SNB 318 MEMORY_OBJECT_CONTROL_USE_GTT_ENTRY, 319 MEMORY_OBJECT_CONTROL_NEITHER_LLC_NOR_MLC, 320 MEMORY_OBJECT_CONTROL_LLC_NOT_MLC, 321 MEMORY_OBJECT_CONTROL_LLC_AND_MLC, 322 323 // IVB 324 MEMORY_OBJECT_CONTROL_FROM_GTT_ENTRY = MEMORY_OBJECT_CONTROL_USE_GTT_ENTRY, // Caching dependent on pte 325 MEMORY_OBJECT_CONTROL_L3, // Cached in L3$ 326 MEMORY_OBJECT_CONTROL_LLC, // Cached in LLC 327 MEMORY_OBJECT_CONTROL_LLC_L3, // Cached in LLC & L3$ 328 329 // HSW 330 MEMORY_OBJECT_CONTROL_USE_PTE = MEMORY_OBJECT_CONTROL_FROM_GTT_ENTRY, // Caching dependent on pte 331 MEMORY_OBJECT_CONTROL_L3_USE_PTE, 332 MEMORY_OBJECT_CONTROL_UC, // Uncached 333 MEMORY_OBJECT_CONTROL_L3_UC, 334 MEMORY_OBJECT_CONTROL_LLC_ELLC, 335 MEMORY_OBJECT_CONTROL_L3_LLC_ELLC, 336 MEMORY_OBJECT_CONTROL_ELLC, 337 MEMORY_OBJECT_CONTROL_L3_ELLC, 338 339 // BDW 340 MEMORY_OBJECT_CONTROL_BDW_ELLC_ONLY = 0, 341 MEMORY_OBJECT_CONTROL_BDW_LLC_ONLY, 342 MEMORY_OBJECT_CONTROL_BDW_LLC_ELLC_ALLOWED, 343 MEMORY_OBJECT_CONTROL_BDW_L3_LLC_ELLC_ALLOWED, 344 345 // SKL 346 // CNL 347 // ICL 348 MEMORY_OBJECT_CONTROL_SKL_DEFAULT = 0, 349 MEMORY_OBJECT_CONTROL_SKL_NO_L3, 350 MEMORY_OBJECT_CONTROL_SKL_NO_LLC_ELLC, 351 MEMORY_OBJECT_CONTROL_SKL_NO_LLC, 352 MEMORY_OBJECT_CONTROL_SKL_NO_ELLC, 353 MEMORY_OBJECT_CONTROL_SKL_NO_LLC_L3, 354 MEMORY_OBJECT_CONTROL_SKL_NO_ELLC_L3, 355 MEMORY_OBJECT_CONTROL_SKL_NO_CACHE, 356 357 // Unified memory object control type for SKL+ 358 MEMORY_OBJECT_CONTROL_DEFAULT = 0x0, 359 MEMORY_OBJECT_CONTROL_NO_L3, 360 MEMORY_OBJECT_CONTROL_NO_LLC_ELLC, 361 MEMORY_OBJECT_CONTROL_NO_LLC, 362 MEMORY_OBJECT_CONTROL_NO_ELLC, 363 MEMORY_OBJECT_CONTROL_NO_LLC_L3, 364 MEMORY_OBJECT_CONTROL_NO_ELLC_L3, 365 MEMORY_OBJECT_CONTROL_NO_CACHE, 366 MEMORY_OBJECT_CONTROL_L1_ENABLED, 367 368 MEMORY_OBJECT_CONTROL_TOTAL, 369 // 370 MEMORY_OBJECT_CONTROL_UNKNOW = 0xff 371 } MEMORY_OBJECT_CONTROL; 372 373 typedef enum _MEMORY_TYPE { 374 CM_USE_PTE, 375 CM_UN_CACHEABLE, 376 CM_WRITE_THROUGH, 377 CM_WRITE_BACK, 378 379 // BDW 380 MEMORY_TYPE_BDW_UC_WITH_FENCE = 0, 381 MEMORY_TYPE_BDW_UC, 382 MEMORY_TYPE_BDW_WT, 383 MEMORY_TYPE_BDW_WB 384 385 } MEMORY_TYPE; 386 387 typedef struct _CM_SURFACE_MEM_OBJ_CTRL { 388 int32_t mem_ctrl; 389 MEMORY_TYPE mem_type; 390 int32_t age; 391 } CM_SURFACE_MEM_OBJ_CTRL; 392 393 //GT-PIN 394 #define CM_MAX_ENTRY_FOR_A_SURFACE 6 //maxium planes(3)*dual state(2) 395 #define CM_GTPIN_BUFFER_NUM 3 396 397 typedef enum _CM_SAMPLER8x8_SURFACE_ 398 { 399 CM_AVS_SURFACE = 0, 400 CM_VA_SURFACE = 1 401 }CM_SAMPLER8x8_SURFACE; 402 403 typedef enum _CM_SURFACE_ADDRESS_CONTROL_MODE_ 404 { 405 CM_SURFACE_CLAMP = 0, 406 CM_SURFACE_MIRROR = 1 407 }CM_SURFACE_ADDRESS_CONTROL_MODE; 408 409 typedef struct _CM_SAMPLER_STATE 410 { 411 CM_TEXTURE_FILTER_TYPE minFilterType; 412 CM_TEXTURE_FILTER_TYPE magFilterType; 413 CM_TEXTURE_ADDRESS_TYPE addressU; 414 CM_TEXTURE_ADDRESS_TYPE addressV; 415 CM_TEXTURE_ADDRESS_TYPE addressW; 416 } CM_SAMPLER_STATE; 417 418 typedef enum _CM_PIXEL_TYPE 419 { 420 CM_PIXEL_UINT, 421 CM_PIXEL_SINT, 422 CM_PIXEL_OTHER 423 } CM_PIXEL_TYPE; 424 425 typedef struct _CM_SAMPLER_STATE_EX 426 { 427 CM_TEXTURE_FILTER_TYPE minFilterType; 428 CM_TEXTURE_FILTER_TYPE magFilterType; 429 CM_TEXTURE_ADDRESS_TYPE addressU; 430 CM_TEXTURE_ADDRESS_TYPE addressV; 431 CM_TEXTURE_ADDRESS_TYPE addressW; 432 433 CM_PIXEL_TYPE SurfaceFormat; 434 union { 435 uint32_t BorderColorRedU; 436 int32_t BorderColorRedS; 437 float BorderColorRedF; 438 }; 439 440 union { 441 uint32_t BorderColorGreenU; 442 int32_t BorderColorGreenS; 443 float BorderColorGreenF; 444 }; 445 446 union { 447 uint32_t BorderColorBlueU; 448 int32_t BorderColorBlueS; 449 float BorderColorBlueF; 450 }; 451 452 union { 453 uint32_t BorderColorAlphaU; 454 int32_t BorderColorAlphaS; 455 float BorderColorAlphaF; 456 }; 457 } CM_SAMPLER_STATE_EX; 458 459 typedef struct _CM_AVS_INTERNEL_COEFF_TABLE{ 460 float FilterCoeff_0_0; 461 float FilterCoeff_0_1; 462 float FilterCoeff_0_2; 463 float FilterCoeff_0_3; 464 float FilterCoeff_0_4; 465 float FilterCoeff_0_5; 466 float FilterCoeff_0_6; 467 float FilterCoeff_0_7; 468 }CM_AVS_INTERNEL_COEFF_TABLE; 469 470 #define CM_NUM_COEFF_ROWS 17 471 #define CM_NUM_COEFF_ROWS_SKL 32 472 473 typedef struct _CM_AVS_NONPIPLINED_STATE{ 474 bool BypassXAF; 475 bool BypassYAF; 476 uint8_t DefaultSharpLvl; 477 uint8_t maxDerivative4Pixels; 478 uint8_t maxDerivative8Pixels; 479 uint8_t transitionArea4Pixels; 480 uint8_t transitionArea8Pixels; 481 CM_AVS_COEFF_TABLE Tbl0X[ CM_NUM_COEFF_ROWS_SKL ]; 482 CM_AVS_COEFF_TABLE Tbl0Y[ CM_NUM_COEFF_ROWS_SKL ]; 483 CM_AVS_COEFF_TABLE Tbl1X[ CM_NUM_COEFF_ROWS_SKL ]; 484 CM_AVS_COEFF_TABLE Tbl1Y[ CM_NUM_COEFF_ROWS_SKL ]; 485 bool bEnableRGBAdaptive; 486 bool bAdaptiveFilterAllChannels; 487 }CM_AVS_NONPIPLINED_STATE; 488 489 typedef struct _CM_AVS_INTERNEL_NONPIPLINED_STATE{ 490 bool BypassXAF; 491 bool BypassYAF; 492 uint8_t DefaultSharpLvl; 493 uint8_t maxDerivative4Pixels; 494 uint8_t maxDerivative8Pixels; 495 uint8_t transitionArea4Pixels; 496 uint8_t transitionArea8Pixels; 497 CM_AVS_INTERNEL_COEFF_TABLE Tbl0X[ CM_NUM_COEFF_ROWS_SKL ]; 498 CM_AVS_INTERNEL_COEFF_TABLE Tbl0Y[ CM_NUM_COEFF_ROWS_SKL ]; 499 CM_AVS_INTERNEL_COEFF_TABLE Tbl1X[ CM_NUM_COEFF_ROWS_SKL ]; 500 CM_AVS_INTERNEL_COEFF_TABLE Tbl1Y[ CM_NUM_COEFF_ROWS_SKL ]; 501 bool bEnableRGBAdaptive; 502 bool bAdaptiveFilterAllChannels; 503 }CM_AVS_INTERNEL_NONPIPLINED_STATE, *PCM_AVS_INTERNEL_NONPIPLINED_STATE; 504 505 typedef struct _CM_AVS_STATE_MSG{ 506 bool AVSTYPE; //true nearest, false adaptive 507 bool EightTapAFEnable; //HSW+ 508 bool BypassIEF; //ignored for BWL, moved to sampler8x8 payload. 509 bool ShuffleOutputWriteback; //SKL mode only to be set when AVS msg sequence is 4x4 or 8x4 510 bool HDCDirectWriteEnable; 511 unsigned short GainFactor; 512 unsigned char GlobalNoiseEstm; 513 unsigned char StrongEdgeThr; 514 unsigned char WeakEdgeThr; 515 unsigned char StrongEdgeWght; 516 unsigned char RegularWght; 517 unsigned char NonEdgeWght; 518 unsigned short wR3xCoefficient; 519 unsigned short wR3cCoefficient; 520 unsigned short wR5xCoefficient; 521 unsigned short wR5cxCoefficient; 522 unsigned short wR5cCoefficient; 523 //For Non-piplined states 524 unsigned short stateID; 525 CM_AVS_NONPIPLINED_STATE * AvsState; 526 } CM_AVS_STATE_MSG; 527 528 /* 529 * CONVOLVE STATE DATA STRUCTURES 530 */ 531 typedef struct _CM_CONVOLVE_COEFF_TABLE{ 532 float FilterCoeff_0_0; 533 float FilterCoeff_0_1; 534 float FilterCoeff_0_2; 535 float FilterCoeff_0_3; 536 float FilterCoeff_0_4; 537 float FilterCoeff_0_5; 538 float FilterCoeff_0_6; 539 float FilterCoeff_0_7; 540 float FilterCoeff_0_8; 541 float FilterCoeff_0_9; 542 float FilterCoeff_0_10; 543 float FilterCoeff_0_11; 544 float FilterCoeff_0_12; 545 float FilterCoeff_0_13; 546 float FilterCoeff_0_14; 547 float FilterCoeff_0_15; 548 float FilterCoeff_0_16; 549 float FilterCoeff_0_17; 550 float FilterCoeff_0_18; 551 float FilterCoeff_0_19; 552 float FilterCoeff_0_20; 553 float FilterCoeff_0_21; 554 float FilterCoeff_0_22; 555 float FilterCoeff_0_23; 556 float FilterCoeff_0_24; 557 float FilterCoeff_0_25; 558 float FilterCoeff_0_26; 559 float FilterCoeff_0_27; 560 float FilterCoeff_0_28; 561 float FilterCoeff_0_29; 562 float FilterCoeff_0_30; 563 float FilterCoeff_0_31; 564 }CM_CONVOLVE_COEFF_TABLE; 565 566 #define CM_NUM_CONVOLVE_ROWS_SKL 31 567 typedef struct _CM_CONVOLVE_STATE_MSG{ 568 bool CoeffSize; //true 16-bit, false 8-bit 569 byte SclDwnValue; //Scale down value 570 byte Width; //Kernel Width 571 byte Height; //Kernel Height 572 //SKL mode 573 bool isVertical32Mode; 574 bool isHorizontal32Mode; 575 bool skl_mode; // new added 576 CM_CONVOLVE_SKL_TYPE nConvolveType; 577 CM_CONVOLVE_COEFF_TABLE Table[ CM_NUM_CONVOLVE_ROWS_SKL ]; 578 } CM_CONVOLVE_STATE_MSG; 579 580 /* 581 * MISC SAMPLER8x8 State 582 */ 583 typedef struct _CM_MISC_STATE { 584 //uint32_t 0 585 union{ 586 struct{ 587 uint32_t Row0 : 16; 588 uint32_t Reserved : 8; 589 uint32_t Width : 4; 590 uint32_t Height : 4; 591 }; 592 struct{ 593 uint32_t value; 594 }; 595 }DW0; 596 597 //uint32_t 1 598 union{ 599 struct{ 600 uint32_t Row1 : 16; 601 uint32_t Row2 : 16; 602 }; 603 struct{ 604 uint32_t value; 605 }; 606 }DW1; 607 608 //uint32_t 2 609 union{ 610 struct{ 611 uint32_t Row3 : 16; 612 uint32_t Row4 : 16; 613 }; 614 struct{ 615 uint32_t value; 616 }; 617 }DW2; 618 619 //uint32_t 3 620 union{ 621 struct{ 622 uint32_t Row5 : 16; 623 uint32_t Row6 : 16; 624 }; 625 struct{ 626 uint32_t value; 627 }; 628 }DW3; 629 630 //uint32_t 4 631 union{ 632 struct{ 633 uint32_t Row7 : 16; 634 uint32_t Row8 : 16; 635 }; 636 struct{ 637 uint32_t value; 638 }; 639 }DW4; 640 641 //uint32_t 5 642 union{ 643 struct{ 644 uint32_t Row9 : 16; 645 uint32_t Row10 : 16; 646 }; 647 struct{ 648 uint32_t value; 649 }; 650 }DW5; 651 652 //uint32_t 6 653 union{ 654 struct{ 655 uint32_t Row11 : 16; 656 uint32_t Row12 : 16; 657 }; 658 struct{ 659 uint32_t value; 660 }; 661 }DW6; 662 663 //uint32_t 7 664 union{ 665 struct{ 666 uint32_t Row13 : 16; 667 uint32_t Row14 : 16; 668 }; 669 struct{ 670 uint32_t value; 671 }; 672 }DW7; 673 } CM_MISC_STATE; 674 675 typedef struct _CM_MISC_STATE_MSG{ 676 //uint32_t 0 677 union{ 678 struct{ 679 uint32_t Row0 : 16; 680 uint32_t Reserved : 8; 681 uint32_t Width : 4; 682 uint32_t Height : 4; 683 }; 684 struct{ 685 uint32_t value; 686 }; 687 }DW0; 688 689 //uint32_t 1 690 union{ 691 struct{ 692 uint32_t Row1 : 16; 693 uint32_t Row2 : 16; 694 }; 695 struct{ 696 uint32_t value; 697 }; 698 }DW1; 699 700 //uint32_t 2 701 union{ 702 struct{ 703 uint32_t Row3 : 16; 704 uint32_t Row4 : 16; 705 }; 706 struct{ 707 uint32_t value; 708 }; 709 }DW2; 710 711 //uint32_t 3 712 union{ 713 struct{ 714 uint32_t Row5 : 16; 715 uint32_t Row6 : 16; 716 }; 717 struct{ 718 uint32_t value; 719 }; 720 }DW3; 721 722 //uint32_t 4 723 union{ 724 struct{ 725 uint32_t Row7 : 16; 726 uint32_t Row8 : 16; 727 }; 728 struct{ 729 uint32_t value; 730 }; 731 }DW4; 732 733 //uint32_t 5 734 union{ 735 struct{ 736 uint32_t Row9 : 16; 737 uint32_t Row10 : 16; 738 }; 739 struct{ 740 uint32_t value; 741 }; 742 }DW5; 743 744 //uint32_t 6 745 union{ 746 struct{ 747 uint32_t Row11 : 16; 748 uint32_t Row12 : 16; 749 }; 750 struct{ 751 uint32_t value; 752 }; 753 }DW6; 754 755 //uint32_t 7 756 union{ 757 struct{ 758 uint32_t Row13 : 16; 759 uint32_t Row14 : 16; 760 }; 761 struct{ 762 uint32_t value; 763 }; 764 }DW7; 765 } CM_MISC_STATE_MSG; 766 767 typedef CM_HAL_SAMPLER_8X8_TYPE CM_SAMPLER_STATE_TYPE; 768 769 typedef struct _CM_SAMPLER_8X8_DESCR{ 770 CM_SAMPLER_STATE_TYPE stateType; 771 union 772 { 773 CM_AVS_STATE_MSG * avs; 774 CM_CONVOLVE_STATE_MSG * conv; 775 CM_MISC_STATE_MSG * misc; //ERODE/DILATE/MINMAX 776 }; 777 } CM_SAMPLER_8X8_DESCR; 778 779 typedef enum _CM_ROTATION 780 { 781 CM_ROTATION_IDENTITY = 0, //!< Rotation 0 degrees 782 CM_ROTATION_90, //!< Rotation 90 degrees 783 CM_ROTATION_180, //!< Rotation 180 degrees 784 CM_ROTATION_270, //!< Rotation 270 degrees 785 } CM_ROTATION; 786 787 // to support new flag with current API 788 // new flag/field could be add to the end of this structure 789 // 790 struct CM_FLAG { 791 CM_FLAG(); 792 CM_ROTATION rotationFlag; 793 int32_t chromaSiting; 794 }; 795 796 // parameters used to set the surface state of the CmSurface 797 struct CM_VME_SURFACE_STATE_PARAM 798 { 799 uint32_t width; 800 uint32_t height; 801 }; 802 803 // parameters used to set the surface state of the CmSurface 804 typedef struct _CM_SURFACE2D_STATE_PARAM 805 { 806 uint32_t format; //[IN] MOS_FORMAT 807 uint32_t width; 808 uint32_t height; 809 uint32_t depth; 810 uint32_t pitch; 811 uint16_t memory_object_control; 812 uint32_t surface_x_offset; // Horizontal offset to the origin of the surface, in columns of pixels. 813 uint32_t surface_y_offset; // Vertical offset to the origin of the surface, in rows of pixels. 814 uint32_t surface_offset; // Offset to the origin of the surface, in bytes. 815 uint32_t reserved[3]; // for future usage 816 } CM_SURFACE2D_STATE_PARAM; 817 818 #endif // #ifndef MEDIADRIVER_AGNOSTIC_COMMON_CM_CMDEF_H_ 819