1 /* 2 * Copyright (c) 2010-2020, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file vphal_render_common.h 24 //! \brief Unified VP HAL shared rendering definitions 25 //! 26 //! 27 //! \file vphal_render_common.h 28 //! \brief The header file of common struct/macro definitions shared by low level renderers 29 //! \details Common struct/macro for different renderers, e.g. DNDI or Comp 30 //! 31 #ifndef __VPHAL_RENDER_COMMON_H__ 32 #define __VPHAL_RENDER_COMMON_H__ 33 34 #include "vphal.h" 35 #include "renderhal.h" 36 #include "mhw_utilities.h" 37 #include "mos_os.h" 38 #include "hal_kerneldll.h" 39 40 //! 41 //! \brief Max number of Media Threads 42 //! 43 #define VPHAL_USE_MEDIA_THREADS_MAX 0 44 45 //! 46 //! \brief Similar definition from MHAL 47 //! 48 #define VPHAL_YTILE_H_ALIGNMENT 32 49 #define VPHAL_YTILE_W_ALIGNMENT 128 50 #define VPHAL_XTILE_H_ALIGNMENT 8 51 #define VPHAL_XTILE_W_ALIGNMENT 512 52 53 #define VPHAL_YTILE_H_SHIFTBITS 5 54 #define VPHAL_YTILE_W_SHIFTBITS 7 55 #define VPHAL_XTILE_H_SHITFBITS 3 56 #define VPHAL_XTILE_W_SHIFTBITS 9 57 58 #define VPHAL_MACROBLOCK_SIZE 16 59 #define VPHAL_PAGE_SIZE 0x1000 60 61 //! 62 //! \brief STE Parameters 63 //! 64 #define VPHAL_STE_OPTIMAL 3 // for perfect HD-HQV Score 65 66 //! 67 //! \brief used to map STE Factor to parameters(SATP1, SATS0, SATS1) for 68 //! STE Factor values <= VPHAL_STE_OPTIMAL 69 //! 70 #define VPHAL_STE_LTEO(dwSteFactor, fSatp1, fSats0, fSats1) \ 71 fSatp1 = (-6) + ((3 - (float)dwSteFactor) * 2); \ 72 fSats0 = (float)29 / (fSatp1 + 31) * 256; \ 73 fSats1 = (float)4 / (6 - fSatp1) * 256; 74 75 //! 76 //! \brief used to map STE Factor to parameters(SATP1, SATS0, SATS1) for 77 //! STE Factor values > VPHAL_STE_OPTIMAL 78 //! 79 #define VPHAL_STE_GTO(dwSteFactor, fSatp1, fSats0, fSats1) \ 80 fSatp1 = (-20) + ((9 - (float)dwSteFactor) * 2); \ 81 fSats0 = (float)31 / (fSatp1 + 31) * 256; \ 82 fSats1 = (float)31 / (31 - fSatp1) * 256; 83 84 //! 85 //! \brief Alignment 86 //! 87 #define VPHAL_CURBE_BLOCK_ALIGN_G7 32 88 89 // Defined DP used FC kernel for computation. 90 struct MEDIA_DP_FC_STATIC_DATA 91 { 92 // DWORD 0 - GRF R1.0 93 union 94 { 95 // CSC 96 struct 97 { 98 uint32_t CscConstantC0 : 16; 99 uint32_t CscConstantC1 : 16; 100 }; 101 102 uint32_t Value; 103 } DW0; 104 105 // DWORD 1 - GRF R1.1 106 union 107 { 108 // CSC 109 struct 110 { 111 uint32_t CscConstantC2 : 16; 112 uint32_t CscConstantC3 : 16; 113 }; 114 115 uint32_t Value; 116 } DW1; 117 118 // DWORD 2 - GRF R1.2 119 union 120 { 121 // CSC 122 struct 123 { 124 uint32_t CscConstantC4 : 16; 125 uint32_t CscConstantC5 : 16; 126 }; 127 128 uint32_t Value; 129 } DW2; 130 131 // DWORD 3 - GRF R1.3 132 union 133 { 134 // CSC 135 struct 136 { 137 uint32_t CscConstantC6 : 16; 138 uint32_t CscConstantC7 : 16; 139 }; 140 141 uint32_t Value; 142 } DW3; 143 144 // DWORD 4 - GRF R1.4 145 union 146 { 147 // CSC 148 struct 149 { 150 uint32_t CscConstantC8 : 16; 151 uint32_t CscConstantC9 : 16; 152 }; 153 154 uint32_t Value; 155 } DW4; 156 157 // DWORD 5 - GRF R1.5 158 union 159 { 160 // CSC 161 struct 162 { 163 uint32_t CscConstantC10 : 16; 164 uint32_t CscConstantC11 : 16; 165 }; 166 167 uint32_t Value; 168 } DW5; 169 170 // DWORD 6 - GRF R1.6 171 union 172 { 173 // Dataport-based rotation 174 struct 175 { 176 uint32_t InputPictureWidth : 16; 177 uint32_t InputPictureHeight : 16; 178 }; 179 180 uint32_t Value; 181 } DW6; 182 183 // DWORD 7 - GRF R1.7 distWidth and distHeight 184 union 185 { 186 struct 187 { 188 uint32_t DestinationRectangleWidth : 16; 189 uint32_t DestinationRectangleHeight : 16; 190 }; 191 192 uint32_t Value; 193 } DW7; 194 195 // DWORD 8 - GRF R1.8 196 union 197 { 198 struct 199 { 200 uint32_t RotationChromaSitingFlag; 201 }; 202 203 uint32_t Value; 204 } DW8; 205 206 // DWORD 9 - GRF R1.9 input DeltaX 207 union 208 { 209 struct 210 { 211 float HorizontalScalingStepRatioLayer0; 212 }; 213 214 uint32_t Value; 215 } DW9; 216 217 // DWORD 10 - GRF R2.0 input DeltaY 218 union 219 { 220 struct 221 { 222 float VerticalScalingStepRatioLayer0; 223 }; 224 225 uint32_t Value; 226 } DW10; 227 228 // DWORD 11 - GRF R2.1 input orignin x 229 union 230 { 231 struct 232 { 233 float HorizontalFrameOriginLayer0; 234 }; 235 236 uint32_t Value; 237 } DW11; 238 239 // DWORD 12 - GRF R2.2 input orignin Y 240 union 241 { 242 struct 243 { 244 float VerticalFrameOriginLayer0; 245 }; 246 247 uint32_t Value; 248 } DW12; 249 250 // DWORD13 - GRF R2.3 topleft[2] 251 union 252 { 253 struct 254 { 255 uint32_t DestXTopLeftLayer0 : 16; 256 uint32_t DestYTopLeftLayer0 : 16; 257 }; 258 259 uint32_t Value; 260 } DW13; 261 262 // DWORD14 - GRF R2.4 bottomRight 263 union 264 { 265 struct 266 { 267 uint32_t DestXBottomRightLayer0 : 16; 268 uint32_t DestYBottomRightLayer0 : 16; 269 }; 270 271 uint32_t Value; 272 } DW14; 273 274 // DWORD15 - GRF R2.4 waflag and dstpitch 275 union 276 { 277 struct 278 { 279 uint32_t waFlag : 16; 280 uint32_t StatisticsSurfacePitch : 16; 281 }; 282 283 uint32_t Value; 284 } DW15; 285 286 }; 287 // Defined in Inline parameter computation 288 struct MEDIA_WALKER_KA2_STATIC_DATA 289 { 290 // DWORD 0 - GRF R1.0 291 union 292 { 293 // CSC 294 struct 295 { 296 uint32_t CscConstantC0 : 16; 297 uint32_t CscConstantC1 : 16; 298 }; 299 300 // Chroma Denoise 301 struct 302 { 303 uint32_t LocalDifferenceThresholdU : 8; 304 uint32_t LocalDifferenceThresholdV : 8; 305 uint32_t SobelEdgeThresholdU : 8; 306 uint32_t SobelEdgeThresholdV : 8; 307 }; 308 309 // Dataport-based rotation 310 struct 311 { 312 uint32_t InputPictureWidth : 16; 313 uint32_t InputPictureHeight : 16; 314 }; 315 316 uint32_t Value; 317 } DW00; 318 319 // DWORD 1 - GRF R1.1 320 union 321 { 322 // CSC 323 struct 324 { 325 uint32_t CscConstantC2 : 16; 326 uint32_t CscConstantC3 : 16; 327 }; 328 329 // Chroma Denoise 330 struct 331 { 332 uint32_t HistoryInitialValueU : 8; 333 uint32_t HistoryInitialValueV : 8; 334 uint32_t HistoryMaxU : 8; 335 uint32_t HistoryMaxV : 8; 336 }; 337 338 // Dataport-based rotation 339 struct 340 { 341 uint32_t RotationMirrorMode : 8; 342 uint32_t DestinationRGBFormat : 8; 343 uint32_t : 16; 344 }; 345 346 uint32_t Value; 347 } DW01; 348 349 // DWORD 2 - GRF R1.2 350 union 351 { 352 // CSC 353 struct 354 { 355 uint32_t CscConstantC4 : 16; 356 uint32_t CscConstantC5 : 16; 357 }; 358 359 // Chroma Denoise 360 struct 361 { 362 uint32_t HistoryDeltaU : 8; 363 uint32_t HistoryDeltaV : 8; 364 uint32_t DNSADThresholdU : 8; 365 uint32_t DNSADThresholdV : 8; 366 }; 367 368 // Dataport-based rotation 369 struct 370 { 371 uint32_t CscConstantC0 : 16; 372 uint32_t CscConstantC1 : 16; 373 }; 374 375 uint32_t Value; 376 } DW02; 377 378 // DWORD 3 - GRF R1.3 379 union 380 { 381 // CSC 382 struct 383 { 384 uint32_t CscConstantC6 : 16; 385 uint32_t CscConstantC7 : 16; 386 }; 387 388 // Chroma Denoise 389 struct 390 { 391 uint32_t DNTDThresholdU : 8; 392 uint32_t DNTDThresholdV : 8; 393 uint32_t DNLTDThresholdU : 8; 394 uint32_t DNLTDThresholdV : 8; 395 }; 396 397 // Dataport-based rotation 398 struct 399 { 400 uint32_t CscConstantC2 : 16; 401 uint32_t CscConstantC3 : 16; 402 }; 403 404 uint32_t Value; 405 } DW03; 406 407 // DWORD 4 - GRF R1.4 408 union 409 { 410 // CSC 411 struct 412 { 413 uint32_t CscConstantC8 : 16; 414 uint32_t CscConstantC9 : 16; 415 }; 416 417 // Dataport-based rotation 418 struct 419 { 420 uint32_t CscConstantC4 : 16; 421 uint32_t CscConstantC5 : 16; 422 }; 423 424 uint32_t Value; 425 } DW04; 426 427 // DWORD 5 - GRF R1.5 428 union 429 { 430 // CSC 431 struct 432 { 433 uint32_t CscConstantC10 : 16; 434 uint32_t CscConstantC11 : 16; 435 }; 436 437 // Dataport-based rotation 438 struct 439 { 440 uint32_t CscConstantC6 : 16; 441 uint32_t CscConstantC7 : 16; 442 }; 443 444 uint32_t Value; 445 } DW05; 446 447 // DWORD 6 - GRF R1.6 448 union 449 { 450 // Const Blending 451 struct 452 { 453 uint32_t ConstantBlendingAlphaLayer1 : 8; 454 uint32_t ConstantBlendingAlphaLayer2 : 8; 455 uint32_t ConstantBlendingAlphaLayer3 : 8; 456 uint32_t ConstantBlendingAlphaLayer4 : 8; 457 }; 458 459 // DNDI 460 struct 461 { 462 uint32_t HalfStatisticsSurfacePitch : 16; // Statistics surface pitch divided by 2 463 uint32_t StatisticsSurfaceHeight : 16; // Statistics surface height divided by 4 464 }; 465 466 // Dataport-based rotation 467 struct 468 { 469 uint32_t CscConstantC8 : 16; 470 uint32_t CscConstantC9 : 16; 471 }; 472 473 uint32_t Value; 474 } DW06; 475 476 // DWORD 7 - GRF R1.7 477 union 478 { 479 // Const Blending 480 struct 481 { 482 uint32_t ConstantBlendingAlphaLayer5 : 8; 483 uint32_t ConstantBlendingAlphaLayer6 : 8; 484 uint32_t ConstantBlendingAlphaLayer7 : 8; 485 uint32_t PointerToInlineParameters : 8; 486 }; 487 488 struct 489 { 490 uint32_t ConstantBlendingAlphaLayer51 : 8; 491 uint32_t ConstantBlendingAlphaLayer61 : 8; 492 uint32_t ConstantBlendingAlphaLayer71 : 8; 493 uint32_t OutputDepth : 8; 494 }; 495 496 // DNDI 497 struct 498 { 499 uint32_t TopFieldFirst : 8; 500 uint32_t : 24; 501 }; 502 503 // Dataport-based rotation 504 struct 505 { 506 uint32_t CscConstantC10 : 16; 507 uint32_t CscConstantC11 : 16; 508 }; 509 510 uint32_t Value; 511 } DW07; 512 513 // DWORD 8 - GRF R2.0 514 union 515 { 516 struct 517 { 518 uint32_t DestinationRectangleWidth : 16; 519 uint32_t DestinationRectangleHeight : 16; 520 }; 521 522 // Dataport-based rotation 523 struct 524 { 525 uint32_t InputIndex : 32; 526 }; 527 528 uint32_t Value; 529 } DW08; 530 531 // DWORD 9 - GRF R2.1 532 union 533 { 534 // Common structure for all gens 535 struct 536 { 537 uint32_t RotationMirrorMode : 3; 538 uint32_t RotationMirrorAllLayer : 1; 539 uint32_t DualOutputMode : 1; 540 uint32_t : 11; 541 uint32_t ChannelSwap : 1; 542 uint32_t : 1; 543 uint32_t : 1; 544 uint32_t : 13; 545 }; 546 547 // Bit field(s) for gen8+ only 548 struct 549 { 550 uint32_t : 3; 551 uint32_t : 1; 552 uint32_t : 12; 553 uint32_t : 1; 554 uint32_t : 10; 555 uint32_t IEFByPassEnable : 1; 556 uint32_t : 4; 557 }; 558 559 // Bit field(s) for Gen9+ only 560 struct 561 { 562 uint32_t : 5; 563 uint32_t : 3; 564 uint32_t : 8; 565 uint32_t : 1; 566 uint32_t : 1; 567 uint32_t AlphaChannelCalculation : 1; 568 uint32_t : 8; 569 uint32_t : 1; 570 uint32_t : 4; 571 }; 572 573 // Dataport-based rotation 574 struct 575 { 576 uint32_t OutputIndex : 32; 577 }; 578 579 uint32_t Value; 580 } DW09; 581 582 // DWORD 10 - GRF R2.2 583 union 584 { 585 struct // Gen7.5 and Gen8 Chroma Siting 586 { 587 uint32_t ChromaSitingLocation : 3; 588 uint32_t : 29; 589 }; 590 591 uint32_t Value; 592 } DW10; 593 594 // DWORD 11 - GRF R2.3 595 union 596 { 597 uint32_t Value; 598 } DW11; 599 600 // DWORD 12 - GRF R2.4 601 union 602 { 603 // CE 604 struct 605 { 606 uint32_t ColorProcessingEnable : 1; 607 uint32_t : 1; 608 uint32_t MessageFormat : 2; 609 uint32_t : 1; 610 uint32_t ColorProcessingStatePointer : 27; 611 }; 612 613 uint32_t Value; 614 } DW12; 615 616 // DWORD 13 - GRF R2.5 617 union 618 { 619 // Colorfill ARGB 620 struct 621 { 622 uint32_t ColorFill_R : 8; // R 623 uint32_t ColorFill_G : 8; // G 624 uint32_t ColorFill_B : 8; // B 625 uint32_t ColorFill_A : 8; // A 626 }; 627 628 // Colorfill AYUV 629 struct 630 { 631 uint32_t ColorFill_V : 8; // V 632 uint32_t ColorFill_Y : 8; // Y 633 uint32_t ColorFill_U : 8; // U 634 uint32_t : 8; // A 635 }; 636 637 uint32_t Value; 638 } DW13; 639 640 // DWORD 14 - GRF R2.6 641 union 642 { 643 // Lumakey, NLAS 644 struct 645 { 646 uint32_t LumakeyLowThreshold : 8; 647 uint32_t LumakeyHighThreshold : 8; 648 uint32_t NLASEnable : 8; 649 uint32_t Reserved : 8; 650 }; 651 652 uint32_t Value; 653 } DW14; 654 655 // DWORD 15 - GRF R2.7 656 union 657 { 658 // Save 659 struct 660 { 661 uint8_t DestinationPackedYOffset; 662 uint8_t DestinationPackedUOffset; 663 uint8_t DestinationPackedVOffset; 664 uint8_t DestinationRGBFormat; 665 }; 666 667 uint32_t Value; 668 } DW15; 669 670 // DWORD 16 - GRF R3.0 671 union 672 { 673 // Sampler Load 674 struct 675 { 676 float HorizontalScalingStepRatioLayer0; 677 }; 678 679 uint32_t Value; 680 } DW16; 681 682 // DWORD 17 - GRF R3.1 683 union 684 { 685 // Sampler Load 686 struct 687 { 688 float HorizontalScalingStepRatioLayer1; 689 }; 690 691 uint32_t Value; 692 } DW17; 693 694 // DWORD 18 - GRF R3.2 695 union 696 { 697 // Sampler Load 698 struct 699 { 700 float HorizontalScalingStepRatioLayer2; 701 }; 702 703 uint32_t Value; 704 } DW18; 705 706 // DWORD 19 - GRF R3.3 707 union 708 { 709 // Sampler Load 710 struct 711 { 712 float HorizontalScalingStepRatioLayer3; 713 }; 714 715 uint32_t Value; 716 } DW19; 717 718 // DWORD 20 - GRF R3.4 719 union 720 { 721 // Sampler Load 722 struct 723 { 724 float HorizontalScalingStepRatioLayer4; 725 }; 726 727 uint32_t Value; 728 } DW20; 729 730 // DWORD 21 - GRF R3.5 731 union 732 { 733 // Sampler Load 734 struct 735 { 736 float HorizontalScalingStepRatioLayer5; 737 }; 738 739 uint32_t Value; 740 } DW21; 741 742 // DWORD 22 - GRF R3.6 743 union 744 { 745 // Sampler Load 746 struct 747 { 748 float HorizontalScalingStepRatioLayer6; 749 }; 750 751 uint32_t Value; 752 } DW22; 753 754 // DWORD 23 - GRF R3.7 755 union 756 { 757 // Sampler Load 758 struct 759 { 760 float HorizontalScalingStepRatioLayer7; 761 }; 762 763 uint32_t Value; 764 } DW23; 765 766 // DWORD 24 - GRF R4.0 767 union 768 { 769 // Sampler Load 770 struct 771 { 772 float VerticalScalingStepRatioLayer0; 773 }; 774 775 // Dataport Load 776 struct 777 { 778 uint8_t SourcePackedYOffset; 779 uint8_t SourcePackedUOffset; 780 uint8_t SourcePackedVOffset; 781 uint8_t Reserved; 782 }; 783 784 uint32_t Value; 785 } DW24; 786 787 // DWORD 25 - GRF R4.1 788 union 789 { 790 // Sampler Load 791 struct 792 { 793 float VerticalScalingStepRatioLayer1; 794 }; 795 796 uint32_t Value; 797 } DW25; 798 799 // DWORD 26 - GRF R4.2 800 union 801 { 802 // Sampler Load 803 struct 804 { 805 float VerticalScalingStepRatioLayer2; 806 }; 807 808 // Dataport Load 809 struct 810 { 811 uint32_t HorizontalFrameOriginOffset : 16; 812 uint32_t VerticalFrameOriginOffset : 16; 813 }; 814 815 uint32_t Value; 816 } DW26; 817 818 // DWORD 27 - GRF R4.3 819 union 820 { 821 // Sampler Load 822 struct 823 { 824 float VerticalScalingStepRatioLayer3; 825 }; 826 827 uint32_t Value; 828 } DW27; 829 830 // DWORD 28 - GRF R4.4 831 union 832 { 833 // Sampler Load 834 struct 835 { 836 float VerticalScalingStepRatioLayer4; 837 }; 838 839 uint32_t Value; 840 } DW28; 841 842 // DWORD 29 - GRF R4.5 843 union 844 { 845 // Sampler Load 846 struct 847 { 848 float VerticalScalingStepRatioLayer5; 849 }; 850 851 uint32_t Value; 852 } DW29; 853 854 // DWORD 30 - GRF R4.6 855 union 856 { 857 // Sampler Load 858 struct 859 { 860 float VerticalScalingStepRatioLayer6; 861 }; 862 863 uint32_t Value; 864 } DW30; 865 866 // DWORD 31 - GRF R4.7 867 union 868 { 869 // Sampler Load 870 struct 871 { 872 float VerticalScalingStepRatioLayer7; 873 }; 874 875 uint32_t Value; 876 } DW31; 877 878 // DWORD 32 - GRF R5.0 879 union 880 { 881 // Sampler Load 882 struct 883 { 884 float VerticalFrameOriginLayer0; 885 }; 886 887 uint32_t Value; 888 } DW32; 889 890 // DWORD 33 - GRF R5.1 891 union 892 { 893 // Sampler Load 894 struct 895 { 896 float VerticalFrameOriginLayer1; 897 }; 898 899 uint32_t Value; 900 } DW33; 901 902 // DWORD 34 - GRF R5.2 903 union 904 { 905 // Sampler Load 906 struct 907 { 908 float VerticalFrameOriginLayer2; 909 }; 910 911 uint32_t Value; 912 } DW34; 913 914 // DWORD 35 - GRF R5.3 915 union 916 { 917 // Sampler Load 918 struct 919 { 920 float VerticalFrameOriginLayer3; 921 }; 922 923 uint32_t Value; 924 } DW35; 925 926 // DWORD 36 - GRF R5.4 927 union 928 { 929 // Sampler Load 930 struct 931 { 932 float VerticalFrameOriginLayer4; 933 }; 934 935 uint32_t Value; 936 } DW36; 937 938 // DWORD 37 - GRF R5.5 939 union 940 { 941 // Sampler Load 942 struct 943 { 944 float VerticalFrameOriginLayer5; 945 }; 946 947 uint32_t Value; 948 } DW37; 949 950 // DWORD 38 - GRF R5.6 951 union 952 { 953 // Sampler Load 954 struct 955 { 956 float VerticalFrameOriginLayer6; 957 }; 958 959 uint32_t Value; 960 } DW38; 961 962 // DWORD 39 - GRF R5.7 963 union 964 { 965 // Sampler Load 966 struct 967 { 968 float VerticalFrameOriginLayer7; 969 }; 970 971 uint32_t Value; 972 } DW39; 973 974 // DWORD 40 - GRF R6.0 975 union 976 { 977 // Sampler Load 978 struct 979 { 980 float HorizontalFrameOriginLayer0; 981 }; 982 983 uint32_t Value; 984 } DW40; 985 986 // DWORD 41 - GRF R6.1 987 union 988 { 989 // Sampler Load 990 struct 991 { 992 float HorizontalFrameOriginLayer1; 993 }; 994 995 uint32_t Value; 996 } DW41; 997 998 // DWORD 42 - GRF R6.2 999 union 1000 { 1001 // Sampler Load 1002 struct 1003 { 1004 float HorizontalFrameOriginLayer2; 1005 }; 1006 1007 uint32_t Value; 1008 } DW42; 1009 1010 // DWORD 43 - GRF R6.3 1011 union 1012 { 1013 // Sampler Load 1014 struct 1015 { 1016 float HorizontalFrameOriginLayer3; 1017 }; 1018 1019 uint32_t Value; 1020 } DW43; 1021 1022 // DWORD 44 - GRF R6.4 1023 union 1024 { 1025 // Sampler Load 1026 struct 1027 { 1028 float HorizontalFrameOriginLayer4; 1029 }; 1030 1031 uint32_t Value; 1032 } DW44; 1033 1034 // DWORD 45 - GRF R6.5 1035 union 1036 { 1037 // Sampler Load 1038 struct 1039 { 1040 float HorizontalFrameOriginLayer5; 1041 }; 1042 1043 uint32_t Value; 1044 } DW45; 1045 1046 // DWORD 46 - GRF R6.6 1047 union 1048 { 1049 // Sampler Load 1050 struct 1051 { 1052 float HorizontalFrameOriginLayer6; 1053 }; 1054 1055 uint32_t Value; 1056 } DW46; 1057 1058 // DWORD 47 - GRF R6.7 1059 union 1060 { 1061 // Sampler Load 1062 struct 1063 { 1064 float HorizontalFrameOriginLayer7; 1065 }; 1066 1067 uint32_t Value; 1068 } DW47; 1069 1070 // DWORD48 - GRF R7.0 1071 union 1072 { 1073 struct 1074 { 1075 uint32_t DestXTopLeftLayer0 : BITFIELD_RANGE(0,15); 1076 uint32_t DestYTopLeftLayer0 : BITFIELD_RANGE(16,31); 1077 }; 1078 1079 uint32_t Value; 1080 } DW48; 1081 1082 // DWORD49 - GRF R7.1 1083 union 1084 { 1085 struct 1086 { 1087 uint32_t DestXTopLeftLayer1 : BITFIELD_RANGE(0,15); 1088 uint32_t DestYTopLeftLayer1 : BITFIELD_RANGE(16,31); 1089 }; 1090 1091 uint32_t Value; 1092 } DW49; 1093 1094 // DWORD50 - GRF R7.2 1095 union 1096 { 1097 struct 1098 { 1099 uint32_t DestXTopLeftLayer2 : BITFIELD_RANGE(0,15); 1100 uint32_t DestYTopLeftLayer2 : BITFIELD_RANGE(16,31); 1101 }; 1102 1103 uint32_t Value; 1104 } DW50; 1105 1106 // DWORD51 - GRF R7.3 1107 union 1108 { 1109 struct 1110 { 1111 uint32_t DestXTopLeftLayer3 : BITFIELD_RANGE(0,15); 1112 uint32_t DestYTopLeftLayer3 : BITFIELD_RANGE(16,31); 1113 }; 1114 1115 uint32_t Value; 1116 } DW51; 1117 1118 // DWORD52 - GRF R7.4 1119 union 1120 { 1121 struct 1122 { 1123 uint32_t DestXTopLeftLayer4 : BITFIELD_RANGE(0,15); 1124 uint32_t DestYTopLeftLayer4 : BITFIELD_RANGE(16,31); 1125 }; 1126 1127 uint32_t Value; 1128 } DW52; 1129 1130 // DWORD53 - GRF R7.5 1131 union 1132 { 1133 struct 1134 { 1135 uint32_t DestXTopLeftLayer5 : BITFIELD_RANGE(0,15); 1136 uint32_t DestYTopLeftLayer5 : BITFIELD_RANGE(16,31); 1137 }; 1138 1139 uint32_t Value; 1140 } DW53; 1141 1142 // DWORD54 - GRF R7.6 1143 union 1144 { 1145 struct 1146 { 1147 uint32_t DestXTopLeftLayer6 : BITFIELD_RANGE(0,15); 1148 uint32_t DestYTopLeftLayer6 : BITFIELD_RANGE(16,31); 1149 }; 1150 1151 uint32_t Value; 1152 } DW54; 1153 1154 // DWORD55 - GRF R7.7 1155 union 1156 { 1157 struct 1158 { 1159 uint32_t DestXTopLeftLayer7 : BITFIELD_RANGE(0,15); 1160 uint32_t DestYTopLeftLayer7 : BITFIELD_RANGE(16,31); 1161 }; 1162 1163 uint32_t Value; 1164 } DW55; 1165 1166 // DWORD56 - GRF R8.0 1167 union 1168 { 1169 struct 1170 { 1171 uint32_t DestXBottomRightLayer0 : BITFIELD_RANGE(0,15); 1172 uint32_t DestYBottomRightLayer0 : BITFIELD_RANGE(16,31); 1173 }; 1174 1175 uint32_t Value; 1176 } DW56; 1177 1178 // DWORD57 - GRF R8.1 1179 union 1180 { 1181 struct 1182 { 1183 uint32_t DestXBottomRightLayer1 : BITFIELD_RANGE(0,15); 1184 uint32_t DestYBottomRightLayer1 : BITFIELD_RANGE(16,31); 1185 }; 1186 1187 uint32_t Value; 1188 } DW57; 1189 1190 // DWORD58 - GRF R8.2 1191 union 1192 { 1193 struct 1194 { 1195 uint32_t DestXBottomRightLayer2 : BITFIELD_RANGE(0,15); 1196 uint32_t DestYBottomRightLayer2 : BITFIELD_RANGE(16,31); 1197 }; 1198 1199 uint32_t Value; 1200 } DW58; 1201 1202 // DWORD59 - GRF R8.3 1203 union 1204 { 1205 struct 1206 { 1207 uint32_t DestXBottomRightLayer3 : BITFIELD_RANGE(0,15); 1208 uint32_t DestYBottomRightLayer3 : BITFIELD_RANGE(16,31); 1209 }; 1210 1211 uint32_t Value; 1212 } DW59; 1213 1214 // DWORD60 - GRF R8.4 1215 union 1216 { 1217 struct 1218 { 1219 uint32_t DestXBottomRightLayer4 : BITFIELD_RANGE(0,15); 1220 uint32_t DestYBottomRightLayer4 : BITFIELD_RANGE(16,31); 1221 }; 1222 1223 uint32_t Value; 1224 } DW60; 1225 1226 // DWORD61 - GRF R8.5 1227 union 1228 { 1229 struct 1230 { 1231 uint32_t DestXBottomRightLayer5 : BITFIELD_RANGE(0,15); 1232 uint32_t DestYBottomRightLayer5 : BITFIELD_RANGE(16,31); 1233 }; 1234 1235 uint32_t Value; 1236 } DW61; 1237 1238 // DWORD62 - GRF R8.6 1239 union 1240 { 1241 struct 1242 { 1243 uint32_t DestXBottomRightLayer6 : BITFIELD_RANGE(0,15); 1244 uint32_t DestYBottomRightLayer6 : BITFIELD_RANGE(16,31); 1245 }; 1246 1247 uint32_t Value; 1248 } DW62; 1249 1250 // DWORD63 - GRF R8.7 1251 union 1252 { 1253 struct 1254 { 1255 uint32_t DestXBottomRightLayer7 : BITFIELD_RANGE(0,15); 1256 uint32_t DestYBottomRightLayer7 : BITFIELD_RANGE(16,31); 1257 }; 1258 1259 uint32_t Value; 1260 } DW63; 1261 1262 // DWORD64 - GRF R9.0 1263 union 1264 { 1265 struct 1266 { 1267 float MainVideoXScalingStepLeft; 1268 }; 1269 1270 uint32_t Value; 1271 } DW64; 1272 1273 // DWORD65 - GRF R9.1 1274 union 1275 { 1276 struct 1277 { 1278 float VideoStepDeltaForNonLinearRegion; 1279 }; 1280 1281 uint32_t Value; 1282 } DW65; 1283 1284 // DWORD66 - GRF R9.2 1285 union 1286 { 1287 struct 1288 { 1289 uint32_t StartofLinearScalingInPixelPositionC0 : BITFIELD_RANGE(0,15); 1290 uint32_t StartofRHSNonLinearScalingInPixelPositionC1 : BITFIELD_RANGE(16,31); 1291 }; 1292 1293 uint32_t Value; 1294 } DW66; 1295 1296 // DWORD 67 - GRF R9.3 1297 union 1298 { 1299 // Sampler Load 1300 struct 1301 { 1302 float MainVideoXScalingStepCenter; 1303 }; 1304 1305 uint32_t Value; 1306 } DW67; 1307 1308 // DWORD 68 - GRF R9.4 1309 union 1310 { 1311 // Sampler Load 1312 struct 1313 { 1314 float MainVideoXScalingStepRight; 1315 }; 1316 1317 uint32_t Value; 1318 } DW68; 1319 1320 // DWORD63 - GRF R8.7 1321 union 1322 { 1323 struct 1324 { 1325 uint32_t DestHorizontalBlockOrigin : BITFIELD_RANGE(0,15); 1326 uint32_t DestVerticalBlockOrigin : BITFIELD_RANGE(16,31); 1327 }; 1328 1329 uint32_t Value; 1330 } DW69; 1331 1332 // DWORD 70-71 - GRF 9.6-9.7 - Padding is needed as we program ConstantURBEntryReadLength = iCurbeLength >> 5 1333 uint32_t dwPad[2]; 1334 }; 1335 1336 // Defined in Inline parameter computation 1337 struct MEDIA_OBJECT_KA2_STATIC_DATA 1338 { 1339 // DWORD 0 - GRF R1.0 1340 union 1341 { 1342 // CSC 1343 struct 1344 { 1345 uint32_t CscConstantC0 : 16; 1346 uint32_t CscConstantC1 : 16; 1347 }; 1348 1349 // Chroma Denoise 1350 struct 1351 { 1352 uint32_t LocalDifferenceThresholdU : 8; 1353 uint32_t LocalDifferenceThresholdV : 8; 1354 uint32_t SobelEdgeThresholdU : 8; 1355 uint32_t SobelEdgeThresholdV : 8; 1356 }; 1357 1358 uint32_t Value; 1359 } DW00; 1360 1361 // DWORD 1 - GRF R1.1 1362 union 1363 { 1364 // CSC 1365 struct 1366 { 1367 uint32_t CscConstantC2 : 16; 1368 uint32_t CscConstantC3 : 16; 1369 }; 1370 1371 // Chroma Denoise 1372 struct 1373 { 1374 uint32_t HistoryInitialValueU : 8; 1375 uint32_t HistoryInitialValueV : 8; 1376 uint32_t HistoryMaxU : 8; 1377 uint32_t HistoryMaxV : 8; 1378 }; 1379 1380 uint32_t Value; 1381 } DW01; 1382 1383 // DWORD 2 - GRF R1.2 1384 union 1385 { 1386 // CSC 1387 struct 1388 { 1389 uint32_t CscConstantC4 : 16; 1390 uint32_t CscConstantC5 : 16; 1391 }; 1392 1393 // Chroma Denoise 1394 struct 1395 { 1396 uint32_t HistoryDeltaU : 8; 1397 uint32_t HistoryDeltaV : 8; 1398 uint32_t DNSADThresholdU : 8; 1399 uint32_t DNSADThresholdV : 8; 1400 }; 1401 1402 uint32_t Value; 1403 } DW02; 1404 1405 // DWORD 3 - GRF R1.3 1406 union 1407 { 1408 // CSC 1409 struct 1410 { 1411 uint32_t CscConstantC6 : 16; 1412 uint32_t CscConstantC7 : 16; 1413 }; 1414 1415 // Chroma Denoise 1416 struct 1417 { 1418 uint32_t DNTDThresholdU : 8; 1419 uint32_t DNTDThresholdV : 8; 1420 uint32_t DNLTDThresholdU : 8; 1421 uint32_t DNLTDThresholdV : 8; 1422 }; 1423 1424 uint32_t Value; 1425 } DW03; 1426 1427 // DWORD 4 - GRF R1.4 1428 union 1429 { 1430 // CSC 1431 struct 1432 { 1433 uint32_t CscConstantC8 : 16; 1434 uint32_t CscConstantC9 : 16; 1435 }; 1436 1437 uint32_t Value; 1438 } DW04; 1439 1440 // DWORD 5 - GRF R1.5 1441 union 1442 { 1443 // CSC 1444 struct 1445 { 1446 uint32_t CscConstantC10 : 16; 1447 uint32_t CscConstantC11 : 16; 1448 }; 1449 1450 uint32_t Value; 1451 } DW05; 1452 1453 // DWORD 6 - GRF R1.6 1454 union 1455 { 1456 // Const Blending 1457 struct 1458 { 1459 uint32_t ConstantBlendingAlphaLayer1 : 8; 1460 uint32_t ConstantBlendingAlphaLayer2 : 8; 1461 uint32_t ConstantBlendingAlphaLayer3 : 8; 1462 uint32_t ConstantBlendingAlphaLayer4 : 8; 1463 }; 1464 1465 // DNDI 1466 struct 1467 { 1468 uint32_t HalfStatisticsSurfacePitch : 16; // Statistics surface pitch divided by 2 1469 uint32_t StatisticsSurfaceHeight : 16; // Statistics surface height divided by 4 1470 }; 1471 1472 uint32_t Value; 1473 } DW06; 1474 1475 // DWORD 7 - GRF R1.7 1476 union 1477 { 1478 // Const Blending 1479 struct 1480 { 1481 uint32_t ConstantBlendingAlphaLayer5 : 8; 1482 uint32_t ConstantBlendingAlphaLayer6 : 8; 1483 uint32_t ConstantBlendingAlphaLayer7 : 8; 1484 uint32_t PointerToInlineParameters : 8; 1485 }; 1486 1487 struct 1488 { 1489 uint32_t ConstantBlendingAlphaLayer51 : 8; 1490 uint32_t ConstantBlendingAlphaLayer61 : 8; 1491 uint32_t ConstantBlendingAlphaLayer71 : 8; 1492 uint32_t OutputDepth : 8; 1493 }; 1494 1495 // DNDI 1496 struct 1497 { 1498 uint32_t TopFieldFirst : 8; 1499 uint32_t : 24; 1500 }; 1501 1502 uint32_t Value; 1503 } DW07; 1504 1505 // DWORD 8 - GRF R2.0 1506 union 1507 { 1508 struct 1509 { 1510 uint32_t DestinationRectangleWidth : 16; 1511 uint32_t DestinationRectangleHeight : 16; 1512 }; 1513 1514 uint32_t Value; 1515 } DW08; 1516 1517 // DWORD 9 - GRF R2.1 1518 union 1519 { 1520 struct 1521 { 1522 uint32_t RotationMirrorMode : 3; 1523 uint32_t RotationMirrorAllLayer : 1; 1524 uint32_t DualOutputMode : 1; 1525 uint32_t : 11; 1526 uint32_t ChannelSwap : 1; 1527 uint32_t : 1; 1528 uint32_t : 1; 1529 uint32_t : 13; 1530 }; 1531 1532 // Bit field(s) for gen8+ only 1533 struct 1534 { 1535 uint32_t : 8; // Dual output 1536 uint32_t : 8; // Reserved 1537 uint32_t ChannelSwap : 1; 1538 uint32_t AlphaChannelCalculation : 1; 1539 uint32_t : 9; 1540 uint32_t IEFByPassEnable : 1; 1541 uint32_t : 4; 1542 }ObjKa2Gen8; 1543 1544 // Bit field(s) for Gen9+ only 1545 struct 1546 { 1547 uint32_t : 5; 1548 uint32_t : 3; 1549 uint32_t : 8; 1550 uint32_t ChannelSwap : 1; 1551 uint32_t DitheringAvdFlag : 1; 1552 uint32_t AlphaChannelCalculation : 1; 1553 uint32_t : 8; 1554 uint32_t IEFByPassEnable : 1; 1555 uint32_t : 4; 1556 }ObjKa2Gen9; 1557 1558 uint32_t Value; 1559 } DW09; 1560 1561 // DWORD 10 - GRF R2.2 1562 union 1563 { 1564 struct // Gen7.5 and Gen8 Chroma Siting 1565 { 1566 uint32_t ChromaSitingLocation : 3; 1567 uint32_t : 29; 1568 }; 1569 1570 struct // Gen9+ Rotation 1571 { 1572 uint32_t RotationAngleofLayer0 : 3; 1573 uint32_t RotationAngleofLayer1 : 3; 1574 uint32_t RotationAngleofLayer2 : 3; 1575 uint32_t RotationAngleofLayer3 : 3; 1576 uint32_t RotationAngleofLayer4 : 3; 1577 uint32_t RotationAngleofLayer5 : 3; 1578 uint32_t RotationAngleofLayer6 : 3; 1579 uint32_t RotationAngleofLayer7 : 3; 1580 uint32_t ChromaSitingLocation : 3; 1581 uint32_t MonoXORCompositeMask : 3; 1582 uint32_t : 2; 1583 } ObjKa2Gen9; 1584 1585 uint32_t Value; 1586 } DW10; 1587 1588 // DWORD 11 - GRF R2.3 1589 union 1590 { 1591 struct 1592 { 1593 float TopBottomDelta; // Used for interlace scaling on Gen8- 1594 }; 1595 1596 struct 1597 { 1598 float ChromasitingUOffset; // Param for 3D Sampler use case 1599 }; 1600 1601 uint32_t Value; 1602 } DW11; 1603 1604 // DWORD 12 - GRF R2.4 1605 union 1606 { 1607 // CE 1608 struct 1609 { 1610 uint32_t ColorProcessingEnable : 1; 1611 uint32_t : 1; 1612 uint32_t MessageFormat : 2; 1613 uint32_t : 1; 1614 uint32_t ColorProcessingStatePointer : 27; 1615 }; 1616 1617 struct 1618 { 1619 float TopBottomDelta; // Used for interlace scaling on Gen9+ 1620 }; 1621 1622 struct 1623 { 1624 float ChromasitingVOffset; // Param only for 3D Sampler use case 1625 }; 1626 1627 uint32_t Value; 1628 } DW12; 1629 1630 // DWORD 13 - GRF R2.5 1631 union 1632 { 1633 // Colorfill ARGB 1634 struct 1635 { 1636 uint32_t ColorFill_R : 8; // R 1637 uint32_t ColorFill_G : 8; // G 1638 uint32_t ColorFill_B : 8; // B 1639 uint32_t ColorFill_A : 8; // A 1640 }; 1641 1642 // Colorfill AYUV 1643 struct 1644 { 1645 uint32_t ColorFill_V : 8; // V 1646 uint32_t ColorFill_Y : 8; // Y 1647 uint32_t ColorFill_U : 8; // U 1648 uint32_t : 8; // A 1649 }; 1650 1651 uint32_t Value; 1652 } DW13; 1653 1654 // DWORD 14 - GRF R2.6 1655 union 1656 { 1657 // Lumakey, NLAS 1658 struct 1659 { 1660 uint32_t LumakeyLowThreshold : 8; 1661 uint32_t LumakeyHighThreshold : 8; 1662 uint32_t NLASEnable : 8; 1663 uint32_t Reserved : 8; 1664 }; 1665 1666 uint32_t Value; 1667 } DW14; 1668 1669 // DWORD 15 - GRF R2.7 1670 union 1671 { 1672 // Save 1673 struct 1674 { 1675 uint8_t DestinationPackedYOffset; 1676 uint8_t DestinationPackedUOffset; 1677 uint8_t DestinationPackedVOffset; 1678 uint8_t DestinationRGBFormat; 1679 }; 1680 1681 uint32_t Value; 1682 } DW15; 1683 1684 // DWORD 16 - GRF R3.0 1685 union 1686 { 1687 // Sampler Load 1688 struct 1689 { 1690 float HorizontalScalingStepRatioLayer0; 1691 }; 1692 1693 uint32_t Value; 1694 } DW16; 1695 1696 // DWORD 17 - GRF R3.1 1697 union 1698 { 1699 // Sampler Load 1700 struct 1701 { 1702 float HorizontalScalingStepRatioLayer1; 1703 }; 1704 1705 uint32_t Value; 1706 } DW17; 1707 1708 // DWORD 18 - GRF R3.2 1709 union 1710 { 1711 // Sampler Load 1712 struct 1713 { 1714 float HorizontalScalingStepRatioLayer2; 1715 }; 1716 1717 uint32_t Value; 1718 } DW18; 1719 1720 // DWORD 19 - GRF R3.3 1721 union 1722 { 1723 // Sampler Load 1724 struct 1725 { 1726 float HorizontalScalingStepRatioLayer3; 1727 }; 1728 1729 uint32_t Value; 1730 } DW19; 1731 1732 // DWORD 20 - GRF R3.4 1733 union 1734 { 1735 // Sampler Load 1736 struct 1737 { 1738 float HorizontalScalingStepRatioLayer4; 1739 }; 1740 1741 uint32_t Value; 1742 } DW20; 1743 1744 // DWORD 21 - GRF R3.5 1745 union 1746 { 1747 // Sampler Load 1748 struct 1749 { 1750 float HorizontalScalingStepRatioLayer5; 1751 }; 1752 1753 uint32_t Value; 1754 } DW21; 1755 1756 // DWORD 22 - GRF R3.6 1757 union 1758 { 1759 // Sampler Load 1760 struct 1761 { 1762 float HorizontalScalingStepRatioLayer6; 1763 }; 1764 1765 uint32_t Value; 1766 } DW22; 1767 1768 // DWORD 23 - GRF R3.7 1769 union 1770 { 1771 // Sampler Load 1772 struct 1773 { 1774 float HorizontalScalingStepRatioLayer7; 1775 }; 1776 1777 uint32_t Value; 1778 } DW23; 1779 1780 // DWORD 24 - GRF R4.0 1781 union 1782 { 1783 // Sampler Load 1784 struct 1785 { 1786 float VerticalScalingStepRatioLayer0; 1787 }; 1788 1789 // Dataport Load 1790 struct 1791 { 1792 uint8_t SourcePackedYOffset; 1793 uint8_t SourcePackedUOffset; 1794 uint8_t SourcePackedVOffset; 1795 uint8_t Reserved; 1796 }; 1797 1798 uint32_t Value; 1799 } DW24; 1800 1801 // DWORD 25 - GRF R4.1 1802 union 1803 { 1804 // Sampler Load 1805 struct 1806 { 1807 float VerticalScalingStepRatioLayer1; 1808 }; 1809 1810 uint32_t Value; 1811 } DW25; 1812 1813 // DWORD 26 - GRF R4.2 1814 union 1815 { 1816 // Sampler Load 1817 struct 1818 { 1819 float VerticalScalingStepRatioLayer2; 1820 }; 1821 1822 // Dataport Load 1823 struct 1824 { 1825 uint32_t HorizontalFrameOriginOffset : 16; 1826 uint32_t VerticalFrameOriginOffset : 16; 1827 }; 1828 1829 uint32_t Value; 1830 } DW26; 1831 1832 // DWORD 27 - GRF R4.3 1833 union 1834 { 1835 // Sampler Load 1836 struct 1837 { 1838 float VerticalScalingStepRatioLayer3; 1839 }; 1840 1841 uint32_t Value; 1842 } DW27; 1843 1844 // DWORD 28 - GRF R4.4 1845 union 1846 { 1847 // Sampler Load 1848 struct 1849 { 1850 float VerticalScalingStepRatioLayer4; 1851 }; 1852 1853 uint32_t Value; 1854 } DW28; 1855 1856 // DWORD 29 - GRF R4.5 1857 union 1858 { 1859 // Sampler Load 1860 struct 1861 { 1862 float VerticalScalingStepRatioLayer5; 1863 }; 1864 1865 uint32_t Value; 1866 } DW29; 1867 1868 // DWORD 30 - GRF R4.6 1869 union 1870 { 1871 // Sampler Load 1872 struct 1873 { 1874 float VerticalScalingStepRatioLayer6; 1875 }; 1876 1877 uint32_t Value; 1878 } DW30; 1879 1880 // DWORD 31 - GRF R4.7 1881 union 1882 { 1883 // Sampler Load 1884 struct 1885 { 1886 float VerticalScalingStepRatioLayer7; 1887 }; 1888 1889 uint32_t Value; 1890 } DW31; 1891 1892 // DWORD 32 - GRF R5.0 1893 union 1894 { 1895 // Sampler Load 1896 struct 1897 { 1898 float VerticalFrameOriginLayer0; 1899 }; 1900 1901 uint32_t Value; 1902 } DW32; 1903 1904 // DWORD 33 - GRF R5.1 1905 union 1906 { 1907 // Sampler Load 1908 struct 1909 { 1910 float VerticalFrameOriginLayer1; 1911 }; 1912 1913 uint32_t Value; 1914 } DW33; 1915 1916 // DWORD 34 - GRF R5.2 1917 union 1918 { 1919 // Sampler Load 1920 struct 1921 { 1922 float VerticalFrameOriginLayer2; 1923 }; 1924 1925 uint32_t Value; 1926 } DW34; 1927 1928 // DWORD 35 - GRF R5.3 1929 union 1930 { 1931 // Sampler Load 1932 struct 1933 { 1934 float VerticalFrameOriginLayer3; 1935 }; 1936 1937 uint32_t Value; 1938 } DW35; 1939 1940 // DWORD 36 - GRF R5.4 1941 union 1942 { 1943 // Sampler Load 1944 struct 1945 { 1946 float VerticalFrameOriginLayer4; 1947 }; 1948 1949 uint32_t Value; 1950 } DW36; 1951 1952 // DWORD 37 - GRF R5.5 1953 union 1954 { 1955 // Sampler Load 1956 struct 1957 { 1958 float VerticalFrameOriginLayer5; 1959 }; 1960 1961 uint32_t Value; 1962 } DW37; 1963 1964 // DWORD 38 - GRF R5.6 1965 union 1966 { 1967 // Sampler Load 1968 struct 1969 { 1970 float VerticalFrameOriginLayer6; 1971 }; 1972 1973 uint32_t Value; 1974 } DW38; 1975 1976 // DWORD 39 - GRF R5.7 1977 union 1978 { 1979 // Sampler Load 1980 struct 1981 { 1982 float VerticalFrameOriginLayer7; 1983 }; 1984 1985 uint32_t Value; 1986 } DW39; 1987 1988 // DWORD 40 - GRF R6.0 1989 union 1990 { 1991 // Sampler Load 1992 struct 1993 { 1994 float HorizontalFrameOriginLayer0; 1995 }; 1996 1997 uint32_t Value; 1998 } DW40; 1999 2000 // DWORD 41 - GRF R6.1 2001 union 2002 { 2003 // Sampler Load 2004 struct 2005 { 2006 float HorizontalFrameOriginLayer1; 2007 }; 2008 2009 uint32_t Value; 2010 } DW41; 2011 2012 // DWORD 42 - GRF R6.2 2013 union 2014 { 2015 // Sampler Load 2016 struct 2017 { 2018 float HorizontalFrameOriginLayer2; 2019 }; 2020 2021 uint32_t Value; 2022 } DW42; 2023 2024 // DWORD 43 - GRF R6.3 2025 union 2026 { 2027 // Sampler Load 2028 struct 2029 { 2030 float HorizontalFrameOriginLayer3; 2031 }; 2032 2033 uint32_t Value; 2034 } DW43; 2035 2036 // DWORD 44 - GRF R6.4 2037 union 2038 { 2039 // Sampler Load 2040 struct 2041 { 2042 float HorizontalFrameOriginLayer4; 2043 }; 2044 2045 uint32_t Value; 2046 } DW44; 2047 2048 // DWORD 45 - GRF R6.5 2049 union 2050 { 2051 // Sampler Load 2052 struct 2053 { 2054 float HorizontalFrameOriginLayer5; 2055 }; 2056 2057 uint32_t Value; 2058 } DW45; 2059 2060 // DWORD 46 - GRF R6.6 2061 union 2062 { 2063 // Sampler Load 2064 struct 2065 { 2066 float HorizontalFrameOriginLayer6; 2067 }; 2068 2069 uint32_t Value; 2070 } DW46; 2071 2072 // DWORD 47 - GRF R6.7 2073 union 2074 { 2075 // Sampler Load 2076 struct 2077 { 2078 float HorizontalFrameOriginLayer7; 2079 }; 2080 2081 uint32_t Value; 2082 } DW47; 2083 }; 2084 2085 struct MEDIA_OBJECT_KA2_INLINE_DATA 2086 { 2087 // DWORD 0 - GRF R7.0 2088 union 2089 { 2090 // All 2091 struct 2092 { 2093 uint32_t DestinationBlockHorizontalOrigin : 16; 2094 uint32_t DestinationBlockVerticalOrigin : 16; 2095 }; 2096 2097 // Secure Block Copy 2098 struct 2099 { 2100 uint32_t BlockHeight : 16; 2101 uint32_t BufferOffset : 16; 2102 }; 2103 2104 // FMD Summation 2105 struct 2106 { 2107 uint32_t StartRowOffset; 2108 }; 2109 2110 uint32_t Value; 2111 } DW00; 2112 2113 // DWORD 1 - GRF R7.1 2114 union 2115 { 2116 // Composite 2117 struct 2118 { 2119 uint32_t HorizontalBlockCompositeMaskLayer0 : 16; 2120 uint32_t VerticalBlockCompositeMaskLayer0 : 16; 2121 }; 2122 2123 // FMD Summation 2124 struct 2125 { 2126 uint32_t TotalRows; 2127 }; 2128 2129 uint32_t Value; 2130 } DW01; 2131 2132 // DWORD 2 - GRF R7.2 2133 union 2134 { 2135 // Composite 2136 struct 2137 { 2138 uint32_t HorizontalBlockCompositeMaskLayer1 : 16; 2139 uint32_t VerticalBlockCompositeMaskLayer1 : 16; 2140 }; 2141 2142 // FMD Summation 2143 struct 2144 { 2145 uint32_t StartColumnOffset; 2146 }; 2147 2148 uint32_t Value; 2149 } DW02; 2150 2151 // DWORD 3 - GRF R7.3 2152 union 2153 { 2154 // Composite 2155 struct 2156 { 2157 uint32_t HorizontalBlockCompositeMaskLayer2 : 16; 2158 uint32_t VerticalBlockCompositeMaskLayer2 : 16; 2159 }; 2160 2161 // FMD Summation 2162 struct 2163 { 2164 uint32_t TotalColumns; 2165 }; 2166 2167 uint32_t Value; 2168 } DW03; 2169 2170 // DWORD 4 - GRF R7.4 2171 union 2172 { 2173 // Sampler Load 2174 struct 2175 { 2176 float VideoXScalingStep; 2177 }; 2178 2179 uint32_t Value; 2180 } DW04; 2181 2182 // DWORD 5 - GRF R7.5 2183 union 2184 { 2185 // NLAS 2186 struct 2187 { 2188 float VideoStepDelta; 2189 }; 2190 2191 uint32_t Value; 2192 } DW05; 2193 2194 // DWORD 6 - GRF R7.6 2195 union 2196 { 2197 // AVScaling 2198 struct 2199 { 2200 uint32_t VerticalBlockNumber :17; 2201 uint32_t AreaOfInterest :1; 2202 uint32_t :14; 2203 }; 2204 2205 uint32_t Value; 2206 } DW06; 2207 2208 // DWORD 7 - GRF R7.7 2209 union 2210 { 2211 // AVScaling 2212 struct 2213 { 2214 uint32_t GroupIDNumber; 2215 }; 2216 2217 uint32_t Value; 2218 } DW07; 2219 2220 // DWORD 8 - GRF R8.0 2221 union 2222 { 2223 // Composite 2224 struct 2225 { 2226 uint32_t HorizontalBlockCompositeMaskLayer3 : 16; 2227 uint32_t VerticalBlockCompositeMaskLayer3 : 16; 2228 }; 2229 2230 uint32_t Value; 2231 } DW08; 2232 2233 // DWORD 9 - GRF R8.1 2234 union 2235 { 2236 // Composite 2237 struct 2238 { 2239 uint32_t HorizontalBlockCompositeMaskLayer4 : 16; 2240 uint32_t VerticalBlockCompositeMaskLayer4 : 16; 2241 }; 2242 2243 uint32_t Value; 2244 } DW09; 2245 2246 // DWORD 10 - GRF R8.2 2247 union 2248 { 2249 // Composite 2250 struct 2251 { 2252 uint32_t HorizontalBlockCompositeMaskLayer5 : 16; 2253 uint32_t VerticalBlockCompositeMaskLayer5 : 16; 2254 }; 2255 2256 uint32_t Value; 2257 } DW10; 2258 2259 // DWORD 11 - GRF R8.3 2260 union 2261 { 2262 // Composite 2263 struct 2264 { 2265 uint32_t HorizontalBlockCompositeMaskLayer6 : 16; 2266 uint32_t VerticalBlockCompositeMaskLayer6 : 16; 2267 }; 2268 2269 uint32_t Value; 2270 } DW11; 2271 2272 // DWORD 12 - GRF R8.4 2273 union 2274 { 2275 // Composite 2276 struct 2277 { 2278 uint32_t HorizontalBlockCompositeMaskLayer7 : 16; 2279 uint32_t VerticalBlockCompositeMaskLayer7 : 16; 2280 }; 2281 2282 uint32_t Value; 2283 } DW12; 2284 2285 // DWORD 13 - GRF R8.5 2286 union 2287 { 2288 struct 2289 { 2290 uint32_t Reserved; 2291 }; 2292 2293 uint32_t Value; 2294 } DW13; 2295 2296 // DWORD 14 - GRF R8.6 2297 union 2298 { 2299 struct 2300 { 2301 uint32_t Reserved; 2302 }; 2303 2304 uint32_t Value; 2305 } DW14; 2306 2307 // DWORD 15 - GRF R8.7 2308 union 2309 { 2310 struct 2311 { 2312 uint32_t Reserved; 2313 }; 2314 2315 uint32_t Value; 2316 } DW15; 2317 }; 2318 2319 extern const MEDIA_OBJECT_KA2_INLINE_DATA g_cInit_MEDIA_OBJECT_KA2_INLINE_DATA; 2320 2321 //! 2322 //! \brief Vebox mode of operation 2323 //! 2324 typedef enum _VEBOX_EXECUTION_MODE 2325 { 2326 VEBOX_EXEC_MODE_0 = 0, //!< Non-parallel serial legacy mode. Vphal_VeboxRender() processes current frame. 2327 VEBOX_EXEC_MODE_0_TO_2 = 1, //!< Future frame detected so transition from serial to parallel mode. Vphal_VeboxRender() processes current and future frame. 2328 VEBOX_EXEC_MODE_2 = 2, //!< Parallel execution. Vphal_VeboxRender() processes future frame. 2329 VEBOX_EXEC_MODE_2_TO_0 = 3 //!< No future frame so switch back to non-parallel serial legacy mode. 2330 } VEBOX_EXECUTION_MODE; 2331 2332 #define MAX_VEBOX_EXECUTION_MODE 4 2333 //! 2334 //! \brief Controls Vebox execution mode 2335 //! 2336 typedef struct _VPHAL_VEBOX_EXEC_STATE 2337 { 2338 bool bEnable = false; //!< false, legacy serial execution. true, capable of parallel vebox/render execution 2339 VEBOX_EXECUTION_MODE Mode = VEBOX_EXEC_MODE_0; //!< Current mode of operation. 2340 bool bDIOutputPair01 = false; //!< Used to alternate between ADI output pairs. 2341 bool bSpeculativeCopy = false; //!< true, update VEBOX state for frame N+1 using frame N state 2342 bool bFrcActive = false; //!< When FRC is active, stay in VEBOX_EXEC_MODE_0 2343 bool bPostponedFMDCalc = false; //!< When in mode2, need to calc fmd variance after composition 2344 uint32_t ModeCount[MAX_VEBOX_EXECUTION_MODE] = {0}; 2345 } VPHAL_VEBOX_EXEC_STATE, *PVPHAL_VEBOX_EXEC_STATE; 2346 2347 #define RESET_VEBOX_SPECULATIVE_COPY(_a) (_a->bSpeculativeCopy = false) 2348 2349 //! 2350 //! \brief Should only request in Mode2 or Mode0->Mode2 2351 //! 2352 #define REQUEST_VEBOX_SPECULATIVE_COPY(_a) (_a->bSpeculativeCopy = true) 2353 #define IS_VEBOX_SPECULATIVE_COPY_REQUESTED(_a) (_a->bSpeculativeCopy == true) 2354 #define SET_VEBOX_EXECUTION_MODE(_a, _Mode) \ 2355 { \ 2356 (_a->Mode = _Mode); \ 2357 VPHAL_RENDER_NORMALMESSAGE("VEBOX_EXECUTION_MODE %d", _Mode); \ 2358 } 2359 #define IS_VEBOX_EXECUTION_MODE_PARALLEL_CAPABLE(_a) (_a->bEnable == true) 2360 #define IS_VEBOX_EXECUTION_MODE_0(_a) (_a->Mode == VEBOX_EXEC_MODE_0) 2361 #define IS_VEBOX_EXECUTION_MODE_0_TO_2(_a) (_a->Mode == VEBOX_EXEC_MODE_0_TO_2) 2362 #define IS_VEBOX_EXECUTION_MODE_2(_a) (_a->Mode == VEBOX_EXEC_MODE_2) 2363 #define IS_VEBOX_EXECUTION_MODE_2_TO_0(_a) (_a->Mode == VEBOX_EXEC_MODE_2_TO_0) 2364 #define VEBOX_EXECUTION_OVERRIDE_ENABLE 1 2365 #define VEBOX_EXECUTION_OVERRIDE_DISABLE 2 2366 #define RESET_VEBOX_POSTPONED_FMD_CALC(_a) (_a->bPostponedFMDCalc = false) 2367 2368 //! 2369 //! \brief Should only request in Mode2 or Mode0->Mode2 2370 //! 2371 #define REQUEST_VEBOX_POSTPONED_FMD_CALC(_a) (_a->bPostponedFMDCalc = true) 2372 #define IS_VEBOX_POSTPONED_FMD_CALC_REQUESTED(_a) (_a->bPostponedFMDCalc == true) 2373 2374 //------------------------------------------------------------------------------ 2375 // GLOBAL DEFINITIONS 2376 //------------------------------------------------------------------------------ 2377 2378 #define VPHAL_SAMPLER_BIAS_GEN575 0.015625f 2379 #define VPHAL_HW_LINEAR_SHIFT 0.5f 2380 #define FIRST_FRAME -1024 2381 2382 //! 2383 //! \brief The size of the General Register File(GRF) 2384 //! 2385 #define GRF_SIZE (8 * sizeof(uint32_t)) 2386 2387 //------------------------------------------------------------------------------ 2388 // COMPOSITING DEFINITIONS 2389 //------------------------------------------------------------------------------ 2390 #define VPHAL_COMP_MAX_LAYERS 8 2391 #define CM_MAX_KERNELS_PER_TASK 16 2392 2393 #define VPHAL_BB_ALIGN_SIZE 32768 2394 2395 //! 2396 //! \brief SLM: sharedlocalmemory. DC: data cache. 2397 //! I/S: instruction/state cache 2398 //! C: constant cache. T: texture cache 2399 //! Default for GT1/GT2 2400 //! SLM URB DC RO I/S C T 2401 //! { 0, 256, 0, 256, 0, 0, 0, } 2402 //! Default TLB settings value provided by perf team 2403 //! 2404 #define VPHAL_L3_CACHE_CONFIG_SQCREG1_VALUE_G75 0x00610000 2405 #define VPHAL_L3_CACHE_CONFIG_CNTLREG2_VALUE_G75 0x00880040 2406 #define VPHAL_L3_CACHE_CONFIG_CNTLREG3_VALUE_G75 0x00000000 2407 #define VPHAL_L3_CACHE_CONFIG_L3LRA1REG_VALUE_G75 0x27FD007F 2408 2409 //! 2410 //! \brief Initialize MHW Kernel Param struct for loading Kernel 2411 //! 2412 #define INIT_MHW_KERNEL_PARAM(MhwKernelParam, _pKernelEntry) \ 2413 do \ 2414 { \ 2415 MOS_ZeroMemory(&(MhwKernelParam), sizeof(MhwKernelParam)); \ 2416 (MhwKernelParam).pBinary = (_pKernelEntry)->pBinary; \ 2417 (MhwKernelParam).iSize = (_pKernelEntry)->iSize; \ 2418 (MhwKernelParam).iKUID = (_pKernelEntry)->iKUID; \ 2419 (MhwKernelParam).iKCID = (_pKernelEntry)->iKCID; \ 2420 } while(0) 2421 2422 //! 2423 //! \brief Enum of the phase of Image Stabilization 2424 //! 2425 typedef enum _VPHAL_ISTAB_PHASE 2426 { 2427 ISTAB_PH_NONE = -1, 2428 ISTAB_PH1_DS , //!< Down Scaling 2429 ISTAB_PH2_ME , //!< Motion Estimation 2430 ISTAB_PH3_GMC , //!< Global Motion Compensation 2431 ISTAB_PH4_FW , //!< Frame Warping 2432 ISTAB_PH_MAX 2433 } VPHAL_ISTAB_PHASE; 2434 2435 typedef struct _VPHAL_BATCH_BUFFER *PVPHAL_BATCH_BUFFER; 2436 2437 //! 2438 //! \brief Compositing BB arguments 2439 //! 2440 typedef struct _VPHAL_BB_COMP_ARGS 2441 { 2442 int32_t iMediaID; //!< Media ID used to generate CBs 2443 float fStepX; //!< X step (first layer) 2444 int32_t iLayers; //!< Valid layers 2445 RECT rcOutput; //!< Block aligned output area 2446 RECT rcDst[VPHAL_COMP_MAX_LAYERS]; //!< Dest rectangles for each layer 2447 bool bSkipBlocks; //!< Render all blocks 2448 bool bEnableNLAS; //!< NLAS enable 2449 VPHAL_ROTATION Rotation[VPHAL_COMP_MAX_LAYERS]; //!< Rotation parameter 2450 VPHAL_NLAS_PARAMS NLASParams; //!< NLAS parameters 2451 } VPHAL_BB_COMP_ARGS, *PVPHAL_BB_COMP_ARGS; 2452 2453 //! 2454 //! \brief Generic BB Args 2455 //! 2456 typedef struct 2457 { 2458 int32_t iMediaID; //!< Media ID 2459 uint32_t uiKuid; //!< Unique Kernel ID 2460 uint32_t uiParamId; //!< Unique ID for the param (for handling changes) 2461 } VPHAL_BB_GENERIC_ARGS, *PVPHAL_BB_GENERIC_ARGS; 2462 2463 //! 2464 //! \brief Advanced Processing Definitions 2465 //! 2466 typedef struct _VPHAL_ADVPROC_BB_ARGS 2467 { 2468 int32_t iMediaID; //!< Media ID used to generate CBs 2469 RECT rcDst; //!< layer target 2470 int32_t BlockWd; //!< Media Obj Block Width 2471 int32_t BlockHt; //!< Media Obj Block Height 2472 } VPHAL_ADVPROC_BB_ARGS, *PVPHAL_ADVPROC_BB_ARGS; 2473 2474 //! 2475 //! \brief Image Stabilization BB Args 2476 //! 2477 typedef struct _VPHAL_ISTAB_BB_ARGS 2478 { 2479 VPHAL_ISTAB_PHASE IStabPhase; 2480 uint32_t dwWidth; 2481 uint32_t dwHeight; 2482 } VPHAL_ISTAB_BB_ARGS, *PVPHAL_ISTAB_BB_ARGS; 2483 2484 //! 2485 //! \brief Batch buffer kind 2486 //! 2487 typedef enum _VPHAL_BB_TYPE 2488 { 2489 VPHAL_BB_TYPE_COMPOSITING, 2490 VPHAL_BB_TYPE_ADVANCED, 2491 VPHAL_BB_TYPE_GENERIC, 2492 VPHAL_BB_TYPE_PRIVATE 2493 } VPHAL_BB_TYPE; 2494 2495 //! 2496 //! \brief CM BB Args 2497 //! 2498 typedef struct _VPHAL_BB_CM_ARGS 2499 { 2500 uint64_t uiKernelIds[CM_MAX_KERNELS_PER_TASK]; 2501 uint64_t uiRefCount; 2502 bool bLatest; 2503 } VPHAL_BB_CM_ARGS, *PVPHAL_BB_CM_ARGS; 2504 2505 //! 2506 //! \brief Global BB parameters 2507 //! 2508 typedef struct _VPHAL_BATCH_BUFFER_PARAMS 2509 { 2510 bool bMatch; //!< Indicates match 2511 int32_t iCallID; //!< CallID last used 2512 VPHAL_BB_TYPE iType; //!< Indicates the render type 2513 int32_t iSize; //!< Size of the current render args 2514 union //!< Union of renders' args 2515 { 2516 VPHAL_BB_COMP_ARGS CompositeBB; 2517 VPHAL_ADVPROC_BB_ARGS AdvProcBB; 2518 VPHAL_BB_GENERIC_ARGS BbGenericArgs; 2519 VPHAL_BB_CM_ARGS BbCmArgs; 2520 } BbArgs; 2521 } VPHAL_BATCH_BUFFER_PARAMS, *PVPHAL_BATCH_BUFFER_PARAMS; 2522 2523 typedef struct _VPHAL_BATCH_BUFFER 2524 { 2525 MOS_RESOURCE OsResource; // OS Buffer 2526 int32_t iSize; // Batch buffer size 2527 int32_t iCurrent; // Current offset in CB 2528 bool bLocked; // True if locked in memory (pData must be valid) 2529 uint8_t* pData; // Pointer to BB data 2530 2531 // Batch Buffer synchronization logic 2532 bool bBusy; // Busy flag (clear when Sync Tag is reached) 2533 uint32_t dwSyncTag; // BB sync tag 2534 PVPHAL_BATCH_BUFFER pNext; // Next BB in the sync list 2535 PVPHAL_BATCH_BUFFER pPrev; // Prev BB in the sync list 2536 2537 // Rendering data associated with BB 2538 PVPHAL_BATCH_BUFFER_PARAMS pBBRenderData; // Batch Buffer rendering data 2539 } VPHAL_BATCH_BUFFER; 2540 2541 //! 2542 //! \brief Unified Batch Buffer Table 2543 //! 2544 typedef struct _VPHAL_BATCH_BUFFER_TABLE 2545 { 2546 int32_t* piBatchBufferCount; //!< Pointer to the count of allocated BBs in render's BB array 2547 int32_t iBbCountMax; //!< Maximum count of BB that can be allocated of the render 2548 PMHW_BATCH_BUFFER pBatchBufferHeader; //!< Pointer to the BB entry of the render 2549 PVPHAL_BATCH_BUFFER_PARAMS pBbParamsHeader; //!< Pointer to the BB params entry of the render 2550 } VPHAL_BATCH_BUFFER_TABLE, *PVPHAL_BATCH_BUFFER_TABLE; 2551 2552 //! 2553 //! \brief Performance data value 2554 //! 2555 typedef struct 2556 { 2557 uint32_t uiVal; 2558 bool bEnabled; 2559 }VPHAL_RNDR_PERF_DATA_VAL; 2560 2561 //! 2562 //! \brief Performance data collection 2563 //! 2564 typedef struct 2565 { 2566 VPHAL_RNDR_PERF_DATA_VAL CompMaxThreads; 2567 VPHAL_RNDR_PERF_DATA_VAL DndiMaxThreads; 2568 VPHAL_RNDR_PERF_DATA_VAL VdiFrameShareEnable; 2569 VPHAL_RNDR_PERF_DATA_VAL VdiStride; 2570 VPHAL_RNDR_PERF_DATA_VAL VdiColumnWidth; 2571 VPHAL_RNDR_PERF_DATA_VAL L3SQCReg1Override; 2572 VPHAL_RNDR_PERF_DATA_VAL L3CntlReg2Override; 2573 VPHAL_RNDR_PERF_DATA_VAL L3CntlReg3Override; 2574 VPHAL_RNDR_PERF_DATA_VAL L3LRA1RegOverride; 2575 VPHAL_RNDR_PERF_DATA_VAL L3SQCReg4Override; 2576 VPHAL_RNDR_PERF_DATA_VAL L3CntlRegOverride; 2577 } VPHAL_RNDR_PERF_DATA, *PVPHAL_RNDR_PERF_DATA; 2578 2579 //! 2580 //! \brief Get the aligned the surface height and width unit 2581 //! \details Accoring to the format of the surface, get the aligned unit for the surface 2582 //! width and height 2583 //! \param [in,out] pwWidthAlignUnit 2584 //! Pointer to the surface width alignment unit 2585 //! \param [in,out] pwHeightAlignUnit 2586 //! Pointer to the surface height alignment unit 2587 //! \param [in] format 2588 //! The format of the surface 2589 //! \return void 2590 //! 2591 void VpHal_RndrGetAlignUnit( 2592 uint16_t* pwWidthAlignUnit, 2593 uint16_t* pwHeightAlignUnit, 2594 MOS_FORMAT format); 2595 2596 //! 2597 //! \brief Set packed YUV component offsets 2598 //! \details Accoring to the format of the surface, set packed YUV component offsets 2599 //! \param [in] format 2600 //! The format of the surface 2601 //! \param [in,out] pOffsetY 2602 //! The offset of Y 2603 //! \param [in,out] pOffsetU 2604 //! The offset of U 2605 //! \param [in,out] pOffsetV 2606 //! The offset of V 2607 //! \return MOS_STATUS 2608 //! Return MOS_STATUS_SUCCESS if successful, otherwise failed 2609 //! 2610 MOS_STATUS VpHal_RndrSetYUVComponents( 2611 MOS_FORMAT format, 2612 uint8_t* pOffsetY, 2613 uint8_t* pOffsetU, 2614 uint8_t* pOffsetV); 2615 2616 //! 2617 //! \brief Set the numbers of Slice, Sub-slice, EUs for power mode 2618 //! \details Set the numbers of Slice, Sub-slice, EUs recommended for 2619 //! the given kernel type for power mode 2620 //! \param [in] pRenderHal 2621 //! Pointer to RenderHal Interface Structure 2622 //! \param [in] KernelID 2623 //! VP render Kernel ID 2624 //! \return MOS_STATUS 2625 //! MOS_STATUS_SUCCESS if success. Error code otherwise 2626 //! 2627 MOS_STATUS VpHal_RndrCommonSetPowerMode( 2628 PRENDERHAL_INTERFACE pRenderHal, 2629 VpKernelID KernelID); 2630 2631 //! 2632 //! \brief Initialized RenderHal Surface according to incoming VPHAL Surface 2633 //! \param [in] pVpSurface 2634 //! Pointer to the VPHAL surface 2635 //! \param [out] pRenderHalSurface 2636 //! Pointer to the RenderHal surface 2637 //! \return MOS_STATUS 2638 //! 2639 MOS_STATUS VpHal_RndrCommonInitRenderHalSurface( 2640 PVPHAL_SURFACE pVpSurface, 2641 PRENDERHAL_SURFACE pRenderHalSurface); 2642 2643 //! 2644 //! \brief Get output RenderHal Surface parameters back to VPHAL Surface 2645 //! \param [in] pRenderHalSurface 2646 //! Pointer to the RenderHal surface 2647 //! \param [in,out] pVpSurface 2648 //! Pointer to the VPHAL surface 2649 //! \return MOS_STATUS 2650 //! 2651 MOS_STATUS VpHal_RndrCommonGetBackVpSurfaceParams( 2652 PRENDERHAL_SURFACE pRenderHalSurface, 2653 PVPHAL_SURFACE pVpSurface); 2654 2655 //! 2656 //! \brief Set Surface for HW Access 2657 //! \details Common Function for setting up surface state, if render would 2658 //! use CP HM, need use VpHal_CommonSetSurfaceForHwAccess instead 2659 //! \param [in] pRenderHal 2660 //! Pointer to RenderHal Interface Structure 2661 //! \param [in] pSurface 2662 //! Pointer to Surface 2663 //! \param [in] pSurfaceParams 2664 //! Pointer to RenderHal Surface Params 2665 //! \param [in] iBindingTable 2666 //! Binding Table to bind surface 2667 //! \param [in] iBTEntry 2668 //! Binding Table Entry index 2669 //! \param [in] bWrite 2670 //! Write mode flag 2671 //! \return MOS_STATUS 2672 //! MOS_STATUS_SUCCESS if success. Error code otherwise 2673 //! 2674 MOS_STATUS VpHal_RndrCommonSetSurfaceForHwAccess( 2675 PRENDERHAL_INTERFACE pRenderHal, 2676 PVPHAL_SURFACE pSurface, 2677 PRENDERHAL_SURFACE_STATE_PARAMS pSurfaceParams, 2678 int32_t iBindingTable, 2679 int32_t iBTEntry, 2680 bool bWrite); 2681 2682 //! 2683 //! \brief Set Buffer Surface for HW Access 2684 //! \details Common Function for setting up buffer surface state, if render would 2685 //! use CP HM, need use VpHal_CommonSetBufferSurfaceForHwAccess instead 2686 //! \param [in] pRenderHal 2687 //! Pointer to RenderHal Interface Structure 2688 //! \param [in] pSurface 2689 //! Pointer to Surface 2690 //! \param [in,out] pSurfaceParams 2691 //! Pointer to RenderHal Surface Params 2692 //! \param [in] iBindingTable 2693 //! Binding Table to Bind Surface 2694 //! \param [in] iBTEntry 2695 //! Binding Table Entry index 2696 //! \param [in] bWrite 2697 //! Write mode flag 2698 //! \return MOS_STATUS 2699 //! MOS_STATUS_SUCCESS if success. Error code otherwise 2700 //! 2701 MOS_STATUS VpHal_RndrCommonSetBufferSurfaceForHwAccess( 2702 PRENDERHAL_INTERFACE pRenderHal, 2703 PVPHAL_SURFACE pSurface, 2704 PRENDERHAL_SURFACE_STATE_PARAMS pSurfaceParams, 2705 int32_t iBindingTable, 2706 int32_t iBTEntry, 2707 bool bWrite); 2708 2709 //! 2710 //! \brief Set Surface for HW Access for CP HM 2711 //! \details Common Function for setting up surface state, need to use this function 2712 //! if render would use CP HM 2713 //! \param [in] pRenderHal 2714 //! Pointer to RenderHal Interface Structure 2715 //! \param [in] pSurface 2716 //! Pointer to Surface 2717 //! \param [in] pRenderSurface 2718 //! Pointer to Render Surface 2719 //! \param [in] pSurfaceParams 2720 //! Pointer to RenderHal Surface Params 2721 //! \param [in] iBindingTable 2722 //! Binding Table to bind surface 2723 //! \param [in] iBTEntry 2724 //! Binding Table Entry index 2725 //! \param [in] bWrite 2726 //! Write mode flag 2727 //! \return MOS_STATUS 2728 //! MOS_STATUS_SUCCESS if success. Error code otherwise 2729 //! 2730 MOS_STATUS VpHal_CommonSetSurfaceForHwAccess( 2731 PRENDERHAL_INTERFACE pRenderHal, 2732 PVPHAL_SURFACE pSurface, 2733 PRENDERHAL_SURFACE pRenderSurface, 2734 PRENDERHAL_SURFACE_STATE_PARAMS pSurfaceParams, 2735 int32_t iBindingTable, 2736 int32_t iBTEntry, 2737 bool bWrite); 2738 2739 //! 2740 //! \brief Set Buffer Surface for HW Access for CP HM 2741 //! \details Common Function for setting up buffer surface state, need to use this function 2742 //! if render would use CP HM 2743 //! \param [in] pRenderHal 2744 //! Pointer to RenderHal Interface Structure 2745 //! \param [in] pSurface 2746 //! Pointer to Surface 2747 //! \param [in] pRenderSurface 2748 //! Pointer to Render Surface 2749 //! \param [in,out] pSurfaceParams 2750 //! Pointer to RenderHal Surface Params 2751 //! \param [in] iBindingTable 2752 //! Binding Table to Bind Surface 2753 //! \param [in] iBTEntry 2754 //! Binding Table Entry index 2755 //! \param [in] bWrite 2756 //! Write mode flag 2757 //! \return MOS_STATUS 2758 //! MOS_STATUS_SUCCESS if success. Error code otherwise 2759 //! 2760 MOS_STATUS VpHal_CommonSetBufferSurfaceForHwAccess( 2761 PRENDERHAL_INTERFACE pRenderHal, 2762 PVPHAL_SURFACE pSurface, 2763 PRENDERHAL_SURFACE pRenderSurface, 2764 PRENDERHAL_SURFACE_STATE_PARAMS pSurfaceParams, 2765 int32_t iBindingTable, 2766 int32_t iBTEntry, 2767 bool bWrite); 2768 2769 //! 2770 //! \brief Submit commands for rendering 2771 //! \param [in] pRenderHal 2772 //! Pointer to RenderHal Interface Structure 2773 //! \param [in] pBatchBuffer 2774 //! Pointer to batch buffer 2775 //! \param [in] bNullRendering 2776 //! Indicate whether is Null rendering 2777 //! \param [in] pWalkerParams 2778 //! Pointer to walker parameters 2779 //! \param [in] pGpGpuWalkerParams 2780 //! Pointer to GPGPU walker parameters 2781 //! \param [in] KernelID 2782 //! VP Kernel ID 2783 //! \param [in] bLastSubmission 2784 //! whether it is the last submission 2785 //! \return MOS_STATUS 2786 //! 2787 MOS_STATUS VpHal_RndrCommonSubmitCommands( 2788 PRENDERHAL_INTERFACE pRenderHal, 2789 PMHW_BATCH_BUFFER pBatchBuffer, 2790 bool bNullRendering, 2791 PMHW_WALKER_PARAMS pWalkerParams, 2792 PMHW_GPGPU_WALKER_PARAMS pGpGpuWalkerParams, 2793 VpKernelID KernelID, 2794 bool bLastSubmission); 2795 2796 //! 2797 //! \brief Submit commands for rendering 2798 //! \details Submit commands for rendering with status table update enabling 2799 //! \param [in] pRenderHal 2800 //! Pointer to RenderHal Interface Structure 2801 //! \param [in] pBatchBuffer 2802 //! Pointer to batch buffer 2803 //! \param [in] bNullRendering 2804 //! Indicate whether is Null rendering 2805 //! \param [in] pWalkerParams 2806 //! Pointer to walker parameters 2807 //! \param [in] pGpGpuWalkerParams 2808 //! Pointer to GPGPU walker parameters 2809 //! \param [in] pStatusTableUpdateParams 2810 //! Pointer to pStatusTableUpdateParams 2811 //! \param [in] KernelID 2812 //! VP Kernel ID 2813 //! \param [in] FcKernelCount 2814 //! VP FC Kernel Count 2815 //! \param [in] FcKernelList 2816 //! VP FC Kernel List 2817 //! \param [in] bLastSubmission 2818 //! whether it is the last submission 2819 //! \return MOS_STATUS 2820 //! 2821 MOS_STATUS VpHal_RndrSubmitCommands( 2822 PRENDERHAL_INTERFACE pRenderHal, 2823 PMHW_BATCH_BUFFER pBatchBuffer, 2824 bool bNullRendering, 2825 PMHW_WALKER_PARAMS pWalkerParams, 2826 PMHW_GPGPU_WALKER_PARAMS pGpGpuWalkerParams, 2827 PSTATUS_TABLE_UPDATE_PARAMS pStatusTableUpdateParams, 2828 VpKernelID KernelID, 2829 int FcKernelCount, 2830 int *FcKernelList, 2831 bool bLastSubmission); 2832 2833 //! 2834 //! \brief Is Alignment WA needed 2835 //! \details Decide WA is needed for VEBOX/Render engine 2836 //! RENDER limitation with composition BOB: 2837 //! Height should be a multiple of 4, otherwise disable DI in Comp 2838 //! VEBOX limitation with TiledY NV12 input(Gen75): 2839 //! Height should be a multiple of 4, otherwise bypass adv render 2840 //! VEBOX limitation with TiledY NV12 input(Gen8/9): 2841 //! 3D/GMM regresses to allocate linear surface when height is not 2842 //! a multiple of 4, no need to bypass adv render 2843 //! \param [in] pSurface 2844 //! Input surface 2845 //! \param [in] GpuContext 2846 //! GpuContext to indicate Render/Vebox 2847 //! \return bool 2848 //! true - Solution is needed; false - Solution is not needed 2849 //! 2850 bool VpHal_RndrCommonIsAlignmentWANeeded( 2851 PVPHAL_SURFACE pSurface, 2852 MOS_GPU_CONTEXT GpuContext); 2853 2854 //! 2855 //! \brief Set params for AVS table 2856 //! \details Set 4-tap or 8-tap filtering AVS table 2857 //! \param [in] pAvsParams 2858 //! Pointer to avs parameter 2859 //! \param [in,out] pMhwSamplerAvsTableParam 2860 //! Pointer to avs table parameter 2861 //! \return MOS_STATUS 2862 //! 2863 MOS_STATUS VpHal_RenderCommonSetAVSTableParam( 2864 PMHW_AVS_PARAMS pAvsParams, 2865 PMHW_SAMPLER_AVS_TABLE_PARAM pMhwSamplerAvsTableParam); 2866 2867 //! 2868 //! \brief Initialize AVS parameters shared by Renderers 2869 //! \details Initialize the members of the AVS parameter and allocate memory for its coefficient tables 2870 //! \param [in,out] pAVS_Params 2871 //! Pointer to MHW AVS parameter 2872 //! \param [in] uiYCoeffTableSize 2873 //! Size of the Y coefficient table 2874 //! \param [in] uiUVCoeffTableSize 2875 //! Size of the UV coefficient table 2876 //! \return MOS_STATUS 2877 //! Return MOS_STATUS_SUCCESS if successful, otherwise failed 2878 //! 2879 MOS_STATUS VpHal_RndrCommonInitAVSParams( 2880 PMHW_AVS_PARAMS pAVS_Params, 2881 uint32_t uiYCoeffTableSize, 2882 uint32_t uiUVCoeffTableSize); 2883 2884 //! 2885 //! \brief Destroy AVS parameters shared by Renderers 2886 //! \details Free the memory of AVS parameter's coefficient tables 2887 //! \param [in,out] pAVS_Params 2888 //! Pointer to VPHAL AVS parameter 2889 //! \return void 2890 //! 2891 void VpHal_RndrCommonDestroyAVSParams( 2892 PMHW_AVS_PARAMS pAVS_Params); 2893 2894 //! 2895 //! \brief update status report rely on command buffer sync tag 2896 //! \param [in] pOsInterface 2897 //! pointer to os interface 2898 //! \param [in,out] pStatusTableUpdateParams 2899 //! pointer to STATUS_TABLE_UPDATE_PARAMS for updating status table 2900 //! \param [in] eMosGpuContext 2901 //! current mos contexnt enum 2902 //! \param [in] eLastStatus 2903 //! indicating last submition is successful or not 2904 //! \return MOS_STATUS 2905 //! Return MOS_STATUS_SUCCESS if successful, otherwise failed 2906 //! 2907 MOS_STATUS VpHal_RndrUpdateStatusTableAfterSubmit( 2908 PMOS_INTERFACE pOsInterface, 2909 PSTATUS_TABLE_UPDATE_PARAMS pStatusTableUpdateParams, 2910 MOS_GPU_CONTEXT eMosGpuContext, 2911 MOS_STATUS eLastStatus 2912 ); 2913 2914 //! 2915 //! \brief Determine if the Batch Buffer End is needed to add in the end 2916 //! \details Detect platform OS and return the flag whether the Batch Buffer End is needed to add in the end 2917 //! \param [in] pOsInterface 2918 //! Pointer to MOS_INTERFACE 2919 //! \return bool 2920 //! The flag of adding Batch Buffer End 2921 //! 2922 bool VpHal_RndrCommonIsMiBBEndNeeded( 2923 PMOS_INTERFACE pOsInterface); 2924 2925 struct AvsCoeffsCacheTag 2926 { 2927 bool operator==(const AvsCoeffsCacheTag &rhs) const 2928 { 2929 return (this->m_format == rhs.m_format && 2930 this->m_8TapAdaptiveEnable == rhs.m_8TapAdaptiveEnable && 2931 this->m_balancedFilter == rhs.m_balancedFilter && 2932 this->m_forcePolyPhaseCoefs == rhs.m_forcePolyPhaseCoefs && 2933 this->m_chromaSiting == rhs.m_chromaSiting && 2934 fabsf(this->m_scaleX - rhs.m_scaleX) < 1e-6 && 2935 fabsf(this->m_scaleY - rhs.m_scaleY) < 1e-6); 2936 } 2937 2938 MOS_FORMAT m_format; 2939 bool m_8TapAdaptiveEnable; 2940 bool m_balancedFilter; 2941 bool m_forcePolyPhaseCoefs; 2942 uint32_t m_chromaSiting; 2943 float m_scaleX; 2944 float m_scaleY; 2945 }; 2946 2947 struct AvsCoeffsCacheEntry 2948 { 2949 AvsCoeffsCacheTag m_tag; 2950 MHW_AVS_PARAMS m_AvsParams; 2951 bool m_valid; 2952 }; 2953 2954 template <int N> 2955 class AvsCoeffsCache 2956 { 2957 public: AvsCoeffsCache()2958 AvsCoeffsCache(): 2959 m_evictIndex(0), 2960 m_YCoeffTableSize(0), 2961 m_UVCoeffTableSize(0) 2962 { 2963 MOS_ZeroMemory(m_entries, sizeof(m_entries)); 2964 } 2965 ~AvsCoeffsCache()2966 ~AvsCoeffsCache() 2967 { 2968 for (int i = 0; i < N; ++i) 2969 { 2970 VpHal_RndrCommonDestroyAVSParams(&m_entries[i].m_AvsParams); 2971 } 2972 } 2973 Init(int YCoeffTableSize,int UVCoeffTableSize)2974 void Init(int YCoeffTableSize, int UVCoeffTableSize) 2975 { 2976 m_YCoeffTableSize = YCoeffTableSize; 2977 m_UVCoeffTableSize = UVCoeffTableSize; 2978 2979 for (int i = 0; i < N; i++) 2980 { 2981 VpHal_RndrCommonInitAVSParams(&m_entries[i].m_AvsParams, 2982 YCoeffTableSize, 2983 UVCoeffTableSize); 2984 } 2985 } 2986 Find(const AvsCoeffsCacheTag & tag)2987 const MHW_AVS_PARAMS* Find(const AvsCoeffsCacheTag &tag) const 2988 { 2989 for (int i = 0; i < N; i++) 2990 { 2991 if (m_entries[i].m_valid && m_entries[i].m_tag == tag) 2992 { 2993 return &m_entries[i].m_AvsParams; 2994 } 2995 } 2996 return nullptr; 2997 } 2998 Insert(const AvsCoeffsCacheTag & tag,const MHW_AVS_PARAMS & params)2999 void Insert(const AvsCoeffsCacheTag &tag, const MHW_AVS_PARAMS ¶ms) 3000 { 3001 m_entries[m_evictIndex].m_tag = tag; 3002 Clone(params, m_entries[m_evictIndex].m_AvsParams); 3003 m_entries[m_evictIndex].m_valid = true; 3004 m_evictIndex = (m_evictIndex + 1) % N; 3005 } 3006 Clone(const MHW_AVS_PARAMS & from,MHW_AVS_PARAMS & to)3007 void Clone(const MHW_AVS_PARAMS &from, MHW_AVS_PARAMS &to) 3008 { 3009 to.Format = from.Format; 3010 to.fScaleX = from.fScaleX; 3011 to.fScaleY = from.fScaleY; 3012 to.bForcePolyPhaseCoefs = from.bForcePolyPhaseCoefs; 3013 3014 MOS_SecureMemcpy(to.piYCoefsX, m_YCoeffTableSize, from.piYCoefsX, m_YCoeffTableSize); 3015 MOS_SecureMemcpy(to.piYCoefsY, m_YCoeffTableSize, from.piYCoefsY, m_YCoeffTableSize); 3016 MOS_SecureMemcpy(to.piUVCoefsX, m_UVCoeffTableSize, from.piUVCoefsX, m_UVCoeffTableSize); 3017 MOS_SecureMemcpy(to.piUVCoefsY, m_UVCoeffTableSize, from.piUVCoefsY, m_UVCoeffTableSize); 3018 } 3019 3020 private: 3021 AvsCoeffsCacheEntry m_entries[N]; 3022 int m_evictIndex; 3023 int m_YCoeffTableSize; 3024 int m_UVCoeffTableSize; 3025 }; 3026 3027 #endif // __VPHAL_RENDER_COMMON_H__ 3028