1 /*
2 * VIDIX driver for nVidia chipsets.
3 *
4 * Copyright (C) 2003-2004 Sascha Sommer
5 * This file is based on sources from RIVATV (rivatv.sf.net)
6 * Multi buffer support and TNT2 fixes by Dmitry Baryshkov.
7 *
8 * This file is part of MPlayer.
9 *
10 * MPlayer is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * MPlayer is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with MPlayer; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23 */
24
25 #include <errno.h>
26 #include <stdio.h>
27 #include <stdlib.h>
28 #include <string.h>
29 #include <math.h>
30 #include <inttypes.h>
31 #include <unistd.h>
32
33
34 #include "config.h"
35 #include "vidix.h"
36 #include "fourcc.h"
37 #include "dha.h"
38 #include "pci_ids.h"
39 #include "pci_names.h"
40 #include "libavutil/common.h"
41 #include "mpbswap.h"
42 #include "mp_msg.h"
43
44
45 static pciinfo_t pci_info;
46
47
48 #define MAX_FRAMES 3
49 #define NV04_BES_SIZE 1024*2000*4
50
51
52 static const vidix_capability_t nvidia_cap = {
53 "NVIDIA RIVA OVERLAY DRIVER",
54 "Sascha Sommer <saschasommer@freenet.de>",
55 TYPE_OUTPUT,
56 { 0, 0, 0, 0 },
57 2046,
58 2046,
59 4,
60 4,
61 -1,
62 FLAG_UPSCALER|FLAG_DOWNSCALER,
63 VENDOR_NVIDIA2,
64 -1,
65 { 0, 0, 0, 0 }
66 };
67
68 #define NV_ARCH_03 0x03
69 #define NV_ARCH_04 0x04
70 #define NV_ARCH_10 0x10
71 #define NV_ARCH_20 0x20
72 #define NV_ARCH_30 0x30
73 #define NV_ARCH_40 0x40
74
75 // since no useful information whatsoever is passed
76 // to the equalizer functions we need this
77 static struct {
78 uint32_t lum; // luminance (brightness + contrast)
79 uint32_t chrom; // chrominance (saturation + hue)
80 uint8_t red_off; // for NV03/NV04
81 uint8_t green_off;
82 uint8_t blue_off;
83 vidix_video_eq_t vals;
84 } eq;
85
86 struct nvidia_cards {
87 unsigned short chip_id;
88 unsigned short arch;
89 };
90
91
92 static struct nvidia_cards nvidia_card_ids[] = {
93 /*NV03*/
94 {DEVICE_NVIDIA2_RIVA128, NV_ARCH_03},
95 {DEVICE_NVIDIA2_RIVA128ZX,NV_ARCH_03},
96 /*NV04*/
97 {DEVICE_NVIDIA_NV4_RIVA_TNT,NV_ARCH_04},
98 {DEVICE_NVIDIA_NV5_RIVA_TNT2_TNT2,NV_ARCH_04},
99 {DEVICE_NVIDIA_NV5_RIVA_TNT2,NV_ARCH_04},
100 {DEVICE_NVIDIA_NV5_RIVA_TNT22,NV_ARCH_04},
101 {DEVICE_NVIDIA_NV5_RIVA_TNT23,NV_ARCH_04},
102 {DEVICE_NVIDIA_NV6_VANTA_VANTA_LT,NV_ARCH_04},
103 {DEVICE_NVIDIA_NV5M64_RIVA_TNT2,NV_ARCH_04},
104 {DEVICE_NVIDIA_NV6_VANTA,NV_ARCH_04},
105 {DEVICE_NVIDIA_NV6_VANTA2,NV_ARCH_04},
106 {DEVICE_NVIDIA2_TNT,NV_ARCH_04},
107 {DEVICE_NVIDIA2_TNT2,NV_ARCH_04},
108 {DEVICE_NVIDIA2_VTNT2,NV_ARCH_04},
109 {DEVICE_NVIDIA2_UTNT2 ,NV_ARCH_04},
110 {DEVICE_NVIDIA2_ITNT2,NV_ARCH_04},
111 {DEVICE_NVIDIA_NV5_ALADDIN_TNT2,NV_ARCH_04},
112 /*NV10*/
113 {DEVICE_NVIDIA_NV18_GEFORCE_PCX,NV_ARCH_10},
114 {DEVICE_NVIDIA_NV10_GEFORCE_256,NV_ARCH_10},
115 {DEVICE_NVIDIA_NV10DDR_GEFORCE_256,NV_ARCH_10},
116 {DEVICE_NVIDIA_NV10GL_QUADRO,NV_ARCH_10},
117 {DEVICE_NVIDIA_NV11_GEFORCE2_MX_MX,NV_ARCH_10},
118 {DEVICE_NVIDIA_NV11DDR_GEFORCE2_MX,NV_ARCH_10},
119 {DEVICE_NVIDIA_NV11_GEFORCE2_GO,NV_ARCH_10},
120 {DEVICE_NVIDIA_NV11GL_QUADRO2_MXR_EX_GO,NV_ARCH_10},
121 {DEVICE_NVIDIA_NV15_GEFORCE2_GTS_PRO,NV_ARCH_10},
122 {DEVICE_NVIDIA_NV15DDR_GEFORCE2_TI,NV_ARCH_10},
123 {DEVICE_NVIDIA_NV15BR_GEFORCE2_ULTRA,NV_ARCH_10},
124 {DEVICE_NVIDIA_NV15GL_QUADRO2_PRO,NV_ARCH_10},
125 {DEVICE_NVIDIA_NV17_GEFORCE4_MX,NV_ARCH_10},
126 {DEVICE_NVIDIA_NV17_GEFORCE4_MX2,NV_ARCH_10},
127 {DEVICE_NVIDIA_NV17_GEFORCE4_MX3,NV_ARCH_10},
128 {DEVICE_NVIDIA_NV17_GEFORCE4_MX4,NV_ARCH_10},
129 {DEVICE_NVIDIA_NV17_GEFORCE4_440,NV_ARCH_10},
130 {DEVICE_NVIDIA_NV17_GEFORCE4_420,NV_ARCH_10},
131 {DEVICE_NVIDIA_NV17_GEFORCE4_4202,NV_ARCH_10},
132 {DEVICE_NVIDIA_NV17_GEFORCE4_460,NV_ARCH_10},
133 {DEVICE_NVIDIA_NV17GL_QUADRO4_550,NV_ARCH_10},
134 {DEVICE_NVIDIA_NV17_GEFORCE4_4203,NV_ARCH_10},
135 {DEVICE_NVIDIA_NV17GL_QUADRO4_200_400,NV_ARCH_10},
136 {DEVICE_NVIDIA_NV17GL_QUADRO4_5502,NV_ARCH_10},
137 {DEVICE_NVIDIA_NV17GL_QUADRO4_550,NV_ARCH_10},
138 {DEVICE_NVIDIA_NV17_GEFORCE4_410,NV_ARCH_10},
139 {DEVICE_NVIDIA_NV18_GEFORCE4_MX,NV_ARCH_10},
140 {DEVICE_NVIDIA_NV18_GEFORCE4_MX2,NV_ARCH_10},
141 {DEVICE_NVIDIA_NV18_GEFORCE4_MX3,NV_ARCH_10},
142 {DEVICE_NVIDIA_NV18_GEFORCE4_MX4,NV_ARCH_10},
143 {DEVICE_NVIDIA_NV18_GEFORCE4_MX5,NV_ARCH_10},
144 {DEVICE_NVIDIA_NV18M_GEFORCE4_448,NV_ARCH_10},
145 {DEVICE_NVIDIA_NV18M_GEFORCE4_488,NV_ARCH_10},
146 {DEVICE_NVIDIA_NV18GL_QUADRO_FX,NV_ARCH_10},
147 {DEVICE_NVIDIA_NV18GL_QUADRO4_580,NV_ARCH_10},
148 {DEVICE_NVIDIA_NV18GL_QUADRO4_NVS,NV_ARCH_10},
149 {DEVICE_NVIDIA_NV18GL_QUADRO4_380,NV_ARCH_10},
150 {DEVICE_NVIDIA_NV18M_GEFORCE4_4482,NV_ARCH_10},
151 {DEVICE_NVIDIA_NVCRUSH11_GEFORCE2_MX,NV_ARCH_10},
152 {DEVICE_NVIDIA_NV18_GEFORCE4_MX5,NV_ARCH_10},
153 {DEVICE_NVIDIA_NV18_GEFORCE_PCX,NV_ARCH_10},
154 /*NV20*/
155 {DEVICE_NVIDIA_NV20_GEFORCE3,NV_ARCH_20},
156 {DEVICE_NVIDIA_NV20_GEFORCE3_TI,NV_ARCH_20},
157 {DEVICE_NVIDIA_NV20_GEFORCE3_TI2,NV_ARCH_20},
158 {DEVICE_NVIDIA_NV20DCC_QUADRO_DCC,NV_ARCH_20},
159 {DEVICE_NVIDIA_NV25_GEFORCE4_TI,NV_ARCH_20},
160 {DEVICE_NVIDIA_NV25_GEFORCE4_TI2,NV_ARCH_20},
161 {DEVICE_NVIDIA_NV25_GEFORCE4_TI3,NV_ARCH_20},
162 {DEVICE_NVIDIA_NV25_GEFORCE4_TI4,NV_ARCH_20},
163 {DEVICE_NVIDIA_NV25GL_QUADRO4_900,NV_ARCH_20},
164 {DEVICE_NVIDIA_NV25GL_QUADRO4_750,NV_ARCH_20},
165 {DEVICE_NVIDIA_NV25GL_QUADRO4_700,NV_ARCH_20},
166 {DEVICE_NVIDIA_NV28_GEFORCE4_TI,NV_ARCH_20},
167 {DEVICE_NVIDIA_NV28_GEFORCE4_TI2,NV_ARCH_20},
168 {DEVICE_NVIDIA_NV28_GEFORCE4_TI3,NV_ARCH_20},
169 {DEVICE_NVIDIA_NV28_GEFORCE4_TI4,NV_ARCH_20},
170 {DEVICE_NVIDIA_NV28GL_QUADRO4_980,NV_ARCH_20},
171 {DEVICE_NVIDIA_NV28GL_QUADRO4_780,NV_ARCH_20},
172 {DEVICE_NVIDIA_NV28GLM_QUADRO4_700,NV_ARCH_20},
173 /*NV30*/
174 {DEVICE_NVIDIA_NV30_GEFORCE_FX,NV_ARCH_30},
175 {DEVICE_NVIDIA_NV30_GEFORCE_FX2,NV_ARCH_30},
176 {DEVICE_NVIDIA_NV30_GEFORCE_FX3,NV_ARCH_30},
177 {DEVICE_NVIDIA_NV30GL_QUADRO_FX,NV_ARCH_30},
178 {DEVICE_NVIDIA_NV30GL_QUADRO_FX2,NV_ARCH_30},
179 {DEVICE_NVIDIA_NV31_GEFORCE_FX,NV_ARCH_30},
180 {DEVICE_NVIDIA_NV31_GEFORCE_FX2,NV_ARCH_30},
181 {DEVICE_NVIDIA_NV31,NV_ARCH_30},
182 {DEVICE_NVIDIA_NV31_GEFORCE_FX3,NV_ARCH_30},
183 {DEVICE_NVIDIA_NV31M,NV_ARCH_30},
184 {DEVICE_NVIDIA_NV31M_PRO,NV_ARCH_30},
185 {DEVICE_NVIDIA_NV31M_GEFORCE_FX,NV_ARCH_30},
186 {DEVICE_NVIDIA_NV31M_GEFORCE_FX2,NV_ARCH_30},
187 {DEVICE_NVIDIA_NVIDIA_QUADRO_FX,NV_ARCH_30},
188 {DEVICE_NVIDIA_NV31GLM,NV_ARCH_30},
189 {DEVICE_NVIDIA_NV31GLM_PRO,NV_ARCH_30},
190 {DEVICE_NVIDIA_NV31GLM_PRO2,NV_ARCH_30},
191 {DEVICE_NVIDIA_NV34_GEFORCE_FX,NV_ARCH_30},
192 {DEVICE_NVIDIA_NV34_GEFORCE_FX2,NV_ARCH_30},
193 {DEVICE_NVIDIA_NV34_GEFORCE_FX3,NV_ARCH_30},
194 {DEVICE_NVIDIA_NV34_GEFORCE_FX4,NV_ARCH_30},
195 {DEVICE_NVIDIA_NV34M_GEFORCE_FX,NV_ARCH_30},
196 {DEVICE_NVIDIA_NV34M_GEFORCE_FX2,NV_ARCH_30},
197 {DEVICE_NVIDIA_NV34_GEFORCE_FX5,NV_ARCH_30},
198 {DEVICE_NVIDIA_NV34_GEFORCE_FX6,NV_ARCH_30},
199 {DEVICE_NVIDIA_NV34M_GEFORCE_FX3,NV_ARCH_30},
200 {DEVICE_NVIDIA_NV34M_GEFORCE_FX4,NV_ARCH_30},
201 {DEVICE_NVIDIA_NV34GL_QUADRO_NVS,NV_ARCH_30},
202 {DEVICE_NVIDIA_NV34GL_QUADRO_FX,NV_ARCH_30},
203 {DEVICE_NVIDIA_NV34GLM_GEFORCE_FX,NV_ARCH_30},
204 {DEVICE_NVIDIA_NV34_GEFORCE_FX7,NV_ARCH_30},
205 {DEVICE_NVIDIA_NV34GL,NV_ARCH_30},
206 {DEVICE_NVIDIA_NV35_GEFORCE_FX,NV_ARCH_30},
207 {DEVICE_NVIDIA_NV35_GEFORCE_FX2,NV_ARCH_30},
208 {DEVICE_NVIDIA_NV35_GEFORCE_FX3,NV_ARCH_30},
209 {DEVICE_NVIDIA_NV38_GEFORCE_FX,NV_ARCH_30},
210 {DEVICE_NVIDIA_NV35_GEFORCE_FX4,NV_ARCH_30},
211 {DEVICE_NVIDIA_NV35GL_QUADRO_FX,NV_ARCH_30},
212 {DEVICE_NVIDIA_NV35GL_QUADRO_FX2,NV_ARCH_30},
213 {DEVICE_NVIDIA_NV35_GEFORCE_PCX,NV_ARCH_30},
214 {DEVICE_NVIDIA_NV36_1_GEFORCE_FX,NV_ARCH_30},
215 {DEVICE_NVIDIA_NV36_2_GEFORCE_FX,NV_ARCH_30},
216 {DEVICE_NVIDIA_NV36_GEFORCE_FX,NV_ARCH_30},
217 {DEVICE_NVIDIA_NV36_4_GEFORCE_FX,NV_ARCH_30},
218 {DEVICE_NVIDIA_NV36_5,NV_ARCH_30},
219 {DEVICE_NVIDIA_NV36_GEFORCE_FX2,NV_ARCH_30},
220 {DEVICE_NVIDIA_NV36_GEFORCE_FX3,NV_ARCH_30},
221 {DEVICE_NVIDIA_NV36_GEFORCE_PCX,NV_ARCH_30},
222 {DEVICE_NVIDIA_NV36M_PRO,NV_ARCH_30},
223 {DEVICE_NVIDIA_NV36MAP,NV_ARCH_30},
224 {DEVICE_NVIDIA_NV36_QUADRO_FX,NV_ARCH_30},
225 {DEVICE_NVIDIA_NV36GL_QUADRO_FX,NV_ARCH_30},
226 {DEVICE_NVIDIA_NV36GL,NV_ARCH_30},
227 {DEVICE_NVIDIA_NV36_GEFORCE_PCX,NV_ARCH_30},
228 {DEVICE_NVIDIA_NV35_GEFORCE_PCX,NV_ARCH_30},
229 {DEVICE_NVIDIA_NV37GL_QUADRO_FX,NV_ARCH_30},
230 {DEVICE_NVIDIA_NV37GL_QUADRO_FX2,NV_ARCH_30},
231 {DEVICE_NVIDIA_NV38GL_QUADRO_FX,NV_ARCH_30},
232 /* NV40: GeForce 6x00 to 7x00 */
233 {DEVICE_NVIDIA_NV40_GEFORCE_6800,NV_ARCH_40},
234 {DEVICE_NVIDIA_NV40_GEFORCE_68002,NV_ARCH_40},
235 {DEVICE_NVIDIA_NV40_2_GEFORCE_6800,NV_ARCH_40},
236 {DEVICE_NVIDIA_NV40_3,NV_ARCH_40},
237 {DEVICE_NVIDIA_NV40_GEFORCE_68003,NV_ARCH_40},
238 {DEVICE_NVIDIA_NV40_GEFORCE_68004,NV_ARCH_40},
239 {DEVICE_NVIDIA_NV40_GEFORCE_68005,NV_ARCH_40},
240 {DEVICE_NVIDIA_NV40_GEFORCE_68006,NV_ARCH_40},
241 {DEVICE_NVIDIA_NV40_GEFORCE_68007,NV_ARCH_40},
242 {DEVICE_NVIDIA_NV40_GEFORCE_68008,NV_ARCH_40},
243 {DEVICE_NVIDIA_NV40_GEFORCE_68009,NV_ARCH_40},
244 {DEVICE_NVIDIA_NV40_GEFORCE_680010,NV_ARCH_40},
245 {DEVICE_NVIDIA_NV40_GEFORCE_680011,NV_ARCH_40},
246 {DEVICE_NVIDIA_NV40_GEFORCE_680012,NV_ARCH_40},
247 {DEVICE_NVIDIA_NV40_GEFORCE_68008,NV_ARCH_40},
248 {DEVICE_NVIDIA_NV40GL,NV_ARCH_40},
249 {DEVICE_NVIDIA_NV40GL_QUADRO_FX,NV_ARCH_40},
250 {DEVICE_NVIDIA_NV40GL_QUADRO_FX2,NV_ARCH_40},
251 {DEVICE_NVIDIA_NV41_GEFORCE_6800,NV_ARCH_40},
252 {DEVICE_NVIDIA_NV41_1_GEFORCE_6800,NV_ARCH_40},
253 {DEVICE_NVIDIA_NV41_2_GEFORCE_6800,NV_ARCH_40},
254 {DEVICE_NVIDIA_NV41_8_GEFORCE_GO,NV_ARCH_40},
255 {DEVICE_NVIDIA_NV41_9_GEFORCE_GO,NV_ARCH_40},
256 {DEVICE_NVIDIA_NV41_QUADRO_FX,NV_ARCH_40},
257 {DEVICE_NVIDIA_NV41_QUADRO_FX2,NV_ARCH_40},
258 {DEVICE_NVIDIA_NV41GL_QUADRO_FX,NV_ARCH_40},
259 {DEVICE_NVIDIA_NV40_GEFORCE_6800_GEFORCE,NV_ARCH_40},
260 {DEVICE_NVIDIA_NV43_GEFORCE_6600_GEFORCE,NV_ARCH_40},
261 {DEVICE_NVIDIA_NV43_GEFORCE_6600_GEFORCE2,NV_ARCH_40},
262 {DEVICE_NVIDIA_NV43_GEFORCE_6200,NV_ARCH_40},
263 {DEVICE_NVIDIA_NV43_GEFORCE_62002,NV_ARCH_40},
264 {DEVICE_NVIDIA_NV43_GEFORCE_6600,NV_ARCH_40},
265 {DEVICE_NVIDIA_NV43_GEFORCE_66002,NV_ARCH_40},
266 {DEVICE_NVIDIA_NV43_GEFORCE_66003,NV_ARCH_40},
267 {DEVICE_NVIDIA_NV43_GEFORCE_66004,NV_ARCH_40},
268 {DEVICE_NVIDIA_NV43_GEFORCE_66005,NV_ARCH_40},
269 {DEVICE_NVIDIA_NV43_GEFORCE_GO,NV_ARCH_40},
270 {DEVICE_NVIDIA_NV43_GEFORCE_GO2,NV_ARCH_40},
271 {DEVICE_NVIDIA_NV43_GEFORCE_GO3,NV_ARCH_40},
272 {DEVICE_NVIDIA_NV43_GEFORCE_GO4,NV_ARCH_40},
273 {DEVICE_NVIDIA_NV43_GEFORCE_GO5,NV_ARCH_40},
274 {DEVICE_NVIDIA_NV43_GEFORCE_GO6,NV_ARCH_40},
275 {DEVICE_NVIDIA_NV43_GEFORCE_6610,NV_ARCH_40},
276 {DEVICE_NVIDIA_NV43GL_QUADRO_FX,NV_ARCH_40},
277 {DEVICE_NVIDIA_GEFORCE_6100_NFORCE,NV_ARCH_40},
278 {DEVICE_NVIDIA_GEFORCE_6100_NFORCE2,NV_ARCH_40},
279 {DEVICE_NVIDIA_GEFORCE_6100_NFORCE3,NV_ARCH_40},
280 {DEVICE_NVIDIA_GEFORCE_6100_NFORCE4,NV_ARCH_40},
281 {DEVICE_NVIDIA_C51G_GEFORCE_6100,NV_ARCH_40},
282 {DEVICE_NVIDIA_C51PV_GEFORCE_6150,NV_ARCH_40},
283 {DEVICE_NVIDIA_NV44_GEFORCE_6200,NV_ARCH_40},
284 {DEVICE_NVIDIA_NV44_GEFORCE_62002,NV_ARCH_40},
285 {DEVICE_NVIDIA_NV44_GEFORCE_62003,NV_ARCH_40},
286 {DEVICE_NVIDIA_NV44_GEFORCE_GO,NV_ARCH_40},
287 {DEVICE_NVIDIA_NV44_QUADRO_NVS,NV_ARCH_40},
288 {DEVICE_NVIDIA_GEFORCE_GO_6200,NV_ARCH_40},
289 {DEVICE_NVIDIA_NV44A_GEFORCE_6200,NV_ARCH_40},
290 {DEVICE_NVIDIA_NV45GL_QUADRO_FX,NV_ARCH_40},
291 {DEVICE_NVIDIA_GEFORCE_GO_7200,NV_ARCH_40},
292 {DEVICE_NVIDIA_QUADRO_NVS_110M,NV_ARCH_40},
293 {DEVICE_NVIDIA_GEFORCE_GO_7400,NV_ARCH_40},
294 {DEVICE_NVIDIA_QUADRO_NVS_110M2,NV_ARCH_40},
295 {DEVICE_NVIDIA_QUADRO_FX_350,NV_ARCH_40},
296 {DEVICE_NVIDIA_G70_GEFORCE_7300,NV_ARCH_40},
297 {DEVICE_NVIDIA_GEFORCE_7300_GS,NV_ARCH_40},
298 {DEVICE_NVIDIA_G70_GEFORCE_7600,NV_ARCH_40},
299 {DEVICE_NVIDIA_G70_GEFORCE_76002,NV_ARCH_40},
300 {DEVICE_NVIDIA_GEFORCE_7600_GS,NV_ARCH_40},
301 {DEVICE_NVIDIA_G70_GEFORCE_GO,NV_ARCH_40},
302 {DEVICE_NVIDIA_QUADRO_FX_560,NV_ARCH_40},
303 {DEVICE_NVIDIA_G70_GEFORCE_7800,NV_ARCH_40},
304 {DEVICE_NVIDIA_G70_GEFORCE_78002,NV_ARCH_40},
305 {DEVICE_NVIDIA_G70_GEFORCE_78003,NV_ARCH_40},
306 {DEVICE_NVIDIA_G70_GEFORCE_78004,NV_ARCH_40},
307 {DEVICE_NVIDIA_G70_GEFORCE_78005,NV_ARCH_40},
308 {DEVICE_NVIDIA_GEFORCE_GO_7800,NV_ARCH_40},
309 {DEVICE_NVIDIA_GEFORCE_7900_GTX,NV_ARCH_40},
310 {DEVICE_NVIDIA_GEFORCE_7900_GT,NV_ARCH_40},
311 {DEVICE_NVIDIA_GEFORCE_7900_GS,NV_ARCH_40},
312 {DEVICE_NVIDIA_GEFORCE_GO_7900,NV_ARCH_40},
313 {DEVICE_NVIDIA_GEFORCE_GO_79002,NV_ARCH_40},
314 {DEVICE_NVIDIA_GE_FORCE_GO,NV_ARCH_40},
315 {DEVICE_NVIDIA_G70GL_QUADRO_FX4500,NV_ARCH_40},
316 {DEVICE_NVIDIA_G71_QUADRO_FX,NV_ARCH_40},
317 {DEVICE_NVIDIA_G71_QUADRO_FX2,NV_ARCH_40}
318 };
319
320
find_chip(unsigned chip_id)321 static int find_chip(unsigned chip_id){
322 unsigned i;
323 for(i = 0;i < sizeof(nvidia_card_ids)/sizeof(struct nvidia_cards);i++)
324 {
325 if(chip_id == nvidia_card_ids[i].chip_id)return i;
326 }
327 return -1;
328 }
329
nv_probe(int verbose,int force)330 static int nv_probe(int verbose, int force){
331 pciinfo_t lst[MAX_PCI_DEVICES];
332 unsigned i,num_pci;
333 int err;
334
335 if (force)
336 mp_msg(MSGT_VO, MSGL_STATUS, "[nvidia_vid]: warning: forcing not supported yet!\n");
337 err = pci_scan(lst,&num_pci);
338 if(err){
339 mp_msg(MSGT_VO, MSGL_STATUS, "[nvidia_vid] Error occurred during pci scan: %s\n",strerror(err));
340 return err;
341 }
342 else {
343 err = ENXIO;
344 for(i=0; i < num_pci; i++){
345 if(lst[i].vendor == VENDOR_NVIDIA2 || lst[i].vendor == VENDOR_NVIDIA){
346 int idx;
347 const char *dname;
348 idx = find_chip(lst[i].device);
349 if(idx == -1)
350 continue;
351 dname = pci_device_name(lst[i].vendor, lst[i].device);
352 dname = dname ? dname : "Unknown chip";
353 mp_msg(MSGT_VO, MSGL_STATUS, "[nvidia_vid] Found chip: %s\n", dname);
354 if ((lst[i].command & PCI_COMMAND_IO) == 0){
355 mp_msg(MSGT_VO, MSGL_STATUS, "[nvidia_vid] Device is disabled, ignoring\n");
356 continue;
357 }
358 err = 0;
359 memcpy(&pci_info, &lst[i], sizeof(pciinfo_t));
360 break;
361 }
362 }
363 }
364 if(err && verbose) mp_msg(MSGT_VO, MSGL_STATUS, "[nvidia_vid] Can't find chip\n");
365 return err;
366 }
367
368
369
370
371 /*
372 * PCI-Memory IO access macros.
373 */
374
375 #define MEM_BARRIER() __asm__ volatile ("" : : : "memory")
376
377 #undef VID_WR08
378 #define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); })
379 #undef VID_RD08
380 #define VID_RD08(p,i) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; })
381
382 #undef VID_WR32
383 #define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=val; })
384 #undef VID_RD32
385 #define VID_RD32(p,i) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]; })
386
387 #define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val))
388 #define VID_OR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)|(val))
389 #define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val))
390
391
392
393
394
395
396 struct rivatv_chip {
397 volatile uint32_t *PMC; /* general control */
398 volatile uint32_t *PME; /* multimedia port */
399 volatile uint32_t *PFB; /* framebuffer control */
400 volatile uint32_t *PVIDEO; /* overlay control */
401 volatile uint8_t *PCIO; /* SVGA (CRTC, ATTR) registers */
402 volatile uint8_t *PVIO; /* SVGA (MISC, GRAPH, SEQ) registers */
403 volatile uint32_t *PRAMIN; /* instance memory */
404 volatile uint32_t *PRAMHT; /* hash table */
405 volatile uint32_t *PRAMFC; /* fifo context table */
406 volatile uint32_t *PRAMRO; /* fifo runout table */
407 volatile uint32_t *PFIFO; /* fifo control region */
408 volatile uint32_t *FIFO; /* fifo channels (USER) */
409 volatile uint32_t *PGRAPH; /* graphics engine */
410
411 unsigned long fbsize; /* framebuffer size */
412 int arch; /* compatible NV_ARCH_XX define */
413 int realarch; /* real architecture */
414 void (* lock) (struct rivatv_chip *, int);
415 };
416 typedef struct rivatv_chip rivatv_chip;
417
418
419 struct rivatv_info {
420 unsigned int use_colorkey;
421 unsigned int colorkey; /* saved xv colorkey*/
422 unsigned int vidixcolorkey; /*currently used colorkey*/
423 unsigned int depth;
424 unsigned int format;
425 unsigned int pitch;
426 unsigned int width,height;
427 unsigned int d_width,d_height; /*scaled width && height*/
428 unsigned int wx,wy; /*window x && y*/
429 unsigned int screen_x; /*screen width*/
430 unsigned int screen_y; /*screen height*/
431 unsigned long buffer_size; /* size of the image buffer */
432 struct rivatv_chip chip; /* NV architecture structure */
433 void* video_base; /* virtual address of control region */
434 void* control_base; /* virtual address of fb region */
435 void* picture_base; /* direct pointer to video picture */
436 unsigned long picture_offset; /* offset of video picture in frame buffer */
437 // struct rivatv_dma dma; /* DMA structure */
438 unsigned int cur_frame;
439 unsigned int num_frames; /* number of buffers */
440 int bps; /* bytes per line */
441 };
442 typedef struct rivatv_info rivatv_info;
443
nvReadVGA(struct rivatv_chip * chip,int index)444 static uint8_t nvReadVGA(struct rivatv_chip *chip, int index)
445 {
446 VID_WR08 (chip->PCIO, 0x3D4, index);
447 return VID_RD08 (chip->PCIO, 0x3D5);
448 }
449
nvWriteVGA(struct rivatv_chip * chip,int index,int data)450 static void nvWriteVGA(struct rivatv_chip *chip, int index, int data)
451 {
452 VID_WR08 (chip->PCIO, 0x3D4, index);
453 VID_WR08 (chip->PCIO, 0x3D5, data);
454 }
455
456 //framebuffer size funcs
rivatv_fbsize_nv03(struct rivatv_chip * chip)457 static unsigned long rivatv_fbsize_nv03 (struct rivatv_chip *chip){
458 if (VID_RD32 (chip->PFB, 0) & 0x00000020) {
459 if (((VID_RD32 (chip->PMC, 0) & 0xF0) == 0x20)
460 && ((VID_RD32 (chip->PMC, 0) & 0x0F) >= 0x02)) {
461 /* SDRAM 128 ZX. */
462 return (1 << (VID_RD32 (chip->PFB, 0) & 0x03)) * 1024 * 1024;
463 }
464 else {
465 return 1024 * 1024 * 8;
466 }
467 }
468 else {
469 /* SGRAM 128. */
470 switch (VID_RD32(chip->PFB, 0) & 0x00000003) {
471 case 0:
472 return 1024 * 1024 * 8;
473 break;
474 case 2:
475 return 1024 * 1024 * 4;
476 break;
477 default:
478 return 1024 * 1024 * 2;
479 break;
480 }
481 }
482 }
rivatv_fbsize_nv04(struct rivatv_chip * chip)483 static unsigned long rivatv_fbsize_nv04 (struct rivatv_chip *chip){
484 if (VID_RD32 (chip->PFB, 0) & 0x00000100) {
485 return ((VID_RD32 (chip->PFB, 0) >> 12) & 0x0F) * 1024 * 1024 * 2
486 + 1024 * 1024 * 2;
487 } else {
488 switch (VID_RD32 (chip->PFB, 0) & 0x00000003) {
489 case 0:
490 return 1024 * 1024 * 32;
491 break;
492 case 1:
493 return 1024 * 1024 * 4;
494 break;
495 case 2:
496 return 1024 * 1024 * 8;
497 break;
498 case 3:
499 default:
500 return 1024 * 1024 * 16;
501 break;
502 }
503 }
504 }
505
rivatv_fbsize_nv10(struct rivatv_chip * chip)506 static unsigned long rivatv_fbsize_nv10 (struct rivatv_chip *chip){
507 return VID_RD32 (chip->PFB, 0x20C) & 0xFFF00000;
508 }
509
510 //lock funcs
rivatv_lock_nv03(struct rivatv_chip * chip,int LockUnlock)511 static void rivatv_lock_nv03 (struct rivatv_chip *chip, int LockUnlock){
512 VID_WR08 (chip->PVIO, 0x3C4, 0x06);
513 VID_WR08 (chip->PVIO, 0x3C5, LockUnlock ? 0x99 : 0x57);
514 }
515
rivatv_lock_nv04(struct rivatv_chip * chip,int LockUnlock)516 static void rivatv_lock_nv04 (struct rivatv_chip *chip, int LockUnlock){
517 rivatv_lock_nv03 (chip, LockUnlock);
518 nvWriteVGA (chip, 0x1F, LockUnlock ? 0x99 : 0x57);
519 }
520
521
522
523
524 /* Enable PFB (Framebuffer), PVIDEO (Overlay unit) and PME (Mediaport) if neccessary. */
rivatv_enable_PMEDIA(struct rivatv_info * info)525 static void rivatv_enable_PMEDIA (struct rivatv_info *info){
526 uint32_t reg;
527
528 /* switch off interrupts once for a while */
529 // VID_WR32 (info->chip.PME, 0x200140, 0x00);
530 // VID_WR32 (info->chip.PMC, 0x000140, 0x00);
531
532 reg = VID_RD32 (info->chip.PMC, 0x000200);
533
534 /* NV3 (0x10100010): NV03_PMC_ENABLE_PMEDIA, NV03_PMC_ENABLE_PFB, NV03_PMC_ENABLE_PVIDEO */
535
536 if ((reg & 0x10100010) != 0x10100010) {
537 mp_msg(MSGT_VO, MSGL_STATUS, "[nvidia_vid] PVIDEO and PFB disabled, enabling...\n");
538 VID_OR32 (info->chip.PMC, 0x000200, 0x10100010);
539 }
540
541 /* save the current colorkey */
542 switch (info->chip.arch ) {
543 case NV_ARCH_10:
544 case NV_ARCH_20:
545 case NV_ARCH_30:
546 case NV_ARCH_40:
547 /* NV_PVIDEO_COLOR_KEY */
548 info->colorkey = VID_RD32 (info->chip.PVIDEO, 0xB00);
549 break;
550 case NV_ARCH_03:
551 case NV_ARCH_04:
552 /* NV_PVIDEO_KEY */
553 info->colorkey = VID_RD32 (info->chip.PVIDEO, 0x240);
554 break;
555 }
556
557
558 /* re-enable interrupts again */
559 // VID_WR32 (info->chip.PMC, 0x000140, 0x01);
560 // VID_WR32 (info->chip.PME, 0x200140, 0x01);
561 }
562
563 /* Stop overlay video. */
rivatv_overlay_stop(struct rivatv_info * info)564 static void rivatv_overlay_stop (struct rivatv_info *info) {
565 switch (info->chip.arch ) {
566 case NV_ARCH_10:
567 case NV_ARCH_20:
568 case NV_ARCH_30:
569 case NV_ARCH_40:
570 /* NV_PVIDEO_COLOR_KEY */
571 /* Xv-Extension-Hack: Restore previously saved value. */
572 VID_WR32 (info->chip.PVIDEO, 0xB00, info->colorkey);
573 /* NV_PVIDEO_STOP */
574 VID_OR32 (info->chip.PVIDEO, 0x704, 0x11);
575 /* NV_PVIDEO_BUFFER */
576 VID_AND32 (info->chip.PVIDEO, 0x700, ~0x11);
577 /* NV_PVIDEO_INTR_EN_BUFFER */
578 // VID_AND32 (info->chip.PVIDEO, 0x140, ~0x11);
579 break;
580 case NV_ARCH_03:
581 case NV_ARCH_04:
582 /* NV_PVIDEO_KEY */
583 VID_WR32 (info->chip.PVIDEO, 0x240, info->colorkey);
584 /* NV_PVIDEO_OVERLAY_VIDEO_OFF */
585 VID_AND32 (info->chip.PVIDEO, 0x244, ~0x01);
586 /* NV_PVIDEO_INTR_EN_0_NOTIFY */
587 // VID_AND32 (info->chip.PVIDEO, 0x140, ~0x01);
588 /* NV_PVIDEO_OE_STATE */
589 VID_WR32 (info->chip.PVIDEO, 0x224, 0);
590 /* NV_PVIDEO_SU_STATE */
591 VID_WR32 (info->chip.PVIDEO, 0x228, 0);
592 /* NV_PVIDEO_RM_STATE */
593 VID_WR32 (info->chip.PVIDEO, 0x22C, 0);
594 break;
595 }
596 }
597
598 /* Get pan offset of the physical screen. */
rivatv_overlay_pan(struct rivatv_info * info)599 static uint32_t rivatv_overlay_pan (struct rivatv_info *info){
600 uint32_t pan;
601 info->chip.lock (&info->chip, 0);
602 pan = nvReadVGA (&info->chip, 0x0D);
603 pan |= nvReadVGA (&info->chip, 0x0C) << 8;
604 pan |= (nvReadVGA (&info->chip, 0x19) & 0x1F) << 16;
605 pan |= (nvReadVGA (&info->chip, 0x2D) & 0x60) << 16;
606 return pan << 2;
607 }
608
609 /* Compute and set colorkey depending on the colour depth. */
rivatv_overlay_colorkey(rivatv_info * info,unsigned int chromakey)610 static void rivatv_overlay_colorkey (rivatv_info* info, unsigned int chromakey){
611 uint32_t r, g, b, key = 0;
612
613 r = (chromakey & 0x00FF0000) >> 16;
614 g = (chromakey & 0x0000FF00) >> 8;
615 b = chromakey & 0x000000FF;
616 switch (info->depth) {
617 case 15:
618 key = ((r >> 3) << 10) | ((g >> 3) << 5) | ((b >> 3));
619
620 #if !defined(__MINGW32__) && !defined(__CYGWIN__)
621 key = key | 0x00008000;
622 #endif
623 break;
624 case 16: // XXX unchecked
625 key = ((r >> 3) << 11) | ((g >> 2) << 5) | ((b >> 3));
626 #if !defined(__MINGW32__) && !defined(__CYGWIN__)
627 key = key | 0x00008000;
628 #endif
629 break;
630 case 24: // XXX unchecked, maybe swap order of masking - FIXME Can the card be in 24 bit mode anyway?
631 key = (chromakey & 0x00FFFFFF) | 0x00800000;
632 break;
633 case 32:
634 key = chromakey;
635 #if !defined(__MINGW32__) && !defined(__CYGWIN__)
636 key = key | 0x80000000;
637 #endif
638 break;
639 }
640 //mp_msg(MSGT_VO, MSGL_STATUS, "[nvidia_vid] depth=%d %08X \n", info->depth, chromakey);
641 switch (info->chip.arch) {
642 case NV_ARCH_10:
643 case NV_ARCH_20:
644 case NV_ARCH_30:
645 case NV_ARCH_40:
646 VID_WR32 (info->chip.PVIDEO, 0xB00, key);
647 break;
648 case NV_ARCH_03:
649 case NV_ARCH_04:
650 VID_WR32 (info->chip.PVIDEO, 0x240, key);
651 break;
652 }
653 }
654
nv_getscreenproperties(struct rivatv_info * info)655 static void nv_getscreenproperties(struct rivatv_info *info){
656 uint32_t bpp=0,x;
657 info->chip.lock(&info->chip, 0);
658 /*get screen depth*/
659 bpp = nvReadVGA (&info->chip, 0x28) & 0x3;
660 if((bpp == 2) && (VID_RD32(info->chip.PVIDEO,0x600) & 0x00001000) == 0x0)info->depth=15;
661 else info->depth = 0x04 << bpp;
662 /*get screen width*/
663 info->screen_x = nvReadVGA (&info->chip, 0x1);
664 /* NV_PCRTC_HORIZ_EXTRA_DISPLAY_END_8 */
665 info->screen_x |= (nvReadVGA (&info->chip, 0x2D) & 0x02) << 7;
666 info->screen_x = (info->screen_x + 1) << 3;
667 /*get screen height*/
668 /* get first 8 bits in VT_DISPLAY_END*/
669 info->screen_y = nvReadVGA (&info->chip, 0x12);
670 /* get 9th bit in CRTC_OVERFLOW*/
671 info->screen_y |= (nvReadVGA (&info->chip, 0x07) & 0x02) << 7;
672 /* and the 10th in CRTC_OVERFLOW*/
673 info->screen_y |= (nvReadVGA (&info->chip, 0x07) & 0x40) << 3;
674 ++info->screen_y;
675
676 if(info->chip.arch >= NV_ARCH_10){
677 /* NV_PCRTC_EXTRA_VERT_DISPLAY_END_10 */
678 info->screen_y |= (nvReadVGA (&info->chip, 0x25) & 0x02) << 9;
679 /* NV_PCRTC_???_VERT_DISPLAY_END_11 */
680 info->screen_y |= (nvReadVGA (&info->chip, 0x41) & 0x04) << 9;
681 }
682
683 /* NV_PCRTC_OFFSET */
684 x = nvReadVGA (&info->chip, 0x13);
685 /* NV_PCRTC_REPAINT0_OFFSET_10_8 */
686 x |= (nvReadVGA (&info->chip, 0x19) & 0xE0) << 3;
687 /* NV_PCRTC_EXTRA_OFFSET_11 */
688 x |= (nvReadVGA (&info->chip, 0x25) & 0x20) << 6; x <<= 3;
689 info->bps = x * bpp;
690 }
691
692
693
694
695 /* Start overlay video. */
rivatv_overlay_start(struct rivatv_info * info,int bufno)696 static void rivatv_overlay_start (struct rivatv_info *info,int bufno){
697 uint32_t base, size, offset, xscale, yscale, pan;
698 uint32_t value;
699 int x=info->wx, y=info->wy;
700 int lwidth=info->d_width, lheight=info->d_height;
701
702 size = info->buffer_size;
703 base = info->picture_offset;
704 offset = bufno*size;
705 /*update depth & dimensions here because it may change with vo vesa or vo fbdev*/
706 nv_getscreenproperties(info);
707
708 if(info->depth){
709 /* get pan offset of the physical screen */
710 pan = rivatv_overlay_pan (info);
711 /* adjust window position depending on the pan offset */
712 if (info->bps != 0)
713 {
714 x = info->wx - (pan % info->bps) * 8 / info->depth;
715 y = info->wy - (pan / info->bps);
716 }
717 } else {
718 // we can't adjust the window position correctly in textmode
719 // setting y to 8 seems to work ok, though
720 if(info->chip.arch < NV_ARCH_10 && y < 8) y = 8;
721 }
722
723 /* adjust negative output window variables */
724 if (x < 0) {
725 lwidth = info->d_width + x;
726 offset += (-x * info->width / info->d_width) << 1;
727 // offset += (-window->x * port->vld_width / window->width) << 1;
728 x = 0;
729 }
730 if (y < 0) {
731 lheight = info->d_height + y;
732 offset += (-y * info->height / info->d_height * info->width) << 1;
733 // offset += (-window->y * port->vld_height / window->height * port->org_width) << 1;
734 y = 0;
735 }
736
737 switch (info->chip.arch) {
738 case NV_ARCH_10:
739 case NV_ARCH_20:
740 case NV_ARCH_30:
741 case NV_ARCH_40:
742
743 /* NV_PVIDEO_BASE */
744 VID_WR32 (info->chip.PVIDEO, 0x900 + 0, base + offset);
745 //VID_WR32 (info->chip.PVIDEO, 0x900 + 4, base);
746 /* NV_PVIDEO_LIMIT */
747 VID_WR32 (info->chip.PVIDEO, 0x908 + 0, base + offset + size - 1);
748 //VID_WR32 (info->chip.PVIDEO, 0x908 + 4, base + size - 1);
749
750 /* extra code for NV20 && NV30 architectures */
751 if (info->chip.arch == NV_ARCH_20 || info->chip.arch == NV_ARCH_30 || info->chip.arch == NV_ARCH_40) {
752 VID_WR32 (info->chip.PVIDEO, 0x800 + 0, base + offset);
753 //VID_WR32 (info->chip.PVIDEO, 0x800 + 4, base);
754 VID_WR32 (info->chip.PVIDEO, 0x808 + 0, base + offset + size - 1);
755 //VID_WR32 (info->chip.PVIDEO, 0x808 + 4, base + size - 1);
756 }
757
758 /* NV_PVIDEO_LUMINANCE */
759 VID_WR32 (info->chip.PVIDEO, 0x910 + 0, eq.lum);
760 //VID_WR32 (info->chip.PVIDEO, 0x910 + 4, 0x00001000);
761 /* NV_PVIDEO_CHROMINANCE */
762 VID_WR32 (info->chip.PVIDEO, 0x918 + 0, eq.chrom);
763 //VID_WR32 (info->chip.PVIDEO, 0x918 + 4, 0x00001000);
764
765 /* NV_PVIDEO_OFFSET */
766 VID_WR32 (info->chip.PVIDEO, 0x920 + 0, 0x0);
767 //VID_WR32 (info->chip.PVIDEO, 0x920 + 4, offset + pitch);
768 /* NV_PVIDEO_SIZE_IN */
769 VID_WR32 (info->chip.PVIDEO, 0x928 + 0, ((info->height) << 16) | info->width);
770 //VID_WR32 (info->chip.PVIDEO, 0x928 + 4, ((port->org_height/2) << 16) | port->org_width);
771 /* NV_PVIDEO_POINT_IN */
772 VID_WR32 (info->chip.PVIDEO, 0x930 + 0, 0x00000000);
773 //VID_WR32 (info->chip.PVIDEO, 0x930 + 4, 0x00000000);
774 /* NV_PVIDEO_DS_DX_RATIO */
775 VID_WR32 (info->chip.PVIDEO, 0x938 + 0, (info->width << 20) / info->d_width);
776 //VID_WR32 (info->chip.PVIDEO, 0x938 + 4, (port->org_width << 20) / window->width);
777 /* NV_PVIDEO_DT_DY_RATIO */
778 VID_WR32 (info->chip.PVIDEO, 0x940 + 0, ((info->height) << 20) / info->d_height);
779 //VID_WR32 (info->chip.PVIDEO, 0x940 + 4, ((port->org_height/2) << 20) / window->height);
780
781 /* NV_PVIDEO_POINT_OUT */
782 VID_WR32 (info->chip.PVIDEO, 0x948 + 0, ((y + 0) << 16) | x);
783 //VID_WR32 (info->chip.PVIDEO, 0x948 + 4, ((y + 0) << 16) | x);
784 /* NV_PVIDEO_SIZE_OUT */
785 VID_WR32 (info->chip.PVIDEO, 0x950 + 0, (lheight << 16) | lwidth);
786 //VID_WR32 (info->chip.PVIDEO, 0x950 + 4, (height << 16) | width);
787
788 /* NV_PVIDEO_FORMAT */
789 value = info->pitch;
790 if(info->use_colorkey)value |= 1 << 20;
791 if(info->format == IMGFMT_YUY2)value |= 1 << 16;
792 VID_WR32 (info->chip.PVIDEO, 0x958 + 0, value);
793 //VID_WR32 (info->chip.PVIDEO, 0x958 + 4, (pitch << 1) | 0x00100000);
794
795 /* NV_PVIDEO_INTR_EN_BUFFER */
796 // VID_OR32 (info->chip.PVIDEO, 0x140, 0x01/*0x11*/);
797 /* NV_PVIDEO_STOP */
798 VID_WR32 (info->chip.PVIDEO, 0x704,0x0);
799 /* NV_PVIDEO_BUFFER */
800 VID_WR32 (info->chip.PVIDEO, 0x700, 0x01/*0x11*/);
801 break;
802
803 case NV_ARCH_03:
804 case NV_ARCH_04:
805
806
807 /* NV_PVIDEO_OE_STATE */
808 VID_WR32 (info->chip.PVIDEO, 0x224, 0);
809 /* NV_PVIDEO_SU_STATE */
810 VID_WR32 (info->chip.PVIDEO, 0x228, 0);
811 /* NV_PVIDEO_RM_STATE */
812 VID_WR32 (info->chip.PVIDEO, 0x22C, 0);
813
814 /* NV_PVIDEO_BUFF0_START_ADDRESS */
815 VID_WR32 (info->chip.PVIDEO, 0x20C + 0, base + offset + 0);
816 VID_WR32 (info->chip.PVIDEO, 0x20C + 4, base + offset + 0);
817 /* NV_PVIDEO_BUFF0_PITCH_LENGTH */
818 VID_WR32 (info->chip.PVIDEO, 0x214 + 0, info->pitch);
819 VID_WR32 (info->chip.PVIDEO, 0x214 + 4, info->pitch);
820
821 /* NV_PVIDEO_WINDOW_START */
822 VID_WR32 (info->chip.PVIDEO, 0x230, (y << 16) | x);
823 /* NV_PVIDEO_WINDOW_SIZE */
824 VID_WR32 (info->chip.PVIDEO, 0x234, (lheight << 16) | lwidth);
825 /* NV_PVIDEO_STEP_SIZE */
826 yscale = ((info->height - 1) << 11) / (info->d_height - 1);
827 xscale = ((info->width - 1) << 11) / (info->d_width - 1);
828 VID_WR32 (info->chip.PVIDEO, 0x200, (yscale << 16) | xscale);
829
830 /* NV_PVIDEO_RED_CSC_OFFSET */
831 VID_WR32 (info->chip.PVIDEO, 0x280, eq.red_off);
832 /* NV_PVIDEO_GREEN_CSC_OFFSET */
833 VID_WR32 (info->chip.PVIDEO, 0x284, eq.green_off);
834 /* NV_PVIDEO_BLUE_CSC_OFFSET */
835 VID_WR32 (info->chip.PVIDEO, 0x288, eq.blue_off);
836 /* NV_PVIDEO_CSC_ADJUST */
837 VID_WR32 (info->chip.PVIDEO, 0x28C, 0x00000); /* No colour correction! */
838
839 /* NV_PVIDEO_CONTROL_Y (BLUR_ON, LINE_HALF) */
840 VID_WR32 (info->chip.PVIDEO, 0x204, 0x001);
841 /* NV_PVIDEO_CONTROL_X (WEIGHT_HEAVY, SHARPENING_ON, SMOOTHING_ON) */
842 VID_WR32 (info->chip.PVIDEO, 0x208, 0x111); /*directx overlay 0x110 */
843
844 /* NV_PVIDEO_FIFO_BURST_LENGTH */
845 VID_WR32 (info->chip.PVIDEO, 0x23C, 0x03);
846 /* NV_PVIDEO_FIFO_THRES_SIZE */
847 VID_WR32 (info->chip.PVIDEO, 0x238, 0x38); /*windows uses 0x40*/
848
849 /* NV_PVIDEO_BUFF0_OFFSET */
850 VID_WR32 (info->chip.PVIDEO, 0x21C + 0, 0);
851 VID_WR32 (info->chip.PVIDEO, 0x21C + 4, 0);
852
853 /* NV_PVIDEO_INTR_EN_0_NOTIFY_ENABLED */
854 // VID_OR32 (info->chip.PVIDEO, 0x140, 0x01);
855
856 /* NV_PVIDEO_OVERLAY (KEY_ON, VIDEO_ON, FORMAT_CCIR) */
857 value = 0x1; /*video on*/
858 if(info->format==IMGFMT_YUY2)value |= 0x100;
859 if(info->use_colorkey)value |=0x10;
860 VID_WR32 (info->chip.PVIDEO, 0x244, value);
861
862 /* NV_PVIDEO_SU_STATE */
863 VID_XOR32 (info->chip.PVIDEO, 0x228, 1 << 16);
864 break;
865 }
866 /*set colorkey*/
867 rivatv_overlay_colorkey(info,info->vidixcolorkey);
868
869 }
870
871
872
873
874
875
876
877 static rivatv_info* info;
878
879
880
881
nv_init(void)882 static int nv_init(void){
883 int mtrr;
884 int chip;
885 info = calloc(1,sizeof(rivatv_info));
886 info->control_base = map_phys_mem(pci_info.base0, 0x00C00000 + 0x00008000);
887 chip = find_chip(pci_info.device);
888 if (chip < 0) chip = 0;
889 info->chip.arch = nvidia_card_ids[chip].arch;
890 mp_msg(MSGT_VO, MSGL_STATUS, "[nvidia_vid] arch %x register base %p\n",info->chip.arch,info->control_base);
891 info->chip.PFIFO = (uint32_t *) (info->control_base + 0x00002000);
892 info->chip.FIFO = (uint32_t *) (info->control_base + 0x00800000);
893 info->chip.PMC = (uint32_t *) (info->control_base + 0x00000000);
894 info->chip.PFB = (uint32_t *) (info->control_base + 0x00100000);
895 info->chip.PME = (uint32_t *) (info->control_base + 0x00000000);
896 info->chip.PCIO = (uint8_t *) (info->control_base + 0x00601000);
897 info->chip.PVIO = (uint8_t *) (info->control_base + 0x000C0000);
898 info->chip.PGRAPH = (uint32_t *) (info->control_base + 0x00400000);
899 /* setup chip specific functions */
900 switch (info->chip.arch) {
901 case NV_ARCH_03:
902 info->chip.lock = rivatv_lock_nv03;
903 info->chip.fbsize = rivatv_fbsize_nv03 (&info->chip);
904 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000);
905 break;
906 case NV_ARCH_04:
907 info->chip.lock = rivatv_lock_nv04;
908 info->chip.fbsize = rivatv_fbsize_nv04 (&info->chip);
909 info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000);
910 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000);
911 break;
912 case NV_ARCH_10:
913 case NV_ARCH_20:
914 case NV_ARCH_30:
915 case NV_ARCH_40:
916 info->chip.lock = rivatv_lock_nv04;
917 info->chip.fbsize = rivatv_fbsize_nv10 (&info->chip);
918 info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000);
919 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00008000);
920 break;
921 }
922 switch (info->chip.arch) {
923 case NV_ARCH_03:
924 {
925 /* This maps framebuffer @6MB, thus 2MB are left for video. */
926 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize);
927 /* This may trash your screen for resolutions greater than 1024x768, sorry. */
928 info->picture_offset = 1024*768* 4 * ((info->chip.fbsize > 4194304)?2:1);
929 info->picture_base = info->video_base + info->picture_offset;
930 info->chip.PRAMIN = (uint32_t *) (info->video_base + 0x00C00000);
931 break;
932 }
933 case NV_ARCH_04:
934 case NV_ARCH_10:
935 case NV_ARCH_20:
936 case NV_ARCH_30:
937 case NV_ARCH_40:
938 {
939 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize);
940 info->picture_offset = info->chip.fbsize - NV04_BES_SIZE;
941 if(info->chip.fbsize > 16*1024*1024)
942 info->picture_offset -= NV04_BES_SIZE;
943 // info->picture_base = (unsigned long)map_phys_mem(pci_info.base1+info->picture_offset,NV04_BES_SIZE);
944 info->picture_base = info->video_base + info->picture_offset;
945 break;
946 }
947 }
948
949 mp_msg(MSGT_VO, MSGL_STATUS, "[nvidia_vid] detected memory size %u MB\n",(uint32_t)(info->chip.fbsize /1024/1024));
950
951 if ((mtrr = mtrr_set_type(pci_info.base1, info->chip.fbsize, MTRR_TYPE_WRCOMB))!= 0)
952 mp_msg(MSGT_VO, MSGL_STATUS, "[nvidia_vid] unable to setup MTRR: %s\n", strerror(mtrr));
953 else
954 mp_msg(MSGT_VO, MSGL_STATUS, "[nvidia_vid] MTRR set up\n");
955
956 nv_getscreenproperties(info);
957 if(!info->depth) mp_msg(MSGT_VO, MSGL_STATUS, "[nvidia_vid] text mode: %ux%u\n",info->screen_x,info->screen_y);
958 else mp_msg(MSGT_VO, MSGL_STATUS, "[nvidia_vid] video mode: %ux%u@%u\n",info->screen_x,info->screen_y, info->depth);
959
960
961 rivatv_enable_PMEDIA(info);
962 info->cur_frame = 0;
963 info->use_colorkey = 0;
964
965 eq.lum = 0x00001000;
966 eq.chrom = 0x00001000;
967 memset(&eq.vals, 0, sizeof(vidix_video_eq_t));
968 eq.vals.cap = VEQ_CAP_BRIGHTNESS;
969 if (info->chip.arch > NV_ARCH_04)
970 eq.vals.cap |= VEQ_CAP_CONTRAST | VEQ_CAP_SATURATION | VEQ_CAP_HUE;
971 eq.red_off = 0x69;
972 eq.green_off = 0x3e;
973 eq.blue_off = 0x89;
974 return 0;
975 }
976
nv_destroy(void)977 static void nv_destroy(void){
978 unmap_phys_mem(info->control_base ,0x00C00000 + 0x00008000);
979 unmap_phys_mem(info->video_base, info->chip.fbsize);
980 free(info);
981 }
982
nv_get_caps(vidix_capability_t * to)983 static int nv_get_caps(vidix_capability_t *to){
984 memcpy(to, &nvidia_cap, sizeof(vidix_capability_t));
985 to->device_id = pci_info.device;
986 return 0;
987 }
988
is_supported_fourcc(uint32_t fourcc)989 static inline int is_supported_fourcc(uint32_t fourcc)
990 {
991 if (fourcc == IMGFMT_UYVY || fourcc == IMGFMT_YUY2)
992 return 1;
993 else
994 return 0;
995 }
996
nv_query_fourcc(vidix_fourcc_t * to)997 static int nv_query_fourcc(vidix_fourcc_t *to){
998 if(is_supported_fourcc(to->fourcc)){
999 to->depth = VID_DEPTH_ALL;
1000 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY;
1001 return 0;
1002 }
1003 return ENOSYS;
1004 }
1005
nv_config_playback(vidix_playback_t * vinfo)1006 static int nv_config_playback(vidix_playback_t *vinfo){
1007 uint32_t i;
1008 // mp_msg(MSGT_VO, MSGL_STATUS, "called %s\n", __FUNCTION__);
1009 if (! is_supported_fourcc(vinfo->fourcc))
1010 return ENOSYS;
1011
1012 info->width = vinfo->src.w;
1013 info->height = vinfo->src.h;
1014
1015 info->d_width = vinfo->dest.w;
1016 info->d_height = vinfo->dest.h;
1017 info->wx = vinfo->dest.x;
1018 info->wy = vinfo->dest.y;
1019 info->format = vinfo->fourcc;
1020
1021 mp_msg(MSGT_VO, MSGL_STATUS, "[nvidia_vid] setting up a %dx%d-%dx%d video window (src %dx%d), format 0x%X\n",
1022 info->d_width, info->d_height, info->wx, info->wy, info->width, info->height, vinfo->fourcc);
1023
1024
1025 vinfo->dga_addr=info->picture_base;
1026
1027 switch (vinfo->fourcc)
1028 {
1029 case IMGFMT_YUY2:
1030 case IMGFMT_UYVY:
1031
1032 vinfo->dest.pitch.y = 64;
1033 vinfo->dest.pitch.u = 0;
1034 vinfo->dest.pitch.v = 0;
1035
1036 vinfo->offset.y = 0;
1037 vinfo->offset.v = 0;
1038 vinfo->offset.u = 0;
1039 info->pitch = ((info->width << 1) + (vinfo->dest.pitch.y-1)) & ~(vinfo->dest.pitch.y-1);
1040 vinfo->frame_size = info->pitch * info->height;
1041 break;
1042 }
1043 info->buffer_size = vinfo->frame_size;
1044 info->num_frames = vinfo->num_frames= (info->chip.fbsize - info->picture_offset)/vinfo->frame_size;
1045 if(vinfo->num_frames > MAX_FRAMES)vinfo->num_frames = MAX_FRAMES;
1046 // vinfo->num_frames = 1;
1047 // mp_msg(MSGT_VO, MSGL_STATUS, "[nvidia_vid] Number of frames %i\n",vinfo->num_frames);
1048 for(i=0;i <vinfo->num_frames;i++)vinfo->offsets[i] = vinfo->frame_size*i;
1049 return 0;
1050 }
1051
nv_playback_on(void)1052 static int nv_playback_on(void){
1053 rivatv_overlay_start(info,info->cur_frame);
1054 return 0;
1055 }
1056
nv_playback_off(void)1057 static int nv_playback_off(void){
1058 rivatv_overlay_stop(info);
1059 return 0;
1060 }
1061
nv_set_gkeys(const vidix_grkey_t * grkey)1062 static int nv_set_gkeys( const vidix_grkey_t * grkey){
1063 if (grkey->ckey.op == CKEY_FALSE)
1064 {
1065 info->use_colorkey = 0;
1066 mp_msg(MSGT_VO, MSGL_STATUS, "[nvidia_vid] colorkeying disabled\n");
1067 }
1068 else {
1069 info->use_colorkey = 1;
1070 info->vidixcolorkey = ((grkey->ckey.red<<16)|(grkey->ckey.green<<8)|grkey->ckey.blue);
1071 mp_msg(MSGT_VO, MSGL_STATUS, "[nvidia_vid] set colorkey 0x%x\n",info->vidixcolorkey);
1072 }
1073 if(info->d_width && info->d_height)rivatv_overlay_start(info,0);
1074 return 0;
1075 }
1076
nv_frame_sel(unsigned int frame)1077 static int nv_frame_sel(unsigned int frame){
1078 // mp_msg(MSGT_VO, MSGL_STATUS, "selecting buffer %d\n", frame);
1079 rivatv_overlay_start(info, frame);
1080 if (info->num_frames >= 1)
1081 info->cur_frame = frame/*(frame+1)%info->num_frames*/;
1082 return 0;
1083 }
1084
nv_set_eq(const vidix_video_eq_t * eq_parm)1085 static int nv_set_eq(const vidix_video_eq_t *eq_parm) {
1086 double angle;
1087 int16_t chrom_cos, chrom_sin;
1088 if (eq_parm->cap & VEQ_CAP_BRIGHTNESS)
1089 eq.vals.brightness = eq_parm->brightness;
1090 if (eq_parm->cap & VEQ_CAP_CONTRAST)
1091 eq.vals.contrast = eq_parm->contrast;
1092 if (eq_parm->cap & VEQ_CAP_SATURATION)
1093 eq.vals.saturation = eq_parm->saturation;
1094 if (eq_parm->cap & VEQ_CAP_HUE)
1095 eq.vals.hue = eq_parm->hue;
1096 eq.lum = (((eq.vals.brightness * 512 + 500) / 1000) << 16) |
1097 ((((eq.vals.contrast + 1000) * 8191 + 1000) / 2000) & 0xffff);
1098 angle = (double)eq.vals.hue / 1000.0 * 3.1415927;
1099 chrom_cos = ((eq.vals.saturation + 1000) * 8191 * cos(angle) + 1000) / 2000;
1100 chrom_sin = ((eq.vals.saturation + 1000) * 8191 * sin(angle) + 1000) / 2000;
1101 eq.chrom = chrom_sin << 16 | chrom_cos;
1102 eq.red_off = 0x69 - eq.vals.brightness * 62 / 1000;
1103 eq.green_off = 0x3e + eq.vals.brightness * 62 / 1000;
1104 eq.blue_off = 0x89 - eq.vals.brightness * 62 / 1000;
1105 return 0;
1106 }
1107
nv_get_eq(vidix_video_eq_t * eq_parm)1108 static int nv_get_eq(vidix_video_eq_t *eq_parm) {
1109 memcpy(eq_parm, &eq.vals, sizeof(vidix_video_eq_t));
1110 return 0;
1111 }
1112
1113 const VDXDriver nvidia_drv = {
1114 "nvidia",
1115 NULL,
1116 .probe = nv_probe,
1117 .get_caps = nv_get_caps,
1118 .query_fourcc = nv_query_fourcc,
1119 .init = nv_init,
1120 .destroy = nv_destroy,
1121 .config_playback = nv_config_playback,
1122 .playback_on = nv_playback_on,
1123 .playback_off = nv_playback_off,
1124 .frame_sel = nv_frame_sel,
1125 .get_eq = nv_get_eq,
1126 .set_eq = nv_set_eq,
1127 .set_gkey = nv_set_gkeys,
1128 };
1129
1130
1131 #if 0
1132 //gcc -o nvidia_vid nvidia_vid.c -I ../ -lm ../vidix/libvidix.a
1133
1134 int main(int argc,char* argv[]){
1135 if(nv_probe(0,0)){
1136 mp_msg(MSGT_VO, MSGL_STATUS, "no supported chip found\n");
1137 return 1;
1138 }
1139 if(nv_init()){
1140 mp_msg(MSGT_VO, MSGL_STATUS, "could not init\n");
1141 return 1;
1142 }
1143 if(info->chip.arch >= NV_ARCH_10){
1144 mp_msg(MSGT_VO, MSGL_STATUS, "NV_PVIDEO_BASE (0x900) 0x%x\n",VID_RD32(info->chip.PVIDEO, 0x900));
1145 mp_msg(MSGT_VO, MSGL_STATUS, "NV_PVIDEO_LIMIT (0x908) 0x%x\n",VID_RD32(info->chip.PVIDEO, 0x908));
1146 mp_msg(MSGT_VO, MSGL_STATUS, "NV_PVIDEO_OFFSET (0x920) 0x%x\n",VID_RD32(info->chip.PVIDEO, 0x920));
1147 mp_msg(MSGT_VO, MSGL_STATUS, "NV_PVIDEO_FORMAT (0x958) 0x%x\n",VID_RD32(info->chip.PVIDEO, 0x958));
1148 mp_msg(MSGT_VO, MSGL_STATUS, "NV_PVIDEO_STOP (0x704) 0x%x\n",VID_RD32(info->chip.PVIDEO, 0x704));
1149 mp_msg(MSGT_VO, MSGL_STATUS, "NV_PVIDEO_BUFFER (0x700) 0x%x\n",VID_RD32(info->chip.PVIDEO, 0x700));
1150 }
1151
1152 nv_destroy();
1153 return 0;
1154 }
1155
1156 #endif
1157