1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/phy/phy.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/clock/g12a-clkc.h> 9#include <dt-bindings/clock/g12a-aoclkc.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 mmc0 = &sd_emmc_b; /* SD card */ 22 mmc1 = &sd_emmc_c; /* eMMC */ 23 mmc2 = &sd_emmc_a; /* SDIO */ 24 }; 25 26 chosen { 27 #address-cells = <2>; 28 #size-cells = <2>; 29 ranges; 30 31 simplefb_cvbs: framebuffer-cvbs { 32 compatible = "amlogic,simple-framebuffer", 33 "simple-framebuffer"; 34 amlogic,pipeline = "vpu-cvbs"; 35 clocks = <&clkc CLKID_HDMI>, 36 <&clkc CLKID_HTX_PCLK>, 37 <&clkc CLKID_VPU_INTR>; 38 status = "disabled"; 39 }; 40 41 simplefb_hdmi: framebuffer-hdmi { 42 compatible = "amlogic,simple-framebuffer", 43 "simple-framebuffer"; 44 amlogic,pipeline = "vpu-hdmi"; 45 clocks = <&clkc CLKID_HDMI>, 46 <&clkc CLKID_HTX_PCLK>, 47 <&clkc CLKID_VPU_INTR>; 48 status = "disabled"; 49 }; 50 }; 51 52 efuse: efuse { 53 compatible = "amlogic,meson-gxbb-efuse"; 54 clocks = <&clkc CLKID_EFUSE>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 read-only; 58 secure-monitor = <&sm>; 59 }; 60 61 gpu_opp_table: gpu-opp-table { 62 compatible = "operating-points-v2"; 63 64 opp-124999998 { 65 opp-hz = /bits/ 64 <124999998>; 66 opp-microvolt = <800000>; 67 }; 68 opp-249999996 { 69 opp-hz = /bits/ 64 <249999996>; 70 opp-microvolt = <800000>; 71 }; 72 opp-285714281 { 73 opp-hz = /bits/ 64 <285714281>; 74 opp-microvolt = <800000>; 75 }; 76 opp-399999994 { 77 opp-hz = /bits/ 64 <399999994>; 78 opp-microvolt = <800000>; 79 }; 80 opp-499999992 { 81 opp-hz = /bits/ 64 <499999992>; 82 opp-microvolt = <800000>; 83 }; 84 opp-666666656 { 85 opp-hz = /bits/ 64 <666666656>; 86 opp-microvolt = <800000>; 87 }; 88 opp-799999987 { 89 opp-hz = /bits/ 64 <799999987>; 90 opp-microvolt = <800000>; 91 }; 92 }; 93 94 psci { 95 compatible = "arm,psci-1.0"; 96 method = "smc"; 97 }; 98 99 reserved-memory { 100 #address-cells = <2>; 101 #size-cells = <2>; 102 ranges; 103 104 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 105 secmon_reserved: secmon@5000000 { 106 reg = <0x0 0x05000000 0x0 0x300000>; 107 no-map; 108 }; 109 110 linux,cma { 111 compatible = "shared-dma-pool"; 112 reusable; 113 size = <0x0 0x10000000>; 114 alignment = <0x0 0x400000>; 115 linux,cma-default; 116 }; 117 }; 118 119 sm: secure-monitor { 120 compatible = "amlogic,meson-gxbb-sm"; 121 }; 122 123 soc { 124 compatible = "simple-bus"; 125 #address-cells = <2>; 126 #size-cells = <2>; 127 ranges; 128 129 pcie: pcie@fc000000 { 130 compatible = "amlogic,g12a-pcie", "snps,dw-pcie"; 131 reg = <0x0 0xfc000000 0x0 0x400000>, 132 <0x0 0xff648000 0x0 0x2000>, 133 <0x0 0xfc400000 0x0 0x200000>; 134 reg-names = "elbi", "cfg", "config"; 135 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 136 #interrupt-cells = <1>; 137 interrupt-map-mask = <0 0 0 0>; 138 interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 139 bus-range = <0x0 0xff>; 140 #address-cells = <3>; 141 #size-cells = <2>; 142 device_type = "pci"; 143 ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000>, 144 <0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>; 145 146 clocks = <&clkc CLKID_PCIE_PHY 147 &clkc CLKID_PCIE_COMB 148 &clkc CLKID_PCIE_PLL>; 149 clock-names = "general", 150 "pclk", 151 "port"; 152 resets = <&reset RESET_PCIE_CTRL_A>, 153 <&reset RESET_PCIE_APB>; 154 reset-names = "port", 155 "apb"; 156 num-lanes = <1>; 157 phys = <&usb3_pcie_phy PHY_TYPE_PCIE>; 158 phy-names = "pcie"; 159 status = "disabled"; 160 }; 161 162 thermal-zones { 163 cpu_thermal: cpu-thermal { 164 polling-delay = <1000>; 165 polling-delay-passive = <100>; 166 thermal-sensors = <&cpu_temp>; 167 168 trips { 169 cpu_passive: cpu-passive { 170 temperature = <85000>; /* millicelsius */ 171 hysteresis = <2000>; /* millicelsius */ 172 type = "passive"; 173 }; 174 175 cpu_hot: cpu-hot { 176 temperature = <95000>; /* millicelsius */ 177 hysteresis = <2000>; /* millicelsius */ 178 type = "hot"; 179 }; 180 181 cpu_critical: cpu-critical { 182 temperature = <110000>; /* millicelsius */ 183 hysteresis = <2000>; /* millicelsius */ 184 type = "critical"; 185 }; 186 }; 187 }; 188 189 ddr_thermal: ddr-thermal { 190 polling-delay = <1000>; 191 polling-delay-passive = <100>; 192 thermal-sensors = <&ddr_temp>; 193 194 trips { 195 ddr_passive: ddr-passive { 196 temperature = <85000>; /* millicelsius */ 197 hysteresis = <2000>; /* millicelsius */ 198 type = "passive"; 199 }; 200 201 ddr_critical: ddr-critical { 202 temperature = <110000>; /* millicelsius */ 203 hysteresis = <2000>; /* millicelsius */ 204 type = "critical"; 205 }; 206 }; 207 208 cooling-maps { 209 map { 210 trip = <&ddr_passive>; 211 cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 212 }; 213 }; 214 }; 215 }; 216 217 ethmac: ethernet@ff3f0000 { 218 compatible = "amlogic,meson-g12a-dwmac", 219 "snps,dwmac-3.70a", 220 "snps,dwmac"; 221 reg = <0x0 0xff3f0000 0x0 0x10000>, 222 <0x0 0xff634540 0x0 0x8>; 223 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 224 interrupt-names = "macirq"; 225 clocks = <&clkc CLKID_ETH>, 226 <&clkc CLKID_FCLK_DIV2>, 227 <&clkc CLKID_MPLL2>, 228 <&clkc CLKID_FCLK_DIV2>; 229 clock-names = "stmmaceth", "clkin0", "clkin1", 230 "timing-adjustment"; 231 rx-fifo-depth = <4096>; 232 tx-fifo-depth = <2048>; 233 status = "disabled"; 234 235 mdio0: mdio { 236 #address-cells = <1>; 237 #size-cells = <0>; 238 compatible = "snps,dwmac-mdio"; 239 }; 240 }; 241 242 apb: bus@ff600000 { 243 compatible = "simple-bus"; 244 reg = <0x0 0xff600000 0x0 0x200000>; 245 #address-cells = <2>; 246 #size-cells = <2>; 247 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 248 249 hdmi_tx: hdmi-tx@0 { 250 compatible = "amlogic,meson-g12a-dw-hdmi"; 251 reg = <0x0 0x0 0x0 0x10000>; 252 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 253 resets = <&reset RESET_HDMITX_CAPB3>, 254 <&reset RESET_HDMITX_PHY>, 255 <&reset RESET_HDMITX>; 256 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 257 clocks = <&clkc CLKID_HDMI>, 258 <&clkc CLKID_HTX_PCLK>, 259 <&clkc CLKID_VPU_INTR>; 260 clock-names = "isfr", "iahb", "venci"; 261 #address-cells = <1>; 262 #size-cells = <0>; 263 #sound-dai-cells = <0>; 264 status = "disabled"; 265 266 /* VPU VENC Input */ 267 hdmi_tx_venc_port: port@0 { 268 reg = <0>; 269 270 hdmi_tx_in: endpoint { 271 remote-endpoint = <&hdmi_tx_out>; 272 }; 273 }; 274 275 /* TMDS Output */ 276 hdmi_tx_tmds_port: port@1 { 277 reg = <1>; 278 }; 279 }; 280 281 apb_efuse: bus@30000 { 282 compatible = "simple-bus"; 283 reg = <0x0 0x30000 0x0 0x2000>; 284 #address-cells = <2>; 285 #size-cells = <2>; 286 ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>; 287 288 hwrng: rng@218 { 289 compatible = "amlogic,meson-rng"; 290 reg = <0x0 0x218 0x0 0x4>; 291 clocks = <&clkc CLKID_RNG0>; 292 clock-names = "core"; 293 }; 294 }; 295 296 acodec: audio-controller@32000 { 297 compatible = "amlogic,t9015"; 298 reg = <0x0 0x32000 0x0 0x14>; 299 #sound-dai-cells = <0>; 300 sound-name-prefix = "ACODEC"; 301 clocks = <&clkc CLKID_AUDIO_CODEC>; 302 clock-names = "pclk"; 303 resets = <&reset RESET_AUDIO_CODEC>; 304 status = "disabled"; 305 }; 306 307 periphs: bus@34400 { 308 compatible = "simple-bus"; 309 reg = <0x0 0x34400 0x0 0x400>; 310 #address-cells = <2>; 311 #size-cells = <2>; 312 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 313 314 periphs_pinctrl: pinctrl@40 { 315 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 316 #address-cells = <2>; 317 #size-cells = <2>; 318 ranges; 319 320 gpio: bank@40 { 321 reg = <0x0 0x40 0x0 0x4c>, 322 <0x0 0xe8 0x0 0x18>, 323 <0x0 0x120 0x0 0x18>, 324 <0x0 0x2c0 0x0 0x40>, 325 <0x0 0x340 0x0 0x1c>; 326 reg-names = "gpio", 327 "pull", 328 "pull-enable", 329 "mux", 330 "ds"; 331 gpio-controller; 332 #gpio-cells = <2>; 333 gpio-ranges = <&periphs_pinctrl 0 0 86>; 334 }; 335 336 cec_ao_a_h_pins: cec_ao_a_h { 337 mux { 338 groups = "cec_ao_a_h"; 339 function = "cec_ao_a_h"; 340 bias-disable; 341 }; 342 }; 343 344 cec_ao_b_h_pins: cec_ao_b_h { 345 mux { 346 groups = "cec_ao_b_h"; 347 function = "cec_ao_b_h"; 348 bias-disable; 349 }; 350 }; 351 352 emmc_ctrl_pins: emmc-ctrl { 353 mux-0 { 354 groups = "emmc_cmd"; 355 function = "emmc"; 356 bias-pull-up; 357 drive-strength-microamp = <4000>; 358 }; 359 360 mux-1 { 361 groups = "emmc_clk"; 362 function = "emmc"; 363 bias-disable; 364 drive-strength-microamp = <4000>; 365 }; 366 }; 367 368 emmc_data_4b_pins: emmc-data-4b { 369 mux-0 { 370 groups = "emmc_nand_d0", 371 "emmc_nand_d1", 372 "emmc_nand_d2", 373 "emmc_nand_d3"; 374 function = "emmc"; 375 bias-pull-up; 376 drive-strength-microamp = <4000>; 377 }; 378 }; 379 380 emmc_data_8b_pins: emmc-data-8b { 381 mux-0 { 382 groups = "emmc_nand_d0", 383 "emmc_nand_d1", 384 "emmc_nand_d2", 385 "emmc_nand_d3", 386 "emmc_nand_d4", 387 "emmc_nand_d5", 388 "emmc_nand_d6", 389 "emmc_nand_d7"; 390 function = "emmc"; 391 bias-pull-up; 392 drive-strength-microamp = <4000>; 393 }; 394 }; 395 396 emmc_ds_pins: emmc-ds { 397 mux { 398 groups = "emmc_nand_ds"; 399 function = "emmc"; 400 bias-pull-down; 401 drive-strength-microamp = <4000>; 402 }; 403 }; 404 405 emmc_clk_gate_pins: emmc_clk_gate { 406 mux { 407 groups = "BOOT_8"; 408 function = "gpio_periphs"; 409 bias-pull-down; 410 drive-strength-microamp = <4000>; 411 }; 412 }; 413 414 hdmitx_ddc_pins: hdmitx_ddc { 415 mux { 416 groups = "hdmitx_sda", 417 "hdmitx_sck"; 418 function = "hdmitx"; 419 bias-disable; 420 drive-strength-microamp = <4000>; 421 }; 422 }; 423 424 hdmitx_hpd_pins: hdmitx_hpd { 425 mux { 426 groups = "hdmitx_hpd_in"; 427 function = "hdmitx"; 428 bias-disable; 429 }; 430 }; 431 432 433 i2c0_sda_c_pins: i2c0-sda-c { 434 mux { 435 groups = "i2c0_sda_c"; 436 function = "i2c0"; 437 bias-disable; 438 drive-strength-microamp = <3000>; 439 440 }; 441 }; 442 443 i2c0_sck_c_pins: i2c0-sck-c { 444 mux { 445 groups = "i2c0_sck_c"; 446 function = "i2c0"; 447 bias-disable; 448 drive-strength-microamp = <3000>; 449 }; 450 }; 451 452 i2c0_sda_z0_pins: i2c0-sda-z0 { 453 mux { 454 groups = "i2c0_sda_z0"; 455 function = "i2c0"; 456 bias-disable; 457 drive-strength-microamp = <3000>; 458 }; 459 }; 460 461 i2c0_sck_z1_pins: i2c0-sck-z1 { 462 mux { 463 groups = "i2c0_sck_z1"; 464 function = "i2c0"; 465 bias-disable; 466 drive-strength-microamp = <3000>; 467 }; 468 }; 469 470 i2c0_sda_z7_pins: i2c0-sda-z7 { 471 mux { 472 groups = "i2c0_sda_z7"; 473 function = "i2c0"; 474 bias-disable; 475 drive-strength-microamp = <3000>; 476 }; 477 }; 478 479 i2c0_sda_z8_pins: i2c0-sda-z8 { 480 mux { 481 groups = "i2c0_sda_z8"; 482 function = "i2c0"; 483 bias-disable; 484 drive-strength-microamp = <3000>; 485 }; 486 }; 487 488 i2c1_sda_x_pins: i2c1-sda-x { 489 mux { 490 groups = "i2c1_sda_x"; 491 function = "i2c1"; 492 bias-disable; 493 drive-strength-microamp = <3000>; 494 }; 495 }; 496 497 i2c1_sck_x_pins: i2c1-sck-x { 498 mux { 499 groups = "i2c1_sck_x"; 500 function = "i2c1"; 501 bias-disable; 502 drive-strength-microamp = <3000>; 503 }; 504 }; 505 506 i2c1_sda_h2_pins: i2c1-sda-h2 { 507 mux { 508 groups = "i2c1_sda_h2"; 509 function = "i2c1"; 510 bias-disable; 511 drive-strength-microamp = <3000>; 512 }; 513 }; 514 515 i2c1_sck_h3_pins: i2c1-sck-h3 { 516 mux { 517 groups = "i2c1_sck_h3"; 518 function = "i2c1"; 519 bias-disable; 520 drive-strength-microamp = <3000>; 521 }; 522 }; 523 524 i2c1_sda_h6_pins: i2c1-sda-h6 { 525 mux { 526 groups = "i2c1_sda_h6"; 527 function = "i2c1"; 528 bias-disable; 529 drive-strength-microamp = <3000>; 530 }; 531 }; 532 533 i2c1_sck_h7_pins: i2c1-sck-h7 { 534 mux { 535 groups = "i2c1_sck_h7"; 536 function = "i2c1"; 537 bias-disable; 538 drive-strength-microamp = <3000>; 539 }; 540 }; 541 542 i2c2_sda_x_pins: i2c2-sda-x { 543 mux { 544 groups = "i2c2_sda_x"; 545 function = "i2c2"; 546 bias-disable; 547 drive-strength-microamp = <3000>; 548 }; 549 }; 550 551 i2c2_sck_x_pins: i2c2-sck-x { 552 mux { 553 groups = "i2c2_sck_x"; 554 function = "i2c2"; 555 bias-disable; 556 drive-strength-microamp = <3000>; 557 }; 558 }; 559 560 i2c2_sda_z_pins: i2c2-sda-z { 561 mux { 562 groups = "i2c2_sda_z"; 563 function = "i2c2"; 564 bias-disable; 565 drive-strength-microamp = <3000>; 566 }; 567 }; 568 569 i2c2_sck_z_pins: i2c2-sck-z { 570 mux { 571 groups = "i2c2_sck_z"; 572 function = "i2c2"; 573 bias-disable; 574 drive-strength-microamp = <3000>; 575 }; 576 }; 577 578 i2c3_sda_h_pins: i2c3-sda-h { 579 mux { 580 groups = "i2c3_sda_h"; 581 function = "i2c3"; 582 bias-disable; 583 drive-strength-microamp = <3000>; 584 }; 585 }; 586 587 i2c3_sck_h_pins: i2c3-sck-h { 588 mux { 589 groups = "i2c3_sck_h"; 590 function = "i2c3"; 591 bias-disable; 592 drive-strength-microamp = <3000>; 593 }; 594 }; 595 596 i2c3_sda_a_pins: i2c3-sda-a { 597 mux { 598 groups = "i2c3_sda_a"; 599 function = "i2c3"; 600 bias-disable; 601 drive-strength-microamp = <3000>; 602 }; 603 }; 604 605 i2c3_sck_a_pins: i2c3-sck-a { 606 mux { 607 groups = "i2c3_sck_a"; 608 function = "i2c3"; 609 bias-disable; 610 drive-strength-microamp = <3000>; 611 }; 612 }; 613 614 mclk0_a_pins: mclk0-a { 615 mux { 616 groups = "mclk0_a"; 617 function = "mclk0"; 618 bias-disable; 619 drive-strength-microamp = <3000>; 620 }; 621 }; 622 623 mclk1_a_pins: mclk1-a { 624 mux { 625 groups = "mclk1_a"; 626 function = "mclk1"; 627 bias-disable; 628 drive-strength-microamp = <3000>; 629 }; 630 }; 631 632 mclk1_x_pins: mclk1-x { 633 mux { 634 groups = "mclk1_x"; 635 function = "mclk1"; 636 bias-disable; 637 drive-strength-microamp = <3000>; 638 }; 639 }; 640 641 mclk1_z_pins: mclk1-z { 642 mux { 643 groups = "mclk1_z"; 644 function = "mclk1"; 645 bias-disable; 646 drive-strength-microamp = <3000>; 647 }; 648 }; 649 650 nor_pins: nor { 651 mux { 652 groups = "nor_d", 653 "nor_q", 654 "nor_c", 655 "nor_cs"; 656 function = "nor"; 657 bias-disable; 658 }; 659 }; 660 661 pdm_din0_a_pins: pdm-din0-a { 662 mux { 663 groups = "pdm_din0_a"; 664 function = "pdm"; 665 bias-disable; 666 }; 667 }; 668 669 pdm_din0_c_pins: pdm-din0-c { 670 mux { 671 groups = "pdm_din0_c"; 672 function = "pdm"; 673 bias-disable; 674 }; 675 }; 676 677 pdm_din0_x_pins: pdm-din0-x { 678 mux { 679 groups = "pdm_din0_x"; 680 function = "pdm"; 681 bias-disable; 682 }; 683 }; 684 685 pdm_din0_z_pins: pdm-din0-z { 686 mux { 687 groups = "pdm_din0_z"; 688 function = "pdm"; 689 bias-disable; 690 }; 691 }; 692 693 pdm_din1_a_pins: pdm-din1-a { 694 mux { 695 groups = "pdm_din1_a"; 696 function = "pdm"; 697 bias-disable; 698 }; 699 }; 700 701 pdm_din1_c_pins: pdm-din1-c { 702 mux { 703 groups = "pdm_din1_c"; 704 function = "pdm"; 705 bias-disable; 706 }; 707 }; 708 709 pdm_din1_x_pins: pdm-din1-x { 710 mux { 711 groups = "pdm_din1_x"; 712 function = "pdm"; 713 bias-disable; 714 }; 715 }; 716 717 pdm_din1_z_pins: pdm-din1-z { 718 mux { 719 groups = "pdm_din1_z"; 720 function = "pdm"; 721 bias-disable; 722 }; 723 }; 724 725 pdm_din2_a_pins: pdm-din2-a { 726 mux { 727 groups = "pdm_din2_a"; 728 function = "pdm"; 729 bias-disable; 730 }; 731 }; 732 733 pdm_din2_c_pins: pdm-din2-c { 734 mux { 735 groups = "pdm_din2_c"; 736 function = "pdm"; 737 bias-disable; 738 }; 739 }; 740 741 pdm_din2_x_pins: pdm-din2-x { 742 mux { 743 groups = "pdm_din2_x"; 744 function = "pdm"; 745 bias-disable; 746 }; 747 }; 748 749 pdm_din2_z_pins: pdm-din2-z { 750 mux { 751 groups = "pdm_din2_z"; 752 function = "pdm"; 753 bias-disable; 754 }; 755 }; 756 757 pdm_din3_a_pins: pdm-din3-a { 758 mux { 759 groups = "pdm_din3_a"; 760 function = "pdm"; 761 bias-disable; 762 }; 763 }; 764 765 pdm_din3_c_pins: pdm-din3-c { 766 mux { 767 groups = "pdm_din3_c"; 768 function = "pdm"; 769 bias-disable; 770 }; 771 }; 772 773 pdm_din3_x_pins: pdm-din3-x { 774 mux { 775 groups = "pdm_din3_x"; 776 function = "pdm"; 777 bias-disable; 778 }; 779 }; 780 781 pdm_din3_z_pins: pdm-din3-z { 782 mux { 783 groups = "pdm_din3_z"; 784 function = "pdm"; 785 bias-disable; 786 }; 787 }; 788 789 pdm_dclk_a_pins: pdm-dclk-a { 790 mux { 791 groups = "pdm_dclk_a"; 792 function = "pdm"; 793 bias-disable; 794 drive-strength-microamp = <500>; 795 }; 796 }; 797 798 pdm_dclk_c_pins: pdm-dclk-c { 799 mux { 800 groups = "pdm_dclk_c"; 801 function = "pdm"; 802 bias-disable; 803 drive-strength-microamp = <500>; 804 }; 805 }; 806 807 pdm_dclk_x_pins: pdm-dclk-x { 808 mux { 809 groups = "pdm_dclk_x"; 810 function = "pdm"; 811 bias-disable; 812 drive-strength-microamp = <500>; 813 }; 814 }; 815 816 pdm_dclk_z_pins: pdm-dclk-z { 817 mux { 818 groups = "pdm_dclk_z"; 819 function = "pdm"; 820 bias-disable; 821 drive-strength-microamp = <500>; 822 }; 823 }; 824 825 pwm_a_pins: pwm-a { 826 mux { 827 groups = "pwm_a"; 828 function = "pwm_a"; 829 bias-disable; 830 }; 831 }; 832 833 pwm_b_x7_pins: pwm-b-x7 { 834 mux { 835 groups = "pwm_b_x7"; 836 function = "pwm_b"; 837 bias-disable; 838 }; 839 }; 840 841 pwm_b_x19_pins: pwm-b-x19 { 842 mux { 843 groups = "pwm_b_x19"; 844 function = "pwm_b"; 845 bias-disable; 846 }; 847 }; 848 849 pwm_c_c_pins: pwm-c-c { 850 mux { 851 groups = "pwm_c_c"; 852 function = "pwm_c"; 853 bias-disable; 854 }; 855 }; 856 857 pwm_c_x5_pins: pwm-c-x5 { 858 mux { 859 groups = "pwm_c_x5"; 860 function = "pwm_c"; 861 bias-disable; 862 }; 863 }; 864 865 pwm_c_x8_pins: pwm-c-x8 { 866 mux { 867 groups = "pwm_c_x8"; 868 function = "pwm_c"; 869 bias-disable; 870 }; 871 }; 872 873 pwm_d_x3_pins: pwm-d-x3 { 874 mux { 875 groups = "pwm_d_x3"; 876 function = "pwm_d"; 877 bias-disable; 878 }; 879 }; 880 881 pwm_d_x6_pins: pwm-d-x6 { 882 mux { 883 groups = "pwm_d_x6"; 884 function = "pwm_d"; 885 bias-disable; 886 }; 887 }; 888 889 pwm_e_pins: pwm-e { 890 mux { 891 groups = "pwm_e"; 892 function = "pwm_e"; 893 bias-disable; 894 }; 895 }; 896 897 pwm_f_x_pins: pwm-f-x { 898 mux { 899 groups = "pwm_f_x"; 900 function = "pwm_f"; 901 bias-disable; 902 }; 903 }; 904 905 pwm_f_h_pins: pwm-f-h { 906 mux { 907 groups = "pwm_f_h"; 908 function = "pwm_f"; 909 bias-disable; 910 }; 911 }; 912 913 sdcard_c_pins: sdcard_c { 914 mux-0 { 915 groups = "sdcard_d0_c", 916 "sdcard_d1_c", 917 "sdcard_d2_c", 918 "sdcard_d3_c", 919 "sdcard_cmd_c"; 920 function = "sdcard"; 921 bias-pull-up; 922 drive-strength-microamp = <4000>; 923 }; 924 925 mux-1 { 926 groups = "sdcard_clk_c"; 927 function = "sdcard"; 928 bias-disable; 929 drive-strength-microamp = <4000>; 930 }; 931 }; 932 933 sdcard_clk_gate_c_pins: sdcard_clk_gate_c { 934 mux { 935 groups = "GPIOC_4"; 936 function = "gpio_periphs"; 937 bias-pull-down; 938 drive-strength-microamp = <4000>; 939 }; 940 }; 941 942 sdcard_z_pins: sdcard_z { 943 mux-0 { 944 groups = "sdcard_d0_z", 945 "sdcard_d1_z", 946 "sdcard_d2_z", 947 "sdcard_d3_z", 948 "sdcard_cmd_z"; 949 function = "sdcard"; 950 bias-pull-up; 951 drive-strength-microamp = <4000>; 952 }; 953 954 mux-1 { 955 groups = "sdcard_clk_z"; 956 function = "sdcard"; 957 bias-disable; 958 drive-strength-microamp = <4000>; 959 }; 960 }; 961 962 sdcard_clk_gate_z_pins: sdcard_clk_gate_z { 963 mux { 964 groups = "GPIOZ_6"; 965 function = "gpio_periphs"; 966 bias-pull-down; 967 drive-strength-microamp = <4000>; 968 }; 969 }; 970 971 sdio_pins: sdio { 972 mux { 973 groups = "sdio_d0", 974 "sdio_d1", 975 "sdio_d2", 976 "sdio_d3", 977 "sdio_clk", 978 "sdio_cmd"; 979 function = "sdio"; 980 bias-disable; 981 drive-strength-microamp = <4000>; 982 }; 983 }; 984 985 sdio_clk_gate_pins: sdio_clk_gate { 986 mux { 987 groups = "GPIOX_4"; 988 function = "gpio_periphs"; 989 bias-pull-down; 990 drive-strength-microamp = <4000>; 991 }; 992 }; 993 994 spdif_in_a10_pins: spdif-in-a10 { 995 mux { 996 groups = "spdif_in_a10"; 997 function = "spdif_in"; 998 bias-disable; 999 }; 1000 }; 1001 1002 spdif_in_a12_pins: spdif-in-a12 { 1003 mux { 1004 groups = "spdif_in_a12"; 1005 function = "spdif_in"; 1006 bias-disable; 1007 }; 1008 }; 1009 1010 spdif_in_h_pins: spdif-in-h { 1011 mux { 1012 groups = "spdif_in_h"; 1013 function = "spdif_in"; 1014 bias-disable; 1015 }; 1016 }; 1017 1018 spdif_out_h_pins: spdif-out-h { 1019 mux { 1020 groups = "spdif_out_h"; 1021 function = "spdif_out"; 1022 drive-strength-microamp = <500>; 1023 bias-disable; 1024 }; 1025 }; 1026 1027 spdif_out_a11_pins: spdif-out-a11 { 1028 mux { 1029 groups = "spdif_out_a11"; 1030 function = "spdif_out"; 1031 drive-strength-microamp = <500>; 1032 bias-disable; 1033 }; 1034 }; 1035 1036 spdif_out_a13_pins: spdif-out-a13 { 1037 mux { 1038 groups = "spdif_out_a13"; 1039 function = "spdif_out"; 1040 drive-strength-microamp = <500>; 1041 bias-disable; 1042 }; 1043 }; 1044 1045 spicc0_x_pins: spicc0-x { 1046 mux { 1047 groups = "spi0_mosi_x", 1048 "spi0_miso_x", 1049 "spi0_clk_x"; 1050 function = "spi0"; 1051 drive-strength-microamp = <4000>; 1052 bias-disable; 1053 }; 1054 }; 1055 1056 spicc0_ss0_x_pins: spicc0-ss0-x { 1057 mux { 1058 groups = "spi0_ss0_x"; 1059 function = "spi0"; 1060 drive-strength-microamp = <4000>; 1061 bias-disable; 1062 }; 1063 }; 1064 1065 spicc0_c_pins: spicc0-c { 1066 mux { 1067 groups = "spi0_mosi_c", 1068 "spi0_miso_c", 1069 "spi0_ss0_c", 1070 "spi0_clk_c"; 1071 function = "spi0"; 1072 drive-strength-microamp = <4000>; 1073 bias-disable; 1074 }; 1075 }; 1076 1077 spicc1_pins: spicc1 { 1078 mux { 1079 groups = "spi1_mosi", 1080 "spi1_miso", 1081 "spi1_clk"; 1082 function = "spi1"; 1083 drive-strength-microamp = <4000>; 1084 }; 1085 }; 1086 1087 spicc1_ss0_pins: spicc1-ss0 { 1088 mux { 1089 groups = "spi1_ss0"; 1090 function = "spi1"; 1091 drive-strength-microamp = <4000>; 1092 bias-disable; 1093 }; 1094 }; 1095 1096 tdm_a_din0_pins: tdm-a-din0 { 1097 mux { 1098 groups = "tdm_a_din0"; 1099 function = "tdm_a"; 1100 bias-disable; 1101 }; 1102 }; 1103 1104 1105 tdm_a_din1_pins: tdm-a-din1 { 1106 mux { 1107 groups = "tdm_a_din1"; 1108 function = "tdm_a"; 1109 bias-disable; 1110 }; 1111 }; 1112 1113 tdm_a_dout0_pins: tdm-a-dout0 { 1114 mux { 1115 groups = "tdm_a_dout0"; 1116 function = "tdm_a"; 1117 bias-disable; 1118 drive-strength-microamp = <3000>; 1119 }; 1120 }; 1121 1122 tdm_a_dout1_pins: tdm-a-dout1 { 1123 mux { 1124 groups = "tdm_a_dout1"; 1125 function = "tdm_a"; 1126 bias-disable; 1127 drive-strength-microamp = <3000>; 1128 }; 1129 }; 1130 1131 tdm_a_fs_pins: tdm-a-fs { 1132 mux { 1133 groups = "tdm_a_fs"; 1134 function = "tdm_a"; 1135 bias-disable; 1136 drive-strength-microamp = <3000>; 1137 }; 1138 }; 1139 1140 tdm_a_sclk_pins: tdm-a-sclk { 1141 mux { 1142 groups = "tdm_a_sclk"; 1143 function = "tdm_a"; 1144 bias-disable; 1145 drive-strength-microamp = <3000>; 1146 }; 1147 }; 1148 1149 tdm_a_slv_fs_pins: tdm-a-slv-fs { 1150 mux { 1151 groups = "tdm_a_slv_fs"; 1152 function = "tdm_a"; 1153 bias-disable; 1154 }; 1155 }; 1156 1157 1158 tdm_a_slv_sclk_pins: tdm-a-slv-sclk { 1159 mux { 1160 groups = "tdm_a_slv_sclk"; 1161 function = "tdm_a"; 1162 bias-disable; 1163 }; 1164 }; 1165 1166 tdm_b_din0_pins: tdm-b-din0 { 1167 mux { 1168 groups = "tdm_b_din0"; 1169 function = "tdm_b"; 1170 bias-disable; 1171 }; 1172 }; 1173 1174 tdm_b_din1_pins: tdm-b-din1 { 1175 mux { 1176 groups = "tdm_b_din1"; 1177 function = "tdm_b"; 1178 bias-disable; 1179 }; 1180 }; 1181 1182 tdm_b_din2_pins: tdm-b-din2 { 1183 mux { 1184 groups = "tdm_b_din2"; 1185 function = "tdm_b"; 1186 bias-disable; 1187 }; 1188 }; 1189 1190 tdm_b_din3_a_pins: tdm-b-din3-a { 1191 mux { 1192 groups = "tdm_b_din3_a"; 1193 function = "tdm_b"; 1194 bias-disable; 1195 }; 1196 }; 1197 1198 tdm_b_din3_h_pins: tdm-b-din3-h { 1199 mux { 1200 groups = "tdm_b_din3_h"; 1201 function = "tdm_b"; 1202 bias-disable; 1203 }; 1204 }; 1205 1206 tdm_b_dout0_pins: tdm-b-dout0 { 1207 mux { 1208 groups = "tdm_b_dout0"; 1209 function = "tdm_b"; 1210 bias-disable; 1211 drive-strength-microamp = <3000>; 1212 }; 1213 }; 1214 1215 tdm_b_dout1_pins: tdm-b-dout1 { 1216 mux { 1217 groups = "tdm_b_dout1"; 1218 function = "tdm_b"; 1219 bias-disable; 1220 drive-strength-microamp = <3000>; 1221 }; 1222 }; 1223 1224 tdm_b_dout2_pins: tdm-b-dout2 { 1225 mux { 1226 groups = "tdm_b_dout2"; 1227 function = "tdm_b"; 1228 bias-disable; 1229 drive-strength-microamp = <3000>; 1230 }; 1231 }; 1232 1233 tdm_b_dout3_a_pins: tdm-b-dout3-a { 1234 mux { 1235 groups = "tdm_b_dout3_a"; 1236 function = "tdm_b"; 1237 bias-disable; 1238 drive-strength-microamp = <3000>; 1239 }; 1240 }; 1241 1242 tdm_b_dout3_h_pins: tdm-b-dout3-h { 1243 mux { 1244 groups = "tdm_b_dout3_h"; 1245 function = "tdm_b"; 1246 bias-disable; 1247 drive-strength-microamp = <3000>; 1248 }; 1249 }; 1250 1251 tdm_b_fs_pins: tdm-b-fs { 1252 mux { 1253 groups = "tdm_b_fs"; 1254 function = "tdm_b"; 1255 bias-disable; 1256 drive-strength-microamp = <3000>; 1257 }; 1258 }; 1259 1260 tdm_b_sclk_pins: tdm-b-sclk { 1261 mux { 1262 groups = "tdm_b_sclk"; 1263 function = "tdm_b"; 1264 bias-disable; 1265 drive-strength-microamp = <3000>; 1266 }; 1267 }; 1268 1269 tdm_b_slv_fs_pins: tdm-b-slv-fs { 1270 mux { 1271 groups = "tdm_b_slv_fs"; 1272 function = "tdm_b"; 1273 bias-disable; 1274 }; 1275 }; 1276 1277 tdm_b_slv_sclk_pins: tdm-b-slv-sclk { 1278 mux { 1279 groups = "tdm_b_slv_sclk"; 1280 function = "tdm_b"; 1281 bias-disable; 1282 }; 1283 }; 1284 1285 tdm_c_din0_a_pins: tdm-c-din0-a { 1286 mux { 1287 groups = "tdm_c_din0_a"; 1288 function = "tdm_c"; 1289 bias-disable; 1290 }; 1291 }; 1292 1293 tdm_c_din0_z_pins: tdm-c-din0-z { 1294 mux { 1295 groups = "tdm_c_din0_z"; 1296 function = "tdm_c"; 1297 bias-disable; 1298 }; 1299 }; 1300 1301 tdm_c_din1_a_pins: tdm-c-din1-a { 1302 mux { 1303 groups = "tdm_c_din1_a"; 1304 function = "tdm_c"; 1305 bias-disable; 1306 }; 1307 }; 1308 1309 tdm_c_din1_z_pins: tdm-c-din1-z { 1310 mux { 1311 groups = "tdm_c_din1_z"; 1312 function = "tdm_c"; 1313 bias-disable; 1314 }; 1315 }; 1316 1317 tdm_c_din2_a_pins: tdm-c-din2-a { 1318 mux { 1319 groups = "tdm_c_din2_a"; 1320 function = "tdm_c"; 1321 bias-disable; 1322 }; 1323 }; 1324 1325 eth_leds_pins: eth-leds { 1326 mux { 1327 groups = "eth_link_led", 1328 "eth_act_led"; 1329 function = "eth"; 1330 bias-disable; 1331 }; 1332 }; 1333 1334 eth_pins: eth { 1335 mux { 1336 groups = "eth_mdio", 1337 "eth_mdc", 1338 "eth_rgmii_rx_clk", 1339 "eth_rx_dv", 1340 "eth_rxd0", 1341 "eth_rxd1", 1342 "eth_txen", 1343 "eth_txd0", 1344 "eth_txd1"; 1345 function = "eth"; 1346 drive-strength-microamp = <4000>; 1347 bias-disable; 1348 }; 1349 }; 1350 1351 eth_rgmii_pins: eth-rgmii { 1352 mux { 1353 groups = "eth_rxd2_rgmii", 1354 "eth_rxd3_rgmii", 1355 "eth_rgmii_tx_clk", 1356 "eth_txd2_rgmii", 1357 "eth_txd3_rgmii"; 1358 function = "eth"; 1359 drive-strength-microamp = <4000>; 1360 bias-disable; 1361 }; 1362 }; 1363 1364 tdm_c_din2_z_pins: tdm-c-din2-z { 1365 mux { 1366 groups = "tdm_c_din2_z"; 1367 function = "tdm_c"; 1368 bias-disable; 1369 }; 1370 }; 1371 1372 tdm_c_din3_a_pins: tdm-c-din3-a { 1373 mux { 1374 groups = "tdm_c_din3_a"; 1375 function = "tdm_c"; 1376 bias-disable; 1377 }; 1378 }; 1379 1380 tdm_c_din3_z_pins: tdm-c-din3-z { 1381 mux { 1382 groups = "tdm_c_din3_z"; 1383 function = "tdm_c"; 1384 bias-disable; 1385 }; 1386 }; 1387 1388 tdm_c_dout0_a_pins: tdm-c-dout0-a { 1389 mux { 1390 groups = "tdm_c_dout0_a"; 1391 function = "tdm_c"; 1392 bias-disable; 1393 drive-strength-microamp = <3000>; 1394 }; 1395 }; 1396 1397 tdm_c_dout0_z_pins: tdm-c-dout0-z { 1398 mux { 1399 groups = "tdm_c_dout0_z"; 1400 function = "tdm_c"; 1401 bias-disable; 1402 drive-strength-microamp = <3000>; 1403 }; 1404 }; 1405 1406 tdm_c_dout1_a_pins: tdm-c-dout1-a { 1407 mux { 1408 groups = "tdm_c_dout1_a"; 1409 function = "tdm_c"; 1410 bias-disable; 1411 drive-strength-microamp = <3000>; 1412 }; 1413 }; 1414 1415 tdm_c_dout1_z_pins: tdm-c-dout1-z { 1416 mux { 1417 groups = "tdm_c_dout1_z"; 1418 function = "tdm_c"; 1419 bias-disable; 1420 drive-strength-microamp = <3000>; 1421 }; 1422 }; 1423 1424 tdm_c_dout2_a_pins: tdm-c-dout2-a { 1425 mux { 1426 groups = "tdm_c_dout2_a"; 1427 function = "tdm_c"; 1428 bias-disable; 1429 drive-strength-microamp = <3000>; 1430 }; 1431 }; 1432 1433 tdm_c_dout2_z_pins: tdm-c-dout2-z { 1434 mux { 1435 groups = "tdm_c_dout2_z"; 1436 function = "tdm_c"; 1437 bias-disable; 1438 drive-strength-microamp = <3000>; 1439 }; 1440 }; 1441 1442 tdm_c_dout3_a_pins: tdm-c-dout3-a { 1443 mux { 1444 groups = "tdm_c_dout3_a"; 1445 function = "tdm_c"; 1446 bias-disable; 1447 drive-strength-microamp = <3000>; 1448 }; 1449 }; 1450 1451 tdm_c_dout3_z_pins: tdm-c-dout3-z { 1452 mux { 1453 groups = "tdm_c_dout3_z"; 1454 function = "tdm_c"; 1455 bias-disable; 1456 drive-strength-microamp = <3000>; 1457 }; 1458 }; 1459 1460 tdm_c_fs_a_pins: tdm-c-fs-a { 1461 mux { 1462 groups = "tdm_c_fs_a"; 1463 function = "tdm_c"; 1464 bias-disable; 1465 drive-strength-microamp = <3000>; 1466 }; 1467 }; 1468 1469 tdm_c_fs_z_pins: tdm-c-fs-z { 1470 mux { 1471 groups = "tdm_c_fs_z"; 1472 function = "tdm_c"; 1473 bias-disable; 1474 drive-strength-microamp = <3000>; 1475 }; 1476 }; 1477 1478 tdm_c_sclk_a_pins: tdm-c-sclk-a { 1479 mux { 1480 groups = "tdm_c_sclk_a"; 1481 function = "tdm_c"; 1482 bias-disable; 1483 drive-strength-microamp = <3000>; 1484 }; 1485 }; 1486 1487 tdm_c_sclk_z_pins: tdm-c-sclk-z { 1488 mux { 1489 groups = "tdm_c_sclk_z"; 1490 function = "tdm_c"; 1491 bias-disable; 1492 drive-strength-microamp = <3000>; 1493 }; 1494 }; 1495 1496 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { 1497 mux { 1498 groups = "tdm_c_slv_fs_a"; 1499 function = "tdm_c"; 1500 bias-disable; 1501 }; 1502 }; 1503 1504 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { 1505 mux { 1506 groups = "tdm_c_slv_fs_z"; 1507 function = "tdm_c"; 1508 bias-disable; 1509 }; 1510 }; 1511 1512 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { 1513 mux { 1514 groups = "tdm_c_slv_sclk_a"; 1515 function = "tdm_c"; 1516 bias-disable; 1517 }; 1518 }; 1519 1520 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { 1521 mux { 1522 groups = "tdm_c_slv_sclk_z"; 1523 function = "tdm_c"; 1524 bias-disable; 1525 }; 1526 }; 1527 1528 uart_a_pins: uart-a { 1529 mux { 1530 groups = "uart_a_tx", 1531 "uart_a_rx"; 1532 function = "uart_a"; 1533 bias-disable; 1534 }; 1535 }; 1536 1537 uart_a_cts_rts_pins: uart-a-cts-rts { 1538 mux { 1539 groups = "uart_a_cts", 1540 "uart_a_rts"; 1541 function = "uart_a"; 1542 bias-disable; 1543 }; 1544 }; 1545 1546 uart_b_pins: uart-b { 1547 mux { 1548 groups = "uart_b_tx", 1549 "uart_b_rx"; 1550 function = "uart_b"; 1551 bias-disable; 1552 }; 1553 }; 1554 1555 uart_c_pins: uart-c { 1556 mux { 1557 groups = "uart_c_tx", 1558 "uart_c_rx"; 1559 function = "uart_c"; 1560 bias-disable; 1561 }; 1562 }; 1563 1564 uart_c_cts_rts_pins: uart-c-cts-rts { 1565 mux { 1566 groups = "uart_c_cts", 1567 "uart_c_rts"; 1568 function = "uart_c"; 1569 bias-disable; 1570 }; 1571 }; 1572 }; 1573 }; 1574 1575 cpu_temp: temperature-sensor@34800 { 1576 compatible = "amlogic,g12a-cpu-thermal", 1577 "amlogic,g12a-thermal"; 1578 reg = <0x0 0x34800 0x0 0x50>; 1579 interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>; 1580 clocks = <&clkc CLKID_TS>; 1581 #thermal-sensor-cells = <0>; 1582 amlogic,ao-secure = <&sec_AO>; 1583 }; 1584 1585 ddr_temp: temperature-sensor@34c00 { 1586 compatible = "amlogic,g12a-ddr-thermal", 1587 "amlogic,g12a-thermal"; 1588 reg = <0x0 0x34c00 0x0 0x50>; 1589 interrupts = <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>; 1590 clocks = <&clkc CLKID_TS>; 1591 #thermal-sensor-cells = <0>; 1592 amlogic,ao-secure = <&sec_AO>; 1593 }; 1594 1595 usb2_phy0: phy@36000 { 1596 compatible = "amlogic,g12a-usb2-phy"; 1597 reg = <0x0 0x36000 0x0 0x2000>; 1598 clocks = <&xtal>; 1599 clock-names = "xtal"; 1600 resets = <&reset RESET_USB_PHY20>; 1601 reset-names = "phy"; 1602 #phy-cells = <0>; 1603 }; 1604 1605 dmc: bus@38000 { 1606 compatible = "simple-bus"; 1607 reg = <0x0 0x38000 0x0 0x400>; 1608 #address-cells = <2>; 1609 #size-cells = <2>; 1610 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; 1611 1612 canvas: video-lut@48 { 1613 compatible = "amlogic,canvas"; 1614 reg = <0x0 0x48 0x0 0x14>; 1615 }; 1616 }; 1617 1618 usb2_phy1: phy@3a000 { 1619 compatible = "amlogic,g12a-usb2-phy"; 1620 reg = <0x0 0x3a000 0x0 0x2000>; 1621 clocks = <&xtal>; 1622 clock-names = "xtal"; 1623 resets = <&reset RESET_USB_PHY21>; 1624 reset-names = "phy"; 1625 #phy-cells = <0>; 1626 }; 1627 1628 hiu: bus@3c000 { 1629 compatible = "simple-bus"; 1630 reg = <0x0 0x3c000 0x0 0x1400>; 1631 #address-cells = <2>; 1632 #size-cells = <2>; 1633 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 1634 1635 hhi: system-controller@0 { 1636 compatible = "amlogic,meson-gx-hhi-sysctrl", 1637 "simple-mfd", "syscon"; 1638 reg = <0 0 0 0x400>; 1639 1640 clkc: clock-controller { 1641 compatible = "amlogic,g12a-clkc"; 1642 #clock-cells = <1>; 1643 clocks = <&xtal>; 1644 clock-names = "xtal"; 1645 }; 1646 1647 pwrc: power-controller { 1648 compatible = "amlogic,meson-g12a-pwrc"; 1649 #power-domain-cells = <1>; 1650 amlogic,ao-sysctrl = <&rti>; 1651 resets = <&reset RESET_VIU>, 1652 <&reset RESET_VENC>, 1653 <&reset RESET_VCBUS>, 1654 <&reset RESET_BT656>, 1655 <&reset RESET_RDMA>, 1656 <&reset RESET_VENCI>, 1657 <&reset RESET_VENCP>, 1658 <&reset RESET_VDAC>, 1659 <&reset RESET_VDI6>, 1660 <&reset RESET_VENCL>, 1661 <&reset RESET_VID_LOCK>; 1662 reset-names = "viu", "venc", "vcbus", "bt656", 1663 "rdma", "venci", "vencp", "vdac", 1664 "vdi6", "vencl", "vid_lock"; 1665 clocks = <&clkc CLKID_VPU>, 1666 <&clkc CLKID_VAPB>; 1667 clock-names = "vpu", "vapb"; 1668 /* 1669 * VPU clocking is provided by two identical clock paths 1670 * VPU_0 and VPU_1 muxed to a single clock by a glitch 1671 * free mux to safely change frequency while running. 1672 * Same for VAPB but with a final gate after the glitch free mux. 1673 */ 1674 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 1675 <&clkc CLKID_VPU_0>, 1676 <&clkc CLKID_VPU>, /* Glitch free mux */ 1677 <&clkc CLKID_VAPB_0_SEL>, 1678 <&clkc CLKID_VAPB_0>, 1679 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 1680 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 1681 <0>, /* Do Nothing */ 1682 <&clkc CLKID_VPU_0>, 1683 <&clkc CLKID_FCLK_DIV4>, 1684 <0>, /* Do Nothing */ 1685 <&clkc CLKID_VAPB_0>; 1686 assigned-clock-rates = <0>, /* Do Nothing */ 1687 <666666666>, 1688 <0>, /* Do Nothing */ 1689 <0>, /* Do Nothing */ 1690 <250000000>, 1691 <0>; /* Do Nothing */ 1692 }; 1693 }; 1694 }; 1695 1696 usb3_pcie_phy: phy@46000 { 1697 compatible = "amlogic,g12a-usb3-pcie-phy"; 1698 reg = <0x0 0x46000 0x0 0x2000>; 1699 clocks = <&clkc CLKID_PCIE_PLL>; 1700 clock-names = "ref_clk"; 1701 resets = <&reset RESET_PCIE_PHY>; 1702 reset-names = "phy"; 1703 assigned-clocks = <&clkc CLKID_PCIE_PLL>; 1704 assigned-clock-rates = <100000000>; 1705 #phy-cells = <1>; 1706 }; 1707 1708 eth_phy: mdio-multiplexer@4c000 { 1709 compatible = "amlogic,g12a-mdio-mux"; 1710 reg = <0x0 0x4c000 0x0 0xa4>; 1711 clocks = <&clkc CLKID_ETH_PHY>, 1712 <&xtal>, 1713 <&clkc CLKID_MPLL_50M>; 1714 clock-names = "pclk", "clkin0", "clkin1"; 1715 mdio-parent-bus = <&mdio0>; 1716 #address-cells = <1>; 1717 #size-cells = <0>; 1718 1719 ext_mdio: mdio@0 { 1720 reg = <0>; 1721 #address-cells = <1>; 1722 #size-cells = <0>; 1723 }; 1724 1725 int_mdio: mdio@1 { 1726 reg = <1>; 1727 #address-cells = <1>; 1728 #size-cells = <0>; 1729 1730 internal_ephy: ethernet_phy@8 { 1731 compatible = "ethernet-phy-id0180.3301", 1732 "ethernet-phy-ieee802.3-c22"; 1733 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1734 reg = <8>; 1735 max-speed = <100>; 1736 }; 1737 }; 1738 }; 1739 }; 1740 1741 aobus: bus@ff800000 { 1742 compatible = "simple-bus"; 1743 reg = <0x0 0xff800000 0x0 0x100000>; 1744 #address-cells = <2>; 1745 #size-cells = <2>; 1746 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1747 1748 rti: sys-ctrl@0 { 1749 compatible = "amlogic,meson-gx-ao-sysctrl", 1750 "simple-mfd", "syscon"; 1751 reg = <0x0 0x0 0x0 0x100>; 1752 #address-cells = <2>; 1753 #size-cells = <2>; 1754 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 1755 1756 clkc_AO: clock-controller { 1757 compatible = "amlogic,meson-g12a-aoclkc"; 1758 #clock-cells = <1>; 1759 #reset-cells = <1>; 1760 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1761 clock-names = "xtal", "mpeg-clk"; 1762 }; 1763 1764 ao_pinctrl: pinctrl@14 { 1765 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 1766 #address-cells = <2>; 1767 #size-cells = <2>; 1768 ranges; 1769 1770 gpio_ao: bank@14 { 1771 reg = <0x0 0x14 0x0 0x8>, 1772 <0x0 0x1c 0x0 0x8>, 1773 <0x0 0x24 0x0 0x14>; 1774 reg-names = "mux", 1775 "ds", 1776 "gpio"; 1777 gpio-controller; 1778 #gpio-cells = <2>; 1779 gpio-ranges = <&ao_pinctrl 0 0 15>; 1780 }; 1781 1782 i2c_ao_sck_pins: i2c_ao_sck_pins { 1783 mux { 1784 groups = "i2c_ao_sck"; 1785 function = "i2c_ao"; 1786 bias-disable; 1787 drive-strength-microamp = <3000>; 1788 }; 1789 }; 1790 1791 i2c_ao_sda_pins: i2c_ao_sda { 1792 mux { 1793 groups = "i2c_ao_sda"; 1794 function = "i2c_ao"; 1795 bias-disable; 1796 drive-strength-microamp = <3000>; 1797 }; 1798 }; 1799 1800 i2c_ao_sck_e_pins: i2c_ao_sck_e { 1801 mux { 1802 groups = "i2c_ao_sck_e"; 1803 function = "i2c_ao"; 1804 bias-disable; 1805 drive-strength-microamp = <3000>; 1806 }; 1807 }; 1808 1809 i2c_ao_sda_e_pins: i2c_ao_sda_e { 1810 mux { 1811 groups = "i2c_ao_sda_e"; 1812 function = "i2c_ao"; 1813 bias-disable; 1814 drive-strength-microamp = <3000>; 1815 }; 1816 }; 1817 1818 mclk0_ao_pins: mclk0-ao { 1819 mux { 1820 groups = "mclk0_ao"; 1821 function = "mclk0_ao"; 1822 bias-disable; 1823 drive-strength-microamp = <3000>; 1824 }; 1825 }; 1826 1827 tdm_ao_b_din0_pins: tdm-ao-b-din0 { 1828 mux { 1829 groups = "tdm_ao_b_din0"; 1830 function = "tdm_ao_b"; 1831 bias-disable; 1832 }; 1833 }; 1834 1835 spdif_ao_out_pins: spdif-ao-out { 1836 mux { 1837 groups = "spdif_ao_out"; 1838 function = "spdif_ao_out"; 1839 drive-strength-microamp = <500>; 1840 bias-disable; 1841 }; 1842 }; 1843 1844 tdm_ao_b_din1_pins: tdm-ao-b-din1 { 1845 mux { 1846 groups = "tdm_ao_b_din1"; 1847 function = "tdm_ao_b"; 1848 bias-disable; 1849 }; 1850 }; 1851 1852 tdm_ao_b_din2_pins: tdm-ao-b-din2 { 1853 mux { 1854 groups = "tdm_ao_b_din2"; 1855 function = "tdm_ao_b"; 1856 bias-disable; 1857 }; 1858 }; 1859 1860 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { 1861 mux { 1862 groups = "tdm_ao_b_dout0"; 1863 function = "tdm_ao_b"; 1864 bias-disable; 1865 drive-strength-microamp = <3000>; 1866 }; 1867 }; 1868 1869 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { 1870 mux { 1871 groups = "tdm_ao_b_dout1"; 1872 function = "tdm_ao_b"; 1873 bias-disable; 1874 drive-strength-microamp = <3000>; 1875 }; 1876 }; 1877 1878 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { 1879 mux { 1880 groups = "tdm_ao_b_dout2"; 1881 function = "tdm_ao_b"; 1882 bias-disable; 1883 drive-strength-microamp = <3000>; 1884 }; 1885 }; 1886 1887 tdm_ao_b_fs_pins: tdm-ao-b-fs { 1888 mux { 1889 groups = "tdm_ao_b_fs"; 1890 function = "tdm_ao_b"; 1891 bias-disable; 1892 drive-strength-microamp = <3000>; 1893 }; 1894 }; 1895 1896 tdm_ao_b_sclk_pins: tdm-ao-b-sclk { 1897 mux { 1898 groups = "tdm_ao_b_sclk"; 1899 function = "tdm_ao_b"; 1900 bias-disable; 1901 drive-strength-microamp = <3000>; 1902 }; 1903 }; 1904 1905 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { 1906 mux { 1907 groups = "tdm_ao_b_slv_fs"; 1908 function = "tdm_ao_b"; 1909 bias-disable; 1910 }; 1911 }; 1912 1913 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { 1914 mux { 1915 groups = "tdm_ao_b_slv_sclk"; 1916 function = "tdm_ao_b"; 1917 bias-disable; 1918 }; 1919 }; 1920 1921 uart_ao_a_pins: uart-a-ao { 1922 mux { 1923 groups = "uart_ao_a_tx", 1924 "uart_ao_a_rx"; 1925 function = "uart_ao_a"; 1926 bias-disable; 1927 }; 1928 }; 1929 1930 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 1931 mux { 1932 groups = "uart_ao_a_cts", 1933 "uart_ao_a_rts"; 1934 function = "uart_ao_a"; 1935 bias-disable; 1936 }; 1937 }; 1938 1939 pwm_a_e_pins: pwm-a-e { 1940 mux { 1941 groups = "pwm_a_e"; 1942 function = "pwm_a_e"; 1943 bias-disable; 1944 }; 1945 }; 1946 1947 pwm_ao_a_pins: pwm-ao-a { 1948 mux { 1949 groups = "pwm_ao_a"; 1950 function = "pwm_ao_a"; 1951 bias-disable; 1952 }; 1953 }; 1954 1955 pwm_ao_b_pins: pwm-ao-b { 1956 mux { 1957 groups = "pwm_ao_b"; 1958 function = "pwm_ao_b"; 1959 bias-disable; 1960 }; 1961 }; 1962 1963 pwm_ao_c_4_pins: pwm-ao-c-4 { 1964 mux { 1965 groups = "pwm_ao_c_4"; 1966 function = "pwm_ao_c"; 1967 bias-disable; 1968 }; 1969 }; 1970 1971 pwm_ao_c_6_pins: pwm-ao-c-6 { 1972 mux { 1973 groups = "pwm_ao_c_6"; 1974 function = "pwm_ao_c"; 1975 bias-disable; 1976 }; 1977 }; 1978 1979 pwm_ao_d_5_pins: pwm-ao-d-5 { 1980 mux { 1981 groups = "pwm_ao_d_5"; 1982 function = "pwm_ao_d"; 1983 bias-disable; 1984 }; 1985 }; 1986 1987 pwm_ao_d_10_pins: pwm-ao-d-10 { 1988 mux { 1989 groups = "pwm_ao_d_10"; 1990 function = "pwm_ao_d"; 1991 bias-disable; 1992 }; 1993 }; 1994 1995 pwm_ao_d_e_pins: pwm-ao-d-e { 1996 mux { 1997 groups = "pwm_ao_d_e"; 1998 function = "pwm_ao_d"; 1999 }; 2000 }; 2001 2002 remote_input_ao_pins: remote-input-ao { 2003 mux { 2004 groups = "remote_ao_input"; 2005 function = "remote_ao_input"; 2006 bias-disable; 2007 }; 2008 }; 2009 }; 2010 }; 2011 2012 vrtc: rtc@a8 { 2013 compatible = "amlogic,meson-vrtc"; 2014 reg = <0x0 0x000a8 0x0 0x4>; 2015 }; 2016 2017 cec_AO: cec@100 { 2018 compatible = "amlogic,meson-gx-ao-cec"; 2019 reg = <0x0 0x00100 0x0 0x14>; 2020 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 2021 clocks = <&clkc_AO CLKID_AO_CEC>; 2022 clock-names = "core"; 2023 status = "disabled"; 2024 }; 2025 2026 sec_AO: ao-secure@140 { 2027 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 2028 reg = <0x0 0x140 0x0 0x140>; 2029 amlogic,has-chip-id; 2030 }; 2031 2032 cecb_AO: cec@280 { 2033 compatible = "amlogic,meson-g12a-ao-cec"; 2034 reg = <0x0 0x00280 0x0 0x1c>; 2035 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 2036 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; 2037 clock-names = "oscin"; 2038 status = "disabled"; 2039 }; 2040 2041 pwm_AO_cd: pwm@2000 { 2042 compatible = "amlogic,meson-g12a-ao-pwm-cd"; 2043 reg = <0x0 0x2000 0x0 0x20>; 2044 #pwm-cells = <3>; 2045 status = "disabled"; 2046 }; 2047 2048 uart_AO: serial@3000 { 2049 compatible = "amlogic,meson-gx-uart", 2050 "amlogic,meson-ao-uart"; 2051 reg = <0x0 0x3000 0x0 0x18>; 2052 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 2053 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; 2054 clock-names = "xtal", "pclk", "baud"; 2055 status = "disabled"; 2056 }; 2057 2058 uart_AO_B: serial@4000 { 2059 compatible = "amlogic,meson-gx-uart", 2060 "amlogic,meson-ao-uart"; 2061 reg = <0x0 0x4000 0x0 0x18>; 2062 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 2063 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 2064 clock-names = "xtal", "pclk", "baud"; 2065 status = "disabled"; 2066 }; 2067 2068 i2c_AO: i2c@5000 { 2069 compatible = "amlogic,meson-axg-i2c"; 2070 status = "disabled"; 2071 reg = <0x0 0x05000 0x0 0x20>; 2072 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 2073 #address-cells = <1>; 2074 #size-cells = <0>; 2075 clocks = <&clkc CLKID_I2C>; 2076 }; 2077 2078 pwm_AO_ab: pwm@7000 { 2079 compatible = "amlogic,meson-g12a-ao-pwm-ab"; 2080 reg = <0x0 0x7000 0x0 0x20>; 2081 #pwm-cells = <3>; 2082 status = "disabled"; 2083 }; 2084 2085 ir: ir@8000 { 2086 compatible = "amlogic,meson-gxbb-ir"; 2087 reg = <0x0 0x8000 0x0 0x20>; 2088 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 2089 status = "disabled"; 2090 }; 2091 2092 saradc: adc@9000 { 2093 compatible = "amlogic,meson-g12a-saradc", 2094 "amlogic,meson-saradc"; 2095 reg = <0x0 0x9000 0x0 0x48>; 2096 #io-channel-cells = <1>; 2097 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 2098 clocks = <&xtal>, 2099 <&clkc_AO CLKID_AO_SAR_ADC>, 2100 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 2101 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 2102 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 2103 status = "disabled"; 2104 }; 2105 }; 2106 2107 vdec: video-decoder@ff620000 { 2108 compatible = "amlogic,g12a-vdec"; 2109 reg = <0x0 0xff620000 0x0 0x10000>, 2110 <0x0 0xffd0e180 0x0 0xe4>; 2111 reg-names = "dos", "esparser"; 2112 interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 2113 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>; 2114 interrupt-names = "vdec", "esparser"; 2115 2116 amlogic,ao-sysctrl = <&rti>; 2117 amlogic,canvas = <&canvas>; 2118 2119 clocks = <&clkc CLKID_PARSER>, 2120 <&clkc CLKID_DOS>, 2121 <&clkc CLKID_VDEC_1>, 2122 <&clkc CLKID_VDEC_HEVC>, 2123 <&clkc CLKID_VDEC_HEVCF>; 2124 clock-names = "dos_parser", "dos", "vdec_1", 2125 "vdec_hevc", "vdec_hevcf"; 2126 resets = <&reset RESET_PARSER>; 2127 reset-names = "esparser"; 2128 }; 2129 2130 vpu: vpu@ff900000 { 2131 compatible = "amlogic,meson-g12a-vpu"; 2132 reg = <0x0 0xff900000 0x0 0x100000>, 2133 <0x0 0xff63c000 0x0 0x1000>; 2134 reg-names = "vpu", "hhi"; 2135 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2136 #address-cells = <1>; 2137 #size-cells = <0>; 2138 amlogic,canvas = <&canvas>; 2139 2140 /* CVBS VDAC output port */ 2141 cvbs_vdac_port: port@0 { 2142 reg = <0>; 2143 }; 2144 2145 /* HDMI-TX output port */ 2146 hdmi_tx_port: port@1 { 2147 reg = <1>; 2148 2149 hdmi_tx_out: endpoint { 2150 remote-endpoint = <&hdmi_tx_in>; 2151 }; 2152 }; 2153 }; 2154 2155 gic: interrupt-controller@ffc01000 { 2156 compatible = "arm,gic-400"; 2157 reg = <0x0 0xffc01000 0 0x1000>, 2158 <0x0 0xffc02000 0 0x2000>, 2159 <0x0 0xffc04000 0 0x2000>, 2160 <0x0 0xffc06000 0 0x2000>; 2161 interrupt-controller; 2162 interrupts = <GIC_PPI 9 2163 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2164 #interrupt-cells = <3>; 2165 #address-cells = <0>; 2166 }; 2167 2168 cbus: bus@ffd00000 { 2169 compatible = "simple-bus"; 2170 reg = <0x0 0xffd00000 0x0 0x100000>; 2171 #address-cells = <2>; 2172 #size-cells = <2>; 2173 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 2174 2175 reset: reset-controller@1004 { 2176 compatible = "amlogic,meson-axg-reset"; 2177 reg = <0x0 0x1004 0x0 0x9c>; 2178 #reset-cells = <1>; 2179 }; 2180 2181 gpio_intc: interrupt-controller@f080 { 2182 compatible = "amlogic,meson-g12a-gpio-intc", 2183 "amlogic,meson-gpio-intc"; 2184 reg = <0x0 0xf080 0x0 0x10>; 2185 interrupt-controller; 2186 #interrupt-cells = <2>; 2187 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 2188 }; 2189 2190 watchdog: watchdog@f0d0 { 2191 compatible = "amlogic,meson-gxbb-wdt"; 2192 reg = <0x0 0xf0d0 0x0 0x10>; 2193 clocks = <&xtal>; 2194 }; 2195 2196 spicc0: spi@13000 { 2197 compatible = "amlogic,meson-g12a-spicc"; 2198 reg = <0x0 0x13000 0x0 0x44>; 2199 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 2200 clocks = <&clkc CLKID_SPICC0>, 2201 <&clkc CLKID_SPICC0_SCLK>; 2202 clock-names = "core", "pclk"; 2203 #address-cells = <1>; 2204 #size-cells = <0>; 2205 status = "disabled"; 2206 }; 2207 2208 spicc1: spi@15000 { 2209 compatible = "amlogic,meson-g12a-spicc"; 2210 reg = <0x0 0x15000 0x0 0x44>; 2211 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 2212 clocks = <&clkc CLKID_SPICC1>, 2213 <&clkc CLKID_SPICC1_SCLK>; 2214 clock-names = "core", "pclk"; 2215 #address-cells = <1>; 2216 #size-cells = <0>; 2217 status = "disabled"; 2218 }; 2219 2220 spifc: spi@14000 { 2221 compatible = "amlogic,meson-gxbb-spifc"; 2222 status = "disabled"; 2223 reg = <0x0 0x14000 0x0 0x80>; 2224 #address-cells = <1>; 2225 #size-cells = <0>; 2226 clocks = <&clkc CLKID_CLK81>; 2227 }; 2228 2229 pwm_ef: pwm@19000 { 2230 compatible = "amlogic,meson-g12a-ee-pwm"; 2231 reg = <0x0 0x19000 0x0 0x20>; 2232 #pwm-cells = <3>; 2233 status = "disabled"; 2234 }; 2235 2236 pwm_cd: pwm@1a000 { 2237 compatible = "amlogic,meson-g12a-ee-pwm"; 2238 reg = <0x0 0x1a000 0x0 0x20>; 2239 #pwm-cells = <3>; 2240 status = "disabled"; 2241 }; 2242 2243 pwm_ab: pwm@1b000 { 2244 compatible = "amlogic,meson-g12a-ee-pwm"; 2245 reg = <0x0 0x1b000 0x0 0x20>; 2246 #pwm-cells = <3>; 2247 status = "disabled"; 2248 }; 2249 2250 i2c3: i2c@1c000 { 2251 compatible = "amlogic,meson-axg-i2c"; 2252 status = "disabled"; 2253 reg = <0x0 0x1c000 0x0 0x20>; 2254 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 2255 #address-cells = <1>; 2256 #size-cells = <0>; 2257 clocks = <&clkc CLKID_I2C>; 2258 }; 2259 2260 i2c2: i2c@1d000 { 2261 compatible = "amlogic,meson-axg-i2c"; 2262 status = "disabled"; 2263 reg = <0x0 0x1d000 0x0 0x20>; 2264 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 2265 #address-cells = <1>; 2266 #size-cells = <0>; 2267 clocks = <&clkc CLKID_I2C>; 2268 }; 2269 2270 i2c1: i2c@1e000 { 2271 compatible = "amlogic,meson-axg-i2c"; 2272 status = "disabled"; 2273 reg = <0x0 0x1e000 0x0 0x20>; 2274 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 2275 #address-cells = <1>; 2276 #size-cells = <0>; 2277 clocks = <&clkc CLKID_I2C>; 2278 }; 2279 2280 i2c0: i2c@1f000 { 2281 compatible = "amlogic,meson-axg-i2c"; 2282 status = "disabled"; 2283 reg = <0x0 0x1f000 0x0 0x20>; 2284 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 2285 #address-cells = <1>; 2286 #size-cells = <0>; 2287 clocks = <&clkc CLKID_I2C>; 2288 }; 2289 2290 clk_msr: clock-measure@18000 { 2291 compatible = "amlogic,meson-g12a-clk-measure"; 2292 reg = <0x0 0x18000 0x0 0x10>; 2293 }; 2294 2295 uart_C: serial@22000 { 2296 compatible = "amlogic,meson-gx-uart"; 2297 reg = <0x0 0x22000 0x0 0x18>; 2298 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 2299 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 2300 clock-names = "xtal", "pclk", "baud"; 2301 status = "disabled"; 2302 }; 2303 2304 uart_B: serial@23000 { 2305 compatible = "amlogic,meson-gx-uart"; 2306 reg = <0x0 0x23000 0x0 0x18>; 2307 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 2308 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 2309 clock-names = "xtal", "pclk", "baud"; 2310 status = "disabled"; 2311 }; 2312 2313 uart_A: serial@24000 { 2314 compatible = "amlogic,meson-gx-uart"; 2315 reg = <0x0 0x24000 0x0 0x18>; 2316 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 2317 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 2318 clock-names = "xtal", "pclk", "baud"; 2319 status = "disabled"; 2320 }; 2321 }; 2322 2323 sd_emmc_a: sd@ffe03000 { 2324 compatible = "amlogic,meson-axg-mmc"; 2325 reg = <0x0 0xffe03000 0x0 0x800>; 2326 interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>; 2327 status = "disabled"; 2328 clocks = <&clkc CLKID_SD_EMMC_A>, 2329 <&clkc CLKID_SD_EMMC_A_CLK0>, 2330 <&clkc CLKID_FCLK_DIV2>; 2331 clock-names = "core", "clkin0", "clkin1"; 2332 resets = <&reset RESET_SD_EMMC_A>; 2333 }; 2334 2335 sd_emmc_b: sd@ffe05000 { 2336 compatible = "amlogic,meson-axg-mmc"; 2337 reg = <0x0 0xffe05000 0x0 0x800>; 2338 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; 2339 status = "disabled"; 2340 clocks = <&clkc CLKID_SD_EMMC_B>, 2341 <&clkc CLKID_SD_EMMC_B_CLK0>, 2342 <&clkc CLKID_FCLK_DIV2>; 2343 clock-names = "core", "clkin0", "clkin1"; 2344 resets = <&reset RESET_SD_EMMC_B>; 2345 }; 2346 2347 sd_emmc_c: mmc@ffe07000 { 2348 compatible = "amlogic,meson-axg-mmc"; 2349 reg = <0x0 0xffe07000 0x0 0x800>; 2350 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; 2351 status = "disabled"; 2352 clocks = <&clkc CLKID_SD_EMMC_C>, 2353 <&clkc CLKID_SD_EMMC_C_CLK0>, 2354 <&clkc CLKID_FCLK_DIV2>; 2355 clock-names = "core", "clkin0", "clkin1"; 2356 resets = <&reset RESET_SD_EMMC_C>; 2357 }; 2358 2359 usb: usb@ffe09000 { 2360 status = "disabled"; 2361 compatible = "amlogic,meson-g12a-usb-ctrl"; 2362 reg = <0x0 0xffe09000 0x0 0xa0>; 2363 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 2364 #address-cells = <2>; 2365 #size-cells = <2>; 2366 ranges; 2367 2368 clocks = <&clkc CLKID_USB>; 2369 resets = <&reset RESET_USB>; 2370 2371 dr_mode = "otg"; 2372 2373 phys = <&usb2_phy0>, <&usb2_phy1>, 2374 <&usb3_pcie_phy PHY_TYPE_USB3>; 2375 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 2376 2377 dwc2: usb@ff400000 { 2378 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 2379 reg = <0x0 0xff400000 0x0 0x40000>; 2380 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2381 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 2382 clock-names = "otg"; 2383 phys = <&usb2_phy1>; 2384 phy-names = "usb2-phy"; 2385 dr_mode = "peripheral"; 2386 g-rx-fifo-size = <192>; 2387 g-np-tx-fifo-size = <128>; 2388 g-tx-fifo-size = <128 128 16 16 16>; 2389 }; 2390 2391 dwc3: usb@ff500000 { 2392 compatible = "snps,dwc3"; 2393 reg = <0x0 0xff500000 0x0 0x100000>; 2394 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2395 dr_mode = "host"; 2396 snps,dis_u2_susphy_quirk; 2397 snps,quirk-frame-length-adjustment = <0x20>; 2398 snps,parkmode-disable-ss-quirk; 2399 }; 2400 }; 2401 2402 mali: gpu@ffe40000 { 2403 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 2404 reg = <0x0 0xffe40000 0x0 0x40000>; 2405 interrupt-parent = <&gic>; 2406 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 2407 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 2408 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2409 interrupt-names = "job", "mmu", "gpu"; 2410 clocks = <&clkc CLKID_MALI>; 2411 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 2412 operating-points-v2 = <&gpu_opp_table>; 2413 #cooling-cells = <2>; 2414 }; 2415 }; 2416 2417 timer { 2418 compatible = "arm,armv8-timer"; 2419 interrupts = <GIC_PPI 13 2420 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2421 <GIC_PPI 14 2422 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2423 <GIC_PPI 11 2424 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2425 <GIC_PPI 10 2426 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 2427 arm,no-tick-in-suspend; 2428 }; 2429 2430 xtal: xtal-clk { 2431 compatible = "fixed-clock"; 2432 clock-frequency = <24000000>; 2433 clock-output-names = "xtal"; 2434 #clock-cells = <0>; 2435 }; 2436 2437}; 2438