1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * SMP support for ppc.
4 *
5 * Written by Cort Dougan (cort@cs.nmt.edu) borrowing a great
6 * deal of code from the sparc and intel versions.
7 *
8 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
9 *
10 * PowerPC-64 Support added by Dave Engebretsen, Peter Bergner, and
11 * Mike Corrigan {engebret|bergner|mikec}@us.ibm.com
12 */
13
14 #undef DEBUG
15
16 #include <linux/kernel.h>
17 #include <linux/export.h>
18 #include <linux/sched/mm.h>
19 #include <linux/sched/task_stack.h>
20 #include <linux/sched/topology.h>
21 #include <linux/smp.h>
22 #include <linux/interrupt.h>
23 #include <linux/delay.h>
24 #include <linux/init.h>
25 #include <linux/spinlock.h>
26 #include <linux/cache.h>
27 #include <linux/err.h>
28 #include <linux/device.h>
29 #include <linux/cpu.h>
30 #include <linux/notifier.h>
31 #include <linux/topology.h>
32 #include <linux/profile.h>
33 #include <linux/processor.h>
34 #include <linux/random.h>
35 #include <linux/stackprotector.h>
36 #include <linux/pgtable.h>
37 #include <linux/clockchips.h>
38
39 #include <asm/ptrace.h>
40 #include <linux/atomic.h>
41 #include <asm/irq.h>
42 #include <asm/hw_irq.h>
43 #include <asm/kvm_ppc.h>
44 #include <asm/dbell.h>
45 #include <asm/page.h>
46 #include <asm/prom.h>
47 #include <asm/smp.h>
48 #include <asm/time.h>
49 #include <asm/machdep.h>
50 #include <asm/cputhreads.h>
51 #include <asm/cputable.h>
52 #include <asm/mpic.h>
53 #include <asm/vdso_datapage.h>
54 #ifdef CONFIG_PPC64
55 #include <asm/paca.h>
56 #endif
57 #include <asm/vdso.h>
58 #include <asm/debug.h>
59 #include <asm/kexec.h>
60 #include <asm/asm-prototypes.h>
61 #include <asm/cpu_has_feature.h>
62 #include <asm/ftrace.h>
63 #include <asm/kup.h>
64
65 #ifdef DEBUG
66 #include <asm/udbg.h>
67 #define DBG(fmt...) udbg_printf(fmt)
68 #else
69 #define DBG(fmt...)
70 #endif
71
72 #ifdef CONFIG_HOTPLUG_CPU
73 /* State of each CPU during hotplug phases */
74 static DEFINE_PER_CPU(int, cpu_state) = { 0 };
75 #endif
76
77 struct task_struct *secondary_current;
78 bool has_big_cores;
79 bool coregroup_enabled;
80 bool thread_group_shares_l2;
81
82 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map);
83 DEFINE_PER_CPU(cpumask_var_t, cpu_smallcore_map);
84 DEFINE_PER_CPU(cpumask_var_t, cpu_l2_cache_map);
85 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map);
86 static DEFINE_PER_CPU(cpumask_var_t, cpu_coregroup_map);
87
88 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
89 EXPORT_PER_CPU_SYMBOL(cpu_l2_cache_map);
90 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
91 EXPORT_SYMBOL_GPL(has_big_cores);
92
93 enum {
94 #ifdef CONFIG_SCHED_SMT
95 smt_idx,
96 #endif
97 cache_idx,
98 mc_idx,
99 die_idx,
100 };
101
102 #define MAX_THREAD_LIST_SIZE 8
103 #define THREAD_GROUP_SHARE_L1 1
104 #define THREAD_GROUP_SHARE_L2 2
105 struct thread_groups {
106 unsigned int property;
107 unsigned int nr_groups;
108 unsigned int threads_per_group;
109 unsigned int thread_list[MAX_THREAD_LIST_SIZE];
110 };
111
112 /* Maximum number of properties that groups of threads within a core can share */
113 #define MAX_THREAD_GROUP_PROPERTIES 2
114
115 struct thread_groups_list {
116 unsigned int nr_properties;
117 struct thread_groups property_tgs[MAX_THREAD_GROUP_PROPERTIES];
118 };
119
120 static struct thread_groups_list tgl[NR_CPUS] __initdata;
121 /*
122 * On big-cores system, thread_group_l1_cache_map for each CPU corresponds to
123 * the set its siblings that share the L1-cache.
124 */
125 static DEFINE_PER_CPU(cpumask_var_t, thread_group_l1_cache_map);
126
127 /*
128 * On some big-cores system, thread_group_l2_cache_map for each CPU
129 * corresponds to the set its siblings within the core that share the
130 * L2-cache.
131 */
132 static DEFINE_PER_CPU(cpumask_var_t, thread_group_l2_cache_map);
133
134 /* SMP operations for this machine */
135 struct smp_ops_t *smp_ops;
136
137 /* Can't be static due to PowerMac hackery */
138 volatile unsigned int cpu_callin_map[NR_CPUS];
139
140 int smt_enabled_at_boot = 1;
141
142 /*
143 * Returns 1 if the specified cpu should be brought up during boot.
144 * Used to inhibit booting threads if they've been disabled or
145 * limited on the command line
146 */
smp_generic_cpu_bootable(unsigned int nr)147 int smp_generic_cpu_bootable(unsigned int nr)
148 {
149 /* Special case - we inhibit secondary thread startup
150 * during boot if the user requests it.
151 */
152 if (system_state < SYSTEM_RUNNING && cpu_has_feature(CPU_FTR_SMT)) {
153 if (!smt_enabled_at_boot && cpu_thread_in_core(nr) != 0)
154 return 0;
155 if (smt_enabled_at_boot
156 && cpu_thread_in_core(nr) >= smt_enabled_at_boot)
157 return 0;
158 }
159
160 return 1;
161 }
162
163
164 #ifdef CONFIG_PPC64
smp_generic_kick_cpu(int nr)165 int smp_generic_kick_cpu(int nr)
166 {
167 if (nr < 0 || nr >= nr_cpu_ids)
168 return -EINVAL;
169
170 /*
171 * The processor is currently spinning, waiting for the
172 * cpu_start field to become non-zero After we set cpu_start,
173 * the processor will continue on to secondary_start
174 */
175 if (!paca_ptrs[nr]->cpu_start) {
176 paca_ptrs[nr]->cpu_start = 1;
177 smp_mb();
178 return 0;
179 }
180
181 #ifdef CONFIG_HOTPLUG_CPU
182 /*
183 * Ok it's not there, so it might be soft-unplugged, let's
184 * try to bring it back
185 */
186 generic_set_cpu_up(nr);
187 smp_wmb();
188 smp_send_reschedule(nr);
189 #endif /* CONFIG_HOTPLUG_CPU */
190
191 return 0;
192 }
193 #endif /* CONFIG_PPC64 */
194
call_function_action(int irq,void * data)195 static irqreturn_t call_function_action(int irq, void *data)
196 {
197 generic_smp_call_function_interrupt();
198 return IRQ_HANDLED;
199 }
200
reschedule_action(int irq,void * data)201 static irqreturn_t reschedule_action(int irq, void *data)
202 {
203 scheduler_ipi();
204 return IRQ_HANDLED;
205 }
206
207 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
tick_broadcast_ipi_action(int irq,void * data)208 static irqreturn_t tick_broadcast_ipi_action(int irq, void *data)
209 {
210 timer_broadcast_interrupt();
211 return IRQ_HANDLED;
212 }
213 #endif
214
215 #ifdef CONFIG_NMI_IPI
nmi_ipi_action(int irq,void * data)216 static irqreturn_t nmi_ipi_action(int irq, void *data)
217 {
218 smp_handle_nmi_ipi(get_irq_regs());
219 return IRQ_HANDLED;
220 }
221 #endif
222
223 static irq_handler_t smp_ipi_action[] = {
224 [PPC_MSG_CALL_FUNCTION] = call_function_action,
225 [PPC_MSG_RESCHEDULE] = reschedule_action,
226 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
227 [PPC_MSG_TICK_BROADCAST] = tick_broadcast_ipi_action,
228 #endif
229 #ifdef CONFIG_NMI_IPI
230 [PPC_MSG_NMI_IPI] = nmi_ipi_action,
231 #endif
232 };
233
234 /*
235 * The NMI IPI is a fallback and not truly non-maskable. It is simpler
236 * than going through the call function infrastructure, and strongly
237 * serialized, so it is more appropriate for debugging.
238 */
239 const char *smp_ipi_name[] = {
240 [PPC_MSG_CALL_FUNCTION] = "ipi call function",
241 [PPC_MSG_RESCHEDULE] = "ipi reschedule",
242 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
243 [PPC_MSG_TICK_BROADCAST] = "ipi tick-broadcast",
244 #endif
245 #ifdef CONFIG_NMI_IPI
246 [PPC_MSG_NMI_IPI] = "nmi ipi",
247 #endif
248 };
249
250 /* optional function to request ipi, for controllers with >= 4 ipis */
smp_request_message_ipi(int virq,int msg)251 int smp_request_message_ipi(int virq, int msg)
252 {
253 int err;
254
255 if (msg < 0 || msg > PPC_MSG_NMI_IPI)
256 return -EINVAL;
257 #ifndef CONFIG_NMI_IPI
258 if (msg == PPC_MSG_NMI_IPI)
259 return 1;
260 #endif
261
262 err = request_irq(virq, smp_ipi_action[msg],
263 IRQF_PERCPU | IRQF_NO_THREAD | IRQF_NO_SUSPEND,
264 smp_ipi_name[msg], NULL);
265 WARN(err < 0, "unable to request_irq %d for %s (rc %d)\n",
266 virq, smp_ipi_name[msg], err);
267
268 return err;
269 }
270
271 #ifdef CONFIG_PPC_SMP_MUXED_IPI
272 struct cpu_messages {
273 long messages; /* current messages */
274 };
275 static DEFINE_PER_CPU_SHARED_ALIGNED(struct cpu_messages, ipi_message);
276
smp_muxed_ipi_set_message(int cpu,int msg)277 void smp_muxed_ipi_set_message(int cpu, int msg)
278 {
279 struct cpu_messages *info = &per_cpu(ipi_message, cpu);
280 char *message = (char *)&info->messages;
281
282 /*
283 * Order previous accesses before accesses in the IPI handler.
284 */
285 smp_mb();
286 message[msg] = 1;
287 }
288
smp_muxed_ipi_message_pass(int cpu,int msg)289 void smp_muxed_ipi_message_pass(int cpu, int msg)
290 {
291 smp_muxed_ipi_set_message(cpu, msg);
292
293 /*
294 * cause_ipi functions are required to include a full barrier
295 * before doing whatever causes the IPI.
296 */
297 smp_ops->cause_ipi(cpu);
298 }
299
300 #ifdef __BIG_ENDIAN__
301 #define IPI_MESSAGE(A) (1uL << ((BITS_PER_LONG - 8) - 8 * (A)))
302 #else
303 #define IPI_MESSAGE(A) (1uL << (8 * (A)))
304 #endif
305
smp_ipi_demux(void)306 irqreturn_t smp_ipi_demux(void)
307 {
308 mb(); /* order any irq clear */
309
310 return smp_ipi_demux_relaxed();
311 }
312
313 /* sync-free variant. Callers should ensure synchronization */
smp_ipi_demux_relaxed(void)314 irqreturn_t smp_ipi_demux_relaxed(void)
315 {
316 struct cpu_messages *info;
317 unsigned long all;
318
319 info = this_cpu_ptr(&ipi_message);
320 do {
321 all = xchg(&info->messages, 0);
322 #if defined(CONFIG_KVM_XICS) && defined(CONFIG_KVM_BOOK3S_HV_POSSIBLE)
323 /*
324 * Must check for PPC_MSG_RM_HOST_ACTION messages
325 * before PPC_MSG_CALL_FUNCTION messages because when
326 * a VM is destroyed, we call kick_all_cpus_sync()
327 * to ensure that any pending PPC_MSG_RM_HOST_ACTION
328 * messages have completed before we free any VCPUs.
329 */
330 if (all & IPI_MESSAGE(PPC_MSG_RM_HOST_ACTION))
331 kvmppc_xics_ipi_action();
332 #endif
333 if (all & IPI_MESSAGE(PPC_MSG_CALL_FUNCTION))
334 generic_smp_call_function_interrupt();
335 if (all & IPI_MESSAGE(PPC_MSG_RESCHEDULE))
336 scheduler_ipi();
337 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
338 if (all & IPI_MESSAGE(PPC_MSG_TICK_BROADCAST))
339 timer_broadcast_interrupt();
340 #endif
341 #ifdef CONFIG_NMI_IPI
342 if (all & IPI_MESSAGE(PPC_MSG_NMI_IPI))
343 nmi_ipi_action(0, NULL);
344 #endif
345 } while (info->messages);
346
347 return IRQ_HANDLED;
348 }
349 #endif /* CONFIG_PPC_SMP_MUXED_IPI */
350
do_message_pass(int cpu,int msg)351 static inline void do_message_pass(int cpu, int msg)
352 {
353 if (smp_ops->message_pass)
354 smp_ops->message_pass(cpu, msg);
355 #ifdef CONFIG_PPC_SMP_MUXED_IPI
356 else
357 smp_muxed_ipi_message_pass(cpu, msg);
358 #endif
359 }
360
smp_send_reschedule(int cpu)361 void smp_send_reschedule(int cpu)
362 {
363 if (likely(smp_ops))
364 do_message_pass(cpu, PPC_MSG_RESCHEDULE);
365 }
366 EXPORT_SYMBOL_GPL(smp_send_reschedule);
367
arch_send_call_function_single_ipi(int cpu)368 void arch_send_call_function_single_ipi(int cpu)
369 {
370 do_message_pass(cpu, PPC_MSG_CALL_FUNCTION);
371 }
372
arch_send_call_function_ipi_mask(const struct cpumask * mask)373 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
374 {
375 unsigned int cpu;
376
377 for_each_cpu(cpu, mask)
378 do_message_pass(cpu, PPC_MSG_CALL_FUNCTION);
379 }
380
381 #ifdef CONFIG_NMI_IPI
382
383 /*
384 * "NMI IPI" system.
385 *
386 * NMI IPIs may not be recoverable, so should not be used as ongoing part of
387 * a running system. They can be used for crash, debug, halt/reboot, etc.
388 *
389 * The IPI call waits with interrupts disabled until all targets enter the
390 * NMI handler, then returns. Subsequent IPIs can be issued before targets
391 * have returned from their handlers, so there is no guarantee about
392 * concurrency or re-entrancy.
393 *
394 * A new NMI can be issued before all targets exit the handler.
395 *
396 * The IPI call may time out without all targets entering the NMI handler.
397 * In that case, there is some logic to recover (and ignore subsequent
398 * NMI interrupts that may eventually be raised), but the platform interrupt
399 * handler may not be able to distinguish this from other exception causes,
400 * which may cause a crash.
401 */
402
403 static atomic_t __nmi_ipi_lock = ATOMIC_INIT(0);
404 static struct cpumask nmi_ipi_pending_mask;
405 static bool nmi_ipi_busy = false;
406 static void (*nmi_ipi_function)(struct pt_regs *) = NULL;
407
nmi_ipi_lock_start(unsigned long * flags)408 static void nmi_ipi_lock_start(unsigned long *flags)
409 {
410 raw_local_irq_save(*flags);
411 hard_irq_disable();
412 while (atomic_cmpxchg(&__nmi_ipi_lock, 0, 1) == 1) {
413 raw_local_irq_restore(*flags);
414 spin_until_cond(atomic_read(&__nmi_ipi_lock) == 0);
415 raw_local_irq_save(*flags);
416 hard_irq_disable();
417 }
418 }
419
nmi_ipi_lock(void)420 static void nmi_ipi_lock(void)
421 {
422 while (atomic_cmpxchg(&__nmi_ipi_lock, 0, 1) == 1)
423 spin_until_cond(atomic_read(&__nmi_ipi_lock) == 0);
424 }
425
nmi_ipi_unlock(void)426 static void nmi_ipi_unlock(void)
427 {
428 smp_mb();
429 WARN_ON(atomic_read(&__nmi_ipi_lock) != 1);
430 atomic_set(&__nmi_ipi_lock, 0);
431 }
432
nmi_ipi_unlock_end(unsigned long * flags)433 static void nmi_ipi_unlock_end(unsigned long *flags)
434 {
435 nmi_ipi_unlock();
436 raw_local_irq_restore(*flags);
437 }
438
439 /*
440 * Platform NMI handler calls this to ack
441 */
smp_handle_nmi_ipi(struct pt_regs * regs)442 int smp_handle_nmi_ipi(struct pt_regs *regs)
443 {
444 void (*fn)(struct pt_regs *) = NULL;
445 unsigned long flags;
446 int me = raw_smp_processor_id();
447 int ret = 0;
448
449 /*
450 * Unexpected NMIs are possible here because the interrupt may not
451 * be able to distinguish NMI IPIs from other types of NMIs, or
452 * because the caller may have timed out.
453 */
454 nmi_ipi_lock_start(&flags);
455 if (cpumask_test_cpu(me, &nmi_ipi_pending_mask)) {
456 cpumask_clear_cpu(me, &nmi_ipi_pending_mask);
457 fn = READ_ONCE(nmi_ipi_function);
458 WARN_ON_ONCE(!fn);
459 ret = 1;
460 }
461 nmi_ipi_unlock_end(&flags);
462
463 if (fn)
464 fn(regs);
465
466 return ret;
467 }
468
do_smp_send_nmi_ipi(int cpu,bool safe)469 static void do_smp_send_nmi_ipi(int cpu, bool safe)
470 {
471 if (!safe && smp_ops->cause_nmi_ipi && smp_ops->cause_nmi_ipi(cpu))
472 return;
473
474 if (cpu >= 0) {
475 do_message_pass(cpu, PPC_MSG_NMI_IPI);
476 } else {
477 int c;
478
479 for_each_online_cpu(c) {
480 if (c == raw_smp_processor_id())
481 continue;
482 do_message_pass(c, PPC_MSG_NMI_IPI);
483 }
484 }
485 }
486
487 /*
488 * - cpu is the target CPU (must not be this CPU), or NMI_IPI_ALL_OTHERS.
489 * - fn is the target callback function.
490 * - delay_us > 0 is the delay before giving up waiting for targets to
491 * begin executing the handler, == 0 specifies indefinite delay.
492 */
__smp_send_nmi_ipi(int cpu,void (* fn)(struct pt_regs *),u64 delay_us,bool safe)493 static int __smp_send_nmi_ipi(int cpu, void (*fn)(struct pt_regs *),
494 u64 delay_us, bool safe)
495 {
496 unsigned long flags;
497 int me = raw_smp_processor_id();
498 int ret = 1;
499
500 BUG_ON(cpu == me);
501 BUG_ON(cpu < 0 && cpu != NMI_IPI_ALL_OTHERS);
502
503 if (unlikely(!smp_ops))
504 return 0;
505
506 nmi_ipi_lock_start(&flags);
507 while (nmi_ipi_busy) {
508 nmi_ipi_unlock_end(&flags);
509 spin_until_cond(!nmi_ipi_busy);
510 nmi_ipi_lock_start(&flags);
511 }
512 nmi_ipi_busy = true;
513 nmi_ipi_function = fn;
514
515 WARN_ON_ONCE(!cpumask_empty(&nmi_ipi_pending_mask));
516
517 if (cpu < 0) {
518 /* ALL_OTHERS */
519 cpumask_copy(&nmi_ipi_pending_mask, cpu_online_mask);
520 cpumask_clear_cpu(me, &nmi_ipi_pending_mask);
521 } else {
522 cpumask_set_cpu(cpu, &nmi_ipi_pending_mask);
523 }
524
525 nmi_ipi_unlock();
526
527 /* Interrupts remain hard disabled */
528
529 do_smp_send_nmi_ipi(cpu, safe);
530
531 nmi_ipi_lock();
532 /* nmi_ipi_busy is set here, so unlock/lock is okay */
533 while (!cpumask_empty(&nmi_ipi_pending_mask)) {
534 nmi_ipi_unlock();
535 udelay(1);
536 nmi_ipi_lock();
537 if (delay_us) {
538 delay_us--;
539 if (!delay_us)
540 break;
541 }
542 }
543
544 if (!cpumask_empty(&nmi_ipi_pending_mask)) {
545 /* Timeout waiting for CPUs to call smp_handle_nmi_ipi */
546 ret = 0;
547 cpumask_clear(&nmi_ipi_pending_mask);
548 }
549
550 nmi_ipi_function = NULL;
551 nmi_ipi_busy = false;
552
553 nmi_ipi_unlock_end(&flags);
554
555 return ret;
556 }
557
smp_send_nmi_ipi(int cpu,void (* fn)(struct pt_regs *),u64 delay_us)558 int smp_send_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), u64 delay_us)
559 {
560 return __smp_send_nmi_ipi(cpu, fn, delay_us, false);
561 }
562
smp_send_safe_nmi_ipi(int cpu,void (* fn)(struct pt_regs *),u64 delay_us)563 int smp_send_safe_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), u64 delay_us)
564 {
565 return __smp_send_nmi_ipi(cpu, fn, delay_us, true);
566 }
567 #endif /* CONFIG_NMI_IPI */
568
569 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
tick_broadcast(const struct cpumask * mask)570 void tick_broadcast(const struct cpumask *mask)
571 {
572 unsigned int cpu;
573
574 for_each_cpu(cpu, mask)
575 do_message_pass(cpu, PPC_MSG_TICK_BROADCAST);
576 }
577 #endif
578
579 #ifdef CONFIG_DEBUGGER
debugger_ipi_callback(struct pt_regs * regs)580 static void debugger_ipi_callback(struct pt_regs *regs)
581 {
582 debugger_ipi(regs);
583 }
584
smp_send_debugger_break(void)585 void smp_send_debugger_break(void)
586 {
587 smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, debugger_ipi_callback, 1000000);
588 }
589 #endif
590
591 #ifdef CONFIG_KEXEC_CORE
crash_send_ipi(void (* crash_ipi_callback)(struct pt_regs *))592 void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *))
593 {
594 int cpu;
595
596 smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, crash_ipi_callback, 1000000);
597 if (kdump_in_progress() && crash_wake_offline) {
598 for_each_present_cpu(cpu) {
599 if (cpu_online(cpu))
600 continue;
601 /*
602 * crash_ipi_callback will wait for
603 * all cpus, including offline CPUs.
604 * We don't care about nmi_ipi_function.
605 * Offline cpus will jump straight into
606 * crash_ipi_callback, we can skip the
607 * entire NMI dance and waiting for
608 * cpus to clear pending mask, etc.
609 */
610 do_smp_send_nmi_ipi(cpu, false);
611 }
612 }
613 }
614 #endif
615
616 #ifdef CONFIG_NMI_IPI
nmi_stop_this_cpu(struct pt_regs * regs)617 static void nmi_stop_this_cpu(struct pt_regs *regs)
618 {
619 /*
620 * IRQs are already hard disabled by the smp_handle_nmi_ipi.
621 */
622 spin_begin();
623 while (1)
624 spin_cpu_relax();
625 }
626
smp_send_stop(void)627 void smp_send_stop(void)
628 {
629 smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, nmi_stop_this_cpu, 1000000);
630 }
631
632 #else /* CONFIG_NMI_IPI */
633
stop_this_cpu(void * dummy)634 static void stop_this_cpu(void *dummy)
635 {
636 hard_irq_disable();
637 spin_begin();
638 while (1)
639 spin_cpu_relax();
640 }
641
smp_send_stop(void)642 void smp_send_stop(void)
643 {
644 static bool stopped = false;
645
646 /*
647 * Prevent waiting on csd lock from a previous smp_send_stop.
648 * This is racy, but in general callers try to do the right
649 * thing and only fire off one smp_send_stop (e.g., see
650 * kernel/panic.c)
651 */
652 if (stopped)
653 return;
654
655 stopped = true;
656
657 smp_call_function(stop_this_cpu, NULL, 0);
658 }
659 #endif /* CONFIG_NMI_IPI */
660
661 struct task_struct *current_set[NR_CPUS];
662
smp_store_cpu_info(int id)663 static void smp_store_cpu_info(int id)
664 {
665 per_cpu(cpu_pvr, id) = mfspr(SPRN_PVR);
666 #ifdef CONFIG_PPC_FSL_BOOK3E
667 per_cpu(next_tlbcam_idx, id)
668 = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) - 1;
669 #endif
670 }
671
672 /*
673 * Relationships between CPUs are maintained in a set of per-cpu cpumasks so
674 * rather than just passing around the cpumask we pass around a function that
675 * returns the that cpumask for the given CPU.
676 */
set_cpus_related(int i,int j,struct cpumask * (* get_cpumask)(int))677 static void set_cpus_related(int i, int j, struct cpumask *(*get_cpumask)(int))
678 {
679 cpumask_set_cpu(i, get_cpumask(j));
680 cpumask_set_cpu(j, get_cpumask(i));
681 }
682
683 #ifdef CONFIG_HOTPLUG_CPU
set_cpus_unrelated(int i,int j,struct cpumask * (* get_cpumask)(int))684 static void set_cpus_unrelated(int i, int j,
685 struct cpumask *(*get_cpumask)(int))
686 {
687 cpumask_clear_cpu(i, get_cpumask(j));
688 cpumask_clear_cpu(j, get_cpumask(i));
689 }
690 #endif
691
692 /*
693 * Extends set_cpus_related. Instead of setting one CPU at a time in
694 * dstmask, set srcmask at oneshot. dstmask should be super set of srcmask.
695 */
or_cpumasks_related(int i,int j,struct cpumask * (* srcmask)(int),struct cpumask * (* dstmask)(int))696 static void or_cpumasks_related(int i, int j, struct cpumask *(*srcmask)(int),
697 struct cpumask *(*dstmask)(int))
698 {
699 struct cpumask *mask;
700 int k;
701
702 mask = srcmask(j);
703 for_each_cpu(k, srcmask(i))
704 cpumask_or(dstmask(k), dstmask(k), mask);
705
706 if (i == j)
707 return;
708
709 mask = srcmask(i);
710 for_each_cpu(k, srcmask(j))
711 cpumask_or(dstmask(k), dstmask(k), mask);
712 }
713
714 /*
715 * parse_thread_groups: Parses the "ibm,thread-groups" device tree
716 * property for the CPU device node @dn and stores
717 * the parsed output in the thread_groups_list
718 * structure @tglp.
719 *
720 * @dn: The device node of the CPU device.
721 * @tglp: Pointer to a thread group list structure into which the parsed
722 * output of "ibm,thread-groups" is stored.
723 *
724 * ibm,thread-groups[0..N-1] array defines which group of threads in
725 * the CPU-device node can be grouped together based on the property.
726 *
727 * This array can represent thread groupings for multiple properties.
728 *
729 * ibm,thread-groups[i + 0] tells us the property based on which the
730 * threads are being grouped together. If this value is 1, it implies
731 * that the threads in the same group share L1, translation cache. If
732 * the value is 2, it implies that the threads in the same group share
733 * the same L2 cache.
734 *
735 * ibm,thread-groups[i+1] tells us how many such thread groups exist for the
736 * property ibm,thread-groups[i]
737 *
738 * ibm,thread-groups[i+2] tells us the number of threads in each such
739 * group.
740 * Suppose k = (ibm,thread-groups[i+1] * ibm,thread-groups[i+2]), then,
741 *
742 * ibm,thread-groups[i+3..i+k+2] (is the list of threads identified by
743 * "ibm,ppc-interrupt-server#s" arranged as per their membership in
744 * the grouping.
745 *
746 * Example:
747 * If "ibm,thread-groups" = [1,2,4,8,10,12,14,9,11,13,15,2,2,4,8,10,12,14,9,11,13,15]
748 * This can be decomposed up into two consecutive arrays:
749 * a) [1,2,4,8,10,12,14,9,11,13,15]
750 * b) [2,2,4,8,10,12,14,9,11,13,15]
751 *
752 * where in,
753 *
754 * a) provides information of Property "1" being shared by "2" groups,
755 * each with "4" threads each. The "ibm,ppc-interrupt-server#s" of
756 * the first group is {8,10,12,14} and the
757 * "ibm,ppc-interrupt-server#s" of the second group is
758 * {9,11,13,15}. Property "1" is indicative of the thread in the
759 * group sharing L1 cache, translation cache and Instruction Data
760 * flow.
761 *
762 * b) provides information of Property "2" being shared by "2" groups,
763 * each group with "4" threads. The "ibm,ppc-interrupt-server#s" of
764 * the first group is {8,10,12,14} and the
765 * "ibm,ppc-interrupt-server#s" of the second group is
766 * {9,11,13,15}. Property "2" indicates that the threads in each
767 * group share the L2-cache.
768 *
769 * Returns 0 on success, -EINVAL if the property does not exist,
770 * -ENODATA if property does not have a value, and -EOVERFLOW if the
771 * property data isn't large enough.
772 */
parse_thread_groups(struct device_node * dn,struct thread_groups_list * tglp)773 static int parse_thread_groups(struct device_node *dn,
774 struct thread_groups_list *tglp)
775 {
776 unsigned int property_idx = 0;
777 u32 *thread_group_array;
778 size_t total_threads;
779 int ret = 0, count;
780 u32 *thread_list;
781 int i = 0;
782
783 count = of_property_count_u32_elems(dn, "ibm,thread-groups");
784 thread_group_array = kcalloc(count, sizeof(u32), GFP_KERNEL);
785 ret = of_property_read_u32_array(dn, "ibm,thread-groups",
786 thread_group_array, count);
787 if (ret)
788 goto out_free;
789
790 while (i < count && property_idx < MAX_THREAD_GROUP_PROPERTIES) {
791 int j;
792 struct thread_groups *tg = &tglp->property_tgs[property_idx++];
793
794 tg->property = thread_group_array[i];
795 tg->nr_groups = thread_group_array[i + 1];
796 tg->threads_per_group = thread_group_array[i + 2];
797 total_threads = tg->nr_groups * tg->threads_per_group;
798
799 thread_list = &thread_group_array[i + 3];
800
801 for (j = 0; j < total_threads; j++)
802 tg->thread_list[j] = thread_list[j];
803 i = i + 3 + total_threads;
804 }
805
806 tglp->nr_properties = property_idx;
807
808 out_free:
809 kfree(thread_group_array);
810 return ret;
811 }
812
813 /*
814 * get_cpu_thread_group_start : Searches the thread group in tg->thread_list
815 * that @cpu belongs to.
816 *
817 * @cpu : The logical CPU whose thread group is being searched.
818 * @tg : The thread-group structure of the CPU node which @cpu belongs
819 * to.
820 *
821 * Returns the index to tg->thread_list that points to the the start
822 * of the thread_group that @cpu belongs to.
823 *
824 * Returns -1 if cpu doesn't belong to any of the groups pointed to by
825 * tg->thread_list.
826 */
get_cpu_thread_group_start(int cpu,struct thread_groups * tg)827 static int get_cpu_thread_group_start(int cpu, struct thread_groups *tg)
828 {
829 int hw_cpu_id = get_hard_smp_processor_id(cpu);
830 int i, j;
831
832 for (i = 0; i < tg->nr_groups; i++) {
833 int group_start = i * tg->threads_per_group;
834
835 for (j = 0; j < tg->threads_per_group; j++) {
836 int idx = group_start + j;
837
838 if (tg->thread_list[idx] == hw_cpu_id)
839 return group_start;
840 }
841 }
842
843 return -1;
844 }
845
get_thread_groups(int cpu,int group_property,int * err)846 static struct thread_groups *__init get_thread_groups(int cpu,
847 int group_property,
848 int *err)
849 {
850 struct device_node *dn = of_get_cpu_node(cpu, NULL);
851 struct thread_groups_list *cpu_tgl = &tgl[cpu];
852 struct thread_groups *tg = NULL;
853 int i;
854 *err = 0;
855
856 if (!dn) {
857 *err = -ENODATA;
858 return NULL;
859 }
860
861 if (!cpu_tgl->nr_properties) {
862 *err = parse_thread_groups(dn, cpu_tgl);
863 if (*err)
864 goto out;
865 }
866
867 for (i = 0; i < cpu_tgl->nr_properties; i++) {
868 if (cpu_tgl->property_tgs[i].property == group_property) {
869 tg = &cpu_tgl->property_tgs[i];
870 break;
871 }
872 }
873
874 if (!tg)
875 *err = -EINVAL;
876 out:
877 of_node_put(dn);
878 return tg;
879 }
880
init_thread_group_cache_map(int cpu,int cache_property)881 static int __init init_thread_group_cache_map(int cpu, int cache_property)
882
883 {
884 int first_thread = cpu_first_thread_sibling(cpu);
885 int i, cpu_group_start = -1, err = 0;
886 struct thread_groups *tg = NULL;
887 cpumask_var_t *mask = NULL;
888
889 if (cache_property != THREAD_GROUP_SHARE_L1 &&
890 cache_property != THREAD_GROUP_SHARE_L2)
891 return -EINVAL;
892
893 tg = get_thread_groups(cpu, cache_property, &err);
894 if (!tg)
895 return err;
896
897 cpu_group_start = get_cpu_thread_group_start(cpu, tg);
898
899 if (unlikely(cpu_group_start == -1)) {
900 WARN_ON_ONCE(1);
901 return -ENODATA;
902 }
903
904 if (cache_property == THREAD_GROUP_SHARE_L1)
905 mask = &per_cpu(thread_group_l1_cache_map, cpu);
906 else if (cache_property == THREAD_GROUP_SHARE_L2)
907 mask = &per_cpu(thread_group_l2_cache_map, cpu);
908
909 zalloc_cpumask_var_node(mask, GFP_KERNEL, cpu_to_node(cpu));
910
911 for (i = first_thread; i < first_thread + threads_per_core; i++) {
912 int i_group_start = get_cpu_thread_group_start(i, tg);
913
914 if (unlikely(i_group_start == -1)) {
915 WARN_ON_ONCE(1);
916 return -ENODATA;
917 }
918
919 if (i_group_start == cpu_group_start)
920 cpumask_set_cpu(i, *mask);
921 }
922
923 return 0;
924 }
925
926 static bool shared_caches;
927
928 #ifdef CONFIG_SCHED_SMT
929 /* cpumask of CPUs with asymmetric SMT dependency */
powerpc_smt_flags(void)930 static int powerpc_smt_flags(void)
931 {
932 int flags = SD_SHARE_CPUCAPACITY | SD_SHARE_PKG_RESOURCES;
933
934 if (cpu_has_feature(CPU_FTR_ASYM_SMT)) {
935 printk_once(KERN_INFO "Enabling Asymmetric SMT scheduling\n");
936 flags |= SD_ASYM_PACKING;
937 }
938 return flags;
939 }
940 #endif
941
942 /*
943 * P9 has a slightly odd architecture where pairs of cores share an L2 cache.
944 * This topology makes it *much* cheaper to migrate tasks between adjacent cores
945 * since the migrated task remains cache hot. We want to take advantage of this
946 * at the scheduler level so an extra topology level is required.
947 */
powerpc_shared_cache_flags(void)948 static int powerpc_shared_cache_flags(void)
949 {
950 return SD_SHARE_PKG_RESOURCES;
951 }
952
953 /*
954 * We can't just pass cpu_l2_cache_mask() directly because
955 * returns a non-const pointer and the compiler barfs on that.
956 */
shared_cache_mask(int cpu)957 static const struct cpumask *shared_cache_mask(int cpu)
958 {
959 return per_cpu(cpu_l2_cache_map, cpu);
960 }
961
962 #ifdef CONFIG_SCHED_SMT
smallcore_smt_mask(int cpu)963 static const struct cpumask *smallcore_smt_mask(int cpu)
964 {
965 return cpu_smallcore_mask(cpu);
966 }
967 #endif
968
cpu_coregroup_mask(int cpu)969 static struct cpumask *cpu_coregroup_mask(int cpu)
970 {
971 return per_cpu(cpu_coregroup_map, cpu);
972 }
973
has_coregroup_support(void)974 static bool has_coregroup_support(void)
975 {
976 return coregroup_enabled;
977 }
978
cpu_mc_mask(int cpu)979 static const struct cpumask *cpu_mc_mask(int cpu)
980 {
981 return cpu_coregroup_mask(cpu);
982 }
983
984 static struct sched_domain_topology_level powerpc_topology[] = {
985 #ifdef CONFIG_SCHED_SMT
986 { cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) },
987 #endif
988 { shared_cache_mask, powerpc_shared_cache_flags, SD_INIT_NAME(CACHE) },
989 { cpu_mc_mask, SD_INIT_NAME(MC) },
990 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
991 { NULL, },
992 };
993
init_big_cores(void)994 static int __init init_big_cores(void)
995 {
996 int cpu;
997
998 for_each_possible_cpu(cpu) {
999 int err = init_thread_group_cache_map(cpu, THREAD_GROUP_SHARE_L1);
1000
1001 if (err)
1002 return err;
1003
1004 zalloc_cpumask_var_node(&per_cpu(cpu_smallcore_map, cpu),
1005 GFP_KERNEL,
1006 cpu_to_node(cpu));
1007 }
1008
1009 has_big_cores = true;
1010
1011 for_each_possible_cpu(cpu) {
1012 int err = init_thread_group_cache_map(cpu, THREAD_GROUP_SHARE_L2);
1013
1014 if (err)
1015 return err;
1016 }
1017
1018 thread_group_shares_l2 = true;
1019 pr_debug("L2 cache only shared by the threads in the small core\n");
1020 return 0;
1021 }
1022
smp_prepare_cpus(unsigned int max_cpus)1023 void __init smp_prepare_cpus(unsigned int max_cpus)
1024 {
1025 unsigned int cpu;
1026
1027 DBG("smp_prepare_cpus\n");
1028
1029 /*
1030 * setup_cpu may need to be called on the boot cpu. We havent
1031 * spun any cpus up but lets be paranoid.
1032 */
1033 BUG_ON(boot_cpuid != smp_processor_id());
1034
1035 /* Fixup boot cpu */
1036 smp_store_cpu_info(boot_cpuid);
1037 cpu_callin_map[boot_cpuid] = 1;
1038
1039 for_each_possible_cpu(cpu) {
1040 zalloc_cpumask_var_node(&per_cpu(cpu_sibling_map, cpu),
1041 GFP_KERNEL, cpu_to_node(cpu));
1042 zalloc_cpumask_var_node(&per_cpu(cpu_l2_cache_map, cpu),
1043 GFP_KERNEL, cpu_to_node(cpu));
1044 zalloc_cpumask_var_node(&per_cpu(cpu_core_map, cpu),
1045 GFP_KERNEL, cpu_to_node(cpu));
1046 if (has_coregroup_support())
1047 zalloc_cpumask_var_node(&per_cpu(cpu_coregroup_map, cpu),
1048 GFP_KERNEL, cpu_to_node(cpu));
1049
1050 #ifdef CONFIG_NEED_MULTIPLE_NODES
1051 /*
1052 * numa_node_id() works after this.
1053 */
1054 if (cpu_present(cpu)) {
1055 set_cpu_numa_node(cpu, numa_cpu_lookup_table[cpu]);
1056 set_cpu_numa_mem(cpu,
1057 local_memory_node(numa_cpu_lookup_table[cpu]));
1058 }
1059 #endif
1060 }
1061
1062 /* Init the cpumasks so the boot CPU is related to itself */
1063 cpumask_set_cpu(boot_cpuid, cpu_sibling_mask(boot_cpuid));
1064 cpumask_set_cpu(boot_cpuid, cpu_l2_cache_mask(boot_cpuid));
1065 cpumask_set_cpu(boot_cpuid, cpu_core_mask(boot_cpuid));
1066
1067 if (has_coregroup_support())
1068 cpumask_set_cpu(boot_cpuid, cpu_coregroup_mask(boot_cpuid));
1069
1070 init_big_cores();
1071 if (has_big_cores) {
1072 cpumask_set_cpu(boot_cpuid,
1073 cpu_smallcore_mask(boot_cpuid));
1074 }
1075
1076 if (cpu_to_chip_id(boot_cpuid) != -1) {
1077 int idx = num_possible_cpus() / threads_per_core;
1078
1079 /*
1080 * All threads of a core will all belong to the same core,
1081 * chip_id_lookup_table will have one entry per core.
1082 * Assumption: if boot_cpuid doesn't have a chip-id, then no
1083 * other CPUs, will also not have chip-id.
1084 */
1085 chip_id_lookup_table = kcalloc(idx, sizeof(int), GFP_KERNEL);
1086 if (chip_id_lookup_table)
1087 memset(chip_id_lookup_table, -1, sizeof(int) * idx);
1088 }
1089
1090 if (smp_ops && smp_ops->probe)
1091 smp_ops->probe();
1092 }
1093
smp_prepare_boot_cpu(void)1094 void smp_prepare_boot_cpu(void)
1095 {
1096 BUG_ON(smp_processor_id() != boot_cpuid);
1097 #ifdef CONFIG_PPC64
1098 paca_ptrs[boot_cpuid]->__current = current;
1099 #endif
1100 set_numa_node(numa_cpu_lookup_table[boot_cpuid]);
1101 current_set[boot_cpuid] = current;
1102 }
1103
1104 #ifdef CONFIG_HOTPLUG_CPU
1105
generic_cpu_disable(void)1106 int generic_cpu_disable(void)
1107 {
1108 unsigned int cpu = smp_processor_id();
1109
1110 if (cpu == boot_cpuid)
1111 return -EBUSY;
1112
1113 set_cpu_online(cpu, false);
1114 #ifdef CONFIG_PPC64
1115 vdso_data->processorCount--;
1116 #endif
1117 /* Update affinity of all IRQs previously aimed at this CPU */
1118 irq_migrate_all_off_this_cpu();
1119
1120 /*
1121 * Depending on the details of the interrupt controller, it's possible
1122 * that one of the interrupts we just migrated away from this CPU is
1123 * actually already pending on this CPU. If we leave it in that state
1124 * the interrupt will never be EOI'ed, and will never fire again. So
1125 * temporarily enable interrupts here, to allow any pending interrupt to
1126 * be received (and EOI'ed), before we take this CPU offline.
1127 */
1128 local_irq_enable();
1129 mdelay(1);
1130 local_irq_disable();
1131
1132 return 0;
1133 }
1134
generic_cpu_die(unsigned int cpu)1135 void generic_cpu_die(unsigned int cpu)
1136 {
1137 int i;
1138
1139 for (i = 0; i < 100; i++) {
1140 smp_rmb();
1141 if (is_cpu_dead(cpu))
1142 return;
1143 msleep(100);
1144 }
1145 printk(KERN_ERR "CPU%d didn't die...\n", cpu);
1146 }
1147
generic_set_cpu_dead(unsigned int cpu)1148 void generic_set_cpu_dead(unsigned int cpu)
1149 {
1150 per_cpu(cpu_state, cpu) = CPU_DEAD;
1151 }
1152
1153 /*
1154 * The cpu_state should be set to CPU_UP_PREPARE in kick_cpu(), otherwise
1155 * the cpu_state is always CPU_DEAD after calling generic_set_cpu_dead(),
1156 * which makes the delay in generic_cpu_die() not happen.
1157 */
generic_set_cpu_up(unsigned int cpu)1158 void generic_set_cpu_up(unsigned int cpu)
1159 {
1160 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
1161 }
1162
generic_check_cpu_restart(unsigned int cpu)1163 int generic_check_cpu_restart(unsigned int cpu)
1164 {
1165 return per_cpu(cpu_state, cpu) == CPU_UP_PREPARE;
1166 }
1167
is_cpu_dead(unsigned int cpu)1168 int is_cpu_dead(unsigned int cpu)
1169 {
1170 return per_cpu(cpu_state, cpu) == CPU_DEAD;
1171 }
1172
secondaries_inhibited(void)1173 static bool secondaries_inhibited(void)
1174 {
1175 return kvm_hv_mode_active();
1176 }
1177
1178 #else /* HOTPLUG_CPU */
1179
1180 #define secondaries_inhibited() 0
1181
1182 #endif
1183
cpu_idle_thread_init(unsigned int cpu,struct task_struct * idle)1184 static void cpu_idle_thread_init(unsigned int cpu, struct task_struct *idle)
1185 {
1186 #ifdef CONFIG_PPC64
1187 paca_ptrs[cpu]->__current = idle;
1188 paca_ptrs[cpu]->kstack = (unsigned long)task_stack_page(idle) +
1189 THREAD_SIZE - STACK_FRAME_OVERHEAD;
1190 #endif
1191 idle->cpu = cpu;
1192 secondary_current = current_set[cpu] = idle;
1193 }
1194
__cpu_up(unsigned int cpu,struct task_struct * tidle)1195 int __cpu_up(unsigned int cpu, struct task_struct *tidle)
1196 {
1197 int rc, c;
1198
1199 /*
1200 * Don't allow secondary threads to come online if inhibited
1201 */
1202 if (threads_per_core > 1 && secondaries_inhibited() &&
1203 cpu_thread_in_subcore(cpu))
1204 return -EBUSY;
1205
1206 if (smp_ops == NULL ||
1207 (smp_ops->cpu_bootable && !smp_ops->cpu_bootable(cpu)))
1208 return -EINVAL;
1209
1210 cpu_idle_thread_init(cpu, tidle);
1211
1212 /*
1213 * The platform might need to allocate resources prior to bringing
1214 * up the CPU
1215 */
1216 if (smp_ops->prepare_cpu) {
1217 rc = smp_ops->prepare_cpu(cpu);
1218 if (rc)
1219 return rc;
1220 }
1221
1222 /* Make sure callin-map entry is 0 (can be leftover a CPU
1223 * hotplug
1224 */
1225 cpu_callin_map[cpu] = 0;
1226
1227 /* The information for processor bringup must
1228 * be written out to main store before we release
1229 * the processor.
1230 */
1231 smp_mb();
1232
1233 /* wake up cpus */
1234 DBG("smp: kicking cpu %d\n", cpu);
1235 rc = smp_ops->kick_cpu(cpu);
1236 if (rc) {
1237 pr_err("smp: failed starting cpu %d (rc %d)\n", cpu, rc);
1238 return rc;
1239 }
1240
1241 /*
1242 * wait to see if the cpu made a callin (is actually up).
1243 * use this value that I found through experimentation.
1244 * -- Cort
1245 */
1246 if (system_state < SYSTEM_RUNNING)
1247 for (c = 50000; c && !cpu_callin_map[cpu]; c--)
1248 udelay(100);
1249 #ifdef CONFIG_HOTPLUG_CPU
1250 else
1251 /*
1252 * CPUs can take much longer to come up in the
1253 * hotplug case. Wait five seconds.
1254 */
1255 for (c = 5000; c && !cpu_callin_map[cpu]; c--)
1256 msleep(1);
1257 #endif
1258
1259 if (!cpu_callin_map[cpu]) {
1260 printk(KERN_ERR "Processor %u is stuck.\n", cpu);
1261 return -ENOENT;
1262 }
1263
1264 DBG("Processor %u found.\n", cpu);
1265
1266 if (smp_ops->give_timebase)
1267 smp_ops->give_timebase();
1268
1269 /* Wait until cpu puts itself in the online & active maps */
1270 spin_until_cond(cpu_online(cpu));
1271
1272 return 0;
1273 }
1274
1275 /* Return the value of the reg property corresponding to the given
1276 * logical cpu.
1277 */
cpu_to_core_id(int cpu)1278 int cpu_to_core_id(int cpu)
1279 {
1280 struct device_node *np;
1281 const __be32 *reg;
1282 int id = -1;
1283
1284 np = of_get_cpu_node(cpu, NULL);
1285 if (!np)
1286 goto out;
1287
1288 reg = of_get_property(np, "reg", NULL);
1289 if (!reg)
1290 goto out;
1291
1292 id = be32_to_cpup(reg);
1293 out:
1294 of_node_put(np);
1295 return id;
1296 }
1297 EXPORT_SYMBOL_GPL(cpu_to_core_id);
1298
1299 /* Helper routines for cpu to core mapping */
cpu_core_index_of_thread(int cpu)1300 int cpu_core_index_of_thread(int cpu)
1301 {
1302 return cpu >> threads_shift;
1303 }
1304 EXPORT_SYMBOL_GPL(cpu_core_index_of_thread);
1305
cpu_first_thread_of_core(int core)1306 int cpu_first_thread_of_core(int core)
1307 {
1308 return core << threads_shift;
1309 }
1310 EXPORT_SYMBOL_GPL(cpu_first_thread_of_core);
1311
1312 /* Must be called when no change can occur to cpu_present_mask,
1313 * i.e. during cpu online or offline.
1314 */
cpu_to_l2cache(int cpu)1315 static struct device_node *cpu_to_l2cache(int cpu)
1316 {
1317 struct device_node *np;
1318 struct device_node *cache;
1319
1320 if (!cpu_present(cpu))
1321 return NULL;
1322
1323 np = of_get_cpu_node(cpu, NULL);
1324 if (np == NULL)
1325 return NULL;
1326
1327 cache = of_find_next_cache_node(np);
1328
1329 of_node_put(np);
1330
1331 return cache;
1332 }
1333
update_mask_by_l2(int cpu,cpumask_var_t * mask)1334 static bool update_mask_by_l2(int cpu, cpumask_var_t *mask)
1335 {
1336 struct cpumask *(*submask_fn)(int) = cpu_sibling_mask;
1337 struct device_node *l2_cache, *np;
1338 int i;
1339
1340 if (has_big_cores)
1341 submask_fn = cpu_smallcore_mask;
1342
1343 /*
1344 * If the threads in a thread-group share L2 cache, then the
1345 * L2-mask can be obtained from thread_group_l2_cache_map.
1346 */
1347 if (thread_group_shares_l2) {
1348 cpumask_set_cpu(cpu, cpu_l2_cache_mask(cpu));
1349
1350 for_each_cpu(i, per_cpu(thread_group_l2_cache_map, cpu)) {
1351 if (cpu_online(i))
1352 set_cpus_related(i, cpu, cpu_l2_cache_mask);
1353 }
1354
1355 /* Verify that L1-cache siblings are a subset of L2 cache-siblings */
1356 if (!cpumask_equal(submask_fn(cpu), cpu_l2_cache_mask(cpu)) &&
1357 !cpumask_subset(submask_fn(cpu), cpu_l2_cache_mask(cpu))) {
1358 pr_warn_once("CPU %d : Inconsistent L1 and L2 cache siblings\n",
1359 cpu);
1360 }
1361
1362 return true;
1363 }
1364
1365 l2_cache = cpu_to_l2cache(cpu);
1366 if (!l2_cache || !*mask) {
1367 /* Assume only core siblings share cache with this CPU */
1368 for_each_cpu(i, submask_fn(cpu))
1369 set_cpus_related(cpu, i, cpu_l2_cache_mask);
1370
1371 return false;
1372 }
1373
1374 cpumask_and(*mask, cpu_online_mask, cpu_cpu_mask(cpu));
1375
1376 /* Update l2-cache mask with all the CPUs that are part of submask */
1377 or_cpumasks_related(cpu, cpu, submask_fn, cpu_l2_cache_mask);
1378
1379 /* Skip all CPUs already part of current CPU l2-cache mask */
1380 cpumask_andnot(*mask, *mask, cpu_l2_cache_mask(cpu));
1381
1382 for_each_cpu(i, *mask) {
1383 /*
1384 * when updating the marks the current CPU has not been marked
1385 * online, but we need to update the cache masks
1386 */
1387 np = cpu_to_l2cache(i);
1388
1389 /* Skip all CPUs already part of current CPU l2-cache */
1390 if (np == l2_cache) {
1391 or_cpumasks_related(cpu, i, submask_fn, cpu_l2_cache_mask);
1392 cpumask_andnot(*mask, *mask, submask_fn(i));
1393 } else {
1394 cpumask_andnot(*mask, *mask, cpu_l2_cache_mask(i));
1395 }
1396
1397 of_node_put(np);
1398 }
1399 of_node_put(l2_cache);
1400
1401 return true;
1402 }
1403
1404 #ifdef CONFIG_HOTPLUG_CPU
remove_cpu_from_masks(int cpu)1405 static void remove_cpu_from_masks(int cpu)
1406 {
1407 struct cpumask *(*mask_fn)(int) = cpu_sibling_mask;
1408 int i;
1409
1410 if (shared_caches)
1411 mask_fn = cpu_l2_cache_mask;
1412
1413 for_each_cpu(i, mask_fn(cpu)) {
1414 set_cpus_unrelated(cpu, i, cpu_l2_cache_mask);
1415 set_cpus_unrelated(cpu, i, cpu_sibling_mask);
1416 if (has_big_cores)
1417 set_cpus_unrelated(cpu, i, cpu_smallcore_mask);
1418 }
1419
1420 for_each_cpu(i, cpu_core_mask(cpu))
1421 set_cpus_unrelated(cpu, i, cpu_core_mask);
1422
1423 if (has_coregroup_support()) {
1424 for_each_cpu(i, cpu_coregroup_mask(cpu))
1425 set_cpus_unrelated(cpu, i, cpu_coregroup_mask);
1426 }
1427 }
1428 #endif
1429
add_cpu_to_smallcore_masks(int cpu)1430 static inline void add_cpu_to_smallcore_masks(int cpu)
1431 {
1432 int i;
1433
1434 if (!has_big_cores)
1435 return;
1436
1437 cpumask_set_cpu(cpu, cpu_smallcore_mask(cpu));
1438
1439 for_each_cpu(i, per_cpu(thread_group_l1_cache_map, cpu)) {
1440 if (cpu_online(i))
1441 set_cpus_related(i, cpu, cpu_smallcore_mask);
1442 }
1443 }
1444
update_coregroup_mask(int cpu,cpumask_var_t * mask)1445 static void update_coregroup_mask(int cpu, cpumask_var_t *mask)
1446 {
1447 struct cpumask *(*submask_fn)(int) = cpu_sibling_mask;
1448 int coregroup_id = cpu_to_coregroup_id(cpu);
1449 int i;
1450
1451 if (shared_caches)
1452 submask_fn = cpu_l2_cache_mask;
1453
1454 if (!*mask) {
1455 /* Assume only siblings are part of this CPU's coregroup */
1456 for_each_cpu(i, submask_fn(cpu))
1457 set_cpus_related(cpu, i, cpu_coregroup_mask);
1458
1459 return;
1460 }
1461
1462 cpumask_and(*mask, cpu_online_mask, cpu_cpu_mask(cpu));
1463
1464 /* Update coregroup mask with all the CPUs that are part of submask */
1465 or_cpumasks_related(cpu, cpu, submask_fn, cpu_coregroup_mask);
1466
1467 /* Skip all CPUs already part of coregroup mask */
1468 cpumask_andnot(*mask, *mask, cpu_coregroup_mask(cpu));
1469
1470 for_each_cpu(i, *mask) {
1471 /* Skip all CPUs not part of this coregroup */
1472 if (coregroup_id == cpu_to_coregroup_id(i)) {
1473 or_cpumasks_related(cpu, i, submask_fn, cpu_coregroup_mask);
1474 cpumask_andnot(*mask, *mask, submask_fn(i));
1475 } else {
1476 cpumask_andnot(*mask, *mask, cpu_coregroup_mask(i));
1477 }
1478 }
1479 }
1480
add_cpu_to_masks(int cpu)1481 static void add_cpu_to_masks(int cpu)
1482 {
1483 struct cpumask *(*submask_fn)(int) = cpu_sibling_mask;
1484 int first_thread = cpu_first_thread_sibling(cpu);
1485 cpumask_var_t mask;
1486 int chip_id = -1;
1487 bool ret;
1488 int i;
1489
1490 /*
1491 * This CPU will not be in the online mask yet so we need to manually
1492 * add it to it's own thread sibling mask.
1493 */
1494 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
1495
1496 for (i = first_thread; i < first_thread + threads_per_core; i++)
1497 if (cpu_online(i))
1498 set_cpus_related(i, cpu, cpu_sibling_mask);
1499
1500 add_cpu_to_smallcore_masks(cpu);
1501
1502 /* In CPU-hotplug path, hence use GFP_ATOMIC */
1503 ret = alloc_cpumask_var_node(&mask, GFP_ATOMIC, cpu_to_node(cpu));
1504 update_mask_by_l2(cpu, &mask);
1505
1506 if (has_coregroup_support())
1507 update_coregroup_mask(cpu, &mask);
1508
1509 if (chip_id_lookup_table && ret)
1510 chip_id = cpu_to_chip_id(cpu);
1511
1512 if (chip_id == -1) {
1513 cpumask_copy(per_cpu(cpu_core_map, cpu), cpu_cpu_mask(cpu));
1514 goto out;
1515 }
1516
1517 if (shared_caches)
1518 submask_fn = cpu_l2_cache_mask;
1519
1520 /* Update core_mask with all the CPUs that are part of submask */
1521 or_cpumasks_related(cpu, cpu, submask_fn, cpu_core_mask);
1522
1523 /* Skip all CPUs already part of current CPU core mask */
1524 cpumask_andnot(mask, cpu_online_mask, cpu_core_mask(cpu));
1525
1526 for_each_cpu(i, mask) {
1527 if (chip_id == cpu_to_chip_id(i)) {
1528 or_cpumasks_related(cpu, i, submask_fn, cpu_core_mask);
1529 cpumask_andnot(mask, mask, submask_fn(i));
1530 } else {
1531 cpumask_andnot(mask, mask, cpu_core_mask(i));
1532 }
1533 }
1534
1535 out:
1536 free_cpumask_var(mask);
1537 }
1538
1539 /* Activate a secondary processor. */
start_secondary(void * unused)1540 void start_secondary(void *unused)
1541 {
1542 unsigned int cpu = raw_smp_processor_id();
1543
1544 mmgrab(&init_mm);
1545 current->active_mm = &init_mm;
1546
1547 smp_store_cpu_info(cpu);
1548 set_dec(tb_ticks_per_jiffy);
1549 rcu_cpu_starting(cpu);
1550 preempt_disable();
1551 cpu_callin_map[cpu] = 1;
1552
1553 if (smp_ops->setup_cpu)
1554 smp_ops->setup_cpu(cpu);
1555 if (smp_ops->take_timebase)
1556 smp_ops->take_timebase();
1557
1558 secondary_cpu_time_init();
1559
1560 #ifdef CONFIG_PPC64
1561 if (system_state == SYSTEM_RUNNING)
1562 vdso_data->processorCount++;
1563
1564 vdso_getcpu_init();
1565 #endif
1566 set_numa_node(numa_cpu_lookup_table[cpu]);
1567 set_numa_mem(local_memory_node(numa_cpu_lookup_table[cpu]));
1568
1569 /* Update topology CPU masks */
1570 add_cpu_to_masks(cpu);
1571
1572 /*
1573 * Check for any shared caches. Note that this must be done on a
1574 * per-core basis because one core in the pair might be disabled.
1575 */
1576 if (!shared_caches) {
1577 struct cpumask *(*sibling_mask)(int) = cpu_sibling_mask;
1578 struct cpumask *mask = cpu_l2_cache_mask(cpu);
1579
1580 if (has_big_cores)
1581 sibling_mask = cpu_smallcore_mask;
1582
1583 if (cpumask_weight(mask) > cpumask_weight(sibling_mask(cpu)))
1584 shared_caches = true;
1585 }
1586
1587 smp_wmb();
1588 notify_cpu_starting(cpu);
1589 set_cpu_online(cpu, true);
1590
1591 boot_init_stack_canary();
1592
1593 local_irq_enable();
1594
1595 /* We can enable ftrace for secondary cpus now */
1596 this_cpu_enable_ftrace();
1597
1598 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
1599
1600 BUG();
1601 }
1602
setup_profiling_timer(unsigned int multiplier)1603 int setup_profiling_timer(unsigned int multiplier)
1604 {
1605 return 0;
1606 }
1607
fixup_topology(void)1608 static void fixup_topology(void)
1609 {
1610 int i;
1611
1612 #ifdef CONFIG_SCHED_SMT
1613 if (has_big_cores) {
1614 pr_info("Big cores detected but using small core scheduling\n");
1615 powerpc_topology[smt_idx].mask = smallcore_smt_mask;
1616 }
1617 #endif
1618
1619 if (!has_coregroup_support())
1620 powerpc_topology[mc_idx].mask = powerpc_topology[cache_idx].mask;
1621
1622 /*
1623 * Try to consolidate topology levels here instead of
1624 * allowing scheduler to degenerate.
1625 * - Dont consolidate if masks are different.
1626 * - Dont consolidate if sd_flags exists and are different.
1627 */
1628 for (i = 1; i <= die_idx; i++) {
1629 if (powerpc_topology[i].mask != powerpc_topology[i - 1].mask)
1630 continue;
1631
1632 if (powerpc_topology[i].sd_flags && powerpc_topology[i - 1].sd_flags &&
1633 powerpc_topology[i].sd_flags != powerpc_topology[i - 1].sd_flags)
1634 continue;
1635
1636 if (!powerpc_topology[i - 1].sd_flags)
1637 powerpc_topology[i - 1].sd_flags = powerpc_topology[i].sd_flags;
1638
1639 powerpc_topology[i].mask = powerpc_topology[i + 1].mask;
1640 powerpc_topology[i].sd_flags = powerpc_topology[i + 1].sd_flags;
1641 #ifdef CONFIG_SCHED_DEBUG
1642 powerpc_topology[i].name = powerpc_topology[i + 1].name;
1643 #endif
1644 }
1645 }
1646
smp_cpus_done(unsigned int max_cpus)1647 void __init smp_cpus_done(unsigned int max_cpus)
1648 {
1649 /*
1650 * We are running pinned to the boot CPU, see rest_init().
1651 */
1652 if (smp_ops && smp_ops->setup_cpu)
1653 smp_ops->setup_cpu(boot_cpuid);
1654
1655 if (smp_ops && smp_ops->bringup_done)
1656 smp_ops->bringup_done();
1657
1658 dump_numa_cpu_topology();
1659
1660 fixup_topology();
1661 set_sched_topology(powerpc_topology);
1662 }
1663
1664 #ifdef CONFIG_HOTPLUG_CPU
__cpu_disable(void)1665 int __cpu_disable(void)
1666 {
1667 int cpu = smp_processor_id();
1668 int err;
1669
1670 if (!smp_ops->cpu_disable)
1671 return -ENOSYS;
1672
1673 this_cpu_disable_ftrace();
1674
1675 err = smp_ops->cpu_disable();
1676 if (err)
1677 return err;
1678
1679 /* Update sibling maps */
1680 remove_cpu_from_masks(cpu);
1681
1682 return 0;
1683 }
1684
__cpu_die(unsigned int cpu)1685 void __cpu_die(unsigned int cpu)
1686 {
1687 if (smp_ops->cpu_die)
1688 smp_ops->cpu_die(cpu);
1689 }
1690
arch_cpu_idle_dead(void)1691 void arch_cpu_idle_dead(void)
1692 {
1693 sched_preempt_enable_no_resched();
1694
1695 /*
1696 * Disable on the down path. This will be re-enabled by
1697 * start_secondary() via start_secondary_resume() below
1698 */
1699 this_cpu_disable_ftrace();
1700
1701 if (smp_ops->cpu_offline_self)
1702 smp_ops->cpu_offline_self();
1703
1704 /* If we return, we re-enter start_secondary */
1705 start_secondary_resume();
1706 }
1707
1708 #endif
1709