1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __SMU_V13_0_H__ 24 #define __SMU_V13_0_H__ 25 26 #include "amdgpu_smu.h" 27 28 #define SMU13_DRIVER_IF_VERSION_INV 0xFFFFFFFF 29 #define SMU13_DRIVER_IF_VERSION_ALDE 0x6 30 31 /* MP Apertures */ 32 #define MP0_Public 0x03800000 33 #define MP0_SRAM 0x03900000 34 #define MP1_Public 0x03b00000 35 #define MP1_SRAM 0x03c00004 36 37 /* address block */ 38 #define smnMP1_FIRMWARE_FLAGS 0x3010024 39 #define smnMP0_FW_INTF 0x30101c0 40 #define smnMP1_PUB_CTRL 0x3010b14 41 42 #define TEMP_RANGE_MIN (0) 43 #define TEMP_RANGE_MAX (80 * 1000) 44 45 #define SMU13_TOOL_SIZE 0x19000 46 47 #define MAX_DPM_LEVELS 16 48 #define MAX_PCIE_CONF 2 49 50 #define CTF_OFFSET_EDGE 5 51 #define CTF_OFFSET_HOTSPOT 5 52 #define CTF_OFFSET_MEM 5 53 54 static const struct smu_temperature_range smu13_thermal_policy[] = 55 { 56 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000}, 57 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000}, 58 }; 59 60 struct smu_13_0_max_sustainable_clocks { 61 uint32_t display_clock; 62 uint32_t phy_clock; 63 uint32_t pixel_clock; 64 uint32_t uclock; 65 uint32_t dcef_clock; 66 uint32_t soc_clock; 67 }; 68 69 struct smu_13_0_dpm_clk_level { 70 bool enabled; 71 uint32_t value; 72 }; 73 74 struct smu_13_0_dpm_table { 75 uint32_t min; /* MHz */ 76 uint32_t max; /* MHz */ 77 uint32_t count; 78 struct smu_13_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS]; 79 }; 80 81 struct smu_13_0_pcie_table { 82 uint8_t pcie_gen[MAX_PCIE_CONF]; 83 uint8_t pcie_lane[MAX_PCIE_CONF]; 84 }; 85 86 struct smu_13_0_dpm_tables { 87 struct smu_13_0_dpm_table soc_table; 88 struct smu_13_0_dpm_table gfx_table; 89 struct smu_13_0_dpm_table uclk_table; 90 struct smu_13_0_dpm_table eclk_table; 91 struct smu_13_0_dpm_table vclk_table; 92 struct smu_13_0_dpm_table dclk_table; 93 struct smu_13_0_dpm_table dcef_table; 94 struct smu_13_0_dpm_table pixel_table; 95 struct smu_13_0_dpm_table display_table; 96 struct smu_13_0_dpm_table phy_table; 97 struct smu_13_0_dpm_table fclk_table; 98 struct smu_13_0_pcie_table pcie_table; 99 }; 100 101 struct smu_13_0_dpm_context { 102 struct smu_13_0_dpm_tables dpm_tables; 103 uint32_t workload_policy_mask; 104 uint32_t dcef_min_ds_clk; 105 }; 106 107 enum smu_13_0_power_state { 108 SMU_13_0_POWER_STATE__D0 = 0, 109 SMU_13_0_POWER_STATE__D1, 110 SMU_13_0_POWER_STATE__D3, /* Sleep*/ 111 SMU_13_0_POWER_STATE__D4, /* Hibernate*/ 112 SMU_13_0_POWER_STATE__D5, /* Power off*/ 113 }; 114 115 struct smu_13_0_power_context { 116 uint32_t power_source; 117 uint8_t in_power_limit_boost_mode; 118 enum smu_13_0_power_state power_state; 119 }; 120 121 enum smu_v13_0_baco_seq { 122 BACO_SEQ_BACO = 0, 123 BACO_SEQ_MSR, 124 BACO_SEQ_BAMACO, 125 BACO_SEQ_ULPS, 126 BACO_SEQ_COUNT, 127 }; 128 129 #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) 130 131 int smu_v13_0_init_microcode(struct smu_context *smu); 132 133 void smu_v13_0_fini_microcode(struct smu_context *smu); 134 135 int smu_v13_0_load_microcode(struct smu_context *smu); 136 137 int smu_v13_0_init_smc_tables(struct smu_context *smu); 138 139 int smu_v13_0_fini_smc_tables(struct smu_context *smu); 140 141 int smu_v13_0_init_power(struct smu_context *smu); 142 143 int smu_v13_0_fini_power(struct smu_context *smu); 144 145 int smu_v13_0_check_fw_status(struct smu_context *smu); 146 147 int smu_v13_0_setup_pptable(struct smu_context *smu); 148 149 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu); 150 151 int smu_v13_0_check_fw_version(struct smu_context *smu); 152 153 int smu_v13_0_set_driver_table_location(struct smu_context *smu); 154 155 int smu_v13_0_set_tool_table_location(struct smu_context *smu); 156 157 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu); 158 159 int smu_v13_0_system_features_control(struct smu_context *smu, 160 bool en); 161 162 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count); 163 164 int smu_v13_0_set_allowed_mask(struct smu_context *smu); 165 166 int smu_v13_0_notify_display_change(struct smu_context *smu); 167 168 int smu_v13_0_get_current_power_limit(struct smu_context *smu, 169 uint32_t *power_limit); 170 171 int smu_v13_0_set_power_limit(struct smu_context *smu, uint32_t n); 172 173 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu); 174 175 int smu_v13_0_enable_thermal_alert(struct smu_context *smu); 176 177 int smu_v13_0_disable_thermal_alert(struct smu_context *smu); 178 179 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value); 180 181 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk); 182 183 int 184 smu_v13_0_display_clock_voltage_request(struct smu_context *smu, 185 struct pp_display_clock_request 186 *clock_req); 187 188 uint32_t 189 smu_v13_0_get_fan_control_mode(struct smu_context *smu); 190 191 int 192 smu_v13_0_set_fan_control_mode(struct smu_context *smu, 193 uint32_t mode); 194 195 int 196 smu_v13_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed); 197 198 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu, 199 uint32_t speed); 200 201 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu, 202 uint32_t pstate); 203 204 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable); 205 206 int smu_v13_0_register_irq_handler(struct smu_context *smu); 207 208 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu); 209 210 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu, 211 struct pp_smu_nv_clock_table *max_clocks); 212 213 bool smu_v13_0_baco_is_support(struct smu_context *smu); 214 215 enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu); 216 217 int smu_v13_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state); 218 219 int smu_v13_0_baco_enter(struct smu_context *smu); 220 int smu_v13_0_baco_exit(struct smu_context *smu); 221 222 int smu_v13_0_mode1_reset(struct smu_context *smu); 223 int smu_v13_0_mode2_reset(struct smu_context *smu); 224 225 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, 226 uint32_t *min, uint32_t *max); 227 228 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, 229 uint32_t min, uint32_t max); 230 231 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu, 232 enum smu_clk_type clk_type, 233 uint32_t min, 234 uint32_t max); 235 236 int smu_v13_0_set_performance_level(struct smu_context *smu, 237 enum amd_dpm_forced_level level); 238 239 int smu_v13_0_set_power_source(struct smu_context *smu, 240 enum smu_power_src_type power_src); 241 242 int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu, 243 enum smu_clk_type clk_type, 244 uint16_t level, 245 uint32_t *value); 246 247 int smu_v13_0_get_dpm_level_count(struct smu_context *smu, 248 enum smu_clk_type clk_type, 249 uint32_t *value); 250 251 int smu_v13_0_set_single_dpm_table(struct smu_context *smu, 252 enum smu_clk_type clk_type, 253 struct smu_13_0_dpm_table *single_dpm_table); 254 255 int smu_v13_0_get_dpm_level_range(struct smu_context *smu, 256 enum smu_clk_type clk_type, 257 uint32_t *min_value, 258 uint32_t *max_value); 259 260 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu); 261 262 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu); 263 264 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu); 265 266 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu); 267 268 int smu_v13_0_gfx_ulv_control(struct smu_context *smu, 269 bool enablement); 270 271 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event, 272 uint64_t event_arg); 273 274 #endif 275 #endif 276