1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/export.h>
29 #include <linux/i2c.h>
30 #include <linux/notifier.h>
31 #include <linux/slab.h>
32 #include <linux/types.h>
33
34 #include <asm/byteorder.h>
35
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_dp_helper.h>
39 #include <drm/drm_edid.h>
40 #include <drm/drm_probe_helper.h>
41
42 #include "g4x_dp.h"
43 #include "i915_debugfs.h"
44 #include "i915_drv.h"
45 #include "intel_atomic.h"
46 #include "intel_audio.h"
47 #include "intel_connector.h"
48 #include "intel_ddi.h"
49 #include "intel_display_types.h"
50 #include "intel_dp.h"
51 #include "intel_dp_aux.h"
52 #include "intel_dp_link_training.h"
53 #include "intel_dp_mst.h"
54 #include "intel_dpll.h"
55 #include "intel_dpio_phy.h"
56 #include "intel_fifo_underrun.h"
57 #include "intel_hdcp.h"
58 #include "intel_hdmi.h"
59 #include "intel_hotplug.h"
60 #include "intel_lspcon.h"
61 #include "intel_lvds.h"
62 #include "intel_panel.h"
63 #include "intel_pps.h"
64 #include "intel_psr.h"
65 #include "intel_sideband.h"
66 #include "intel_tc.h"
67 #include "intel_vdsc.h"
68 #include "intel_vrr.h"
69
70 #define DP_DPRX_ESI_LEN 14
71
72 /* DP DSC throughput values used for slice count calculations KPixels/s */
73 #define DP_DSC_PEAK_PIXEL_RATE 2720000
74 #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
75 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000
76
77 /* DP DSC FEC Overhead factor = 1/(0.972261) */
78 #define DP_DSC_FEC_OVERHEAD_FACTOR 972261
79
80 /* Compliance test status bits */
81 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
82 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
83 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
84 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
85
86
87 /* Constants for DP DSC configurations */
88 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
89
90 /* With Single pipe configuration, HW is capable of supporting maximum
91 * of 4 slices per line.
92 */
93 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
94
95 /**
96 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
97 * @intel_dp: DP struct
98 *
99 * If a CPU or PCH DP output is attached to an eDP panel, this function
100 * will return true, and false otherwise.
101 */
intel_dp_is_edp(struct intel_dp * intel_dp)102 bool intel_dp_is_edp(struct intel_dp *intel_dp)
103 {
104 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
105
106 return dig_port->base.type == INTEL_OUTPUT_EDP;
107 }
108
109 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
110
111 /* update sink rates from dpcd */
intel_dp_set_sink_rates(struct intel_dp * intel_dp)112 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
113 {
114 static const int dp_rates[] = {
115 162000, 270000, 540000, 810000
116 };
117 int i, max_rate;
118 int max_lttpr_rate;
119
120 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
121 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
122 static const int quirk_rates[] = { 162000, 270000, 324000 };
123
124 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
125 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
126
127 return;
128 }
129
130 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
131 max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
132 if (max_lttpr_rate)
133 max_rate = min(max_rate, max_lttpr_rate);
134
135 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
136 if (dp_rates[i] > max_rate)
137 break;
138 intel_dp->sink_rates[i] = dp_rates[i];
139 }
140
141 intel_dp->num_sink_rates = i;
142 }
143
144 /* Get length of rates array potentially limited by max_rate. */
intel_dp_rate_limit_len(const int * rates,int len,int max_rate)145 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
146 {
147 int i;
148
149 /* Limit results by potentially reduced max rate */
150 for (i = 0; i < len; i++) {
151 if (rates[len - i - 1] <= max_rate)
152 return len - i;
153 }
154
155 return 0;
156 }
157
158 /* Get length of common rates array potentially limited by max_rate. */
intel_dp_common_len_rate_limit(const struct intel_dp * intel_dp,int max_rate)159 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
160 int max_rate)
161 {
162 return intel_dp_rate_limit_len(intel_dp->common_rates,
163 intel_dp->num_common_rates, max_rate);
164 }
165
166 /* Theoretical max between source and sink */
intel_dp_max_common_rate(struct intel_dp * intel_dp)167 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
168 {
169 return intel_dp->common_rates[intel_dp->num_common_rates - 1];
170 }
171
172 /* Theoretical max between source and sink */
intel_dp_max_common_lane_count(struct intel_dp * intel_dp)173 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
174 {
175 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
176 int source_max = dig_port->max_lanes;
177 int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
178 int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
179 int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
180
181 if (lttpr_max)
182 sink_max = min(sink_max, lttpr_max);
183
184 return min3(source_max, sink_max, fia_max);
185 }
186
intel_dp_max_lane_count(struct intel_dp * intel_dp)187 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
188 {
189 return intel_dp->max_link_lane_count;
190 }
191
192 int
intel_dp_link_required(int pixel_clock,int bpp)193 intel_dp_link_required(int pixel_clock, int bpp)
194 {
195 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
196 return DIV_ROUND_UP(pixel_clock * bpp, 8);
197 }
198
199 int
intel_dp_max_data_rate(int max_link_clock,int max_lanes)200 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
201 {
202 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
203 * link rate that is generally expressed in Gbps. Since, 8 bits of data
204 * is transmitted every LS_Clk per lane, there is no need to account for
205 * the channel encoding that is done in the PHY layer here.
206 */
207
208 return max_link_clock * max_lanes;
209 }
210
intel_dp_can_bigjoiner(struct intel_dp * intel_dp)211 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
212 {
213 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
214 struct intel_encoder *encoder = &intel_dig_port->base;
215 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
216
217 return DISPLAY_VER(dev_priv) >= 12 ||
218 (IS_DISPLAY_VER(dev_priv, 11) &&
219 encoder->port != PORT_A);
220 }
221
cnl_max_source_rate(struct intel_dp * intel_dp)222 static int cnl_max_source_rate(struct intel_dp *intel_dp)
223 {
224 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
225 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
226 enum port port = dig_port->base.port;
227
228 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
229
230 /* Low voltage SKUs are limited to max of 5.4G */
231 if (voltage == VOLTAGE_INFO_0_85V)
232 return 540000;
233
234 /* For this SKU 8.1G is supported in all ports */
235 if (IS_CNL_WITH_PORT_F(dev_priv))
236 return 810000;
237
238 /* For other SKUs, max rate on ports A and D is 5.4G */
239 if (port == PORT_A || port == PORT_D)
240 return 540000;
241
242 return 810000;
243 }
244
icl_max_source_rate(struct intel_dp * intel_dp)245 static int icl_max_source_rate(struct intel_dp *intel_dp)
246 {
247 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
248 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
249 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
250
251 if (intel_phy_is_combo(dev_priv, phy) &&
252 !intel_dp_is_edp(intel_dp))
253 return 540000;
254
255 return 810000;
256 }
257
ehl_max_source_rate(struct intel_dp * intel_dp)258 static int ehl_max_source_rate(struct intel_dp *intel_dp)
259 {
260 if (intel_dp_is_edp(intel_dp))
261 return 540000;
262
263 return 810000;
264 }
265
266 static void
intel_dp_set_source_rates(struct intel_dp * intel_dp)267 intel_dp_set_source_rates(struct intel_dp *intel_dp)
268 {
269 /* The values must be in increasing order */
270 static const int cnl_rates[] = {
271 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
272 };
273 static const int bxt_rates[] = {
274 162000, 216000, 243000, 270000, 324000, 432000, 540000
275 };
276 static const int skl_rates[] = {
277 162000, 216000, 270000, 324000, 432000, 540000
278 };
279 static const int hsw_rates[] = {
280 162000, 270000, 540000
281 };
282 static const int g4x_rates[] = {
283 162000, 270000
284 };
285 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
286 struct intel_encoder *encoder = &dig_port->base;
287 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
288 const int *source_rates;
289 int size, max_rate = 0, vbt_max_rate;
290
291 /* This should only be done once */
292 drm_WARN_ON(&dev_priv->drm,
293 intel_dp->source_rates || intel_dp->num_source_rates);
294
295 if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
296 source_rates = cnl_rates;
297 size = ARRAY_SIZE(cnl_rates);
298 if (IS_DISPLAY_VER(dev_priv, 10))
299 max_rate = cnl_max_source_rate(intel_dp);
300 else if (IS_JSL_EHL(dev_priv))
301 max_rate = ehl_max_source_rate(intel_dp);
302 else
303 max_rate = icl_max_source_rate(intel_dp);
304 } else if (IS_GEN9_LP(dev_priv)) {
305 source_rates = bxt_rates;
306 size = ARRAY_SIZE(bxt_rates);
307 } else if (IS_GEN9_BC(dev_priv)) {
308 source_rates = skl_rates;
309 size = ARRAY_SIZE(skl_rates);
310 } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
311 IS_BROADWELL(dev_priv)) {
312 source_rates = hsw_rates;
313 size = ARRAY_SIZE(hsw_rates);
314 } else {
315 source_rates = g4x_rates;
316 size = ARRAY_SIZE(g4x_rates);
317 }
318
319 vbt_max_rate = intel_bios_dp_max_link_rate(encoder);
320 if (max_rate && vbt_max_rate)
321 max_rate = min(max_rate, vbt_max_rate);
322 else if (vbt_max_rate)
323 max_rate = vbt_max_rate;
324
325 if (max_rate)
326 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
327
328 intel_dp->source_rates = source_rates;
329 intel_dp->num_source_rates = size;
330 }
331
intersect_rates(const int * source_rates,int source_len,const int * sink_rates,int sink_len,int * common_rates)332 static int intersect_rates(const int *source_rates, int source_len,
333 const int *sink_rates, int sink_len,
334 int *common_rates)
335 {
336 int i = 0, j = 0, k = 0;
337
338 while (i < source_len && j < sink_len) {
339 if (source_rates[i] == sink_rates[j]) {
340 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
341 return k;
342 common_rates[k] = source_rates[i];
343 ++k;
344 ++i;
345 ++j;
346 } else if (source_rates[i] < sink_rates[j]) {
347 ++i;
348 } else {
349 ++j;
350 }
351 }
352 return k;
353 }
354
355 /* return index of rate in rates array, or -1 if not found */
intel_dp_rate_index(const int * rates,int len,int rate)356 static int intel_dp_rate_index(const int *rates, int len, int rate)
357 {
358 int i;
359
360 for (i = 0; i < len; i++)
361 if (rate == rates[i])
362 return i;
363
364 return -1;
365 }
366
intel_dp_set_common_rates(struct intel_dp * intel_dp)367 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
368 {
369 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
370
371 drm_WARN_ON(&i915->drm,
372 !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
373
374 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
375 intel_dp->num_source_rates,
376 intel_dp->sink_rates,
377 intel_dp->num_sink_rates,
378 intel_dp->common_rates);
379
380 /* Paranoia, there should always be something in common. */
381 if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
382 intel_dp->common_rates[0] = 162000;
383 intel_dp->num_common_rates = 1;
384 }
385 }
386
intel_dp_link_params_valid(struct intel_dp * intel_dp,int link_rate,u8 lane_count)387 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
388 u8 lane_count)
389 {
390 /*
391 * FIXME: we need to synchronize the current link parameters with
392 * hardware readout. Currently fast link training doesn't work on
393 * boot-up.
394 */
395 if (link_rate == 0 ||
396 link_rate > intel_dp->max_link_rate)
397 return false;
398
399 if (lane_count == 0 ||
400 lane_count > intel_dp_max_lane_count(intel_dp))
401 return false;
402
403 return true;
404 }
405
intel_dp_can_link_train_fallback_for_edp(struct intel_dp * intel_dp,int link_rate,u8 lane_count)406 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
407 int link_rate,
408 u8 lane_count)
409 {
410 const struct drm_display_mode *fixed_mode =
411 intel_dp->attached_connector->panel.fixed_mode;
412 int mode_rate, max_rate;
413
414 mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
415 max_rate = intel_dp_max_data_rate(link_rate, lane_count);
416 if (mode_rate > max_rate)
417 return false;
418
419 return true;
420 }
421
intel_dp_get_link_train_fallback_values(struct intel_dp * intel_dp,int link_rate,u8 lane_count)422 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
423 int link_rate, u8 lane_count)
424 {
425 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
426 int index;
427
428 /*
429 * TODO: Enable fallback on MST links once MST link compute can handle
430 * the fallback params.
431 */
432 if (intel_dp->is_mst) {
433 drm_err(&i915->drm, "Link Training Unsuccessful\n");
434 return -1;
435 }
436
437 if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
438 drm_dbg_kms(&i915->drm,
439 "Retrying Link training for eDP with max parameters\n");
440 intel_dp->use_max_params = true;
441 return 0;
442 }
443
444 index = intel_dp_rate_index(intel_dp->common_rates,
445 intel_dp->num_common_rates,
446 link_rate);
447 if (index > 0) {
448 if (intel_dp_is_edp(intel_dp) &&
449 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
450 intel_dp->common_rates[index - 1],
451 lane_count)) {
452 drm_dbg_kms(&i915->drm,
453 "Retrying Link training for eDP with same parameters\n");
454 return 0;
455 }
456 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
457 intel_dp->max_link_lane_count = lane_count;
458 } else if (lane_count > 1) {
459 if (intel_dp_is_edp(intel_dp) &&
460 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
461 intel_dp_max_common_rate(intel_dp),
462 lane_count >> 1)) {
463 drm_dbg_kms(&i915->drm,
464 "Retrying Link training for eDP with same parameters\n");
465 return 0;
466 }
467 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
468 intel_dp->max_link_lane_count = lane_count >> 1;
469 } else {
470 drm_err(&i915->drm, "Link Training Unsuccessful\n");
471 return -1;
472 }
473
474 return 0;
475 }
476
intel_dp_mode_to_fec_clock(u32 mode_clock)477 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
478 {
479 return div_u64(mul_u32_u32(mode_clock, 1000000U),
480 DP_DSC_FEC_OVERHEAD_FACTOR);
481 }
482
483 static int
small_joiner_ram_size_bits(struct drm_i915_private * i915)484 small_joiner_ram_size_bits(struct drm_i915_private *i915)
485 {
486 if (DISPLAY_VER(i915) >= 11)
487 return 7680 * 8;
488 else
489 return 6144 * 8;
490 }
491
intel_dp_dsc_get_output_bpp(struct drm_i915_private * i915,u32 link_clock,u32 lane_count,u32 mode_clock,u32 mode_hdisplay,bool bigjoiner)492 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
493 u32 link_clock, u32 lane_count,
494 u32 mode_clock, u32 mode_hdisplay,
495 bool bigjoiner)
496 {
497 u32 bits_per_pixel, max_bpp_small_joiner_ram;
498 int i;
499
500 /*
501 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
502 * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
503 * for SST -> TimeSlotsPerMTP is 1,
504 * for MST -> TimeSlotsPerMTP has to be calculated
505 */
506 bits_per_pixel = (link_clock * lane_count * 8) /
507 intel_dp_mode_to_fec_clock(mode_clock);
508 drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel);
509
510 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
511 max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
512 mode_hdisplay;
513
514 if (bigjoiner)
515 max_bpp_small_joiner_ram *= 2;
516
517 drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
518 max_bpp_small_joiner_ram);
519
520 /*
521 * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
522 * check, output bpp from small joiner RAM check)
523 */
524 bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
525
526 if (bigjoiner) {
527 u32 max_bpp_bigjoiner =
528 i915->max_cdclk_freq * 48 /
529 intel_dp_mode_to_fec_clock(mode_clock);
530
531 DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
532 bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
533 }
534
535 /* Error out if the max bpp is less than smallest allowed valid bpp */
536 if (bits_per_pixel < valid_dsc_bpp[0]) {
537 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
538 bits_per_pixel, valid_dsc_bpp[0]);
539 return 0;
540 }
541
542 /* Find the nearest match in the array of known BPPs from VESA */
543 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
544 if (bits_per_pixel < valid_dsc_bpp[i + 1])
545 break;
546 }
547 bits_per_pixel = valid_dsc_bpp[i];
548
549 /*
550 * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
551 * fractional part is 0
552 */
553 return bits_per_pixel << 4;
554 }
555
intel_dp_dsc_get_slice_count(struct intel_dp * intel_dp,int mode_clock,int mode_hdisplay,bool bigjoiner)556 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
557 int mode_clock, int mode_hdisplay,
558 bool bigjoiner)
559 {
560 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
561 u8 min_slice_count, i;
562 int max_slice_width;
563
564 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
565 min_slice_count = DIV_ROUND_UP(mode_clock,
566 DP_DSC_MAX_ENC_THROUGHPUT_0);
567 else
568 min_slice_count = DIV_ROUND_UP(mode_clock,
569 DP_DSC_MAX_ENC_THROUGHPUT_1);
570
571 max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
572 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
573 drm_dbg_kms(&i915->drm,
574 "Unsupported slice width %d by DP DSC Sink device\n",
575 max_slice_width);
576 return 0;
577 }
578 /* Also take into account max slice width */
579 min_slice_count = max_t(u8, min_slice_count,
580 DIV_ROUND_UP(mode_hdisplay,
581 max_slice_width));
582
583 /* Find the closest match to the valid slice count values */
584 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
585 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
586
587 if (test_slice_count >
588 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
589 break;
590
591 /* big joiner needs small joiner to be enabled */
592 if (bigjoiner && test_slice_count < 4)
593 continue;
594
595 if (min_slice_count <= test_slice_count)
596 return test_slice_count;
597 }
598
599 drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
600 min_slice_count);
601 return 0;
602 }
603
604 static enum intel_output_format
intel_dp_output_format(struct drm_connector * connector,const struct drm_display_mode * mode)605 intel_dp_output_format(struct drm_connector *connector,
606 const struct drm_display_mode *mode)
607 {
608 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
609 const struct drm_display_info *info = &connector->display_info;
610
611 if (!connector->ycbcr_420_allowed ||
612 !drm_mode_is_420_only(info, mode))
613 return INTEL_OUTPUT_FORMAT_RGB;
614
615 if (intel_dp->dfp.rgb_to_ycbcr &&
616 intel_dp->dfp.ycbcr_444_to_420)
617 return INTEL_OUTPUT_FORMAT_RGB;
618
619 if (intel_dp->dfp.ycbcr_444_to_420)
620 return INTEL_OUTPUT_FORMAT_YCBCR444;
621 else
622 return INTEL_OUTPUT_FORMAT_YCBCR420;
623 }
624
intel_dp_min_bpp(enum intel_output_format output_format)625 int intel_dp_min_bpp(enum intel_output_format output_format)
626 {
627 if (output_format == INTEL_OUTPUT_FORMAT_RGB)
628 return 6 * 3;
629 else
630 return 8 * 3;
631 }
632
intel_dp_output_bpp(enum intel_output_format output_format,int bpp)633 static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
634 {
635 /*
636 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
637 * format of the number of bytes per pixel will be half the number
638 * of bytes of RGB pixel.
639 */
640 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
641 bpp /= 2;
642
643 return bpp;
644 }
645
646 static int
intel_dp_mode_min_output_bpp(struct drm_connector * connector,const struct drm_display_mode * mode)647 intel_dp_mode_min_output_bpp(struct drm_connector *connector,
648 const struct drm_display_mode *mode)
649 {
650 enum intel_output_format output_format =
651 intel_dp_output_format(connector, mode);
652
653 return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
654 }
655
intel_dp_hdisplay_bad(struct drm_i915_private * dev_priv,int hdisplay)656 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
657 int hdisplay)
658 {
659 /*
660 * Older platforms don't like hdisplay==4096 with DP.
661 *
662 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
663 * and frame counter increment), but we don't get vblank interrupts,
664 * and the pipe underruns immediately. The link also doesn't seem
665 * to get trained properly.
666 *
667 * On CHV the vblank interrupts don't seem to disappear but
668 * otherwise the symptoms are similar.
669 *
670 * TODO: confirm the behaviour on HSW+
671 */
672 return hdisplay == 4096 && !HAS_DDI(dev_priv);
673 }
674
675 static enum drm_mode_status
intel_dp_mode_valid_downstream(struct intel_connector * connector,const struct drm_display_mode * mode,int target_clock)676 intel_dp_mode_valid_downstream(struct intel_connector *connector,
677 const struct drm_display_mode *mode,
678 int target_clock)
679 {
680 struct intel_dp *intel_dp = intel_attached_dp(connector);
681 const struct drm_display_info *info = &connector->base.display_info;
682 int tmds_clock;
683
684 /* If PCON supports FRL MODE, check FRL bandwidth constraints */
685 if (intel_dp->dfp.pcon_max_frl_bw) {
686 int target_bw;
687 int max_frl_bw;
688 int bpp = intel_dp_mode_min_output_bpp(&connector->base, mode);
689
690 target_bw = bpp * target_clock;
691
692 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
693
694 /* converting bw from Gbps to Kbps*/
695 max_frl_bw = max_frl_bw * 1000000;
696
697 if (target_bw > max_frl_bw)
698 return MODE_CLOCK_HIGH;
699
700 return MODE_OK;
701 }
702
703 if (intel_dp->dfp.max_dotclock &&
704 target_clock > intel_dp->dfp.max_dotclock)
705 return MODE_CLOCK_HIGH;
706
707 /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
708 tmds_clock = target_clock;
709 if (drm_mode_is_420_only(info, mode))
710 tmds_clock /= 2;
711
712 if (intel_dp->dfp.min_tmds_clock &&
713 tmds_clock < intel_dp->dfp.min_tmds_clock)
714 return MODE_CLOCK_LOW;
715 if (intel_dp->dfp.max_tmds_clock &&
716 tmds_clock > intel_dp->dfp.max_tmds_clock)
717 return MODE_CLOCK_HIGH;
718
719 return MODE_OK;
720 }
721
722 static enum drm_mode_status
intel_dp_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)723 intel_dp_mode_valid(struct drm_connector *connector,
724 struct drm_display_mode *mode)
725 {
726 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
727 struct intel_connector *intel_connector = to_intel_connector(connector);
728 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
729 struct drm_i915_private *dev_priv = to_i915(connector->dev);
730 int target_clock = mode->clock;
731 int max_rate, mode_rate, max_lanes, max_link_clock;
732 int max_dotclk = dev_priv->max_dotclk_freq;
733 u16 dsc_max_output_bpp = 0;
734 u8 dsc_slice_count = 0;
735 enum drm_mode_status status;
736 bool dsc = false, bigjoiner = false;
737
738 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
739 return MODE_NO_DBLESCAN;
740
741 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
742 return MODE_H_ILLEGAL;
743
744 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
745 if (mode->hdisplay != fixed_mode->hdisplay)
746 return MODE_PANEL;
747
748 if (mode->vdisplay != fixed_mode->vdisplay)
749 return MODE_PANEL;
750
751 target_clock = fixed_mode->clock;
752 }
753
754 if (mode->clock < 10000)
755 return MODE_CLOCK_LOW;
756
757 if ((target_clock > max_dotclk || mode->hdisplay > 5120) &&
758 intel_dp_can_bigjoiner(intel_dp)) {
759 bigjoiner = true;
760 max_dotclk *= 2;
761 }
762 if (target_clock > max_dotclk)
763 return MODE_CLOCK_HIGH;
764
765 max_link_clock = intel_dp_max_link_rate(intel_dp);
766 max_lanes = intel_dp_max_lane_count(intel_dp);
767
768 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
769 mode_rate = intel_dp_link_required(target_clock,
770 intel_dp_mode_min_output_bpp(connector, mode));
771
772 if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
773 return MODE_H_ILLEGAL;
774
775 /*
776 * Output bpp is stored in 6.4 format so right shift by 4 to get the
777 * integer value since we support only integer values of bpp.
778 */
779 if (DISPLAY_VER(dev_priv) >= 10 &&
780 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
781 if (intel_dp_is_edp(intel_dp)) {
782 dsc_max_output_bpp =
783 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
784 dsc_slice_count =
785 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
786 true);
787 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
788 dsc_max_output_bpp =
789 intel_dp_dsc_get_output_bpp(dev_priv,
790 max_link_clock,
791 max_lanes,
792 target_clock,
793 mode->hdisplay,
794 bigjoiner) >> 4;
795 dsc_slice_count =
796 intel_dp_dsc_get_slice_count(intel_dp,
797 target_clock,
798 mode->hdisplay,
799 bigjoiner);
800 }
801
802 dsc = dsc_max_output_bpp && dsc_slice_count;
803 }
804
805 /* big joiner configuration needs DSC */
806 if (bigjoiner && !dsc)
807 return MODE_CLOCK_HIGH;
808
809 if (mode_rate > max_rate && !dsc)
810 return MODE_CLOCK_HIGH;
811
812 status = intel_dp_mode_valid_downstream(intel_connector,
813 mode, target_clock);
814 if (status != MODE_OK)
815 return status;
816
817 return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
818 }
819
intel_dp_source_supports_hbr2(struct intel_dp * intel_dp)820 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
821 {
822 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
823
824 return max_rate >= 540000;
825 }
826
intel_dp_source_supports_hbr3(struct intel_dp * intel_dp)827 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
828 {
829 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
830
831 return max_rate >= 810000;
832 }
833
snprintf_int_array(char * str,size_t len,const int * array,int nelem)834 static void snprintf_int_array(char *str, size_t len,
835 const int *array, int nelem)
836 {
837 int i;
838
839 str[0] = '\0';
840
841 for (i = 0; i < nelem; i++) {
842 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
843 if (r >= len)
844 return;
845 str += r;
846 len -= r;
847 }
848 }
849
intel_dp_print_rates(struct intel_dp * intel_dp)850 static void intel_dp_print_rates(struct intel_dp *intel_dp)
851 {
852 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
853 char str[128]; /* FIXME: too big for stack? */
854
855 if (!drm_debug_enabled(DRM_UT_KMS))
856 return;
857
858 snprintf_int_array(str, sizeof(str),
859 intel_dp->source_rates, intel_dp->num_source_rates);
860 drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
861
862 snprintf_int_array(str, sizeof(str),
863 intel_dp->sink_rates, intel_dp->num_sink_rates);
864 drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
865
866 snprintf_int_array(str, sizeof(str),
867 intel_dp->common_rates, intel_dp->num_common_rates);
868 drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
869 }
870
871 int
intel_dp_max_link_rate(struct intel_dp * intel_dp)872 intel_dp_max_link_rate(struct intel_dp *intel_dp)
873 {
874 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
875 int len;
876
877 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
878 if (drm_WARN_ON(&i915->drm, len <= 0))
879 return 162000;
880
881 return intel_dp->common_rates[len - 1];
882 }
883
intel_dp_rate_select(struct intel_dp * intel_dp,int rate)884 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
885 {
886 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
887 int i = intel_dp_rate_index(intel_dp->sink_rates,
888 intel_dp->num_sink_rates, rate);
889
890 if (drm_WARN_ON(&i915->drm, i < 0))
891 i = 0;
892
893 return i;
894 }
895
intel_dp_compute_rate(struct intel_dp * intel_dp,int port_clock,u8 * link_bw,u8 * rate_select)896 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
897 u8 *link_bw, u8 *rate_select)
898 {
899 /* eDP 1.4 rate select method. */
900 if (intel_dp->use_rate_select) {
901 *link_bw = 0;
902 *rate_select =
903 intel_dp_rate_select(intel_dp, port_clock);
904 } else {
905 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
906 *rate_select = 0;
907 }
908 }
909
intel_dp_source_supports_fec(struct intel_dp * intel_dp,const struct intel_crtc_state * pipe_config)910 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
911 const struct intel_crtc_state *pipe_config)
912 {
913 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
914
915 /* On TGL, FEC is supported on all Pipes */
916 if (DISPLAY_VER(dev_priv) >= 12)
917 return true;
918
919 if (IS_DISPLAY_VER(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
920 return true;
921
922 return false;
923 }
924
intel_dp_supports_fec(struct intel_dp * intel_dp,const struct intel_crtc_state * pipe_config)925 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
926 const struct intel_crtc_state *pipe_config)
927 {
928 return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
929 drm_dp_sink_supports_fec(intel_dp->fec_capable);
930 }
931
intel_dp_supports_dsc(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)932 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
933 const struct intel_crtc_state *crtc_state)
934 {
935 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
936 return false;
937
938 return intel_dsc_source_support(crtc_state) &&
939 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
940 }
941
intel_dp_hdmi_ycbcr420(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)942 static bool intel_dp_hdmi_ycbcr420(struct intel_dp *intel_dp,
943 const struct intel_crtc_state *crtc_state)
944 {
945 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
946 (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
947 intel_dp->dfp.ycbcr_444_to_420);
948 }
949
intel_dp_hdmi_tmds_clock(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,int bpc)950 static int intel_dp_hdmi_tmds_clock(struct intel_dp *intel_dp,
951 const struct intel_crtc_state *crtc_state, int bpc)
952 {
953 int clock = crtc_state->hw.adjusted_mode.crtc_clock * bpc / 8;
954
955 if (intel_dp_hdmi_ycbcr420(intel_dp, crtc_state))
956 clock /= 2;
957
958 return clock;
959 }
960
intel_dp_hdmi_tmds_clock_valid(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,int bpc)961 static bool intel_dp_hdmi_tmds_clock_valid(struct intel_dp *intel_dp,
962 const struct intel_crtc_state *crtc_state, int bpc)
963 {
964 int tmds_clock = intel_dp_hdmi_tmds_clock(intel_dp, crtc_state, bpc);
965
966 if (intel_dp->dfp.min_tmds_clock &&
967 tmds_clock < intel_dp->dfp.min_tmds_clock)
968 return false;
969
970 if (intel_dp->dfp.max_tmds_clock &&
971 tmds_clock > intel_dp->dfp.max_tmds_clock)
972 return false;
973
974 return true;
975 }
976
intel_dp_hdmi_deep_color_possible(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,int bpc)977 static bool intel_dp_hdmi_deep_color_possible(struct intel_dp *intel_dp,
978 const struct intel_crtc_state *crtc_state,
979 int bpc)
980 {
981
982 return intel_hdmi_deep_color_possible(crtc_state, bpc,
983 intel_dp->has_hdmi_sink,
984 intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) &&
985 intel_dp_hdmi_tmds_clock_valid(intel_dp, crtc_state, bpc);
986 }
987
intel_dp_max_bpp(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)988 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
989 const struct intel_crtc_state *crtc_state)
990 {
991 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
992 struct intel_connector *intel_connector = intel_dp->attached_connector;
993 int bpp, bpc;
994
995 bpc = crtc_state->pipe_bpp / 3;
996
997 if (intel_dp->dfp.max_bpc)
998 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
999
1000 if (intel_dp->dfp.min_tmds_clock) {
1001 for (; bpc >= 10; bpc -= 2) {
1002 if (intel_dp_hdmi_deep_color_possible(intel_dp, crtc_state, bpc))
1003 break;
1004 }
1005 }
1006
1007 bpp = bpc * 3;
1008 if (intel_dp_is_edp(intel_dp)) {
1009 /* Get bpp from vbt only for panels that dont have bpp in edid */
1010 if (intel_connector->base.display_info.bpc == 0 &&
1011 dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1012 drm_dbg_kms(&dev_priv->drm,
1013 "clamping bpp for eDP panel to BIOS-provided %i\n",
1014 dev_priv->vbt.edp.bpp);
1015 bpp = dev_priv->vbt.edp.bpp;
1016 }
1017 }
1018
1019 return bpp;
1020 }
1021
1022 /* Adjust link config limits based on compliance test requests. */
1023 void
intel_dp_adjust_compliance_config(struct intel_dp * intel_dp,struct intel_crtc_state * pipe_config,struct link_config_limits * limits)1024 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1025 struct intel_crtc_state *pipe_config,
1026 struct link_config_limits *limits)
1027 {
1028 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1029
1030 /* For DP Compliance we override the computed bpp for the pipe */
1031 if (intel_dp->compliance.test_data.bpc != 0) {
1032 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1033
1034 limits->min_bpp = limits->max_bpp = bpp;
1035 pipe_config->dither_force_disable = bpp == 6 * 3;
1036
1037 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1038 }
1039
1040 /* Use values requested by Compliance Test Request */
1041 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1042 int index;
1043
1044 /* Validate the compliance test data since max values
1045 * might have changed due to link train fallback.
1046 */
1047 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1048 intel_dp->compliance.test_lane_count)) {
1049 index = intel_dp_rate_index(intel_dp->common_rates,
1050 intel_dp->num_common_rates,
1051 intel_dp->compliance.test_link_rate);
1052 if (index >= 0)
1053 limits->min_clock = limits->max_clock = index;
1054 limits->min_lane_count = limits->max_lane_count =
1055 intel_dp->compliance.test_lane_count;
1056 }
1057 }
1058 }
1059
1060 /* Optimize link config in order: max bpp, min clock, min lanes */
1061 static int
intel_dp_compute_link_config_wide(struct intel_dp * intel_dp,struct intel_crtc_state * pipe_config,const struct link_config_limits * limits)1062 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1063 struct intel_crtc_state *pipe_config,
1064 const struct link_config_limits *limits)
1065 {
1066 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1067 int bpp, clock, lane_count;
1068 int mode_rate, link_clock, link_avail;
1069
1070 for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1071 int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1072
1073 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1074 output_bpp);
1075
1076 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1077 for (lane_count = limits->min_lane_count;
1078 lane_count <= limits->max_lane_count;
1079 lane_count <<= 1) {
1080 link_clock = intel_dp->common_rates[clock];
1081 link_avail = intel_dp_max_data_rate(link_clock,
1082 lane_count);
1083
1084 if (mode_rate <= link_avail) {
1085 pipe_config->lane_count = lane_count;
1086 pipe_config->pipe_bpp = bpp;
1087 pipe_config->port_clock = link_clock;
1088
1089 return 0;
1090 }
1091 }
1092 }
1093 }
1094
1095 return -EINVAL;
1096 }
1097
intel_dp_dsc_compute_bpp(struct intel_dp * intel_dp,u8 dsc_max_bpc)1098 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
1099 {
1100 int i, num_bpc;
1101 u8 dsc_bpc[3] = {0};
1102
1103 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1104 dsc_bpc);
1105 for (i = 0; i < num_bpc; i++) {
1106 if (dsc_max_bpc >= dsc_bpc[i])
1107 return dsc_bpc[i] * 3;
1108 }
1109
1110 return 0;
1111 }
1112
1113 #define DSC_SUPPORTED_VERSION_MIN 1
1114
intel_dp_dsc_compute_params(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)1115 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
1116 struct intel_crtc_state *crtc_state)
1117 {
1118 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1119 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1120 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1121 u8 line_buf_depth;
1122 int ret;
1123
1124 /*
1125 * RC_MODEL_SIZE is currently a constant across all configurations.
1126 *
1127 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1128 * DP_DSC_RC_BUF_SIZE for this.
1129 */
1130 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1131
1132 ret = intel_dsc_compute_params(encoder, crtc_state);
1133 if (ret)
1134 return ret;
1135
1136 /*
1137 * Slice Height of 8 works for all currently available panels. So start
1138 * with that if pic_height is an integral multiple of 8. Eventually add
1139 * logic to try multiple slice heights.
1140 */
1141 if (vdsc_cfg->pic_height % 8 == 0)
1142 vdsc_cfg->slice_height = 8;
1143 else if (vdsc_cfg->pic_height % 4 == 0)
1144 vdsc_cfg->slice_height = 4;
1145 else
1146 vdsc_cfg->slice_height = 2;
1147
1148 vdsc_cfg->dsc_version_major =
1149 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1150 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1151 vdsc_cfg->dsc_version_minor =
1152 min(DSC_SUPPORTED_VERSION_MIN,
1153 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1154 DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
1155
1156 vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1157 DP_DSC_RGB;
1158
1159 line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
1160 if (!line_buf_depth) {
1161 drm_dbg_kms(&i915->drm,
1162 "DSC Sink Line Buffer Depth invalid\n");
1163 return -EINVAL;
1164 }
1165
1166 if (vdsc_cfg->dsc_version_minor == 2)
1167 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
1168 DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
1169 else
1170 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
1171 DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
1172
1173 vdsc_cfg->block_pred_enable =
1174 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1175 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1176
1177 return drm_dsc_compute_rc_parameters(vdsc_cfg);
1178 }
1179
intel_dp_dsc_compute_config(struct intel_dp * intel_dp,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state,struct link_config_limits * limits)1180 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1181 struct intel_crtc_state *pipe_config,
1182 struct drm_connector_state *conn_state,
1183 struct link_config_limits *limits)
1184 {
1185 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1186 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1187 const struct drm_display_mode *adjusted_mode =
1188 &pipe_config->hw.adjusted_mode;
1189 u8 dsc_max_bpc;
1190 int pipe_bpp;
1191 int ret;
1192
1193 pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
1194 intel_dp_supports_fec(intel_dp, pipe_config);
1195
1196 if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1197 return -EINVAL;
1198
1199 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1200 if (DISPLAY_VER(dev_priv) >= 12)
1201 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
1202 else
1203 dsc_max_bpc = min_t(u8, 10,
1204 conn_state->max_requested_bpc);
1205
1206 pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
1207
1208 /* Min Input BPC for ICL+ is 8 */
1209 if (pipe_bpp < 8 * 3) {
1210 drm_dbg_kms(&dev_priv->drm,
1211 "No DSC support for less than 8bpc\n");
1212 return -EINVAL;
1213 }
1214
1215 /*
1216 * For now enable DSC for max bpp, max link rate, max lane count.
1217 * Optimize this later for the minimum possible link rate/lane count
1218 * with DSC enabled for the requested mode.
1219 */
1220 pipe_config->pipe_bpp = pipe_bpp;
1221 pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
1222 pipe_config->lane_count = limits->max_lane_count;
1223
1224 if (intel_dp_is_edp(intel_dp)) {
1225 pipe_config->dsc.compressed_bpp =
1226 min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1227 pipe_config->pipe_bpp);
1228 pipe_config->dsc.slice_count =
1229 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1230 true);
1231 } else {
1232 u16 dsc_max_output_bpp;
1233 u8 dsc_dp_slice_count;
1234
1235 dsc_max_output_bpp =
1236 intel_dp_dsc_get_output_bpp(dev_priv,
1237 pipe_config->port_clock,
1238 pipe_config->lane_count,
1239 adjusted_mode->crtc_clock,
1240 adjusted_mode->crtc_hdisplay,
1241 pipe_config->bigjoiner);
1242 dsc_dp_slice_count =
1243 intel_dp_dsc_get_slice_count(intel_dp,
1244 adjusted_mode->crtc_clock,
1245 adjusted_mode->crtc_hdisplay,
1246 pipe_config->bigjoiner);
1247 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
1248 drm_dbg_kms(&dev_priv->drm,
1249 "Compressed BPP/Slice Count not supported\n");
1250 return -EINVAL;
1251 }
1252 pipe_config->dsc.compressed_bpp = min_t(u16,
1253 dsc_max_output_bpp >> 4,
1254 pipe_config->pipe_bpp);
1255 pipe_config->dsc.slice_count = dsc_dp_slice_count;
1256 }
1257 /*
1258 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1259 * is greater than the maximum Cdclock and if slice count is even
1260 * then we need to use 2 VDSC instances.
1261 */
1262 if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq ||
1263 pipe_config->bigjoiner) {
1264 if (pipe_config->dsc.slice_count < 2) {
1265 drm_dbg_kms(&dev_priv->drm,
1266 "Cannot split stream to use 2 VDSC instances\n");
1267 return -EINVAL;
1268 }
1269
1270 pipe_config->dsc.dsc_split = true;
1271 }
1272
1273 ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
1274 if (ret < 0) {
1275 drm_dbg_kms(&dev_priv->drm,
1276 "Cannot compute valid DSC parameters for Input Bpp = %d "
1277 "Compressed BPP = %d\n",
1278 pipe_config->pipe_bpp,
1279 pipe_config->dsc.compressed_bpp);
1280 return ret;
1281 }
1282
1283 pipe_config->dsc.compression_enable = true;
1284 drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
1285 "Compressed Bpp = %d Slice Count = %d\n",
1286 pipe_config->pipe_bpp,
1287 pipe_config->dsc.compressed_bpp,
1288 pipe_config->dsc.slice_count);
1289
1290 return 0;
1291 }
1292
1293 static int
intel_dp_compute_link_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)1294 intel_dp_compute_link_config(struct intel_encoder *encoder,
1295 struct intel_crtc_state *pipe_config,
1296 struct drm_connector_state *conn_state)
1297 {
1298 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1299 const struct drm_display_mode *adjusted_mode =
1300 &pipe_config->hw.adjusted_mode;
1301 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1302 struct link_config_limits limits;
1303 int common_len;
1304 int ret;
1305
1306 common_len = intel_dp_common_len_rate_limit(intel_dp,
1307 intel_dp->max_link_rate);
1308
1309 /* No common link rates between source and sink */
1310 drm_WARN_ON(encoder->base.dev, common_len <= 0);
1311
1312 limits.min_clock = 0;
1313 limits.max_clock = common_len - 1;
1314
1315 limits.min_lane_count = 1;
1316 limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
1317
1318 limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
1319 limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config);
1320
1321 if (intel_dp->use_max_params) {
1322 /*
1323 * Use the maximum clock and number of lanes the eDP panel
1324 * advertizes being capable of in case the initial fast
1325 * optimal params failed us. The panels are generally
1326 * designed to support only a single clock and lane
1327 * configuration, and typically on older panels these
1328 * values correspond to the native resolution of the panel.
1329 */
1330 limits.min_lane_count = limits.max_lane_count;
1331 limits.min_clock = limits.max_clock;
1332 }
1333
1334 intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
1335
1336 drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
1337 "max rate %d max bpp %d pixel clock %iKHz\n",
1338 limits.max_lane_count,
1339 intel_dp->common_rates[limits.max_clock],
1340 limits.max_bpp, adjusted_mode->crtc_clock);
1341
1342 if ((adjusted_mode->crtc_clock > i915->max_dotclk_freq ||
1343 adjusted_mode->crtc_hdisplay > 5120) &&
1344 intel_dp_can_bigjoiner(intel_dp))
1345 pipe_config->bigjoiner = true;
1346
1347 /*
1348 * Optimize for slow and wide for everything, because there are some
1349 * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
1350 */
1351 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
1352
1353 /* enable compression if the mode doesn't fit available BW */
1354 drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
1355 if (ret || intel_dp->force_dsc_en || pipe_config->bigjoiner) {
1356 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
1357 conn_state, &limits);
1358 if (ret < 0)
1359 return ret;
1360 }
1361
1362 if (pipe_config->dsc.compression_enable) {
1363 drm_dbg_kms(&i915->drm,
1364 "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
1365 pipe_config->lane_count, pipe_config->port_clock,
1366 pipe_config->pipe_bpp,
1367 pipe_config->dsc.compressed_bpp);
1368
1369 drm_dbg_kms(&i915->drm,
1370 "DP link rate required %i available %i\n",
1371 intel_dp_link_required(adjusted_mode->crtc_clock,
1372 pipe_config->dsc.compressed_bpp),
1373 intel_dp_max_data_rate(pipe_config->port_clock,
1374 pipe_config->lane_count));
1375 } else {
1376 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
1377 pipe_config->lane_count, pipe_config->port_clock,
1378 pipe_config->pipe_bpp);
1379
1380 drm_dbg_kms(&i915->drm,
1381 "DP link rate required %i available %i\n",
1382 intel_dp_link_required(adjusted_mode->crtc_clock,
1383 pipe_config->pipe_bpp),
1384 intel_dp_max_data_rate(pipe_config->port_clock,
1385 pipe_config->lane_count));
1386 }
1387 return 0;
1388 }
1389
intel_dp_limited_color_range(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)1390 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
1391 const struct drm_connector_state *conn_state)
1392 {
1393 const struct intel_digital_connector_state *intel_conn_state =
1394 to_intel_digital_connector_state(conn_state);
1395 const struct drm_display_mode *adjusted_mode =
1396 &crtc_state->hw.adjusted_mode;
1397
1398 /*
1399 * Our YCbCr output is always limited range.
1400 * crtc_state->limited_color_range only applies to RGB,
1401 * and it must never be set for YCbCr or we risk setting
1402 * some conflicting bits in PIPECONF which will mess up
1403 * the colors on the monitor.
1404 */
1405 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
1406 return false;
1407
1408 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1409 /*
1410 * See:
1411 * CEA-861-E - 5.1 Default Encoding Parameters
1412 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1413 */
1414 return crtc_state->pipe_bpp != 18 &&
1415 drm_default_rgb_quant_range(adjusted_mode) ==
1416 HDMI_QUANTIZATION_RANGE_LIMITED;
1417 } else {
1418 return intel_conn_state->broadcast_rgb ==
1419 INTEL_BROADCAST_RGB_LIMITED;
1420 }
1421 }
1422
intel_dp_port_has_audio(struct drm_i915_private * dev_priv,enum port port)1423 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
1424 enum port port)
1425 {
1426 if (IS_G4X(dev_priv))
1427 return false;
1428 if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
1429 return false;
1430
1431 return true;
1432 }
1433
intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state,struct drm_dp_vsc_sdp * vsc)1434 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
1435 const struct drm_connector_state *conn_state,
1436 struct drm_dp_vsc_sdp *vsc)
1437 {
1438 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1439 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1440
1441 /*
1442 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1443 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
1444 * Colorimetry Format indication.
1445 */
1446 vsc->revision = 0x5;
1447 vsc->length = 0x13;
1448
1449 /* DP 1.4a spec, Table 2-120 */
1450 switch (crtc_state->output_format) {
1451 case INTEL_OUTPUT_FORMAT_YCBCR444:
1452 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
1453 break;
1454 case INTEL_OUTPUT_FORMAT_YCBCR420:
1455 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
1456 break;
1457 case INTEL_OUTPUT_FORMAT_RGB:
1458 default:
1459 vsc->pixelformat = DP_PIXELFORMAT_RGB;
1460 }
1461
1462 switch (conn_state->colorspace) {
1463 case DRM_MODE_COLORIMETRY_BT709_YCC:
1464 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1465 break;
1466 case DRM_MODE_COLORIMETRY_XVYCC_601:
1467 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
1468 break;
1469 case DRM_MODE_COLORIMETRY_XVYCC_709:
1470 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
1471 break;
1472 case DRM_MODE_COLORIMETRY_SYCC_601:
1473 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
1474 break;
1475 case DRM_MODE_COLORIMETRY_OPYCC_601:
1476 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
1477 break;
1478 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1479 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
1480 break;
1481 case DRM_MODE_COLORIMETRY_BT2020_RGB:
1482 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
1483 break;
1484 case DRM_MODE_COLORIMETRY_BT2020_YCC:
1485 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
1486 break;
1487 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1488 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1489 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
1490 break;
1491 default:
1492 /*
1493 * RGB->YCBCR color conversion uses the BT.709
1494 * color space.
1495 */
1496 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1497 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1498 else
1499 vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
1500 break;
1501 }
1502
1503 vsc->bpc = crtc_state->pipe_bpp / 3;
1504
1505 /* only RGB pixelformat supports 6 bpc */
1506 drm_WARN_ON(&dev_priv->drm,
1507 vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
1508
1509 /* all YCbCr are always limited range */
1510 vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
1511 vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
1512 }
1513
intel_dp_compute_vsc_sdp(struct intel_dp * intel_dp,struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)1514 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
1515 struct intel_crtc_state *crtc_state,
1516 const struct drm_connector_state *conn_state)
1517 {
1518 struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
1519
1520 /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
1521 if (crtc_state->has_psr)
1522 return;
1523
1524 if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
1525 return;
1526
1527 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
1528 vsc->sdp_type = DP_SDP_VSC;
1529 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1530 &crtc_state->infoframes.vsc);
1531 }
1532
intel_dp_compute_psr_vsc_sdp(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state,struct drm_dp_vsc_sdp * vsc)1533 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
1534 const struct intel_crtc_state *crtc_state,
1535 const struct drm_connector_state *conn_state,
1536 struct drm_dp_vsc_sdp *vsc)
1537 {
1538 vsc->sdp_type = DP_SDP_VSC;
1539
1540 if (intel_dp->psr.psr2_enabled) {
1541 if (intel_dp->psr.colorimetry_support &&
1542 intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
1543 /* [PSR2, +Colorimetry] */
1544 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1545 vsc);
1546 } else {
1547 /*
1548 * [PSR2, -Colorimetry]
1549 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
1550 * 3D stereo + PSR/PSR2 + Y-coordinate.
1551 */
1552 vsc->revision = 0x4;
1553 vsc->length = 0xe;
1554 }
1555 } else {
1556 /*
1557 * [PSR1]
1558 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1559 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
1560 * higher).
1561 */
1562 vsc->revision = 0x2;
1563 vsc->length = 0x8;
1564 }
1565 }
1566
1567 static void
intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp * intel_dp,struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)1568 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
1569 struct intel_crtc_state *crtc_state,
1570 const struct drm_connector_state *conn_state)
1571 {
1572 int ret;
1573 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1574 struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
1575
1576 if (!conn_state->hdr_output_metadata)
1577 return;
1578
1579 ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
1580
1581 if (ret) {
1582 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
1583 return;
1584 }
1585
1586 crtc_state->infoframes.enable |=
1587 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
1588 }
1589
1590 static void
intel_dp_drrs_compute_config(struct intel_dp * intel_dp,struct intel_crtc_state * pipe_config,int output_bpp,bool constant_n)1591 intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
1592 struct intel_crtc_state *pipe_config,
1593 int output_bpp, bool constant_n)
1594 {
1595 struct intel_connector *intel_connector = intel_dp->attached_connector;
1596 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1597 int pixel_clock;
1598
1599 if (pipe_config->vrr.enable)
1600 return;
1601
1602 /*
1603 * DRRS and PSR can't be enable together, so giving preference to PSR
1604 * as it allows more power-savings by complete shutting down display,
1605 * so to guarantee this, intel_dp_drrs_compute_config() must be called
1606 * after intel_psr_compute_config().
1607 */
1608 if (pipe_config->has_psr)
1609 return;
1610
1611 if (!intel_connector->panel.downclock_mode ||
1612 dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
1613 return;
1614
1615 pipe_config->has_drrs = true;
1616
1617 pixel_clock = intel_connector->panel.downclock_mode->clock;
1618 if (pipe_config->splitter.enable)
1619 pixel_clock /= pipe_config->splitter.link_count;
1620
1621 intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
1622 pipe_config->port_clock, &pipe_config->dp_m2_n2,
1623 constant_n, pipe_config->fec_enable);
1624
1625 /* FIXME: abstract this better */
1626 if (pipe_config->splitter.enable)
1627 pipe_config->dp_m2_n2.gmch_m *= pipe_config->splitter.link_count;
1628 }
1629
1630 int
intel_dp_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)1631 intel_dp_compute_config(struct intel_encoder *encoder,
1632 struct intel_crtc_state *pipe_config,
1633 struct drm_connector_state *conn_state)
1634 {
1635 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1636 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1637 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1638 enum port port = encoder->port;
1639 struct intel_connector *intel_connector = intel_dp->attached_connector;
1640 struct intel_digital_connector_state *intel_conn_state =
1641 to_intel_digital_connector_state(conn_state);
1642 bool constant_n = drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CONSTANT_N);
1643 int ret = 0, output_bpp;
1644
1645 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1646 pipe_config->has_pch_encoder = true;
1647
1648 pipe_config->output_format = intel_dp_output_format(&intel_connector->base,
1649 adjusted_mode);
1650
1651 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
1652 ret = intel_pch_panel_fitting(pipe_config, conn_state);
1653 if (ret)
1654 return ret;
1655 }
1656
1657 if (!intel_dp_port_has_audio(dev_priv, port))
1658 pipe_config->has_audio = false;
1659 else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1660 pipe_config->has_audio = intel_dp->has_audio;
1661 else
1662 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
1663
1664 if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1665 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1666 adjusted_mode);
1667
1668 if (HAS_GMCH(dev_priv))
1669 ret = intel_gmch_panel_fitting(pipe_config, conn_state);
1670 else
1671 ret = intel_pch_panel_fitting(pipe_config, conn_state);
1672 if (ret)
1673 return ret;
1674 }
1675
1676 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1677 return -EINVAL;
1678
1679 if (HAS_GMCH(dev_priv) &&
1680 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
1681 return -EINVAL;
1682
1683 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1684 return -EINVAL;
1685
1686 if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
1687 return -EINVAL;
1688
1689 ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
1690 if (ret < 0)
1691 return ret;
1692
1693 pipe_config->limited_color_range =
1694 intel_dp_limited_color_range(pipe_config, conn_state);
1695
1696 if (pipe_config->dsc.compression_enable)
1697 output_bpp = pipe_config->dsc.compressed_bpp;
1698 else
1699 output_bpp = intel_dp_output_bpp(pipe_config->output_format,
1700 pipe_config->pipe_bpp);
1701
1702 if (intel_dp->mso_link_count) {
1703 int n = intel_dp->mso_link_count;
1704 int overlap = intel_dp->mso_pixel_overlap;
1705
1706 pipe_config->splitter.enable = true;
1707 pipe_config->splitter.link_count = n;
1708 pipe_config->splitter.pixel_overlap = overlap;
1709
1710 drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
1711 n, overlap);
1712
1713 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
1714 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
1715 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
1716 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
1717 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
1718 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
1719 adjusted_mode->crtc_clock /= n;
1720 }
1721
1722 intel_link_compute_m_n(output_bpp,
1723 pipe_config->lane_count,
1724 adjusted_mode->crtc_clock,
1725 pipe_config->port_clock,
1726 &pipe_config->dp_m_n,
1727 constant_n, pipe_config->fec_enable);
1728
1729 /* FIXME: abstract this better */
1730 if (pipe_config->splitter.enable)
1731 pipe_config->dp_m_n.gmch_m *= pipe_config->splitter.link_count;
1732
1733 if (!HAS_DDI(dev_priv))
1734 g4x_dp_set_clock(encoder, pipe_config);
1735
1736 intel_vrr_compute_config(pipe_config, conn_state);
1737 intel_psr_compute_config(intel_dp, pipe_config);
1738 intel_dp_drrs_compute_config(intel_dp, pipe_config, output_bpp,
1739 constant_n);
1740 intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
1741 intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
1742
1743 return 0;
1744 }
1745
intel_dp_set_link_params(struct intel_dp * intel_dp,int link_rate,int lane_count)1746 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1747 int link_rate, int lane_count)
1748 {
1749 intel_dp->link_trained = false;
1750 intel_dp->link_rate = link_rate;
1751 intel_dp->lane_count = lane_count;
1752 }
1753
1754 /* Enable backlight PWM and backlight PP control. */
intel_edp_backlight_on(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)1755 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1756 const struct drm_connector_state *conn_state)
1757 {
1758 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
1759 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1760
1761 if (!intel_dp_is_edp(intel_dp))
1762 return;
1763
1764 drm_dbg_kms(&i915->drm, "\n");
1765
1766 intel_panel_enable_backlight(crtc_state, conn_state);
1767 intel_pps_backlight_on(intel_dp);
1768 }
1769
1770 /* Disable backlight PP control and backlight PWM. */
intel_edp_backlight_off(const struct drm_connector_state * old_conn_state)1771 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
1772 {
1773 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
1774 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1775
1776 if (!intel_dp_is_edp(intel_dp))
1777 return;
1778
1779 drm_dbg_kms(&i915->drm, "\n");
1780
1781 intel_pps_backlight_off(intel_dp);
1782 intel_panel_disable_backlight(old_conn_state);
1783 }
1784
downstream_hpd_needs_d0(struct intel_dp * intel_dp)1785 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
1786 {
1787 /*
1788 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
1789 * be capable of signalling downstream hpd with a long pulse.
1790 * Whether or not that means D3 is safe to use is not clear,
1791 * but let's assume so until proven otherwise.
1792 *
1793 * FIXME should really check all downstream ports...
1794 */
1795 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
1796 drm_dp_is_branch(intel_dp->dpcd) &&
1797 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
1798 }
1799
intel_dp_sink_set_decompression_state(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,bool enable)1800 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
1801 const struct intel_crtc_state *crtc_state,
1802 bool enable)
1803 {
1804 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1805 int ret;
1806
1807 if (!crtc_state->dsc.compression_enable)
1808 return;
1809
1810 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
1811 enable ? DP_DECOMPRESSION_EN : 0);
1812 if (ret < 0)
1813 drm_dbg_kms(&i915->drm,
1814 "Failed to %s sink decompression state\n",
1815 enable ? "enable" : "disable");
1816 }
1817
1818 static void
intel_edp_init_source_oui(struct intel_dp * intel_dp,bool careful)1819 intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
1820 {
1821 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1822 u8 oui[] = { 0x00, 0xaa, 0x01 };
1823 u8 buf[3] = { 0 };
1824
1825 /*
1826 * During driver init, we want to be careful and avoid changing the source OUI if it's
1827 * already set to what we want, so as to avoid clearing any state by accident
1828 */
1829 if (careful) {
1830 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
1831 drm_err(&i915->drm, "Failed to read source OUI\n");
1832
1833 if (memcmp(oui, buf, sizeof(oui)) == 0)
1834 return;
1835 }
1836
1837 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
1838 drm_err(&i915->drm, "Failed to write source OUI\n");
1839 }
1840
1841 /* If the device supports it, try to set the power state appropriately */
intel_dp_set_power(struct intel_dp * intel_dp,u8 mode)1842 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
1843 {
1844 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1845 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1846 int ret, i;
1847
1848 /* Should have a valid DPCD by this point */
1849 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1850 return;
1851
1852 if (mode != DP_SET_POWER_D0) {
1853 if (downstream_hpd_needs_d0(intel_dp))
1854 return;
1855
1856 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
1857 } else {
1858 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
1859
1860 lspcon_resume(dp_to_dig_port(intel_dp));
1861
1862 /* Write the source OUI as early as possible */
1863 if (intel_dp_is_edp(intel_dp))
1864 intel_edp_init_source_oui(intel_dp, false);
1865
1866 /*
1867 * When turning on, we need to retry for 1ms to give the sink
1868 * time to wake up.
1869 */
1870 for (i = 0; i < 3; i++) {
1871 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
1872 if (ret == 1)
1873 break;
1874 msleep(1);
1875 }
1876
1877 if (ret == 1 && lspcon->active)
1878 lspcon_wait_pcon_mode(lspcon);
1879 }
1880
1881 if (ret != 1)
1882 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
1883 encoder->base.base.id, encoder->base.name,
1884 mode == DP_SET_POWER_D0 ? "D0" : "D3");
1885 }
1886
1887 static bool
1888 intel_dp_get_dpcd(struct intel_dp *intel_dp);
1889
1890 /**
1891 * intel_dp_sync_state - sync the encoder state during init/resume
1892 * @encoder: intel encoder to sync
1893 * @crtc_state: state for the CRTC connected to the encoder
1894 *
1895 * Sync any state stored in the encoder wrt. HW state during driver init
1896 * and system resume.
1897 */
intel_dp_sync_state(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1898 void intel_dp_sync_state(struct intel_encoder *encoder,
1899 const struct intel_crtc_state *crtc_state)
1900 {
1901 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1902
1903 /*
1904 * Don't clobber DPCD if it's been already read out during output
1905 * setup (eDP) or detect.
1906 */
1907 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
1908 intel_dp_get_dpcd(intel_dp);
1909
1910 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
1911 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
1912 }
1913
intel_dp_initial_fastset_check(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)1914 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
1915 struct intel_crtc_state *crtc_state)
1916 {
1917 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1918 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1919
1920 /*
1921 * If BIOS has set an unsupported or non-standard link rate for some
1922 * reason force an encoder recompute and full modeset.
1923 */
1924 if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
1925 crtc_state->port_clock) < 0) {
1926 drm_dbg_kms(&i915->drm, "Forcing full modeset due to unsupported link rate\n");
1927 crtc_state->uapi.connectors_changed = true;
1928 return false;
1929 }
1930
1931 /*
1932 * FIXME hack to force full modeset when DSC is being used.
1933 *
1934 * As long as we do not have full state readout and config comparison
1935 * of crtc_state->dsc, we have no way to ensure reliable fastset.
1936 * Remove once we have readout for DSC.
1937 */
1938 if (crtc_state->dsc.compression_enable) {
1939 drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n");
1940 crtc_state->uapi.mode_changed = true;
1941 return false;
1942 }
1943
1944 if (CAN_PSR(intel_dp)) {
1945 drm_dbg_kms(&i915->drm, "Forcing full modeset to compute PSR state\n");
1946 crtc_state->uapi.mode_changed = true;
1947 return false;
1948 }
1949
1950 return true;
1951 }
1952
intel_dp_get_pcon_dsc_cap(struct intel_dp * intel_dp)1953 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
1954 {
1955 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1956
1957 /* Clear the cached register set to avoid using stale values */
1958
1959 memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
1960
1961 if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
1962 intel_dp->pcon_dsc_dpcd,
1963 sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
1964 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
1965 DP_PCON_DSC_ENCODER);
1966
1967 drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
1968 (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
1969 }
1970
intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)1971 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
1972 {
1973 int bw_gbps[] = {9, 18, 24, 32, 40, 48};
1974 int i;
1975
1976 for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
1977 if (frl_bw_mask & (1 << i))
1978 return bw_gbps[i];
1979 }
1980 return 0;
1981 }
1982
intel_dp_pcon_set_frl_mask(int max_frl)1983 static int intel_dp_pcon_set_frl_mask(int max_frl)
1984 {
1985 switch (max_frl) {
1986 case 48:
1987 return DP_PCON_FRL_BW_MASK_48GBPS;
1988 case 40:
1989 return DP_PCON_FRL_BW_MASK_40GBPS;
1990 case 32:
1991 return DP_PCON_FRL_BW_MASK_32GBPS;
1992 case 24:
1993 return DP_PCON_FRL_BW_MASK_24GBPS;
1994 case 18:
1995 return DP_PCON_FRL_BW_MASK_18GBPS;
1996 case 9:
1997 return DP_PCON_FRL_BW_MASK_9GBPS;
1998 }
1999
2000 return 0;
2001 }
2002
intel_dp_hdmi_sink_max_frl(struct intel_dp * intel_dp)2003 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
2004 {
2005 struct intel_connector *intel_connector = intel_dp->attached_connector;
2006 struct drm_connector *connector = &intel_connector->base;
2007 int max_frl_rate;
2008 int max_lanes, rate_per_lane;
2009 int max_dsc_lanes, dsc_rate_per_lane;
2010
2011 max_lanes = connector->display_info.hdmi.max_lanes;
2012 rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
2013 max_frl_rate = max_lanes * rate_per_lane;
2014
2015 if (connector->display_info.hdmi.dsc_cap.v_1p2) {
2016 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
2017 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
2018 if (max_dsc_lanes && dsc_rate_per_lane)
2019 max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
2020 }
2021
2022 return max_frl_rate;
2023 }
2024
intel_dp_pcon_start_frl_training(struct intel_dp * intel_dp)2025 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
2026 {
2027 #define TIMEOUT_FRL_READY_MS 500
2028 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
2029
2030 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2031 int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
2032 u8 max_frl_bw_mask = 0, frl_trained_mask;
2033 bool is_active;
2034
2035 ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
2036 if (ret < 0)
2037 return ret;
2038
2039 max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
2040 drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
2041
2042 max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
2043 drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
2044
2045 max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
2046
2047 if (max_frl_bw <= 0)
2048 return -EINVAL;
2049
2050 ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
2051 if (ret < 0)
2052 return ret;
2053 /* Wait for PCON to be FRL Ready */
2054 wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
2055
2056 if (!is_active)
2057 return -ETIMEDOUT;
2058
2059 max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
2060 ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
2061 DP_PCON_ENABLE_SEQUENTIAL_LINK);
2062 if (ret < 0)
2063 return ret;
2064 ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
2065 DP_PCON_FRL_LINK_TRAIN_NORMAL);
2066 if (ret < 0)
2067 return ret;
2068 ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
2069 if (ret < 0)
2070 return ret;
2071 /*
2072 * Wait for FRL to be completed
2073 * Check if the HDMI Link is up and active.
2074 */
2075 wait_for(is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux) == true, TIMEOUT_HDMI_LINK_ACTIVE_MS);
2076
2077 if (!is_active)
2078 return -ETIMEDOUT;
2079
2080 /* Verify HDMI Link configuration shows FRL Mode */
2081 if (drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, &frl_trained_mask) !=
2082 DP_PCON_HDMI_MODE_FRL) {
2083 drm_dbg(&i915->drm, "HDMI couldn't be trained in FRL Mode\n");
2084 return -EINVAL;
2085 }
2086 drm_dbg(&i915->drm, "MAX_FRL_MASK = %u, FRL_TRAINED_MASK = %u\n", max_frl_bw_mask, frl_trained_mask);
2087
2088 intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
2089 intel_dp->frl.is_trained = true;
2090 drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
2091
2092 return 0;
2093 }
2094
intel_dp_is_hdmi_2_1_sink(struct intel_dp * intel_dp)2095 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
2096 {
2097 if (drm_dp_is_branch(intel_dp->dpcd) &&
2098 intel_dp->has_hdmi_sink &&
2099 intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
2100 return true;
2101
2102 return false;
2103 }
2104
intel_dp_check_frl_training(struct intel_dp * intel_dp)2105 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
2106 {
2107 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2108
2109 /*
2110 * Always go for FRL training if:
2111 * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
2112 * -sink is HDMI2.1
2113 */
2114 if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
2115 !intel_dp_is_hdmi_2_1_sink(intel_dp) ||
2116 intel_dp->frl.is_trained)
2117 return;
2118
2119 if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
2120 int ret, mode;
2121
2122 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
2123 ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
2124 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
2125
2126 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
2127 drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
2128 } else {
2129 drm_dbg(&dev_priv->drm, "FRL training Completed\n");
2130 }
2131 }
2132
2133 static int
intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state * crtc_state)2134 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
2135 {
2136 int vactive = crtc_state->hw.adjusted_mode.vdisplay;
2137
2138 return intel_hdmi_dsc_get_slice_height(vactive);
2139 }
2140
2141 static int
intel_dp_pcon_dsc_enc_slices(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)2142 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
2143 const struct intel_crtc_state *crtc_state)
2144 {
2145 struct intel_connector *intel_connector = intel_dp->attached_connector;
2146 struct drm_connector *connector = &intel_connector->base;
2147 int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
2148 int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
2149 int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
2150 int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
2151
2152 return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
2153 pcon_max_slice_width,
2154 hdmi_max_slices, hdmi_throughput);
2155 }
2156
2157 static int
intel_dp_pcon_dsc_enc_bpp(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,int num_slices,int slice_width)2158 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
2159 const struct intel_crtc_state *crtc_state,
2160 int num_slices, int slice_width)
2161 {
2162 struct intel_connector *intel_connector = intel_dp->attached_connector;
2163 struct drm_connector *connector = &intel_connector->base;
2164 int output_format = crtc_state->output_format;
2165 bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
2166 int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
2167 int hdmi_max_chunk_bytes =
2168 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
2169
2170 return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
2171 num_slices, output_format, hdmi_all_bpp,
2172 hdmi_max_chunk_bytes);
2173 }
2174
2175 void
intel_dp_pcon_dsc_configure(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)2176 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
2177 const struct intel_crtc_state *crtc_state)
2178 {
2179 u8 pps_param[6];
2180 int slice_height;
2181 int slice_width;
2182 int num_slices;
2183 int bits_per_pixel;
2184 int ret;
2185 struct intel_connector *intel_connector = intel_dp->attached_connector;
2186 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2187 struct drm_connector *connector;
2188 bool hdmi_is_dsc_1_2;
2189
2190 if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
2191 return;
2192
2193 if (!intel_connector)
2194 return;
2195 connector = &intel_connector->base;
2196 hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
2197
2198 if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
2199 !hdmi_is_dsc_1_2)
2200 return;
2201
2202 slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
2203 if (!slice_height)
2204 return;
2205
2206 num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
2207 if (!num_slices)
2208 return;
2209
2210 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
2211 num_slices);
2212
2213 bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
2214 num_slices, slice_width);
2215 if (!bits_per_pixel)
2216 return;
2217
2218 pps_param[0] = slice_height & 0xFF;
2219 pps_param[1] = slice_height >> 8;
2220 pps_param[2] = slice_width & 0xFF;
2221 pps_param[3] = slice_width >> 8;
2222 pps_param[4] = bits_per_pixel & 0xFF;
2223 pps_param[5] = (bits_per_pixel >> 8) & 0x3;
2224
2225 ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
2226 if (ret < 0)
2227 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
2228 }
2229
intel_dp_configure_protocol_converter(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)2230 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
2231 const struct intel_crtc_state *crtc_state)
2232 {
2233 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2234 u8 tmp;
2235
2236 if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
2237 return;
2238
2239 if (!drm_dp_is_branch(intel_dp->dpcd))
2240 return;
2241
2242 tmp = intel_dp->has_hdmi_sink ?
2243 DP_HDMI_DVI_OUTPUT_CONFIG : 0;
2244
2245 if (drm_dp_dpcd_writeb(&intel_dp->aux,
2246 DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
2247 drm_dbg_kms(&i915->drm, "Failed to set protocol converter HDMI mode to %s\n",
2248 enableddisabled(intel_dp->has_hdmi_sink));
2249
2250 tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
2251 intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
2252
2253 if (drm_dp_dpcd_writeb(&intel_dp->aux,
2254 DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
2255 drm_dbg_kms(&i915->drm,
2256 "Failed to set protocol converter YCbCr 4:2:0 conversion mode to %s\n",
2257 enableddisabled(intel_dp->dfp.ycbcr_444_to_420));
2258
2259 tmp = 0;
2260 if (intel_dp->dfp.rgb_to_ycbcr) {
2261 bool bt2020, bt709;
2262
2263 /*
2264 * FIXME: Currently if userspace selects BT2020 or BT709, but PCON supports only
2265 * RGB->YCbCr for BT601 colorspace, we go ahead with BT601, as default.
2266 *
2267 */
2268 tmp = DP_CONVERSION_BT601_RGB_YCBCR_ENABLE;
2269
2270 bt2020 = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
2271 intel_dp->downstream_ports,
2272 DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
2273 bt709 = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
2274 intel_dp->downstream_ports,
2275 DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
2276 switch (crtc_state->infoframes.vsc.colorimetry) {
2277 case DP_COLORIMETRY_BT2020_RGB:
2278 case DP_COLORIMETRY_BT2020_YCC:
2279 if (bt2020)
2280 tmp = DP_CONVERSION_BT2020_RGB_YCBCR_ENABLE;
2281 break;
2282 case DP_COLORIMETRY_BT709_YCC:
2283 case DP_COLORIMETRY_XVYCC_709:
2284 if (bt709)
2285 tmp = DP_CONVERSION_BT709_RGB_YCBCR_ENABLE;
2286 break;
2287 default:
2288 break;
2289 }
2290 }
2291
2292 if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
2293 drm_dbg_kms(&i915->drm,
2294 "Failed to set protocol converter RGB->YCbCr conversion mode to %s\n",
2295 enableddisabled(tmp ? true : false));
2296 }
2297
2298
intel_dp_get_colorimetry_status(struct intel_dp * intel_dp)2299 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
2300 {
2301 u8 dprx = 0;
2302
2303 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
2304 &dprx) != 1)
2305 return false;
2306 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
2307 }
2308
intel_dp_get_dsc_sink_cap(struct intel_dp * intel_dp)2309 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
2310 {
2311 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2312
2313 /*
2314 * Clear the cached register set to avoid using stale values
2315 * for the sinks that do not support DSC.
2316 */
2317 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
2318
2319 /* Clear fec_capable to avoid using stale values */
2320 intel_dp->fec_capable = 0;
2321
2322 /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
2323 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
2324 intel_dp->edp_dpcd[0] >= DP_EDP_14) {
2325 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
2326 intel_dp->dsc_dpcd,
2327 sizeof(intel_dp->dsc_dpcd)) < 0)
2328 drm_err(&i915->drm,
2329 "Failed to read DPCD register 0x%x\n",
2330 DP_DSC_SUPPORT);
2331
2332 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
2333 (int)sizeof(intel_dp->dsc_dpcd),
2334 intel_dp->dsc_dpcd);
2335
2336 /* FEC is supported only on DP 1.4 */
2337 if (!intel_dp_is_edp(intel_dp) &&
2338 drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
2339 &intel_dp->fec_capable) < 0)
2340 drm_err(&i915->drm,
2341 "Failed to read FEC DPCD register\n");
2342
2343 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
2344 intel_dp->fec_capable);
2345 }
2346 }
2347
intel_edp_mso_mode_fixup(struct intel_connector * connector,struct drm_display_mode * mode)2348 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
2349 struct drm_display_mode *mode)
2350 {
2351 struct intel_dp *intel_dp = intel_attached_dp(connector);
2352 struct drm_i915_private *i915 = to_i915(connector->base.dev);
2353 int n = intel_dp->mso_link_count;
2354 int overlap = intel_dp->mso_pixel_overlap;
2355
2356 if (!mode || !n)
2357 return;
2358
2359 mode->hdisplay = (mode->hdisplay - overlap) * n;
2360 mode->hsync_start = (mode->hsync_start - overlap) * n;
2361 mode->hsync_end = (mode->hsync_end - overlap) * n;
2362 mode->htotal = (mode->htotal - overlap) * n;
2363 mode->clock *= n;
2364
2365 drm_mode_set_name(mode);
2366
2367 drm_dbg_kms(&i915->drm,
2368 "[CONNECTOR:%d:%s] using generated MSO mode: ",
2369 connector->base.base.id, connector->base.name);
2370 drm_mode_debug_printmodeline(mode);
2371 }
2372
intel_edp_mso_init(struct intel_dp * intel_dp)2373 static void intel_edp_mso_init(struct intel_dp *intel_dp)
2374 {
2375 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2376 u8 mso;
2377
2378 if (intel_dp->edp_dpcd[0] < DP_EDP_14)
2379 return;
2380
2381 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
2382 drm_err(&i915->drm, "Failed to read MSO cap\n");
2383 return;
2384 }
2385
2386 /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
2387 mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
2388 if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
2389 drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
2390 mso = 0;
2391 }
2392
2393 if (mso) {
2394 drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration\n",
2395 mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso);
2396 if (!HAS_MSO(i915)) {
2397 drm_err(&i915->drm, "No source MSO support, disabling\n");
2398 mso = 0;
2399 }
2400 }
2401
2402 intel_dp->mso_link_count = mso;
2403 intel_dp->mso_pixel_overlap = 0; /* FIXME: read from DisplayID v2.0 */
2404 }
2405
2406 static bool
intel_edp_init_dpcd(struct intel_dp * intel_dp)2407 intel_edp_init_dpcd(struct intel_dp *intel_dp)
2408 {
2409 struct drm_i915_private *dev_priv =
2410 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
2411
2412 /* this function is meant to be called only once */
2413 drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
2414
2415 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
2416 return false;
2417
2418 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
2419 drm_dp_is_branch(intel_dp->dpcd));
2420
2421 /*
2422 * Read the eDP display control registers.
2423 *
2424 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
2425 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
2426 * set, but require eDP 1.4+ detection (e.g. for supported link rates
2427 * method). The display control registers should read zero if they're
2428 * not supported anyway.
2429 */
2430 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
2431 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
2432 sizeof(intel_dp->edp_dpcd))
2433 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
2434 (int)sizeof(intel_dp->edp_dpcd),
2435 intel_dp->edp_dpcd);
2436
2437 /*
2438 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
2439 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
2440 */
2441 intel_psr_init_dpcd(intel_dp);
2442
2443 /* Read the eDP 1.4+ supported link rates. */
2444 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
2445 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
2446 int i;
2447
2448 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
2449 sink_rates, sizeof(sink_rates));
2450
2451 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
2452 int val = le16_to_cpu(sink_rates[i]);
2453
2454 if (val == 0)
2455 break;
2456
2457 /* Value read multiplied by 200kHz gives the per-lane
2458 * link rate in kHz. The source rates are, however,
2459 * stored in terms of LS_Clk kHz. The full conversion
2460 * back to symbols is
2461 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
2462 */
2463 intel_dp->sink_rates[i] = (val * 200) / 10;
2464 }
2465 intel_dp->num_sink_rates = i;
2466 }
2467
2468 /*
2469 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
2470 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
2471 */
2472 if (intel_dp->num_sink_rates)
2473 intel_dp->use_rate_select = true;
2474 else
2475 intel_dp_set_sink_rates(intel_dp);
2476
2477 intel_dp_set_common_rates(intel_dp);
2478
2479 /* Read the eDP DSC DPCD registers */
2480 if (DISPLAY_VER(dev_priv) >= 10)
2481 intel_dp_get_dsc_sink_cap(intel_dp);
2482
2483 /*
2484 * If needed, program our source OUI so we can make various Intel-specific AUX services
2485 * available (such as HDR backlight controls)
2486 */
2487 intel_edp_init_source_oui(intel_dp, true);
2488
2489 intel_edp_mso_init(intel_dp);
2490
2491 return true;
2492 }
2493
2494 static bool
intel_dp_has_sink_count(struct intel_dp * intel_dp)2495 intel_dp_has_sink_count(struct intel_dp *intel_dp)
2496 {
2497 if (!intel_dp->attached_connector)
2498 return false;
2499
2500 return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
2501 intel_dp->dpcd,
2502 &intel_dp->desc);
2503 }
2504
2505 static bool
intel_dp_get_dpcd(struct intel_dp * intel_dp)2506 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2507 {
2508 int ret;
2509
2510 if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
2511 return false;
2512
2513 /*
2514 * Don't clobber cached eDP rates. Also skip re-reading
2515 * the OUI/ID since we know it won't change.
2516 */
2517 if (!intel_dp_is_edp(intel_dp)) {
2518 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
2519 drm_dp_is_branch(intel_dp->dpcd));
2520
2521 intel_dp_set_sink_rates(intel_dp);
2522 intel_dp_set_common_rates(intel_dp);
2523 }
2524
2525 if (intel_dp_has_sink_count(intel_dp)) {
2526 ret = drm_dp_read_sink_count(&intel_dp->aux);
2527 if (ret < 0)
2528 return false;
2529
2530 /*
2531 * Sink count can change between short pulse hpd hence
2532 * a member variable in intel_dp will track any changes
2533 * between short pulse interrupts.
2534 */
2535 intel_dp->sink_count = ret;
2536
2537 /*
2538 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
2539 * a dongle is present but no display. Unless we require to know
2540 * if a dongle is present or not, we don't need to update
2541 * downstream port information. So, an early return here saves
2542 * time from performing other operations which are not required.
2543 */
2544 if (!intel_dp->sink_count)
2545 return false;
2546 }
2547
2548 return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
2549 intel_dp->downstream_ports) == 0;
2550 }
2551
2552 static bool
intel_dp_can_mst(struct intel_dp * intel_dp)2553 intel_dp_can_mst(struct intel_dp *intel_dp)
2554 {
2555 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2556
2557 return i915->params.enable_dp_mst &&
2558 intel_dp->can_mst &&
2559 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
2560 }
2561
2562 static void
intel_dp_configure_mst(struct intel_dp * intel_dp)2563 intel_dp_configure_mst(struct intel_dp *intel_dp)
2564 {
2565 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2566 struct intel_encoder *encoder =
2567 &dp_to_dig_port(intel_dp)->base;
2568 bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
2569
2570 drm_dbg_kms(&i915->drm,
2571 "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
2572 encoder->base.base.id, encoder->base.name,
2573 yesno(intel_dp->can_mst), yesno(sink_can_mst),
2574 yesno(i915->params.enable_dp_mst));
2575
2576 if (!intel_dp->can_mst)
2577 return;
2578
2579 intel_dp->is_mst = sink_can_mst &&
2580 i915->params.enable_dp_mst;
2581
2582 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
2583 intel_dp->is_mst);
2584 }
2585
2586 static bool
intel_dp_get_sink_irq_esi(struct intel_dp * intel_dp,u8 * sink_irq_vector)2587 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2588 {
2589 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
2590 sink_irq_vector, DP_DPRX_ESI_LEN) ==
2591 DP_DPRX_ESI_LEN;
2592 }
2593
2594 bool
intel_dp_needs_vsc_sdp(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2595 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
2596 const struct drm_connector_state *conn_state)
2597 {
2598 /*
2599 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
2600 * of Color Encoding Format and Content Color Gamut], in order to
2601 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
2602 */
2603 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2604 return true;
2605
2606 switch (conn_state->colorspace) {
2607 case DRM_MODE_COLORIMETRY_SYCC_601:
2608 case DRM_MODE_COLORIMETRY_OPYCC_601:
2609 case DRM_MODE_COLORIMETRY_BT2020_YCC:
2610 case DRM_MODE_COLORIMETRY_BT2020_RGB:
2611 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2612 return true;
2613 default:
2614 break;
2615 }
2616
2617 return false;
2618 }
2619
intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp * vsc,struct dp_sdp * sdp,size_t size)2620 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
2621 struct dp_sdp *sdp, size_t size)
2622 {
2623 size_t length = sizeof(struct dp_sdp);
2624
2625 if (size < length)
2626 return -ENOSPC;
2627
2628 memset(sdp, 0, size);
2629
2630 /*
2631 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
2632 * VSC SDP Header Bytes
2633 */
2634 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
2635 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
2636 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
2637 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
2638
2639 /*
2640 * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
2641 * per DP 1.4a spec.
2642 */
2643 if (vsc->revision != 0x5)
2644 goto out;
2645
2646 /* VSC SDP Payload for DB16 through DB18 */
2647 /* Pixel Encoding and Colorimetry Formats */
2648 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
2649 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
2650
2651 switch (vsc->bpc) {
2652 case 6:
2653 /* 6bpc: 0x0 */
2654 break;
2655 case 8:
2656 sdp->db[17] = 0x1; /* DB17[3:0] */
2657 break;
2658 case 10:
2659 sdp->db[17] = 0x2;
2660 break;
2661 case 12:
2662 sdp->db[17] = 0x3;
2663 break;
2664 case 16:
2665 sdp->db[17] = 0x4;
2666 break;
2667 default:
2668 MISSING_CASE(vsc->bpc);
2669 break;
2670 }
2671 /* Dynamic Range and Component Bit Depth */
2672 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
2673 sdp->db[17] |= 0x80; /* DB17[7] */
2674
2675 /* Content Type */
2676 sdp->db[18] = vsc->content_type & 0x7;
2677
2678 out:
2679 return length;
2680 }
2681
2682 static ssize_t
intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe * drm_infoframe,struct dp_sdp * sdp,size_t size)2683 intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_infoframe,
2684 struct dp_sdp *sdp,
2685 size_t size)
2686 {
2687 size_t length = sizeof(struct dp_sdp);
2688 const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
2689 unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
2690 ssize_t len;
2691
2692 if (size < length)
2693 return -ENOSPC;
2694
2695 memset(sdp, 0, size);
2696
2697 len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
2698 if (len < 0) {
2699 DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
2700 return -ENOSPC;
2701 }
2702
2703 if (len != infoframe_size) {
2704 DRM_DEBUG_KMS("wrong static hdr metadata size\n");
2705 return -ENOSPC;
2706 }
2707
2708 /*
2709 * Set up the infoframe sdp packet for HDR static metadata.
2710 * Prepare VSC Header for SU as per DP 1.4a spec,
2711 * Table 2-100 and Table 2-101
2712 */
2713
2714 /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
2715 sdp->sdp_header.HB0 = 0;
2716 /*
2717 * Packet Type 80h + Non-audio INFOFRAME Type value
2718 * HDMI_INFOFRAME_TYPE_DRM: 0x87
2719 * - 80h + Non-audio INFOFRAME Type value
2720 * - InfoFrame Type: 0x07
2721 * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
2722 */
2723 sdp->sdp_header.HB1 = drm_infoframe->type;
2724 /*
2725 * Least Significant Eight Bits of (Data Byte Count – 1)
2726 * infoframe_size - 1
2727 */
2728 sdp->sdp_header.HB2 = 0x1D;
2729 /* INFOFRAME SDP Version Number */
2730 sdp->sdp_header.HB3 = (0x13 << 2);
2731 /* CTA Header Byte 2 (INFOFRAME Version Number) */
2732 sdp->db[0] = drm_infoframe->version;
2733 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
2734 sdp->db[1] = drm_infoframe->length;
2735 /*
2736 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
2737 * HDMI_INFOFRAME_HEADER_SIZE
2738 */
2739 BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
2740 memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
2741 HDMI_DRM_INFOFRAME_SIZE);
2742
2743 /*
2744 * Size of DP infoframe sdp packet for HDR static metadata consists of
2745 * - DP SDP Header(struct dp_sdp_header): 4 bytes
2746 * - Two Data Blocks: 2 bytes
2747 * CTA Header Byte2 (INFOFRAME Version Number)
2748 * CTA Header Byte3 (Length of INFOFRAME)
2749 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
2750 *
2751 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
2752 * infoframe size. But GEN11+ has larger than that size, write_infoframe
2753 * will pad rest of the size.
2754 */
2755 return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
2756 }
2757
intel_write_dp_sdp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,unsigned int type)2758 static void intel_write_dp_sdp(struct intel_encoder *encoder,
2759 const struct intel_crtc_state *crtc_state,
2760 unsigned int type)
2761 {
2762 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2763 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2764 struct dp_sdp sdp = {};
2765 ssize_t len;
2766
2767 if ((crtc_state->infoframes.enable &
2768 intel_hdmi_infoframe_enable(type)) == 0)
2769 return;
2770
2771 switch (type) {
2772 case DP_SDP_VSC:
2773 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
2774 sizeof(sdp));
2775 break;
2776 case HDMI_PACKET_TYPE_GAMUT_METADATA:
2777 len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state->infoframes.drm.drm,
2778 &sdp, sizeof(sdp));
2779 break;
2780 default:
2781 MISSING_CASE(type);
2782 return;
2783 }
2784
2785 if (drm_WARN_ON(&dev_priv->drm, len < 0))
2786 return;
2787
2788 dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
2789 }
2790
intel_write_dp_vsc_sdp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,struct drm_dp_vsc_sdp * vsc)2791 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
2792 const struct intel_crtc_state *crtc_state,
2793 struct drm_dp_vsc_sdp *vsc)
2794 {
2795 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2796 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2797 struct dp_sdp sdp = {};
2798 ssize_t len;
2799
2800 len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
2801
2802 if (drm_WARN_ON(&dev_priv->drm, len < 0))
2803 return;
2804
2805 dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
2806 &sdp, len);
2807 }
2808
intel_dp_set_infoframes(struct intel_encoder * encoder,bool enable,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2809 void intel_dp_set_infoframes(struct intel_encoder *encoder,
2810 bool enable,
2811 const struct intel_crtc_state *crtc_state,
2812 const struct drm_connector_state *conn_state)
2813 {
2814 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2815 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2816 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
2817 u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
2818 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
2819 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
2820 u32 val = intel_de_read(dev_priv, reg);
2821
2822 /* TODO: Add DSC case (DIP_ENABLE_PPS) */
2823 /* When PSR is enabled, this routine doesn't disable VSC DIP */
2824 if (intel_psr_enabled(intel_dp))
2825 val &= ~dip_enable;
2826 else
2827 val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);
2828
2829 if (!enable) {
2830 intel_de_write(dev_priv, reg, val);
2831 intel_de_posting_read(dev_priv, reg);
2832 return;
2833 }
2834
2835 intel_de_write(dev_priv, reg, val);
2836 intel_de_posting_read(dev_priv, reg);
2837
2838 /* When PSR is enabled, VSC SDP is handled by PSR routine */
2839 if (!intel_psr_enabled(intel_dp))
2840 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
2841
2842 intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
2843 }
2844
intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp * vsc,const void * buffer,size_t size)2845 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
2846 const void *buffer, size_t size)
2847 {
2848 const struct dp_sdp *sdp = buffer;
2849
2850 if (size < sizeof(struct dp_sdp))
2851 return -EINVAL;
2852
2853 memset(vsc, 0, size);
2854
2855 if (sdp->sdp_header.HB0 != 0)
2856 return -EINVAL;
2857
2858 if (sdp->sdp_header.HB1 != DP_SDP_VSC)
2859 return -EINVAL;
2860
2861 vsc->sdp_type = sdp->sdp_header.HB1;
2862 vsc->revision = sdp->sdp_header.HB2;
2863 vsc->length = sdp->sdp_header.HB3;
2864
2865 if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
2866 (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
2867 /*
2868 * - HB2 = 0x2, HB3 = 0x8
2869 * VSC SDP supporting 3D stereo + PSR
2870 * - HB2 = 0x4, HB3 = 0xe
2871 * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
2872 * first scan line of the SU region (applies to eDP v1.4b
2873 * and higher).
2874 */
2875 return 0;
2876 } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
2877 /*
2878 * - HB2 = 0x5, HB3 = 0x13
2879 * VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
2880 * Format.
2881 */
2882 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
2883 vsc->colorimetry = sdp->db[16] & 0xf;
2884 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
2885
2886 switch (sdp->db[17] & 0x7) {
2887 case 0x0:
2888 vsc->bpc = 6;
2889 break;
2890 case 0x1:
2891 vsc->bpc = 8;
2892 break;
2893 case 0x2:
2894 vsc->bpc = 10;
2895 break;
2896 case 0x3:
2897 vsc->bpc = 12;
2898 break;
2899 case 0x4:
2900 vsc->bpc = 16;
2901 break;
2902 default:
2903 MISSING_CASE(sdp->db[17] & 0x7);
2904 return -EINVAL;
2905 }
2906
2907 vsc->content_type = sdp->db[18] & 0x7;
2908 } else {
2909 return -EINVAL;
2910 }
2911
2912 return 0;
2913 }
2914
2915 static int
intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe * drm_infoframe,const void * buffer,size_t size)2916 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
2917 const void *buffer, size_t size)
2918 {
2919 int ret;
2920
2921 const struct dp_sdp *sdp = buffer;
2922
2923 if (size < sizeof(struct dp_sdp))
2924 return -EINVAL;
2925
2926 if (sdp->sdp_header.HB0 != 0)
2927 return -EINVAL;
2928
2929 if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
2930 return -EINVAL;
2931
2932 /*
2933 * Least Significant Eight Bits of (Data Byte Count – 1)
2934 * 1Dh (i.e., Data Byte Count = 30 bytes).
2935 */
2936 if (sdp->sdp_header.HB2 != 0x1D)
2937 return -EINVAL;
2938
2939 /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
2940 if ((sdp->sdp_header.HB3 & 0x3) != 0)
2941 return -EINVAL;
2942
2943 /* INFOFRAME SDP Version Number */
2944 if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
2945 return -EINVAL;
2946
2947 /* CTA Header Byte 2 (INFOFRAME Version Number) */
2948 if (sdp->db[0] != 1)
2949 return -EINVAL;
2950
2951 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
2952 if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
2953 return -EINVAL;
2954
2955 ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
2956 HDMI_DRM_INFOFRAME_SIZE);
2957
2958 return ret;
2959 }
2960
intel_read_dp_vsc_sdp(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_dp_vsc_sdp * vsc)2961 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
2962 struct intel_crtc_state *crtc_state,
2963 struct drm_dp_vsc_sdp *vsc)
2964 {
2965 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2966 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2967 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2968 unsigned int type = DP_SDP_VSC;
2969 struct dp_sdp sdp = {};
2970 int ret;
2971
2972 /* When PSR is enabled, VSC SDP is handled by PSR routine */
2973 if (intel_psr_enabled(intel_dp))
2974 return;
2975
2976 if ((crtc_state->infoframes.enable &
2977 intel_hdmi_infoframe_enable(type)) == 0)
2978 return;
2979
2980 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
2981
2982 ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
2983
2984 if (ret)
2985 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
2986 }
2987
intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct hdmi_drm_infoframe * drm_infoframe)2988 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
2989 struct intel_crtc_state *crtc_state,
2990 struct hdmi_drm_infoframe *drm_infoframe)
2991 {
2992 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2993 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2994 unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
2995 struct dp_sdp sdp = {};
2996 int ret;
2997
2998 if ((crtc_state->infoframes.enable &
2999 intel_hdmi_infoframe_enable(type)) == 0)
3000 return;
3001
3002 dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
3003 sizeof(sdp));
3004
3005 ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
3006 sizeof(sdp));
3007
3008 if (ret)
3009 drm_dbg_kms(&dev_priv->drm,
3010 "Failed to unpack DP HDR Metadata Infoframe SDP\n");
3011 }
3012
intel_read_dp_sdp(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,unsigned int type)3013 void intel_read_dp_sdp(struct intel_encoder *encoder,
3014 struct intel_crtc_state *crtc_state,
3015 unsigned int type)
3016 {
3017 if (encoder->type != INTEL_OUTPUT_DDI)
3018 return;
3019
3020 switch (type) {
3021 case DP_SDP_VSC:
3022 intel_read_dp_vsc_sdp(encoder, crtc_state,
3023 &crtc_state->infoframes.vsc);
3024 break;
3025 case HDMI_PACKET_TYPE_GAMUT_METADATA:
3026 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
3027 &crtc_state->infoframes.drm.drm);
3028 break;
3029 default:
3030 MISSING_CASE(type);
3031 break;
3032 }
3033 }
3034
intel_dp_autotest_link_training(struct intel_dp * intel_dp)3035 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3036 {
3037 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3038 int status = 0;
3039 int test_link_rate;
3040 u8 test_lane_count, test_link_bw;
3041 /* (DP CTS 1.2)
3042 * 4.3.1.11
3043 */
3044 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
3045 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
3046 &test_lane_count);
3047
3048 if (status <= 0) {
3049 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
3050 return DP_TEST_NAK;
3051 }
3052 test_lane_count &= DP_MAX_LANE_COUNT_MASK;
3053
3054 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
3055 &test_link_bw);
3056 if (status <= 0) {
3057 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
3058 return DP_TEST_NAK;
3059 }
3060 test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
3061
3062 /* Validate the requested link rate and lane count */
3063 if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
3064 test_lane_count))
3065 return DP_TEST_NAK;
3066
3067 intel_dp->compliance.test_lane_count = test_lane_count;
3068 intel_dp->compliance.test_link_rate = test_link_rate;
3069
3070 return DP_TEST_ACK;
3071 }
3072
intel_dp_autotest_video_pattern(struct intel_dp * intel_dp)3073 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3074 {
3075 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3076 u8 test_pattern;
3077 u8 test_misc;
3078 __be16 h_width, v_height;
3079 int status = 0;
3080
3081 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
3082 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
3083 &test_pattern);
3084 if (status <= 0) {
3085 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
3086 return DP_TEST_NAK;
3087 }
3088 if (test_pattern != DP_COLOR_RAMP)
3089 return DP_TEST_NAK;
3090
3091 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
3092 &h_width, 2);
3093 if (status <= 0) {
3094 drm_dbg_kms(&i915->drm, "H Width read failed\n");
3095 return DP_TEST_NAK;
3096 }
3097
3098 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
3099 &v_height, 2);
3100 if (status <= 0) {
3101 drm_dbg_kms(&i915->drm, "V Height read failed\n");
3102 return DP_TEST_NAK;
3103 }
3104
3105 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
3106 &test_misc);
3107 if (status <= 0) {
3108 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
3109 return DP_TEST_NAK;
3110 }
3111 if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
3112 return DP_TEST_NAK;
3113 if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
3114 return DP_TEST_NAK;
3115 switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
3116 case DP_TEST_BIT_DEPTH_6:
3117 intel_dp->compliance.test_data.bpc = 6;
3118 break;
3119 case DP_TEST_BIT_DEPTH_8:
3120 intel_dp->compliance.test_data.bpc = 8;
3121 break;
3122 default:
3123 return DP_TEST_NAK;
3124 }
3125
3126 intel_dp->compliance.test_data.video_pattern = test_pattern;
3127 intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
3128 intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
3129 /* Set test active flag here so userspace doesn't interrupt things */
3130 intel_dp->compliance.test_active = true;
3131
3132 return DP_TEST_ACK;
3133 }
3134
intel_dp_autotest_edid(struct intel_dp * intel_dp)3135 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
3136 {
3137 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3138 u8 test_result = DP_TEST_ACK;
3139 struct intel_connector *intel_connector = intel_dp->attached_connector;
3140 struct drm_connector *connector = &intel_connector->base;
3141
3142 if (intel_connector->detect_edid == NULL ||
3143 connector->edid_corrupt ||
3144 intel_dp->aux.i2c_defer_count > 6) {
3145 /* Check EDID read for NACKs, DEFERs and corruption
3146 * (DP CTS 1.2 Core r1.1)
3147 * 4.2.2.4 : Failed EDID read, I2C_NAK
3148 * 4.2.2.5 : Failed EDID read, I2C_DEFER
3149 * 4.2.2.6 : EDID corruption detected
3150 * Use failsafe mode for all cases
3151 */
3152 if (intel_dp->aux.i2c_nack_count > 0 ||
3153 intel_dp->aux.i2c_defer_count > 0)
3154 drm_dbg_kms(&i915->drm,
3155 "EDID read had %d NACKs, %d DEFERs\n",
3156 intel_dp->aux.i2c_nack_count,
3157 intel_dp->aux.i2c_defer_count);
3158 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
3159 } else {
3160 struct edid *block = intel_connector->detect_edid;
3161
3162 /* We have to write the checksum
3163 * of the last block read
3164 */
3165 block += intel_connector->detect_edid->extensions;
3166
3167 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
3168 block->checksum) <= 0)
3169 drm_dbg_kms(&i915->drm,
3170 "Failed to write EDID checksum\n");
3171
3172 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3173 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
3174 }
3175
3176 /* Set test active flag here so userspace doesn't interrupt things */
3177 intel_dp->compliance.test_active = true;
3178
3179 return test_result;
3180 }
3181
intel_dp_phy_pattern_update(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)3182 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
3183 const struct intel_crtc_state *crtc_state)
3184 {
3185 struct drm_i915_private *dev_priv =
3186 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3187 struct drm_dp_phy_test_params *data =
3188 &intel_dp->compliance.test_data.phytest;
3189 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3190 enum pipe pipe = crtc->pipe;
3191 u32 pattern_val;
3192
3193 switch (data->phy_pattern) {
3194 case DP_PHY_TEST_PATTERN_NONE:
3195 DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
3196 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
3197 break;
3198 case DP_PHY_TEST_PATTERN_D10_2:
3199 DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
3200 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3201 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
3202 break;
3203 case DP_PHY_TEST_PATTERN_ERROR_COUNT:
3204 DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
3205 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3206 DDI_DP_COMP_CTL_ENABLE |
3207 DDI_DP_COMP_CTL_SCRAMBLED_0);
3208 break;
3209 case DP_PHY_TEST_PATTERN_PRBS7:
3210 DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
3211 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3212 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
3213 break;
3214 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
3215 /*
3216 * FIXME: Ideally pattern should come from DPCD 0x250. As
3217 * current firmware of DPR-100 could not set it, so hardcoding
3218 * now for complaince test.
3219 */
3220 DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
3221 pattern_val = 0x3e0f83e0;
3222 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
3223 pattern_val = 0x0f83e0f8;
3224 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
3225 pattern_val = 0x0000f83e;
3226 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
3227 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3228 DDI_DP_COMP_CTL_ENABLE |
3229 DDI_DP_COMP_CTL_CUSTOM80);
3230 break;
3231 case DP_PHY_TEST_PATTERN_CP2520:
3232 /*
3233 * FIXME: Ideally pattern should come from DPCD 0x24A. As
3234 * current firmware of DPR-100 could not set it, so hardcoding
3235 * now for complaince test.
3236 */
3237 DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
3238 pattern_val = 0xFB;
3239 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3240 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
3241 pattern_val);
3242 break;
3243 default:
3244 WARN(1, "Invalid Phy Test Pattern\n");
3245 }
3246 }
3247
3248 static void
intel_dp_autotest_phy_ddi_disable(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)3249 intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp,
3250 const struct intel_crtc_state *crtc_state)
3251 {
3252 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3253 struct drm_device *dev = dig_port->base.base.dev;
3254 struct drm_i915_private *dev_priv = to_i915(dev);
3255 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
3256 enum pipe pipe = crtc->pipe;
3257 u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
3258
3259 trans_ddi_func_ctl_value = intel_de_read(dev_priv,
3260 TRANS_DDI_FUNC_CTL(pipe));
3261 trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
3262 dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
3263
3264 trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
3265 TGL_TRANS_DDI_PORT_MASK);
3266 trans_conf_value &= ~PIPECONF_ENABLE;
3267 dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
3268
3269 intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
3270 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
3271 trans_ddi_func_ctl_value);
3272 intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
3273 }
3274
3275 static void
intel_dp_autotest_phy_ddi_enable(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)3276 intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp,
3277 const struct intel_crtc_state *crtc_state)
3278 {
3279 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3280 struct drm_device *dev = dig_port->base.base.dev;
3281 struct drm_i915_private *dev_priv = to_i915(dev);
3282 enum port port = dig_port->base.port;
3283 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
3284 enum pipe pipe = crtc->pipe;
3285 u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
3286
3287 trans_ddi_func_ctl_value = intel_de_read(dev_priv,
3288 TRANS_DDI_FUNC_CTL(pipe));
3289 trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
3290 dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
3291
3292 trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
3293 TGL_TRANS_DDI_SELECT_PORT(port);
3294 trans_conf_value |= PIPECONF_ENABLE;
3295 dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
3296
3297 intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
3298 intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
3299 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
3300 trans_ddi_func_ctl_value);
3301 }
3302
intel_dp_process_phy_request(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)3303 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
3304 const struct intel_crtc_state *crtc_state)
3305 {
3306 struct drm_dp_phy_test_params *data =
3307 &intel_dp->compliance.test_data.phytest;
3308 u8 link_status[DP_LINK_STATUS_SIZE];
3309
3310 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3311 link_status) < 0) {
3312 DRM_DEBUG_KMS("failed to get link status\n");
3313 return;
3314 }
3315
3316 /* retrieve vswing & pre-emphasis setting */
3317 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
3318 link_status);
3319
3320 intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
3321
3322 intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
3323
3324 intel_dp_phy_pattern_update(intel_dp, crtc_state);
3325
3326 intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state);
3327
3328 drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
3329 link_status[DP_DPCD_REV]);
3330 }
3331
intel_dp_autotest_phy_pattern(struct intel_dp * intel_dp)3332 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3333 {
3334 struct drm_dp_phy_test_params *data =
3335 &intel_dp->compliance.test_data.phytest;
3336
3337 if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
3338 DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
3339 return DP_TEST_NAK;
3340 }
3341
3342 /* Set test active flag here so userspace doesn't interrupt things */
3343 intel_dp->compliance.test_active = true;
3344
3345 return DP_TEST_ACK;
3346 }
3347
intel_dp_handle_test_request(struct intel_dp * intel_dp)3348 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3349 {
3350 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3351 u8 response = DP_TEST_NAK;
3352 u8 request = 0;
3353 int status;
3354
3355 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
3356 if (status <= 0) {
3357 drm_dbg_kms(&i915->drm,
3358 "Could not read test request from sink\n");
3359 goto update_status;
3360 }
3361
3362 switch (request) {
3363 case DP_TEST_LINK_TRAINING:
3364 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
3365 response = intel_dp_autotest_link_training(intel_dp);
3366 break;
3367 case DP_TEST_LINK_VIDEO_PATTERN:
3368 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
3369 response = intel_dp_autotest_video_pattern(intel_dp);
3370 break;
3371 case DP_TEST_LINK_EDID_READ:
3372 drm_dbg_kms(&i915->drm, "EDID test requested\n");
3373 response = intel_dp_autotest_edid(intel_dp);
3374 break;
3375 case DP_TEST_LINK_PHY_TEST_PATTERN:
3376 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
3377 response = intel_dp_autotest_phy_pattern(intel_dp);
3378 break;
3379 default:
3380 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
3381 request);
3382 break;
3383 }
3384
3385 if (response & DP_TEST_ACK)
3386 intel_dp->compliance.test_type = request;
3387
3388 update_status:
3389 status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
3390 if (status <= 0)
3391 drm_dbg_kms(&i915->drm,
3392 "Could not write test response to sink\n");
3393 }
3394
3395 static void
intel_dp_mst_hpd_irq(struct intel_dp * intel_dp,u8 * esi,bool * handled)3396 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, bool *handled)
3397 {
3398 drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, handled);
3399
3400 if (esi[1] & DP_CP_IRQ) {
3401 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
3402 *handled = true;
3403 }
3404 }
3405
3406 /**
3407 * intel_dp_check_mst_status - service any pending MST interrupts, check link status
3408 * @intel_dp: Intel DP struct
3409 *
3410 * Read any pending MST interrupts, call MST core to handle these and ack the
3411 * interrupts. Check if the main and AUX link state is ok.
3412 *
3413 * Returns:
3414 * - %true if pending interrupts were serviced (or no interrupts were
3415 * pending) w/o detecting an error condition.
3416 * - %false if an error condition - like AUX failure or a loss of link - is
3417 * detected, which needs servicing from the hotplug work.
3418 */
3419 static bool
intel_dp_check_mst_status(struct intel_dp * intel_dp)3420 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3421 {
3422 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3423 bool link_ok = true;
3424
3425 drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
3426
3427 for (;;) {
3428 /*
3429 * The +2 is because DP_DPRX_ESI_LEN is 14, but we then
3430 * pass in "esi+10" to drm_dp_channel_eq_ok(), which
3431 * takes a 6-byte array. So we actually need 16 bytes
3432 * here.
3433 *
3434 * Somebody who knows what the limits actually are
3435 * should check this, but for now this is at least
3436 * harmless and avoids a valid compiler warning about
3437 * using more of the array than we have allocated.
3438 */
3439 u8 esi[DP_DPRX_ESI_LEN+2] = {};
3440 bool handled;
3441 int retry;
3442
3443 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
3444 drm_dbg_kms(&i915->drm,
3445 "failed to get ESI - device may have failed\n");
3446 link_ok = false;
3447
3448 break;
3449 }
3450
3451 /* check link status - esi[10] = 0x200c */
3452 if (intel_dp->active_mst_links > 0 && link_ok &&
3453 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3454 drm_dbg_kms(&i915->drm,
3455 "channel EQ not ok, retraining\n");
3456 link_ok = false;
3457 }
3458
3459 drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
3460
3461 intel_dp_mst_hpd_irq(intel_dp, esi, &handled);
3462
3463 if (!handled)
3464 break;
3465
3466 for (retry = 0; retry < 3; retry++) {
3467 int wret;
3468
3469 wret = drm_dp_dpcd_write(&intel_dp->aux,
3470 DP_SINK_COUNT_ESI+1,
3471 &esi[1], 3);
3472 if (wret == 3)
3473 break;
3474 }
3475 }
3476
3477 return link_ok;
3478 }
3479
3480 static void
intel_dp_handle_hdmi_link_status_change(struct intel_dp * intel_dp)3481 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
3482 {
3483 bool is_active;
3484 u8 buf = 0;
3485
3486 is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
3487 if (intel_dp->frl.is_trained && !is_active) {
3488 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
3489 return;
3490
3491 buf &= ~DP_PCON_ENABLE_HDMI_LINK;
3492 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
3493 return;
3494
3495 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
3496
3497 /* Restart FRL training or fall back to TMDS mode */
3498 intel_dp_check_frl_training(intel_dp);
3499 }
3500 }
3501
3502 static bool
intel_dp_needs_link_retrain(struct intel_dp * intel_dp)3503 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
3504 {
3505 u8 link_status[DP_LINK_STATUS_SIZE];
3506
3507 if (!intel_dp->link_trained)
3508 return false;
3509
3510 /*
3511 * While PSR source HW is enabled, it will control main-link sending
3512 * frames, enabling and disabling it so trying to do a retrain will fail
3513 * as the link would or not be on or it could mix training patterns
3514 * and frame data at the same time causing retrain to fail.
3515 * Also when exiting PSR, HW will retrain the link anyways fixing
3516 * any link status error.
3517 */
3518 if (intel_psr_enabled(intel_dp))
3519 return false;
3520
3521 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3522 link_status) < 0)
3523 return false;
3524
3525 /*
3526 * Validate the cached values of intel_dp->link_rate and
3527 * intel_dp->lane_count before attempting to retrain.
3528 *
3529 * FIXME would be nice to user the crtc state here, but since
3530 * we need to call this from the short HPD handler that seems
3531 * a bit hard.
3532 */
3533 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
3534 intel_dp->lane_count))
3535 return false;
3536
3537 /* Retrain if Channel EQ or CR not ok */
3538 return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
3539 }
3540
intel_dp_has_connector(struct intel_dp * intel_dp,const struct drm_connector_state * conn_state)3541 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
3542 const struct drm_connector_state *conn_state)
3543 {
3544 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3545 struct intel_encoder *encoder;
3546 enum pipe pipe;
3547
3548 if (!conn_state->best_encoder)
3549 return false;
3550
3551 /* SST */
3552 encoder = &dp_to_dig_port(intel_dp)->base;
3553 if (conn_state->best_encoder == &encoder->base)
3554 return true;
3555
3556 /* MST */
3557 for_each_pipe(i915, pipe) {
3558 encoder = &intel_dp->mst_encoders[pipe]->base;
3559 if (conn_state->best_encoder == &encoder->base)
3560 return true;
3561 }
3562
3563 return false;
3564 }
3565
intel_dp_prep_link_retrain(struct intel_dp * intel_dp,struct drm_modeset_acquire_ctx * ctx,u32 * crtc_mask)3566 static int intel_dp_prep_link_retrain(struct intel_dp *intel_dp,
3567 struct drm_modeset_acquire_ctx *ctx,
3568 u32 *crtc_mask)
3569 {
3570 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3571 struct drm_connector_list_iter conn_iter;
3572 struct intel_connector *connector;
3573 int ret = 0;
3574
3575 *crtc_mask = 0;
3576
3577 if (!intel_dp_needs_link_retrain(intel_dp))
3578 return 0;
3579
3580 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
3581 for_each_intel_connector_iter(connector, &conn_iter) {
3582 struct drm_connector_state *conn_state =
3583 connector->base.state;
3584 struct intel_crtc_state *crtc_state;
3585 struct intel_crtc *crtc;
3586
3587 if (!intel_dp_has_connector(intel_dp, conn_state))
3588 continue;
3589
3590 crtc = to_intel_crtc(conn_state->crtc);
3591 if (!crtc)
3592 continue;
3593
3594 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3595 if (ret)
3596 break;
3597
3598 crtc_state = to_intel_crtc_state(crtc->base.state);
3599
3600 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
3601
3602 if (!crtc_state->hw.active)
3603 continue;
3604
3605 if (conn_state->commit &&
3606 !try_wait_for_completion(&conn_state->commit->hw_done))
3607 continue;
3608
3609 *crtc_mask |= drm_crtc_mask(&crtc->base);
3610 }
3611 drm_connector_list_iter_end(&conn_iter);
3612
3613 if (!intel_dp_needs_link_retrain(intel_dp))
3614 *crtc_mask = 0;
3615
3616 return ret;
3617 }
3618
intel_dp_is_connected(struct intel_dp * intel_dp)3619 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
3620 {
3621 struct intel_connector *connector = intel_dp->attached_connector;
3622
3623 return connector->base.status == connector_status_connected ||
3624 intel_dp->is_mst;
3625 }
3626
intel_dp_retrain_link(struct intel_encoder * encoder,struct drm_modeset_acquire_ctx * ctx)3627 int intel_dp_retrain_link(struct intel_encoder *encoder,
3628 struct drm_modeset_acquire_ctx *ctx)
3629 {
3630 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3631 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3632 struct intel_crtc *crtc;
3633 u32 crtc_mask;
3634 int ret;
3635
3636 if (!intel_dp_is_connected(intel_dp))
3637 return 0;
3638
3639 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3640 ctx);
3641 if (ret)
3642 return ret;
3643
3644 ret = intel_dp_prep_link_retrain(intel_dp, ctx, &crtc_mask);
3645 if (ret)
3646 return ret;
3647
3648 if (crtc_mask == 0)
3649 return 0;
3650
3651 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
3652 encoder->base.base.id, encoder->base.name);
3653
3654 for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
3655 const struct intel_crtc_state *crtc_state =
3656 to_intel_crtc_state(crtc->base.state);
3657
3658 /* Suppress underruns caused by re-training */
3659 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
3660 if (crtc_state->has_pch_encoder)
3661 intel_set_pch_fifo_underrun_reporting(dev_priv,
3662 intel_crtc_pch_transcoder(crtc), false);
3663 }
3664
3665 for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
3666 const struct intel_crtc_state *crtc_state =
3667 to_intel_crtc_state(crtc->base.state);
3668
3669 /* retrain on the MST master transcoder */
3670 if (DISPLAY_VER(dev_priv) >= 12 &&
3671 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
3672 !intel_dp_mst_is_master_trans(crtc_state))
3673 continue;
3674
3675 intel_dp_check_frl_training(intel_dp);
3676 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
3677 intel_dp_start_link_train(intel_dp, crtc_state);
3678 intel_dp_stop_link_train(intel_dp, crtc_state);
3679 break;
3680 }
3681
3682 for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
3683 const struct intel_crtc_state *crtc_state =
3684 to_intel_crtc_state(crtc->base.state);
3685
3686 /* Keep underrun reporting disabled until things are stable */
3687 intel_wait_for_vblank(dev_priv, crtc->pipe);
3688
3689 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
3690 if (crtc_state->has_pch_encoder)
3691 intel_set_pch_fifo_underrun_reporting(dev_priv,
3692 intel_crtc_pch_transcoder(crtc), true);
3693 }
3694
3695 return 0;
3696 }
3697
intel_dp_prep_phy_test(struct intel_dp * intel_dp,struct drm_modeset_acquire_ctx * ctx,u32 * crtc_mask)3698 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
3699 struct drm_modeset_acquire_ctx *ctx,
3700 u32 *crtc_mask)
3701 {
3702 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3703 struct drm_connector_list_iter conn_iter;
3704 struct intel_connector *connector;
3705 int ret = 0;
3706
3707 *crtc_mask = 0;
3708
3709 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
3710 for_each_intel_connector_iter(connector, &conn_iter) {
3711 struct drm_connector_state *conn_state =
3712 connector->base.state;
3713 struct intel_crtc_state *crtc_state;
3714 struct intel_crtc *crtc;
3715
3716 if (!intel_dp_has_connector(intel_dp, conn_state))
3717 continue;
3718
3719 crtc = to_intel_crtc(conn_state->crtc);
3720 if (!crtc)
3721 continue;
3722
3723 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3724 if (ret)
3725 break;
3726
3727 crtc_state = to_intel_crtc_state(crtc->base.state);
3728
3729 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
3730
3731 if (!crtc_state->hw.active)
3732 continue;
3733
3734 if (conn_state->commit &&
3735 !try_wait_for_completion(&conn_state->commit->hw_done))
3736 continue;
3737
3738 *crtc_mask |= drm_crtc_mask(&crtc->base);
3739 }
3740 drm_connector_list_iter_end(&conn_iter);
3741
3742 return ret;
3743 }
3744
intel_dp_do_phy_test(struct intel_encoder * encoder,struct drm_modeset_acquire_ctx * ctx)3745 static int intel_dp_do_phy_test(struct intel_encoder *encoder,
3746 struct drm_modeset_acquire_ctx *ctx)
3747 {
3748 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3749 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3750 struct intel_crtc *crtc;
3751 u32 crtc_mask;
3752 int ret;
3753
3754 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3755 ctx);
3756 if (ret)
3757 return ret;
3758
3759 ret = intel_dp_prep_phy_test(intel_dp, ctx, &crtc_mask);
3760 if (ret)
3761 return ret;
3762
3763 if (crtc_mask == 0)
3764 return 0;
3765
3766 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
3767 encoder->base.base.id, encoder->base.name);
3768
3769 for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
3770 const struct intel_crtc_state *crtc_state =
3771 to_intel_crtc_state(crtc->base.state);
3772
3773 /* test on the MST master transcoder */
3774 if (DISPLAY_VER(dev_priv) >= 12 &&
3775 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
3776 !intel_dp_mst_is_master_trans(crtc_state))
3777 continue;
3778
3779 intel_dp_process_phy_request(intel_dp, crtc_state);
3780 break;
3781 }
3782
3783 return 0;
3784 }
3785
intel_dp_phy_test(struct intel_encoder * encoder)3786 void intel_dp_phy_test(struct intel_encoder *encoder)
3787 {
3788 struct drm_modeset_acquire_ctx ctx;
3789 int ret;
3790
3791 drm_modeset_acquire_init(&ctx, 0);
3792
3793 for (;;) {
3794 ret = intel_dp_do_phy_test(encoder, &ctx);
3795
3796 if (ret == -EDEADLK) {
3797 drm_modeset_backoff(&ctx);
3798 continue;
3799 }
3800
3801 break;
3802 }
3803
3804 drm_modeset_drop_locks(&ctx);
3805 drm_modeset_acquire_fini(&ctx);
3806 drm_WARN(encoder->base.dev, ret,
3807 "Acquiring modeset locks failed with %i\n", ret);
3808 }
3809
intel_dp_check_device_service_irq(struct intel_dp * intel_dp)3810 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
3811 {
3812 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3813 u8 val;
3814
3815 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3816 return;
3817
3818 if (drm_dp_dpcd_readb(&intel_dp->aux,
3819 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
3820 return;
3821
3822 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
3823
3824 if (val & DP_AUTOMATED_TEST_REQUEST)
3825 intel_dp_handle_test_request(intel_dp);
3826
3827 if (val & DP_CP_IRQ)
3828 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
3829
3830 if (val & DP_SINK_SPECIFIC_IRQ)
3831 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
3832 }
3833
intel_dp_check_link_service_irq(struct intel_dp * intel_dp)3834 static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
3835 {
3836 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3837 u8 val;
3838
3839 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3840 return;
3841
3842 if (drm_dp_dpcd_readb(&intel_dp->aux,
3843 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val) {
3844 drm_dbg_kms(&i915->drm, "Error in reading link service irq vector\n");
3845 return;
3846 }
3847
3848 if (drm_dp_dpcd_writeb(&intel_dp->aux,
3849 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1) {
3850 drm_dbg_kms(&i915->drm, "Error in writing link service irq vector\n");
3851 return;
3852 }
3853
3854 if (val & HDMI_LINK_STATUS_CHANGED)
3855 intel_dp_handle_hdmi_link_status_change(intel_dp);
3856 }
3857
3858 /*
3859 * According to DP spec
3860 * 5.1.2:
3861 * 1. Read DPCD
3862 * 2. Configure link according to Receiver Capabilities
3863 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3864 * 4. Check link status on receipt of hot-plug interrupt
3865 *
3866 * intel_dp_short_pulse - handles short pulse interrupts
3867 * when full detection is not required.
3868 * Returns %true if short pulse is handled and full detection
3869 * is NOT required and %false otherwise.
3870 */
3871 static bool
intel_dp_short_pulse(struct intel_dp * intel_dp)3872 intel_dp_short_pulse(struct intel_dp *intel_dp)
3873 {
3874 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3875 u8 old_sink_count = intel_dp->sink_count;
3876 bool ret;
3877
3878 /*
3879 * Clearing compliance test variables to allow capturing
3880 * of values for next automated test request.
3881 */
3882 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
3883
3884 /*
3885 * Now read the DPCD to see if it's actually running
3886 * If the current value of sink count doesn't match with
3887 * the value that was stored earlier or dpcd read failed
3888 * we need to do full detection
3889 */
3890 ret = intel_dp_get_dpcd(intel_dp);
3891
3892 if ((old_sink_count != intel_dp->sink_count) || !ret) {
3893 /* No need to proceed if we are going to do full detect */
3894 return false;
3895 }
3896
3897 intel_dp_check_device_service_irq(intel_dp);
3898 intel_dp_check_link_service_irq(intel_dp);
3899
3900 /* Handle CEC interrupts, if any */
3901 drm_dp_cec_irq(&intel_dp->aux);
3902
3903 /* defer to the hotplug work for link retraining if needed */
3904 if (intel_dp_needs_link_retrain(intel_dp))
3905 return false;
3906
3907 intel_psr_short_pulse(intel_dp);
3908
3909 switch (intel_dp->compliance.test_type) {
3910 case DP_TEST_LINK_TRAINING:
3911 drm_dbg_kms(&dev_priv->drm,
3912 "Link Training Compliance Test requested\n");
3913 /* Send a Hotplug Uevent to userspace to start modeset */
3914 drm_kms_helper_hotplug_event(&dev_priv->drm);
3915 break;
3916 case DP_TEST_LINK_PHY_TEST_PATTERN:
3917 drm_dbg_kms(&dev_priv->drm,
3918 "PHY test pattern Compliance Test requested\n");
3919 /*
3920 * Schedule long hpd to do the test
3921 *
3922 * FIXME get rid of the ad-hoc phy test modeset code
3923 * and properly incorporate it into the normal modeset.
3924 */
3925 return false;
3926 }
3927
3928 return true;
3929 }
3930
3931 /* XXX this is probably wrong for multiple downstream ports */
3932 static enum drm_connector_status
intel_dp_detect_dpcd(struct intel_dp * intel_dp)3933 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3934 {
3935 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3936 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3937 u8 *dpcd = intel_dp->dpcd;
3938 u8 type;
3939
3940 if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
3941 return connector_status_connected;
3942
3943 lspcon_resume(dig_port);
3944
3945 if (!intel_dp_get_dpcd(intel_dp))
3946 return connector_status_disconnected;
3947
3948 /* if there's no downstream port, we're done */
3949 if (!drm_dp_is_branch(dpcd))
3950 return connector_status_connected;
3951
3952 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3953 if (intel_dp_has_sink_count(intel_dp) &&
3954 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3955 return intel_dp->sink_count ?
3956 connector_status_connected : connector_status_disconnected;
3957 }
3958
3959 if (intel_dp_can_mst(intel_dp))
3960 return connector_status_connected;
3961
3962 /* If no HPD, poke DDC gently */
3963 if (drm_probe_ddc(&intel_dp->aux.ddc))
3964 return connector_status_connected;
3965
3966 /* Well we tried, say unknown for unreliable port types */
3967 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3968 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3969 if (type == DP_DS_PORT_TYPE_VGA ||
3970 type == DP_DS_PORT_TYPE_NON_EDID)
3971 return connector_status_unknown;
3972 } else {
3973 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3974 DP_DWN_STRM_PORT_TYPE_MASK;
3975 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3976 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3977 return connector_status_unknown;
3978 }
3979
3980 /* Anything else is out of spec, warn and ignore */
3981 drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
3982 return connector_status_disconnected;
3983 }
3984
3985 static enum drm_connector_status
edp_detect(struct intel_dp * intel_dp)3986 edp_detect(struct intel_dp *intel_dp)
3987 {
3988 return connector_status_connected;
3989 }
3990
3991 /*
3992 * intel_digital_port_connected - is the specified port connected?
3993 * @encoder: intel_encoder
3994 *
3995 * In cases where there's a connector physically connected but it can't be used
3996 * by our hardware we also return false, since the rest of the driver should
3997 * pretty much treat the port as disconnected. This is relevant for type-C
3998 * (starting on ICL) where there's ownership involved.
3999 *
4000 * Return %true if port is connected, %false otherwise.
4001 */
intel_digital_port_connected(struct intel_encoder * encoder)4002 bool intel_digital_port_connected(struct intel_encoder *encoder)
4003 {
4004 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4005 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4006 bool is_connected = false;
4007 intel_wakeref_t wakeref;
4008
4009 with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
4010 is_connected = dig_port->connected(encoder);
4011
4012 return is_connected;
4013 }
4014
4015 static struct edid *
intel_dp_get_edid(struct intel_dp * intel_dp)4016 intel_dp_get_edid(struct intel_dp *intel_dp)
4017 {
4018 struct intel_connector *intel_connector = intel_dp->attached_connector;
4019
4020 /* use cached edid if we have one */
4021 if (intel_connector->edid) {
4022 /* invalid edid */
4023 if (IS_ERR(intel_connector->edid))
4024 return NULL;
4025
4026 return drm_edid_duplicate(intel_connector->edid);
4027 } else
4028 return drm_get_edid(&intel_connector->base,
4029 &intel_dp->aux.ddc);
4030 }
4031
4032 static void
intel_dp_update_dfp(struct intel_dp * intel_dp,const struct edid * edid)4033 intel_dp_update_dfp(struct intel_dp *intel_dp,
4034 const struct edid *edid)
4035 {
4036 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4037 struct intel_connector *connector = intel_dp->attached_connector;
4038
4039 intel_dp->dfp.max_bpc =
4040 drm_dp_downstream_max_bpc(intel_dp->dpcd,
4041 intel_dp->downstream_ports, edid);
4042
4043 intel_dp->dfp.max_dotclock =
4044 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
4045 intel_dp->downstream_ports);
4046
4047 intel_dp->dfp.min_tmds_clock =
4048 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
4049 intel_dp->downstream_ports,
4050 edid);
4051 intel_dp->dfp.max_tmds_clock =
4052 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
4053 intel_dp->downstream_ports,
4054 edid);
4055
4056 intel_dp->dfp.pcon_max_frl_bw =
4057 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
4058 intel_dp->downstream_ports);
4059
4060 drm_dbg_kms(&i915->drm,
4061 "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
4062 connector->base.base.id, connector->base.name,
4063 intel_dp->dfp.max_bpc,
4064 intel_dp->dfp.max_dotclock,
4065 intel_dp->dfp.min_tmds_clock,
4066 intel_dp->dfp.max_tmds_clock,
4067 intel_dp->dfp.pcon_max_frl_bw);
4068
4069 intel_dp_get_pcon_dsc_cap(intel_dp);
4070 }
4071
4072 static void
intel_dp_update_420(struct intel_dp * intel_dp)4073 intel_dp_update_420(struct intel_dp *intel_dp)
4074 {
4075 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4076 struct intel_connector *connector = intel_dp->attached_connector;
4077 bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420, rgb_to_ycbcr;
4078
4079 /* No YCbCr output support on gmch platforms */
4080 if (HAS_GMCH(i915))
4081 return;
4082
4083 /*
4084 * ILK doesn't seem capable of DP YCbCr output. The
4085 * displayed image is severly corrupted. SNB+ is fine.
4086 */
4087 if (IS_IRONLAKE(i915))
4088 return;
4089
4090 is_branch = drm_dp_is_branch(intel_dp->dpcd);
4091 ycbcr_420_passthrough =
4092 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
4093 intel_dp->downstream_ports);
4094 /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
4095 ycbcr_444_to_420 =
4096 dp_to_dig_port(intel_dp)->lspcon.active ||
4097 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
4098 intel_dp->downstream_ports);
4099 rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
4100 intel_dp->downstream_ports,
4101 DP_DS_HDMI_BT601_RGB_YCBCR_CONV |
4102 DP_DS_HDMI_BT709_RGB_YCBCR_CONV |
4103 DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
4104
4105 if (DISPLAY_VER(i915) >= 11) {
4106 /* Let PCON convert from RGB->YCbCr if possible */
4107 if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) {
4108 intel_dp->dfp.rgb_to_ycbcr = true;
4109 intel_dp->dfp.ycbcr_444_to_420 = true;
4110 connector->base.ycbcr_420_allowed = true;
4111 } else {
4112 /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
4113 intel_dp->dfp.ycbcr_444_to_420 =
4114 ycbcr_444_to_420 && !ycbcr_420_passthrough;
4115
4116 connector->base.ycbcr_420_allowed =
4117 !is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough;
4118 }
4119 } else {
4120 /* 4:4:4->4:2:0 conversion is the only way */
4121 intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420;
4122
4123 connector->base.ycbcr_420_allowed = ycbcr_444_to_420;
4124 }
4125
4126 drm_dbg_kms(&i915->drm,
4127 "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
4128 connector->base.base.id, connector->base.name,
4129 yesno(intel_dp->dfp.rgb_to_ycbcr),
4130 yesno(connector->base.ycbcr_420_allowed),
4131 yesno(intel_dp->dfp.ycbcr_444_to_420));
4132 }
4133
4134 static void
intel_dp_set_edid(struct intel_dp * intel_dp)4135 intel_dp_set_edid(struct intel_dp *intel_dp)
4136 {
4137 struct intel_connector *connector = intel_dp->attached_connector;
4138 struct edid *edid;
4139
4140 intel_dp_unset_edid(intel_dp);
4141 edid = intel_dp_get_edid(intel_dp);
4142 connector->detect_edid = edid;
4143
4144 intel_dp_update_dfp(intel_dp, edid);
4145 intel_dp_update_420(intel_dp);
4146
4147 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
4148 intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
4149 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4150 }
4151
4152 drm_dp_cec_set_edid(&intel_dp->aux, edid);
4153 }
4154
4155 static void
intel_dp_unset_edid(struct intel_dp * intel_dp)4156 intel_dp_unset_edid(struct intel_dp *intel_dp)
4157 {
4158 struct intel_connector *connector = intel_dp->attached_connector;
4159
4160 drm_dp_cec_unset_edid(&intel_dp->aux);
4161 kfree(connector->detect_edid);
4162 connector->detect_edid = NULL;
4163
4164 intel_dp->has_hdmi_sink = false;
4165 intel_dp->has_audio = false;
4166
4167 intel_dp->dfp.max_bpc = 0;
4168 intel_dp->dfp.max_dotclock = 0;
4169 intel_dp->dfp.min_tmds_clock = 0;
4170 intel_dp->dfp.max_tmds_clock = 0;
4171
4172 intel_dp->dfp.pcon_max_frl_bw = 0;
4173
4174 intel_dp->dfp.ycbcr_444_to_420 = false;
4175 connector->base.ycbcr_420_allowed = false;
4176 }
4177
4178 static int
intel_dp_detect(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)4179 intel_dp_detect(struct drm_connector *connector,
4180 struct drm_modeset_acquire_ctx *ctx,
4181 bool force)
4182 {
4183 struct drm_i915_private *dev_priv = to_i915(connector->dev);
4184 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4185 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4186 struct intel_encoder *encoder = &dig_port->base;
4187 enum drm_connector_status status;
4188
4189 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4190 connector->base.id, connector->name);
4191 drm_WARN_ON(&dev_priv->drm,
4192 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4193
4194 if (!INTEL_DISPLAY_ENABLED(dev_priv))
4195 return connector_status_disconnected;
4196
4197 /* Can't disconnect eDP */
4198 if (intel_dp_is_edp(intel_dp))
4199 status = edp_detect(intel_dp);
4200 else if (intel_digital_port_connected(encoder))
4201 status = intel_dp_detect_dpcd(intel_dp);
4202 else
4203 status = connector_status_disconnected;
4204
4205 if (status == connector_status_disconnected) {
4206 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4207 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4208
4209 if (intel_dp->is_mst) {
4210 drm_dbg_kms(&dev_priv->drm,
4211 "MST device may have disappeared %d vs %d\n",
4212 intel_dp->is_mst,
4213 intel_dp->mst_mgr.mst_state);
4214 intel_dp->is_mst = false;
4215 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4216 intel_dp->is_mst);
4217 }
4218
4219 goto out;
4220 }
4221
4222 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
4223 if (DISPLAY_VER(dev_priv) >= 11)
4224 intel_dp_get_dsc_sink_cap(intel_dp);
4225
4226 intel_dp_configure_mst(intel_dp);
4227
4228 /*
4229 * TODO: Reset link params when switching to MST mode, until MST
4230 * supports link training fallback params.
4231 */
4232 if (intel_dp->reset_link_params || intel_dp->is_mst) {
4233 /* Initial max link lane count */
4234 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
4235
4236 /* Initial max link rate */
4237 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
4238
4239 intel_dp->reset_link_params = false;
4240 }
4241
4242 intel_dp_print_rates(intel_dp);
4243
4244 if (intel_dp->is_mst) {
4245 /*
4246 * If we are in MST mode then this connector
4247 * won't appear connected or have anything
4248 * with EDID on it
4249 */
4250 status = connector_status_disconnected;
4251 goto out;
4252 }
4253
4254 /*
4255 * Some external monitors do not signal loss of link synchronization
4256 * with an IRQ_HPD, so force a link status check.
4257 */
4258 if (!intel_dp_is_edp(intel_dp)) {
4259 int ret;
4260
4261 ret = intel_dp_retrain_link(encoder, ctx);
4262 if (ret)
4263 return ret;
4264 }
4265
4266 /*
4267 * Clearing NACK and defer counts to get their exact values
4268 * while reading EDID which are required by Compliance tests
4269 * 4.2.2.4 and 4.2.2.5
4270 */
4271 intel_dp->aux.i2c_nack_count = 0;
4272 intel_dp->aux.i2c_defer_count = 0;
4273
4274 intel_dp_set_edid(intel_dp);
4275 if (intel_dp_is_edp(intel_dp) ||
4276 to_intel_connector(connector)->detect_edid)
4277 status = connector_status_connected;
4278
4279 intel_dp_check_device_service_irq(intel_dp);
4280
4281 out:
4282 if (status != connector_status_connected && !intel_dp->is_mst)
4283 intel_dp_unset_edid(intel_dp);
4284
4285 /*
4286 * Make sure the refs for power wells enabled during detect are
4287 * dropped to avoid a new detect cycle triggered by HPD polling.
4288 */
4289 intel_display_power_flush_work(dev_priv);
4290
4291 if (!intel_dp_is_edp(intel_dp))
4292 drm_dp_set_subconnector_property(connector,
4293 status,
4294 intel_dp->dpcd,
4295 intel_dp->downstream_ports);
4296 return status;
4297 }
4298
4299 static void
intel_dp_force(struct drm_connector * connector)4300 intel_dp_force(struct drm_connector *connector)
4301 {
4302 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4303 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4304 struct intel_encoder *intel_encoder = &dig_port->base;
4305 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4306 enum intel_display_power_domain aux_domain =
4307 intel_aux_power_domain(dig_port);
4308 intel_wakeref_t wakeref;
4309
4310 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4311 connector->base.id, connector->name);
4312 intel_dp_unset_edid(intel_dp);
4313
4314 if (connector->status != connector_status_connected)
4315 return;
4316
4317 wakeref = intel_display_power_get(dev_priv, aux_domain);
4318
4319 intel_dp_set_edid(intel_dp);
4320
4321 intel_display_power_put(dev_priv, aux_domain, wakeref);
4322 }
4323
intel_dp_get_modes(struct drm_connector * connector)4324 static int intel_dp_get_modes(struct drm_connector *connector)
4325 {
4326 struct intel_connector *intel_connector = to_intel_connector(connector);
4327 struct edid *edid;
4328 int num_modes = 0;
4329
4330 edid = intel_connector->detect_edid;
4331 if (edid) {
4332 num_modes = intel_connector_update_modes(connector, edid);
4333
4334 if (intel_vrr_is_capable(connector))
4335 drm_connector_set_vrr_capable_property(connector,
4336 true);
4337 }
4338
4339 /* Also add fixed mode, which may or may not be present in EDID */
4340 if (intel_dp_is_edp(intel_attached_dp(intel_connector)) &&
4341 intel_connector->panel.fixed_mode) {
4342 struct drm_display_mode *mode;
4343
4344 mode = drm_mode_duplicate(connector->dev,
4345 intel_connector->panel.fixed_mode);
4346 if (mode) {
4347 drm_mode_probed_add(connector, mode);
4348 num_modes++;
4349 }
4350 }
4351
4352 if (num_modes)
4353 return num_modes;
4354
4355 if (!edid) {
4356 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
4357 struct drm_display_mode *mode;
4358
4359 mode = drm_dp_downstream_mode(connector->dev,
4360 intel_dp->dpcd,
4361 intel_dp->downstream_ports);
4362 if (mode) {
4363 drm_mode_probed_add(connector, mode);
4364 num_modes++;
4365 }
4366 }
4367
4368 return num_modes;
4369 }
4370
4371 static int
intel_dp_connector_register(struct drm_connector * connector)4372 intel_dp_connector_register(struct drm_connector *connector)
4373 {
4374 struct drm_i915_private *i915 = to_i915(connector->dev);
4375 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4376 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4377 struct intel_lspcon *lspcon = &dig_port->lspcon;
4378 int ret;
4379
4380 ret = intel_connector_register(connector);
4381 if (ret)
4382 return ret;
4383
4384 drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
4385 intel_dp->aux.name, connector->kdev->kobj.name);
4386
4387 intel_dp->aux.dev = connector->kdev;
4388 ret = drm_dp_aux_register(&intel_dp->aux);
4389 if (!ret)
4390 drm_dp_cec_register_connector(&intel_dp->aux, connector);
4391
4392 if (!intel_bios_is_lspcon_present(i915, dig_port->base.port))
4393 return ret;
4394
4395 /*
4396 * ToDo: Clean this up to handle lspcon init and resume more
4397 * efficiently and streamlined.
4398 */
4399 if (lspcon_init(dig_port)) {
4400 lspcon_detect_hdr_capability(lspcon);
4401 if (lspcon->hdr_supported)
4402 drm_object_attach_property(&connector->base,
4403 connector->dev->mode_config.hdr_output_metadata_property,
4404 0);
4405 }
4406
4407 return ret;
4408 }
4409
4410 static void
intel_dp_connector_unregister(struct drm_connector * connector)4411 intel_dp_connector_unregister(struct drm_connector *connector)
4412 {
4413 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4414
4415 drm_dp_cec_unregister_connector(&intel_dp->aux);
4416 drm_dp_aux_unregister(&intel_dp->aux);
4417 intel_connector_unregister(connector);
4418 }
4419
intel_dp_encoder_flush_work(struct drm_encoder * encoder)4420 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
4421 {
4422 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4423 struct intel_dp *intel_dp = &dig_port->dp;
4424
4425 intel_dp_mst_encoder_cleanup(dig_port);
4426
4427 intel_pps_vdd_off_sync(intel_dp);
4428
4429 intel_dp_aux_fini(intel_dp);
4430 }
4431
intel_dp_encoder_suspend(struct intel_encoder * intel_encoder)4432 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4433 {
4434 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
4435
4436 intel_pps_vdd_off_sync(intel_dp);
4437 }
4438
intel_dp_encoder_shutdown(struct intel_encoder * intel_encoder)4439 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
4440 {
4441 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
4442
4443 intel_pps_wait_power_cycle(intel_dp);
4444 }
4445
intel_modeset_tile_group(struct intel_atomic_state * state,int tile_group_id)4446 static int intel_modeset_tile_group(struct intel_atomic_state *state,
4447 int tile_group_id)
4448 {
4449 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4450 struct drm_connector_list_iter conn_iter;
4451 struct drm_connector *connector;
4452 int ret = 0;
4453
4454 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
4455 drm_for_each_connector_iter(connector, &conn_iter) {
4456 struct drm_connector_state *conn_state;
4457 struct intel_crtc_state *crtc_state;
4458 struct intel_crtc *crtc;
4459
4460 if (!connector->has_tile ||
4461 connector->tile_group->id != tile_group_id)
4462 continue;
4463
4464 conn_state = drm_atomic_get_connector_state(&state->base,
4465 connector);
4466 if (IS_ERR(conn_state)) {
4467 ret = PTR_ERR(conn_state);
4468 break;
4469 }
4470
4471 crtc = to_intel_crtc(conn_state->crtc);
4472
4473 if (!crtc)
4474 continue;
4475
4476 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
4477 crtc_state->uapi.mode_changed = true;
4478
4479 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
4480 if (ret)
4481 break;
4482 }
4483 drm_connector_list_iter_end(&conn_iter);
4484
4485 return ret;
4486 }
4487
intel_modeset_affected_transcoders(struct intel_atomic_state * state,u8 transcoders)4488 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
4489 {
4490 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4491 struct intel_crtc *crtc;
4492
4493 if (transcoders == 0)
4494 return 0;
4495
4496 for_each_intel_crtc(&dev_priv->drm, crtc) {
4497 struct intel_crtc_state *crtc_state;
4498 int ret;
4499
4500 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
4501 if (IS_ERR(crtc_state))
4502 return PTR_ERR(crtc_state);
4503
4504 if (!crtc_state->hw.enable)
4505 continue;
4506
4507 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
4508 continue;
4509
4510 crtc_state->uapi.mode_changed = true;
4511
4512 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
4513 if (ret)
4514 return ret;
4515
4516 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
4517 if (ret)
4518 return ret;
4519
4520 transcoders &= ~BIT(crtc_state->cpu_transcoder);
4521 }
4522
4523 drm_WARN_ON(&dev_priv->drm, transcoders != 0);
4524
4525 return 0;
4526 }
4527
intel_modeset_synced_crtcs(struct intel_atomic_state * state,struct drm_connector * connector)4528 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
4529 struct drm_connector *connector)
4530 {
4531 const struct drm_connector_state *old_conn_state =
4532 drm_atomic_get_old_connector_state(&state->base, connector);
4533 const struct intel_crtc_state *old_crtc_state;
4534 struct intel_crtc *crtc;
4535 u8 transcoders;
4536
4537 crtc = to_intel_crtc(old_conn_state->crtc);
4538 if (!crtc)
4539 return 0;
4540
4541 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
4542
4543 if (!old_crtc_state->hw.active)
4544 return 0;
4545
4546 transcoders = old_crtc_state->sync_mode_slaves_mask;
4547 if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
4548 transcoders |= BIT(old_crtc_state->master_transcoder);
4549
4550 return intel_modeset_affected_transcoders(state,
4551 transcoders);
4552 }
4553
intel_dp_connector_atomic_check(struct drm_connector * conn,struct drm_atomic_state * _state)4554 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
4555 struct drm_atomic_state *_state)
4556 {
4557 struct drm_i915_private *dev_priv = to_i915(conn->dev);
4558 struct intel_atomic_state *state = to_intel_atomic_state(_state);
4559 int ret;
4560
4561 ret = intel_digital_connector_atomic_check(conn, &state->base);
4562 if (ret)
4563 return ret;
4564
4565 /*
4566 * We don't enable port sync on BDW due to missing w/as and
4567 * due to not having adjusted the modeset sequence appropriately.
4568 */
4569 if (DISPLAY_VER(dev_priv) < 9)
4570 return 0;
4571
4572 if (!intel_connector_needs_modeset(state, conn))
4573 return 0;
4574
4575 if (conn->has_tile) {
4576 ret = intel_modeset_tile_group(state, conn->tile_group->id);
4577 if (ret)
4578 return ret;
4579 }
4580
4581 return intel_modeset_synced_crtcs(state, conn);
4582 }
4583
4584 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4585 .force = intel_dp_force,
4586 .fill_modes = drm_helper_probe_single_connector_modes,
4587 .atomic_get_property = intel_digital_connector_atomic_get_property,
4588 .atomic_set_property = intel_digital_connector_atomic_set_property,
4589 .late_register = intel_dp_connector_register,
4590 .early_unregister = intel_dp_connector_unregister,
4591 .destroy = intel_connector_destroy,
4592 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4593 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
4594 };
4595
4596 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4597 .detect_ctx = intel_dp_detect,
4598 .get_modes = intel_dp_get_modes,
4599 .mode_valid = intel_dp_mode_valid,
4600 .atomic_check = intel_dp_connector_atomic_check,
4601 };
4602
4603 enum irqreturn
intel_dp_hpd_pulse(struct intel_digital_port * dig_port,bool long_hpd)4604 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
4605 {
4606 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
4607 struct intel_dp *intel_dp = &dig_port->dp;
4608
4609 if (dig_port->base.type == INTEL_OUTPUT_EDP &&
4610 (long_hpd || !intel_pps_have_power(intel_dp))) {
4611 /*
4612 * vdd off can generate a long/short pulse on eDP which
4613 * would require vdd on to handle it, and thus we
4614 * would end up in an endless cycle of
4615 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
4616 */
4617 drm_dbg_kms(&i915->drm,
4618 "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
4619 long_hpd ? "long" : "short",
4620 dig_port->base.base.base.id,
4621 dig_port->base.base.name);
4622 return IRQ_HANDLED;
4623 }
4624
4625 drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
4626 dig_port->base.base.base.id,
4627 dig_port->base.base.name,
4628 long_hpd ? "long" : "short");
4629
4630 if (long_hpd) {
4631 intel_dp->reset_link_params = true;
4632 return IRQ_NONE;
4633 }
4634
4635 if (intel_dp->is_mst) {
4636 if (!intel_dp_check_mst_status(intel_dp))
4637 return IRQ_NONE;
4638 } else if (!intel_dp_short_pulse(intel_dp)) {
4639 return IRQ_NONE;
4640 }
4641
4642 return IRQ_HANDLED;
4643 }
4644
4645 /* check the VBT to see whether the eDP is on another port */
intel_dp_is_port_edp(struct drm_i915_private * dev_priv,enum port port)4646 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
4647 {
4648 /*
4649 * eDP not supported on g4x. so bail out early just
4650 * for a bit extra safety in case the VBT is bonkers.
4651 */
4652 if (DISPLAY_VER(dev_priv) < 5)
4653 return false;
4654
4655 if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
4656 return true;
4657
4658 return intel_bios_is_port_edp(dev_priv, port);
4659 }
4660
4661 static void
intel_dp_add_properties(struct intel_dp * intel_dp,struct drm_connector * connector)4662 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4663 {
4664 struct drm_i915_private *dev_priv = to_i915(connector->dev);
4665 enum port port = dp_to_dig_port(intel_dp)->base.port;
4666
4667 if (!intel_dp_is_edp(intel_dp))
4668 drm_connector_attach_dp_subconnector_property(connector);
4669
4670 if (!IS_G4X(dev_priv) && port != PORT_A)
4671 intel_attach_force_audio_property(connector);
4672
4673 intel_attach_broadcast_rgb_property(connector);
4674 if (HAS_GMCH(dev_priv))
4675 drm_connector_attach_max_bpc_property(connector, 6, 10);
4676 else if (DISPLAY_VER(dev_priv) >= 5)
4677 drm_connector_attach_max_bpc_property(connector, 6, 12);
4678
4679 /* Register HDMI colorspace for case of lspcon */
4680 if (intel_bios_is_lspcon_present(dev_priv, port)) {
4681 drm_connector_attach_content_type_property(connector);
4682 intel_attach_hdmi_colorspace_property(connector);
4683 } else {
4684 intel_attach_dp_colorspace_property(connector);
4685 }
4686
4687 if (IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 11)
4688 drm_object_attach_property(&connector->base,
4689 connector->dev->mode_config.hdr_output_metadata_property,
4690 0);
4691
4692 if (intel_dp_is_edp(intel_dp)) {
4693 u32 allowed_scalers;
4694
4695 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
4696 if (!HAS_GMCH(dev_priv))
4697 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
4698
4699 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
4700
4701 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
4702
4703 }
4704
4705 if (HAS_VRR(dev_priv))
4706 drm_connector_attach_vrr_capable_property(connector);
4707 }
4708
4709 /**
4710 * intel_dp_set_drrs_state - program registers for RR switch to take effect
4711 * @dev_priv: i915 device
4712 * @crtc_state: a pointer to the active intel_crtc_state
4713 * @refresh_rate: RR to be programmed
4714 *
4715 * This function gets called when refresh rate (RR) has to be changed from
4716 * one frequency to another. Switches can be between high and low RR
4717 * supported by the panel or to any other RR based on media playback (in
4718 * this case, RR value needs to be passed from user space).
4719 *
4720 * The caller of this function needs to take a lock on dev_priv->drrs.
4721 */
intel_dp_set_drrs_state(struct drm_i915_private * dev_priv,const struct intel_crtc_state * crtc_state,int refresh_rate)4722 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
4723 const struct intel_crtc_state *crtc_state,
4724 int refresh_rate)
4725 {
4726 struct intel_dp *intel_dp = dev_priv->drrs.dp;
4727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
4728 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
4729
4730 if (refresh_rate <= 0) {
4731 drm_dbg_kms(&dev_priv->drm,
4732 "Refresh rate should be positive non-zero.\n");
4733 return;
4734 }
4735
4736 if (intel_dp == NULL) {
4737 drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n");
4738 return;
4739 }
4740
4741 if (!intel_crtc) {
4742 drm_dbg_kms(&dev_priv->drm,
4743 "DRRS: intel_crtc not initialized\n");
4744 return;
4745 }
4746
4747 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
4748 drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
4749 return;
4750 }
4751
4752 if (drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode) ==
4753 refresh_rate)
4754 index = DRRS_LOW_RR;
4755
4756 if (index == dev_priv->drrs.refresh_rate_type) {
4757 drm_dbg_kms(&dev_priv->drm,
4758 "DRRS requested for previously set RR...ignoring\n");
4759 return;
4760 }
4761
4762 if (!crtc_state->hw.active) {
4763 drm_dbg_kms(&dev_priv->drm,
4764 "eDP encoder disabled. CRTC not Active\n");
4765 return;
4766 }
4767
4768 if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
4769 switch (index) {
4770 case DRRS_HIGH_RR:
4771 intel_dp_set_m_n(crtc_state, M1_N1);
4772 break;
4773 case DRRS_LOW_RR:
4774 intel_dp_set_m_n(crtc_state, M2_N2);
4775 break;
4776 case DRRS_MAX_RR:
4777 default:
4778 drm_err(&dev_priv->drm,
4779 "Unsupported refreshrate type\n");
4780 }
4781 } else if (DISPLAY_VER(dev_priv) > 6) {
4782 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
4783 u32 val;
4784
4785 val = intel_de_read(dev_priv, reg);
4786 if (index > DRRS_HIGH_RR) {
4787 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4788 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
4789 else
4790 val |= PIPECONF_EDP_RR_MODE_SWITCH;
4791 } else {
4792 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4793 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
4794 else
4795 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4796 }
4797 intel_de_write(dev_priv, reg, val);
4798 }
4799
4800 dev_priv->drrs.refresh_rate_type = index;
4801
4802 drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
4803 refresh_rate);
4804 }
4805
4806 static void
intel_edp_drrs_enable_locked(struct intel_dp * intel_dp)4807 intel_edp_drrs_enable_locked(struct intel_dp *intel_dp)
4808 {
4809 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4810
4811 dev_priv->drrs.busy_frontbuffer_bits = 0;
4812 dev_priv->drrs.dp = intel_dp;
4813 }
4814
4815 /**
4816 * intel_edp_drrs_enable - init drrs struct if supported
4817 * @intel_dp: DP struct
4818 * @crtc_state: A pointer to the active crtc state.
4819 *
4820 * Initializes frontbuffer_bits and drrs.dp
4821 */
intel_edp_drrs_enable(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)4822 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
4823 const struct intel_crtc_state *crtc_state)
4824 {
4825 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4826
4827 if (!crtc_state->has_drrs)
4828 return;
4829
4830 drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n");
4831
4832 mutex_lock(&dev_priv->drrs.mutex);
4833
4834 if (dev_priv->drrs.dp) {
4835 drm_warn(&dev_priv->drm, "DRRS already enabled\n");
4836 goto unlock;
4837 }
4838
4839 intel_edp_drrs_enable_locked(intel_dp);
4840
4841 unlock:
4842 mutex_unlock(&dev_priv->drrs.mutex);
4843 }
4844
4845 static void
intel_edp_drrs_disable_locked(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)4846 intel_edp_drrs_disable_locked(struct intel_dp *intel_dp,
4847 const struct intel_crtc_state *crtc_state)
4848 {
4849 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4850
4851 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
4852 int refresh;
4853
4854 refresh = drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode);
4855 intel_dp_set_drrs_state(dev_priv, crtc_state, refresh);
4856 }
4857
4858 dev_priv->drrs.dp = NULL;
4859 }
4860
4861 /**
4862 * intel_edp_drrs_disable - Disable DRRS
4863 * @intel_dp: DP struct
4864 * @old_crtc_state: Pointer to old crtc_state.
4865 *
4866 */
intel_edp_drrs_disable(struct intel_dp * intel_dp,const struct intel_crtc_state * old_crtc_state)4867 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
4868 const struct intel_crtc_state *old_crtc_state)
4869 {
4870 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4871
4872 if (!old_crtc_state->has_drrs)
4873 return;
4874
4875 mutex_lock(&dev_priv->drrs.mutex);
4876 if (!dev_priv->drrs.dp) {
4877 mutex_unlock(&dev_priv->drrs.mutex);
4878 return;
4879 }
4880
4881 intel_edp_drrs_disable_locked(intel_dp, old_crtc_state);
4882 mutex_unlock(&dev_priv->drrs.mutex);
4883
4884 cancel_delayed_work_sync(&dev_priv->drrs.work);
4885 }
4886
4887 /**
4888 * intel_edp_drrs_update - Update DRRS state
4889 * @intel_dp: Intel DP
4890 * @crtc_state: new CRTC state
4891 *
4892 * This function will update DRRS states, disabling or enabling DRRS when
4893 * executing fastsets. For full modeset, intel_edp_drrs_disable() and
4894 * intel_edp_drrs_enable() should be called instead.
4895 */
4896 void
intel_edp_drrs_update(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)4897 intel_edp_drrs_update(struct intel_dp *intel_dp,
4898 const struct intel_crtc_state *crtc_state)
4899 {
4900 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4901
4902 if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
4903 return;
4904
4905 mutex_lock(&dev_priv->drrs.mutex);
4906
4907 /* New state matches current one? */
4908 if (crtc_state->has_drrs == !!dev_priv->drrs.dp)
4909 goto unlock;
4910
4911 if (crtc_state->has_drrs)
4912 intel_edp_drrs_enable_locked(intel_dp);
4913 else
4914 intel_edp_drrs_disable_locked(intel_dp, crtc_state);
4915
4916 unlock:
4917 mutex_unlock(&dev_priv->drrs.mutex);
4918 }
4919
intel_edp_drrs_downclock_work(struct work_struct * work)4920 static void intel_edp_drrs_downclock_work(struct work_struct *work)
4921 {
4922 struct drm_i915_private *dev_priv =
4923 container_of(work, typeof(*dev_priv), drrs.work.work);
4924 struct intel_dp *intel_dp;
4925
4926 mutex_lock(&dev_priv->drrs.mutex);
4927
4928 intel_dp = dev_priv->drrs.dp;
4929
4930 if (!intel_dp)
4931 goto unlock;
4932
4933 /*
4934 * The delayed work can race with an invalidate hence we need to
4935 * recheck.
4936 */
4937
4938 if (dev_priv->drrs.busy_frontbuffer_bits)
4939 goto unlock;
4940
4941 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
4942 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
4943
4944 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
4945 drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode));
4946 }
4947
4948 unlock:
4949 mutex_unlock(&dev_priv->drrs.mutex);
4950 }
4951
4952 /**
4953 * intel_edp_drrs_invalidate - Disable Idleness DRRS
4954 * @dev_priv: i915 device
4955 * @frontbuffer_bits: frontbuffer plane tracking bits
4956 *
4957 * This function gets called everytime rendering on the given planes start.
4958 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
4959 *
4960 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
4961 */
intel_edp_drrs_invalidate(struct drm_i915_private * dev_priv,unsigned int frontbuffer_bits)4962 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
4963 unsigned int frontbuffer_bits)
4964 {
4965 struct intel_dp *intel_dp;
4966 struct drm_crtc *crtc;
4967 enum pipe pipe;
4968
4969 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
4970 return;
4971
4972 cancel_delayed_work(&dev_priv->drrs.work);
4973
4974 mutex_lock(&dev_priv->drrs.mutex);
4975
4976 intel_dp = dev_priv->drrs.dp;
4977 if (!intel_dp) {
4978 mutex_unlock(&dev_priv->drrs.mutex);
4979 return;
4980 }
4981
4982 crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
4983 pipe = to_intel_crtc(crtc)->pipe;
4984
4985 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
4986 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
4987
4988 /* invalidate means busy screen hence upclock */
4989 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
4990 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
4991 drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
4992
4993 mutex_unlock(&dev_priv->drrs.mutex);
4994 }
4995
4996 /**
4997 * intel_edp_drrs_flush - Restart Idleness DRRS
4998 * @dev_priv: i915 device
4999 * @frontbuffer_bits: frontbuffer plane tracking bits
5000 *
5001 * This function gets called every time rendering on the given planes has
5002 * completed or flip on a crtc is completed. So DRRS should be upclocked
5003 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5004 * if no other planes are dirty.
5005 *
5006 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5007 */
intel_edp_drrs_flush(struct drm_i915_private * dev_priv,unsigned int frontbuffer_bits)5008 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5009 unsigned int frontbuffer_bits)
5010 {
5011 struct intel_dp *intel_dp;
5012 struct drm_crtc *crtc;
5013 enum pipe pipe;
5014
5015 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5016 return;
5017
5018 cancel_delayed_work(&dev_priv->drrs.work);
5019
5020 mutex_lock(&dev_priv->drrs.mutex);
5021
5022 intel_dp = dev_priv->drrs.dp;
5023 if (!intel_dp) {
5024 mutex_unlock(&dev_priv->drrs.mutex);
5025 return;
5026 }
5027
5028 crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5029 pipe = to_intel_crtc(crtc)->pipe;
5030
5031 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5032 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5033
5034 /* flush means busy screen hence upclock */
5035 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5036 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5037 drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
5038
5039 /*
5040 * flush also means no more activity hence schedule downclock, if all
5041 * other fbs are quiescent too
5042 */
5043 if (!dev_priv->drrs.busy_frontbuffer_bits)
5044 schedule_delayed_work(&dev_priv->drrs.work,
5045 msecs_to_jiffies(1000));
5046 mutex_unlock(&dev_priv->drrs.mutex);
5047 }
5048
5049 /**
5050 * DOC: Display Refresh Rate Switching (DRRS)
5051 *
5052 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5053 * which enables swtching between low and high refresh rates,
5054 * dynamically, based on the usage scenario. This feature is applicable
5055 * for internal panels.
5056 *
5057 * Indication that the panel supports DRRS is given by the panel EDID, which
5058 * would list multiple refresh rates for one resolution.
5059 *
5060 * DRRS is of 2 types - static and seamless.
5061 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5062 * (may appear as a blink on screen) and is used in dock-undock scenario.
5063 * Seamless DRRS involves changing RR without any visual effect to the user
5064 * and can be used during normal system usage. This is done by programming
5065 * certain registers.
5066 *
5067 * Support for static/seamless DRRS may be indicated in the VBT based on
5068 * inputs from the panel spec.
5069 *
5070 * DRRS saves power by switching to low RR based on usage scenarios.
5071 *
5072 * The implementation is based on frontbuffer tracking implementation. When
5073 * there is a disturbance on the screen triggered by user activity or a periodic
5074 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5075 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5076 * made.
5077 *
5078 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5079 * and intel_edp_drrs_flush() are called.
5080 *
5081 * DRRS can be further extended to support other internal panels and also
5082 * the scenario of video playback wherein RR is set based on the rate
5083 * requested by userspace.
5084 */
5085
5086 /**
5087 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5088 * @connector: eDP connector
5089 * @fixed_mode: preferred mode of panel
5090 *
5091 * This function is called only once at driver load to initialize basic
5092 * DRRS stuff.
5093 *
5094 * Returns:
5095 * Downclock mode if panel supports it, else return NULL.
5096 * DRRS support is determined by the presence of downclock mode (apart
5097 * from VBT setting).
5098 */
5099 static struct drm_display_mode *
intel_dp_drrs_init(struct intel_connector * connector,struct drm_display_mode * fixed_mode)5100 intel_dp_drrs_init(struct intel_connector *connector,
5101 struct drm_display_mode *fixed_mode)
5102 {
5103 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
5104 struct drm_display_mode *downclock_mode = NULL;
5105
5106 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5107 mutex_init(&dev_priv->drrs.mutex);
5108
5109 if (DISPLAY_VER(dev_priv) <= 6) {
5110 drm_dbg_kms(&dev_priv->drm,
5111 "DRRS supported for Gen7 and above\n");
5112 return NULL;
5113 }
5114
5115 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5116 drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n");
5117 return NULL;
5118 }
5119
5120 downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
5121 if (!downclock_mode) {
5122 drm_dbg_kms(&dev_priv->drm,
5123 "Downclock mode is not found. DRRS not supported\n");
5124 return NULL;
5125 }
5126
5127 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5128
5129 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5130 drm_dbg_kms(&dev_priv->drm,
5131 "seamless DRRS supported for eDP panel.\n");
5132 return downclock_mode;
5133 }
5134
intel_edp_init_connector(struct intel_dp * intel_dp,struct intel_connector * intel_connector)5135 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5136 struct intel_connector *intel_connector)
5137 {
5138 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5139 struct drm_device *dev = &dev_priv->drm;
5140 struct drm_connector *connector = &intel_connector->base;
5141 struct drm_display_mode *fixed_mode = NULL;
5142 struct drm_display_mode *downclock_mode = NULL;
5143 bool has_dpcd;
5144 enum pipe pipe = INVALID_PIPE;
5145 struct edid *edid;
5146
5147 if (!intel_dp_is_edp(intel_dp))
5148 return true;
5149
5150 /*
5151 * On IBX/CPT we may get here with LVDS already registered. Since the
5152 * driver uses the only internal power sequencer available for both
5153 * eDP and LVDS bail out early in this case to prevent interfering
5154 * with an already powered-on LVDS power sequencer.
5155 */
5156 if (intel_get_lvds_encoder(dev_priv)) {
5157 drm_WARN_ON(dev,
5158 !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5159 drm_info(&dev_priv->drm,
5160 "LVDS was detected, not registering eDP\n");
5161
5162 return false;
5163 }
5164
5165 intel_pps_init(intel_dp);
5166
5167 /* Cache DPCD and EDID for edp. */
5168 has_dpcd = intel_edp_init_dpcd(intel_dp);
5169
5170 if (!has_dpcd) {
5171 /* if this fails, presume the device is a ghost */
5172 drm_info(&dev_priv->drm,
5173 "failed to retrieve link info, disabling eDP\n");
5174 goto out_vdd_off;
5175 }
5176
5177 mutex_lock(&dev->mode_config.mutex);
5178 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5179 if (edid) {
5180 if (drm_add_edid_modes(connector, edid)) {
5181 drm_connector_update_edid_property(connector, edid);
5182 } else {
5183 kfree(edid);
5184 edid = ERR_PTR(-EINVAL);
5185 }
5186 } else {
5187 edid = ERR_PTR(-ENOENT);
5188 }
5189 intel_connector->edid = edid;
5190
5191 fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
5192 if (fixed_mode)
5193 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
5194
5195 /* multiply the mode clock and horizontal timings for MSO */
5196 intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
5197 intel_edp_mso_mode_fixup(intel_connector, downclock_mode);
5198
5199 /* fallback to VBT if available for eDP */
5200 if (!fixed_mode)
5201 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
5202 mutex_unlock(&dev->mode_config.mutex);
5203
5204 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5205 /*
5206 * Figure out the current pipe for the initial backlight setup.
5207 * If the current pipe isn't valid, try the PPS pipe, and if that
5208 * fails just assume pipe A.
5209 */
5210 pipe = vlv_active_pipe(intel_dp);
5211
5212 if (pipe != PIPE_A && pipe != PIPE_B)
5213 pipe = intel_dp->pps.pps_pipe;
5214
5215 if (pipe != PIPE_A && pipe != PIPE_B)
5216 pipe = PIPE_A;
5217
5218 drm_dbg_kms(&dev_priv->drm,
5219 "using pipe %c for initial backlight setup\n",
5220 pipe_name(pipe));
5221 }
5222
5223 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5224 intel_connector->panel.backlight.power = intel_pps_backlight_power;
5225 intel_panel_setup_backlight(connector, pipe);
5226
5227 if (fixed_mode) {
5228 drm_connector_set_panel_orientation_with_quirk(connector,
5229 dev_priv->vbt.orientation,
5230 fixed_mode->hdisplay, fixed_mode->vdisplay);
5231 }
5232
5233 return true;
5234
5235 out_vdd_off:
5236 intel_pps_vdd_off_sync(intel_dp);
5237
5238 return false;
5239 }
5240
intel_dp_modeset_retry_work_fn(struct work_struct * work)5241 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
5242 {
5243 struct intel_connector *intel_connector;
5244 struct drm_connector *connector;
5245
5246 intel_connector = container_of(work, typeof(*intel_connector),
5247 modeset_retry_work);
5248 connector = &intel_connector->base;
5249 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
5250 connector->name);
5251
5252 /* Grab the locks before changing connector property*/
5253 mutex_lock(&connector->dev->mode_config.mutex);
5254 /* Set connector link status to BAD and send a Uevent to notify
5255 * userspace to do a modeset.
5256 */
5257 drm_connector_set_link_status_property(connector,
5258 DRM_MODE_LINK_STATUS_BAD);
5259 mutex_unlock(&connector->dev->mode_config.mutex);
5260 /* Send Hotplug uevent so userspace can reprobe */
5261 drm_kms_helper_hotplug_event(connector->dev);
5262 }
5263
5264 bool
intel_dp_init_connector(struct intel_digital_port * dig_port,struct intel_connector * intel_connector)5265 intel_dp_init_connector(struct intel_digital_port *dig_port,
5266 struct intel_connector *intel_connector)
5267 {
5268 struct drm_connector *connector = &intel_connector->base;
5269 struct intel_dp *intel_dp = &dig_port->dp;
5270 struct intel_encoder *intel_encoder = &dig_port->base;
5271 struct drm_device *dev = intel_encoder->base.dev;
5272 struct drm_i915_private *dev_priv = to_i915(dev);
5273 enum port port = intel_encoder->port;
5274 enum phy phy = intel_port_to_phy(dev_priv, port);
5275 int type;
5276
5277 /* Initialize the work for modeset in case of link train failure */
5278 INIT_WORK(&intel_connector->modeset_retry_work,
5279 intel_dp_modeset_retry_work_fn);
5280
5281 if (drm_WARN(dev, dig_port->max_lanes < 1,
5282 "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
5283 dig_port->max_lanes, intel_encoder->base.base.id,
5284 intel_encoder->base.name))
5285 return false;
5286
5287 intel_dp_set_source_rates(intel_dp);
5288
5289 intel_dp->reset_link_params = true;
5290 intel_dp->pps.pps_pipe = INVALID_PIPE;
5291 intel_dp->pps.active_pipe = INVALID_PIPE;
5292
5293 /* Preserve the current hw state. */
5294 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
5295 intel_dp->attached_connector = intel_connector;
5296
5297 if (intel_dp_is_port_edp(dev_priv, port)) {
5298 /*
5299 * Currently we don't support eDP on TypeC ports, although in
5300 * theory it could work on TypeC legacy ports.
5301 */
5302 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
5303 type = DRM_MODE_CONNECTOR_eDP;
5304 } else {
5305 type = DRM_MODE_CONNECTOR_DisplayPort;
5306 }
5307
5308 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5309 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
5310
5311 /*
5312 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5313 * for DP the encoder type can be set by the caller to
5314 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5315 */
5316 if (type == DRM_MODE_CONNECTOR_eDP)
5317 intel_encoder->type = INTEL_OUTPUT_EDP;
5318
5319 /* eDP only on port B and/or C on vlv/chv */
5320 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
5321 IS_CHERRYVIEW(dev_priv)) &&
5322 intel_dp_is_edp(intel_dp) &&
5323 port != PORT_B && port != PORT_C))
5324 return false;
5325
5326 drm_dbg_kms(&dev_priv->drm,
5327 "Adding %s connector on [ENCODER:%d:%s]\n",
5328 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5329 intel_encoder->base.base.id, intel_encoder->base.name);
5330
5331 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5332 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5333
5334 if (!HAS_GMCH(dev_priv))
5335 connector->interlace_allowed = true;
5336 connector->doublescan_allowed = 0;
5337
5338 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
5339
5340 intel_dp_aux_init(intel_dp);
5341
5342 intel_connector_attach_encoder(intel_connector, intel_encoder);
5343
5344 if (HAS_DDI(dev_priv))
5345 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5346 else
5347 intel_connector->get_hw_state = intel_connector_get_hw_state;
5348
5349 /* init MST on ports that can support it */
5350 intel_dp_mst_encoder_init(dig_port,
5351 intel_connector->base.base.id);
5352
5353 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5354 intel_dp_aux_fini(intel_dp);
5355 intel_dp_mst_encoder_cleanup(dig_port);
5356 goto fail;
5357 }
5358
5359 intel_dp_add_properties(intel_dp, connector);
5360
5361 if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
5362 int ret = intel_dp_init_hdcp(dig_port, intel_connector);
5363 if (ret)
5364 drm_dbg_kms(&dev_priv->drm,
5365 "HDCP init failed, skipping.\n");
5366 }
5367
5368 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5369 * 0xd. Failure to do so will result in spurious interrupts being
5370 * generated on the port when a cable is not attached.
5371 */
5372 if (IS_G45(dev_priv)) {
5373 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
5374 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
5375 (temp & ~0xf) | 0xd);
5376 }
5377
5378 intel_dp->frl.is_trained = false;
5379 intel_dp->frl.trained_rate_gbps = 0;
5380
5381 intel_psr_init(intel_dp);
5382
5383 return true;
5384
5385 fail:
5386 drm_connector_cleanup(connector);
5387
5388 return false;
5389 }
5390
intel_dp_mst_suspend(struct drm_i915_private * dev_priv)5391 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
5392 {
5393 struct intel_encoder *encoder;
5394
5395 for_each_intel_encoder(&dev_priv->drm, encoder) {
5396 struct intel_dp *intel_dp;
5397
5398 if (encoder->type != INTEL_OUTPUT_DDI)
5399 continue;
5400
5401 intel_dp = enc_to_intel_dp(encoder);
5402
5403 if (!intel_dp->can_mst)
5404 continue;
5405
5406 if (intel_dp->is_mst)
5407 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
5408 }
5409 }
5410
intel_dp_mst_resume(struct drm_i915_private * dev_priv)5411 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
5412 {
5413 struct intel_encoder *encoder;
5414
5415 for_each_intel_encoder(&dev_priv->drm, encoder) {
5416 struct intel_dp *intel_dp;
5417 int ret;
5418
5419 if (encoder->type != INTEL_OUTPUT_DDI)
5420 continue;
5421
5422 intel_dp = enc_to_intel_dp(encoder);
5423
5424 if (!intel_dp->can_mst)
5425 continue;
5426
5427 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
5428 true);
5429 if (ret) {
5430 intel_dp->is_mst = false;
5431 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5432 false);
5433 }
5434 }
5435 }
5436