1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
5 <mdsxyz123@yahoo.com>
6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
7 Copyright (C) 2010 Intel Corporation,
8 David Woodhouse <dwmw2@infradead.org>
9
10 */
11
12 /*
13 * Supports the following Intel I/O Controller Hubs (ICH):
14 *
15 * I/O Block I2C
16 * region SMBus Block proc. block
17 * Chip name PCI ID size PEC buffer call read
18 * ---------------------------------------------------------------------------
19 * 82801AA (ICH) 0x2413 16 no no no no
20 * 82801AB (ICH0) 0x2423 16 no no no no
21 * 82801BA (ICH2) 0x2443 16 no no no no
22 * 82801CA (ICH3) 0x2483 32 soft no no no
23 * 82801DB (ICH4) 0x24c3 32 hard yes no no
24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes
25 * 6300ESB 0x25a4 32 hard yes yes yes
26 * 82801F (ICH6) 0x266a 32 hard yes yes yes
27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
28 * 82801G (ICH7) 0x27da 32 hard yes yes yes
29 * 82801H (ICH8) 0x283e 32 hard yes yes yes
30 * 82801I (ICH9) 0x2930 32 hard yes yes yes
31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
32 * ICH10 0x3a30 32 hard yes yes yes
33 * ICH10 0x3a60 32 hard yes yes yes
34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes
45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
53 * Braswell (SOC) 0x2292 32 hard yes yes yes
54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
56 * DNV (SOC) 0x19df 32 hard yes yes yes
57 * Emmitsburg (PCH) 0x1bc9 32 hard yes yes yes
58 * Broxton (SOC) 0x5ad4 32 hard yes yes yes
59 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes
60 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes
61 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes
62 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes
63 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes
64 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes
65 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes
66 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes
67 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes
68 * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes
69 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes
70 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes
71 * Tiger Lake-H (PCH) 0x43a3 32 hard yes yes yes
72 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes
73 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes
74 * Alder Lake-S (PCH) 0x7aa3 32 hard yes yes yes
75 * Alder Lake-P (PCH) 0x51a3 32 hard yes yes yes
76 * Alder Lake-M (PCH) 0x54a3 32 hard yes yes yes
77 *
78 * Features supported by this driver:
79 * Software PEC no
80 * Hardware PEC yes
81 * Block buffer yes
82 * Block process call transaction yes
83 * I2C block read transaction yes (doesn't use the block buffer)
84 * Slave mode no
85 * SMBus Host Notify yes
86 * Interrupt processing yes
87 *
88 * See the file Documentation/i2c/busses/i2c-i801.rst for details.
89 */
90
91 #include <linux/interrupt.h>
92 #include <linux/module.h>
93 #include <linux/pci.h>
94 #include <linux/kernel.h>
95 #include <linux/stddef.h>
96 #include <linux/delay.h>
97 #include <linux/ioport.h>
98 #include <linux/init.h>
99 #include <linux/i2c.h>
100 #include <linux/i2c-smbus.h>
101 #include <linux/acpi.h>
102 #include <linux/io.h>
103 #include <linux/dmi.h>
104 #include <linux/slab.h>
105 #include <linux/string.h>
106 #include <linux/wait.h>
107 #include <linux/err.h>
108 #include <linux/platform_device.h>
109 #include <linux/platform_data/itco_wdt.h>
110 #include <linux/pm_runtime.h>
111
112 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
113 #include <linux/gpio/machine.h>
114 #include <linux/platform_data/i2c-mux-gpio.h>
115 #endif
116
117 /* I801 SMBus address offsets */
118 #define SMBHSTSTS(p) (0 + (p)->smba)
119 #define SMBHSTCNT(p) (2 + (p)->smba)
120 #define SMBHSTCMD(p) (3 + (p)->smba)
121 #define SMBHSTADD(p) (4 + (p)->smba)
122 #define SMBHSTDAT0(p) (5 + (p)->smba)
123 #define SMBHSTDAT1(p) (6 + (p)->smba)
124 #define SMBBLKDAT(p) (7 + (p)->smba)
125 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
126 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
127 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
128 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */
129 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */
130 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */
131
132 /* PCI Address Constants */
133 #define SMBBAR 4
134 #define SMBPCICTL 0x004
135 #define SMBPCISTS 0x006
136 #define SMBHSTCFG 0x040
137 #define TCOBASE 0x050
138 #define TCOCTL 0x054
139
140 #define SBREG_BAR 0x10
141 #define SBREG_SMBCTRL 0xc6000c
142 #define SBREG_SMBCTRL_DNV 0xcf000c
143
144 /* Host status bits for SMBPCISTS */
145 #define SMBPCISTS_INTS BIT(3)
146
147 /* Control bits for SMBPCICTL */
148 #define SMBPCICTL_INTDIS BIT(10)
149
150 /* Host configuration bits for SMBHSTCFG */
151 #define SMBHSTCFG_HST_EN BIT(0)
152 #define SMBHSTCFG_SMB_SMI_EN BIT(1)
153 #define SMBHSTCFG_I2C_EN BIT(2)
154 #define SMBHSTCFG_SPD_WD BIT(4)
155
156 /* TCO configuration bits for TCOCTL */
157 #define TCOCTL_EN BIT(8)
158
159 /* Auxiliary status register bits, ICH4+ only */
160 #define SMBAUXSTS_CRCE BIT(0)
161 #define SMBAUXSTS_STCO BIT(1)
162
163 /* Auxiliary control register bits, ICH4+ only */
164 #define SMBAUXCTL_CRC BIT(0)
165 #define SMBAUXCTL_E32B BIT(1)
166
167 /* Other settings */
168 #define MAX_RETRIES 400
169
170 /* I801 command constants */
171 #define I801_QUICK 0x00
172 #define I801_BYTE 0x04
173 #define I801_BYTE_DATA 0x08
174 #define I801_WORD_DATA 0x0C
175 #define I801_PROC_CALL 0x10 /* unimplemented */
176 #define I801_BLOCK_DATA 0x14
177 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
178 #define I801_BLOCK_PROC_CALL 0x1C
179
180 /* I801 Host Control register bits */
181 #define SMBHSTCNT_INTREN BIT(0)
182 #define SMBHSTCNT_KILL BIT(1)
183 #define SMBHSTCNT_LAST_BYTE BIT(5)
184 #define SMBHSTCNT_START BIT(6)
185 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */
186
187 /* I801 Hosts Status register bits */
188 #define SMBHSTSTS_BYTE_DONE BIT(7)
189 #define SMBHSTSTS_INUSE_STS BIT(6)
190 #define SMBHSTSTS_SMBALERT_STS BIT(5)
191 #define SMBHSTSTS_FAILED BIT(4)
192 #define SMBHSTSTS_BUS_ERR BIT(3)
193 #define SMBHSTSTS_DEV_ERR BIT(2)
194 #define SMBHSTSTS_INTR BIT(1)
195 #define SMBHSTSTS_HOST_BUSY BIT(0)
196
197 /* Host Notify Status register bits */
198 #define SMBSLVSTS_HST_NTFY_STS BIT(0)
199
200 /* Host Notify Command register bits */
201 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0)
202
203 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
204 SMBHSTSTS_DEV_ERR)
205
206 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
207 STATUS_ERROR_FLAGS)
208
209 /* Older devices have their ID defined in <linux/pci_ids.h> */
210 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3
211 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3
212 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
213 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df
214 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df
215 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS 0x1bc9
216 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
217 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
218 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
219 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
220 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
221 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
222 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
223 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
224 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
225 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
226 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
227 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4
228 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3
229 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
230 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS 0x43a3
231 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23
232 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3
233 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS 0x51a3
234 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS 0x54a3
235 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4
236 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS 0x7aa3
237 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
238 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
239 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
240 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
241 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
242 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
243 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
244 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
245 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
246 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3
247 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3
248 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
249 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3
250 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223
251 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3
252 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323
253 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3
254
255 struct i801_mux_config {
256 char *gpio_chip;
257 unsigned values[3];
258 int n_values;
259 unsigned classes[3];
260 unsigned gpios[2]; /* Relative to gpio_chip->base */
261 int n_gpios;
262 };
263
264 struct i801_priv {
265 struct i2c_adapter adapter;
266 unsigned long smba;
267 unsigned char original_hstcfg;
268 unsigned char original_slvcmd;
269 struct pci_dev *pci_dev;
270 unsigned int features;
271
272 /* isr processing */
273 wait_queue_head_t waitq;
274 u8 status;
275
276 /* Command state used by isr for byte-by-byte block transactions */
277 u8 cmd;
278 bool is_read;
279 int count;
280 int len;
281 u8 *data;
282
283 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
284 const struct i801_mux_config *mux_drvdata;
285 struct platform_device *mux_pdev;
286 struct gpiod_lookup_table *lookup;
287 #endif
288 struct platform_device *tco_pdev;
289
290 /*
291 * If set to true the host controller registers are reserved for
292 * ACPI AML use. Protected by acpi_lock.
293 */
294 bool acpi_reserved;
295 struct mutex acpi_lock;
296 };
297
298 #define FEATURE_SMBUS_PEC BIT(0)
299 #define FEATURE_BLOCK_BUFFER BIT(1)
300 #define FEATURE_BLOCK_PROC BIT(2)
301 #define FEATURE_I2C_BLOCK_READ BIT(3)
302 #define FEATURE_IRQ BIT(4)
303 #define FEATURE_HOST_NOTIFY BIT(5)
304 /* Not really a feature, but it's convenient to handle it as such */
305 #define FEATURE_IDF BIT(15)
306 #define FEATURE_TCO_SPT BIT(16)
307 #define FEATURE_TCO_CNL BIT(17)
308
309 static const char *i801_feature_names[] = {
310 "SMBus PEC",
311 "Block buffer",
312 "Block process call",
313 "I2C block read",
314 "Interrupt",
315 "SMBus Host Notify",
316 };
317
318 static unsigned int disable_features;
319 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
320 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
321 "\t\t 0x01 disable SMBus PEC\n"
322 "\t\t 0x02 disable the block buffer\n"
323 "\t\t 0x08 disable the I2C block read functionality\n"
324 "\t\t 0x10 don't use interrupts\n"
325 "\t\t 0x20 disable SMBus Host Notify ");
326
327 /* Make sure the SMBus host is ready to start transmitting.
328 Return 0 if it is, -EBUSY if it is not. */
i801_check_pre(struct i801_priv * priv)329 static int i801_check_pre(struct i801_priv *priv)
330 {
331 int status;
332
333 status = inb_p(SMBHSTSTS(priv));
334 if (status & SMBHSTSTS_HOST_BUSY) {
335 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
336 return -EBUSY;
337 }
338
339 status &= STATUS_FLAGS;
340 if (status) {
341 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
342 status);
343 outb_p(status, SMBHSTSTS(priv));
344 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
345 if (status) {
346 dev_err(&priv->pci_dev->dev,
347 "Failed clearing status flags (%02x)\n",
348 status);
349 return -EBUSY;
350 }
351 }
352
353 /*
354 * Clear CRC status if needed.
355 * During normal operation, i801_check_post() takes care
356 * of it after every operation. We do it here only in case
357 * the hardware was already in this state when the driver
358 * started.
359 */
360 if (priv->features & FEATURE_SMBUS_PEC) {
361 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
362 if (status) {
363 dev_dbg(&priv->pci_dev->dev,
364 "Clearing aux status flags (%02x)\n", status);
365 outb_p(status, SMBAUXSTS(priv));
366 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
367 if (status) {
368 dev_err(&priv->pci_dev->dev,
369 "Failed clearing aux status flags (%02x)\n",
370 status);
371 return -EBUSY;
372 }
373 }
374 }
375
376 return 0;
377 }
378
379 /*
380 * Convert the status register to an error code, and clear it.
381 * Note that status only contains the bits we want to clear, not the
382 * actual register value.
383 */
i801_check_post(struct i801_priv * priv,int status)384 static int i801_check_post(struct i801_priv *priv, int status)
385 {
386 int result = 0;
387
388 /*
389 * If the SMBus is still busy, we give up
390 * Note: This timeout condition only happens when using polling
391 * transactions. For interrupt operation, NAK/timeout is indicated by
392 * DEV_ERR.
393 */
394 if (unlikely(status < 0)) {
395 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
396 /* try to stop the current command */
397 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
398 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
399 SMBHSTCNT(priv));
400 usleep_range(1000, 2000);
401 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
402 SMBHSTCNT(priv));
403
404 /* Check if it worked */
405 status = inb_p(SMBHSTSTS(priv));
406 if ((status & SMBHSTSTS_HOST_BUSY) ||
407 !(status & SMBHSTSTS_FAILED))
408 dev_err(&priv->pci_dev->dev,
409 "Failed terminating the transaction\n");
410 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
411 return -ETIMEDOUT;
412 }
413
414 if (status & SMBHSTSTS_FAILED) {
415 result = -EIO;
416 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
417 }
418 if (status & SMBHSTSTS_DEV_ERR) {
419 /*
420 * This may be a PEC error, check and clear it.
421 *
422 * AUXSTS is handled differently from HSTSTS.
423 * For HSTSTS, i801_isr() or i801_wait_intr()
424 * has already cleared the error bits in hardware,
425 * and we are passed a copy of the original value
426 * in "status".
427 * For AUXSTS, the hardware register is left
428 * for us to handle here.
429 * This is asymmetric, slightly iffy, but safe,
430 * since all this code is serialized and the CRCE
431 * bit is harmless as long as it's cleared before
432 * the next operation.
433 */
434 if ((priv->features & FEATURE_SMBUS_PEC) &&
435 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
436 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
437 result = -EBADMSG;
438 dev_dbg(&priv->pci_dev->dev, "PEC error\n");
439 } else {
440 result = -ENXIO;
441 dev_dbg(&priv->pci_dev->dev, "No response\n");
442 }
443 }
444 if (status & SMBHSTSTS_BUS_ERR) {
445 result = -EAGAIN;
446 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
447 }
448
449 /* Clear status flags except BYTE_DONE, to be cleared by caller */
450 outb_p(status, SMBHSTSTS(priv));
451
452 return result;
453 }
454
455 /* Wait for BUSY being cleared and either INTR or an error flag being set */
i801_wait_intr(struct i801_priv * priv)456 static int i801_wait_intr(struct i801_priv *priv)
457 {
458 int timeout = 0;
459 int status;
460
461 /* We will always wait for a fraction of a second! */
462 do {
463 usleep_range(250, 500);
464 status = inb_p(SMBHSTSTS(priv));
465 } while (((status & SMBHSTSTS_HOST_BUSY) ||
466 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
467 (timeout++ < MAX_RETRIES));
468
469 if (timeout > MAX_RETRIES) {
470 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
471 return -ETIMEDOUT;
472 }
473 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
474 }
475
476 /* Wait for either BYTE_DONE or an error flag being set */
i801_wait_byte_done(struct i801_priv * priv)477 static int i801_wait_byte_done(struct i801_priv *priv)
478 {
479 int timeout = 0;
480 int status;
481
482 /* We will always wait for a fraction of a second! */
483 do {
484 usleep_range(250, 500);
485 status = inb_p(SMBHSTSTS(priv));
486 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
487 (timeout++ < MAX_RETRIES));
488
489 if (timeout > MAX_RETRIES) {
490 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
491 return -ETIMEDOUT;
492 }
493 return status & STATUS_ERROR_FLAGS;
494 }
495
i801_transaction(struct i801_priv * priv,int xact)496 static int i801_transaction(struct i801_priv *priv, int xact)
497 {
498 int status;
499 int result;
500 const struct i2c_adapter *adap = &priv->adapter;
501
502 result = i801_check_pre(priv);
503 if (result < 0)
504 return result;
505
506 if (priv->features & FEATURE_IRQ) {
507 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
508 SMBHSTCNT(priv));
509 result = wait_event_timeout(priv->waitq,
510 (status = priv->status),
511 adap->timeout);
512 if (!result) {
513 status = -ETIMEDOUT;
514 dev_warn(&priv->pci_dev->dev,
515 "Timeout waiting for interrupt!\n");
516 }
517 priv->status = 0;
518 return i801_check_post(priv, status);
519 }
520
521 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
522 * SMBSCMD are passed in xact */
523 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
524
525 status = i801_wait_intr(priv);
526 return i801_check_post(priv, status);
527 }
528
i801_block_transaction_by_block(struct i801_priv * priv,union i2c_smbus_data * data,char read_write,int command,int hwpec)529 static int i801_block_transaction_by_block(struct i801_priv *priv,
530 union i2c_smbus_data *data,
531 char read_write, int command,
532 int hwpec)
533 {
534 int i, len;
535 int status;
536 int xact = hwpec ? SMBHSTCNT_PEC_EN : 0;
537
538 switch (command) {
539 case I2C_SMBUS_BLOCK_PROC_CALL:
540 xact |= I801_BLOCK_PROC_CALL;
541 break;
542 case I2C_SMBUS_BLOCK_DATA:
543 xact |= I801_BLOCK_DATA;
544 break;
545 default:
546 return -EOPNOTSUPP;
547 }
548
549 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
550
551 /* Use 32-byte buffer to process this transaction */
552 if (read_write == I2C_SMBUS_WRITE) {
553 len = data->block[0];
554 outb_p(len, SMBHSTDAT0(priv));
555 for (i = 0; i < len; i++)
556 outb_p(data->block[i+1], SMBBLKDAT(priv));
557 }
558
559 status = i801_transaction(priv, xact);
560 if (status)
561 return status;
562
563 if (read_write == I2C_SMBUS_READ ||
564 command == I2C_SMBUS_BLOCK_PROC_CALL) {
565 len = inb_p(SMBHSTDAT0(priv));
566 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
567 return -EPROTO;
568
569 data->block[0] = len;
570 for (i = 0; i < len; i++)
571 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
572 }
573 return 0;
574 }
575
i801_isr_byte_done(struct i801_priv * priv)576 static void i801_isr_byte_done(struct i801_priv *priv)
577 {
578 if (priv->is_read) {
579 /* For SMBus block reads, length is received with first byte */
580 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
581 (priv->count == 0)) {
582 priv->len = inb_p(SMBHSTDAT0(priv));
583 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
584 dev_err(&priv->pci_dev->dev,
585 "Illegal SMBus block read size %d\n",
586 priv->len);
587 /* FIXME: Recover */
588 priv->len = I2C_SMBUS_BLOCK_MAX;
589 } else {
590 dev_dbg(&priv->pci_dev->dev,
591 "SMBus block read size is %d\n",
592 priv->len);
593 }
594 priv->data[-1] = priv->len;
595 }
596
597 /* Read next byte */
598 if (priv->count < priv->len)
599 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
600 else
601 dev_dbg(&priv->pci_dev->dev,
602 "Discarding extra byte on block read\n");
603
604 /* Set LAST_BYTE for last byte of read transaction */
605 if (priv->count == priv->len - 1)
606 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
607 SMBHSTCNT(priv));
608 } else if (priv->count < priv->len - 1) {
609 /* Write next byte, except for IRQ after last byte */
610 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
611 }
612
613 /* Clear BYTE_DONE to continue with next byte */
614 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
615 }
616
i801_host_notify_isr(struct i801_priv * priv)617 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
618 {
619 unsigned short addr;
620
621 addr = inb_p(SMBNTFDADD(priv)) >> 1;
622
623 /*
624 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
625 * always returns 0. Our current implementation doesn't provide
626 * data, so we just ignore it.
627 */
628 i2c_handle_smbus_host_notify(&priv->adapter, addr);
629
630 /* clear Host Notify bit and return */
631 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
632 return IRQ_HANDLED;
633 }
634
635 /*
636 * There are three kinds of interrupts:
637 *
638 * 1) i801 signals transaction completion with one of these interrupts:
639 * INTR - Success
640 * DEV_ERR - Invalid command, NAK or communication timeout
641 * BUS_ERR - SMI# transaction collision
642 * FAILED - transaction was canceled due to a KILL request
643 * When any of these occur, update ->status and wake up the waitq.
644 * ->status must be cleared before kicking off the next transaction.
645 *
646 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
647 * occurs for each byte of a byte-by-byte to prepare the next byte.
648 *
649 * 3) Host Notify interrupts
650 */
i801_isr(int irq,void * dev_id)651 static irqreturn_t i801_isr(int irq, void *dev_id)
652 {
653 struct i801_priv *priv = dev_id;
654 u16 pcists;
655 u8 status;
656
657 /* Confirm this is our interrupt */
658 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
659 if (!(pcists & SMBPCISTS_INTS))
660 return IRQ_NONE;
661
662 if (priv->features & FEATURE_HOST_NOTIFY) {
663 status = inb_p(SMBSLVSTS(priv));
664 if (status & SMBSLVSTS_HST_NTFY_STS)
665 return i801_host_notify_isr(priv);
666 }
667
668 status = inb_p(SMBHSTSTS(priv));
669 if (status & SMBHSTSTS_BYTE_DONE)
670 i801_isr_byte_done(priv);
671
672 /*
673 * Clear irq sources and report transaction result.
674 * ->status must be cleared before the next transaction is started.
675 */
676 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
677 if (status) {
678 outb_p(status, SMBHSTSTS(priv));
679 priv->status = status;
680 wake_up(&priv->waitq);
681 }
682
683 return IRQ_HANDLED;
684 }
685
686 /*
687 * For "byte-by-byte" block transactions:
688 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
689 * I2C read uses cmd=I801_I2C_BLOCK_DATA
690 */
i801_block_transaction_byte_by_byte(struct i801_priv * priv,union i2c_smbus_data * data,char read_write,int command,int hwpec)691 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
692 union i2c_smbus_data *data,
693 char read_write, int command,
694 int hwpec)
695 {
696 int i, len;
697 int smbcmd;
698 int status;
699 int result;
700 const struct i2c_adapter *adap = &priv->adapter;
701
702 if (command == I2C_SMBUS_BLOCK_PROC_CALL)
703 return -EOPNOTSUPP;
704
705 result = i801_check_pre(priv);
706 if (result < 0)
707 return result;
708
709 len = data->block[0];
710
711 if (read_write == I2C_SMBUS_WRITE) {
712 outb_p(len, SMBHSTDAT0(priv));
713 outb_p(data->block[1], SMBBLKDAT(priv));
714 }
715
716 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
717 read_write == I2C_SMBUS_READ)
718 smbcmd = I801_I2C_BLOCK_DATA;
719 else
720 smbcmd = I801_BLOCK_DATA;
721
722 if (priv->features & FEATURE_IRQ) {
723 priv->is_read = (read_write == I2C_SMBUS_READ);
724 if (len == 1 && priv->is_read)
725 smbcmd |= SMBHSTCNT_LAST_BYTE;
726 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
727 priv->len = len;
728 priv->count = 0;
729 priv->data = &data->block[1];
730
731 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
732 result = wait_event_timeout(priv->waitq,
733 (status = priv->status),
734 adap->timeout);
735 if (!result) {
736 status = -ETIMEDOUT;
737 dev_warn(&priv->pci_dev->dev,
738 "Timeout waiting for interrupt!\n");
739 }
740 priv->status = 0;
741 return i801_check_post(priv, status);
742 }
743
744 for (i = 1; i <= len; i++) {
745 if (i == len && read_write == I2C_SMBUS_READ)
746 smbcmd |= SMBHSTCNT_LAST_BYTE;
747 outb_p(smbcmd, SMBHSTCNT(priv));
748
749 if (i == 1)
750 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
751 SMBHSTCNT(priv));
752
753 status = i801_wait_byte_done(priv);
754 if (status)
755 goto exit;
756
757 if (i == 1 && read_write == I2C_SMBUS_READ
758 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
759 len = inb_p(SMBHSTDAT0(priv));
760 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
761 dev_err(&priv->pci_dev->dev,
762 "Illegal SMBus block read size %d\n",
763 len);
764 /* Recover */
765 while (inb_p(SMBHSTSTS(priv)) &
766 SMBHSTSTS_HOST_BUSY)
767 outb_p(SMBHSTSTS_BYTE_DONE,
768 SMBHSTSTS(priv));
769 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
770 return -EPROTO;
771 }
772 data->block[0] = len;
773 }
774
775 /* Retrieve/store value in SMBBLKDAT */
776 if (read_write == I2C_SMBUS_READ)
777 data->block[i] = inb_p(SMBBLKDAT(priv));
778 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
779 outb_p(data->block[i+1], SMBBLKDAT(priv));
780
781 /* signals SMBBLKDAT ready */
782 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
783 }
784
785 status = i801_wait_intr(priv);
786 exit:
787 return i801_check_post(priv, status);
788 }
789
i801_set_block_buffer_mode(struct i801_priv * priv)790 static int i801_set_block_buffer_mode(struct i801_priv *priv)
791 {
792 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
793 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
794 return -EIO;
795 return 0;
796 }
797
798 /* Block transaction function */
i801_block_transaction(struct i801_priv * priv,union i2c_smbus_data * data,char read_write,int command,int hwpec)799 static int i801_block_transaction(struct i801_priv *priv,
800 union i2c_smbus_data *data, char read_write,
801 int command, int hwpec)
802 {
803 int result = 0;
804 unsigned char hostc;
805
806 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
807 if (read_write == I2C_SMBUS_WRITE) {
808 /* set I2C_EN bit in configuration register */
809 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
810 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
811 hostc | SMBHSTCFG_I2C_EN);
812 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
813 dev_err(&priv->pci_dev->dev,
814 "I2C block read is unsupported!\n");
815 return -EOPNOTSUPP;
816 }
817 }
818
819 if (read_write == I2C_SMBUS_WRITE
820 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
821 if (data->block[0] < 1)
822 data->block[0] = 1;
823 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
824 data->block[0] = I2C_SMBUS_BLOCK_MAX;
825 } else {
826 data->block[0] = 32; /* max for SMBus block reads */
827 }
828
829 /* Experience has shown that the block buffer can only be used for
830 SMBus (not I2C) block transactions, even though the datasheet
831 doesn't mention this limitation. */
832 if ((priv->features & FEATURE_BLOCK_BUFFER)
833 && command != I2C_SMBUS_I2C_BLOCK_DATA
834 && i801_set_block_buffer_mode(priv) == 0)
835 result = i801_block_transaction_by_block(priv, data,
836 read_write,
837 command, hwpec);
838 else
839 result = i801_block_transaction_byte_by_byte(priv, data,
840 read_write,
841 command, hwpec);
842
843 if (command == I2C_SMBUS_I2C_BLOCK_DATA
844 && read_write == I2C_SMBUS_WRITE) {
845 /* restore saved configuration register value */
846 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
847 }
848 return result;
849 }
850
851 /* Return negative errno on error. */
i801_access(struct i2c_adapter * adap,u16 addr,unsigned short flags,char read_write,u8 command,int size,union i2c_smbus_data * data)852 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
853 unsigned short flags, char read_write, u8 command,
854 int size, union i2c_smbus_data *data)
855 {
856 int hwpec;
857 int block = 0;
858 int ret = 0, xact = 0;
859 struct i801_priv *priv = i2c_get_adapdata(adap);
860
861 mutex_lock(&priv->acpi_lock);
862 if (priv->acpi_reserved) {
863 mutex_unlock(&priv->acpi_lock);
864 return -EBUSY;
865 }
866
867 pm_runtime_get_sync(&priv->pci_dev->dev);
868
869 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
870 && size != I2C_SMBUS_QUICK
871 && size != I2C_SMBUS_I2C_BLOCK_DATA;
872
873 switch (size) {
874 case I2C_SMBUS_QUICK:
875 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
876 SMBHSTADD(priv));
877 xact = I801_QUICK;
878 break;
879 case I2C_SMBUS_BYTE:
880 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
881 SMBHSTADD(priv));
882 if (read_write == I2C_SMBUS_WRITE)
883 outb_p(command, SMBHSTCMD(priv));
884 xact = I801_BYTE;
885 break;
886 case I2C_SMBUS_BYTE_DATA:
887 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
888 SMBHSTADD(priv));
889 outb_p(command, SMBHSTCMD(priv));
890 if (read_write == I2C_SMBUS_WRITE)
891 outb_p(data->byte, SMBHSTDAT0(priv));
892 xact = I801_BYTE_DATA;
893 break;
894 case I2C_SMBUS_WORD_DATA:
895 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
896 SMBHSTADD(priv));
897 outb_p(command, SMBHSTCMD(priv));
898 if (read_write == I2C_SMBUS_WRITE) {
899 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
900 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
901 }
902 xact = I801_WORD_DATA;
903 break;
904 case I2C_SMBUS_BLOCK_DATA:
905 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
906 SMBHSTADD(priv));
907 outb_p(command, SMBHSTCMD(priv));
908 block = 1;
909 break;
910 case I2C_SMBUS_I2C_BLOCK_DATA:
911 /*
912 * NB: page 240 of ICH5 datasheet shows that the R/#W
913 * bit should be cleared here, even when reading.
914 * However if SPD Write Disable is set (Lynx Point and later),
915 * the read will fail if we don't set the R/#W bit.
916 */
917 outb_p(((addr & 0x7f) << 1) |
918 ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
919 (read_write & 0x01) : 0),
920 SMBHSTADD(priv));
921 if (read_write == I2C_SMBUS_READ) {
922 /* NB: page 240 of ICH5 datasheet also shows
923 * that DATA1 is the cmd field when reading */
924 outb_p(command, SMBHSTDAT1(priv));
925 } else
926 outb_p(command, SMBHSTCMD(priv));
927 block = 1;
928 break;
929 case I2C_SMBUS_BLOCK_PROC_CALL:
930 /*
931 * Bit 0 of the slave address register always indicate a write
932 * command.
933 */
934 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
935 outb_p(command, SMBHSTCMD(priv));
936 block = 1;
937 break;
938 default:
939 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
940 size);
941 ret = -EOPNOTSUPP;
942 goto out;
943 }
944
945 if (hwpec) /* enable/disable hardware PEC */
946 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
947 else
948 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
949 SMBAUXCTL(priv));
950
951 if (block)
952 ret = i801_block_transaction(priv, data, read_write, size,
953 hwpec);
954 else
955 ret = i801_transaction(priv, xact);
956
957 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
958 time, so we forcibly disable it after every transaction. Turn off
959 E32B for the same reason. */
960 if (hwpec || block)
961 outb_p(inb_p(SMBAUXCTL(priv)) &
962 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
963
964 if (block)
965 goto out;
966 if (ret)
967 goto out;
968 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
969 goto out;
970
971 switch (xact & 0x7f) {
972 case I801_BYTE: /* Result put in SMBHSTDAT0 */
973 case I801_BYTE_DATA:
974 data->byte = inb_p(SMBHSTDAT0(priv));
975 break;
976 case I801_WORD_DATA:
977 data->word = inb_p(SMBHSTDAT0(priv)) +
978 (inb_p(SMBHSTDAT1(priv)) << 8);
979 break;
980 }
981
982 out:
983 pm_runtime_mark_last_busy(&priv->pci_dev->dev);
984 pm_runtime_put_autosuspend(&priv->pci_dev->dev);
985 mutex_unlock(&priv->acpi_lock);
986 return ret;
987 }
988
989
i801_func(struct i2c_adapter * adapter)990 static u32 i801_func(struct i2c_adapter *adapter)
991 {
992 struct i801_priv *priv = i2c_get_adapdata(adapter);
993
994 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
995 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
996 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
997 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
998 ((priv->features & FEATURE_BLOCK_PROC) ?
999 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) |
1000 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
1001 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
1002 ((priv->features & FEATURE_HOST_NOTIFY) ?
1003 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
1004 }
1005
i801_enable_host_notify(struct i2c_adapter * adapter)1006 static void i801_enable_host_notify(struct i2c_adapter *adapter)
1007 {
1008 struct i801_priv *priv = i2c_get_adapdata(adapter);
1009
1010 if (!(priv->features & FEATURE_HOST_NOTIFY))
1011 return;
1012
1013 if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd))
1014 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd,
1015 SMBSLVCMD(priv));
1016
1017 /* clear Host Notify bit to allow a new notification */
1018 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
1019 }
1020
i801_disable_host_notify(struct i801_priv * priv)1021 static void i801_disable_host_notify(struct i801_priv *priv)
1022 {
1023 if (!(priv->features & FEATURE_HOST_NOTIFY))
1024 return;
1025
1026 outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
1027 }
1028
1029 static const struct i2c_algorithm smbus_algorithm = {
1030 .smbus_xfer = i801_access,
1031 .functionality = i801_func,
1032 };
1033
1034 static const struct pci_device_id i801_ids[] = {
1035 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
1036 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
1037 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
1038 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
1039 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
1040 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
1041 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
1042 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
1043 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
1044 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
1045 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
1046 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
1047 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
1048 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
1049 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
1050 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
1051 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
1052 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
1053 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
1054 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
1055 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
1056 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
1057 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
1058 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
1059 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
1060 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
1061 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
1062 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
1063 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
1064 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
1065 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
1066 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) },
1067 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
1068 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
1069 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
1070 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
1071 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
1072 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
1073 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) },
1074 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
1075 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EBG_SMBUS) },
1076 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
1077 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
1078 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
1079 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) },
1080 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) },
1081 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) },
1082 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) },
1083 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS) },
1084 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS) },
1085 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS) },
1086 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS) },
1087 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS) },
1088 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS) },
1089 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS) },
1090 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS) },
1091 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS) },
1092 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS) },
1093 { 0, }
1094 };
1095
1096 MODULE_DEVICE_TABLE(pci, i801_ids);
1097
1098 #if defined CONFIG_X86 && defined CONFIG_DMI
1099 static unsigned char apanel_addr;
1100
1101 /* Scan the system ROM for the signature "FJKEYINF" */
bios_signature(const void __iomem * bios)1102 static __init const void __iomem *bios_signature(const void __iomem *bios)
1103 {
1104 ssize_t offset;
1105 const unsigned char signature[] = "FJKEYINF";
1106
1107 for (offset = 0; offset < 0x10000; offset += 0x10) {
1108 if (check_signature(bios + offset, signature,
1109 sizeof(signature)-1))
1110 return bios + offset;
1111 }
1112 return NULL;
1113 }
1114
input_apanel_init(void)1115 static void __init input_apanel_init(void)
1116 {
1117 void __iomem *bios;
1118 const void __iomem *p;
1119
1120 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1121 p = bios_signature(bios);
1122 if (p) {
1123 /* just use the first address */
1124 apanel_addr = readb(p + 8 + 3) >> 1;
1125 }
1126 iounmap(bios);
1127 }
1128
1129 struct dmi_onboard_device_info {
1130 const char *name;
1131 u8 type;
1132 unsigned short i2c_addr;
1133 const char *i2c_type;
1134 };
1135
1136 static const struct dmi_onboard_device_info dmi_devices[] = {
1137 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1138 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1139 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1140 };
1141
dmi_check_onboard_device(u8 type,const char * name,struct i2c_adapter * adap)1142 static void dmi_check_onboard_device(u8 type, const char *name,
1143 struct i2c_adapter *adap)
1144 {
1145 int i;
1146 struct i2c_board_info info;
1147
1148 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1149 /* & ~0x80, ignore enabled/disabled bit */
1150 if ((type & ~0x80) != dmi_devices[i].type)
1151 continue;
1152 if (strcasecmp(name, dmi_devices[i].name))
1153 continue;
1154
1155 memset(&info, 0, sizeof(struct i2c_board_info));
1156 info.addr = dmi_devices[i].i2c_addr;
1157 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1158 i2c_new_client_device(adap, &info);
1159 break;
1160 }
1161 }
1162
1163 /* We use our own function to check for onboard devices instead of
1164 dmi_find_device() as some buggy BIOS's have the devices we are interested
1165 in marked as disabled */
dmi_check_onboard_devices(const struct dmi_header * dm,void * adap)1166 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1167 {
1168 int i, count;
1169
1170 if (dm->type != 10)
1171 return;
1172
1173 count = (dm->length - sizeof(struct dmi_header)) / 2;
1174 for (i = 0; i < count; i++) {
1175 const u8 *d = (char *)(dm + 1) + (i * 2);
1176 const char *name = ((char *) dm) + dm->length;
1177 u8 type = d[0];
1178 u8 s = d[1];
1179
1180 if (!s)
1181 continue;
1182 s--;
1183 while (s > 0 && name[0]) {
1184 name += strlen(name) + 1;
1185 s--;
1186 }
1187 if (name[0] == 0) /* Bogus string reference */
1188 continue;
1189
1190 dmi_check_onboard_device(type, name, adap);
1191 }
1192 }
1193
1194 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */
1195 static const char *const acpi_smo8800_ids[] = {
1196 "SMO8800",
1197 "SMO8801",
1198 "SMO8810",
1199 "SMO8811",
1200 "SMO8820",
1201 "SMO8821",
1202 "SMO8830",
1203 "SMO8831",
1204 };
1205
check_acpi_smo88xx_device(acpi_handle obj_handle,u32 nesting_level,void * context,void ** return_value)1206 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle,
1207 u32 nesting_level,
1208 void *context,
1209 void **return_value)
1210 {
1211 struct acpi_device_info *info;
1212 acpi_status status;
1213 char *hid;
1214 int i;
1215
1216 status = acpi_get_object_info(obj_handle, &info);
1217 if (ACPI_FAILURE(status))
1218 return AE_OK;
1219
1220 if (!(info->valid & ACPI_VALID_HID))
1221 goto smo88xx_not_found;
1222
1223 hid = info->hardware_id.string;
1224 if (!hid)
1225 goto smo88xx_not_found;
1226
1227 i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid);
1228 if (i < 0)
1229 goto smo88xx_not_found;
1230
1231 kfree(info);
1232
1233 *((bool *)return_value) = true;
1234 return AE_CTRL_TERMINATE;
1235
1236 smo88xx_not_found:
1237 kfree(info);
1238 return AE_OK;
1239 }
1240
is_dell_system_with_lis3lv02d(void)1241 static bool is_dell_system_with_lis3lv02d(void)
1242 {
1243 bool found;
1244 const char *vendor;
1245
1246 vendor = dmi_get_system_info(DMI_SYS_VENDOR);
1247 if (!vendor || strcmp(vendor, "Dell Inc."))
1248 return false;
1249
1250 /*
1251 * Check that ACPI device SMO88xx is present and is functioning.
1252 * Function acpi_get_devices() already filters all ACPI devices
1253 * which are not present or are not functioning.
1254 * ACPI device SMO88xx represents our ST microelectronics lis3lv02d
1255 * accelerometer but unfortunately ACPI does not provide any other
1256 * information (like I2C address).
1257 */
1258 found = false;
1259 acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL,
1260 (void **)&found);
1261
1262 return found;
1263 }
1264
1265 /*
1266 * Accelerometer's I2C address is not specified in DMI nor ACPI,
1267 * so it is needed to define mapping table based on DMI product names.
1268 */
1269 static const struct {
1270 const char *dmi_product_name;
1271 unsigned short i2c_addr;
1272 } dell_lis3lv02d_devices[] = {
1273 /*
1274 * Dell platform team told us that these Latitude devices have
1275 * ST microelectronics accelerometer at I2C address 0x29.
1276 */
1277 { "Latitude E5250", 0x29 },
1278 { "Latitude E5450", 0x29 },
1279 { "Latitude E5550", 0x29 },
1280 { "Latitude E6440", 0x29 },
1281 { "Latitude E6440 ATG", 0x29 },
1282 { "Latitude E6540", 0x29 },
1283 /*
1284 * Additional individual entries were added after verification.
1285 */
1286 { "Latitude 5480", 0x29 },
1287 { "Vostro V131", 0x1d },
1288 };
1289
register_dell_lis3lv02d_i2c_device(struct i801_priv * priv)1290 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv)
1291 {
1292 struct i2c_board_info info;
1293 const char *dmi_product_name;
1294 int i;
1295
1296 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
1297 for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) {
1298 if (strcmp(dmi_product_name,
1299 dell_lis3lv02d_devices[i].dmi_product_name) == 0)
1300 break;
1301 }
1302
1303 if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) {
1304 dev_warn(&priv->pci_dev->dev,
1305 "Accelerometer lis3lv02d is present on SMBus but its"
1306 " address is unknown, skipping registration\n");
1307 return;
1308 }
1309
1310 memset(&info, 0, sizeof(struct i2c_board_info));
1311 info.addr = dell_lis3lv02d_devices[i].i2c_addr;
1312 strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
1313 i2c_new_client_device(&priv->adapter, &info);
1314 }
1315
1316 /* Register optional slaves */
i801_probe_optional_slaves(struct i801_priv * priv)1317 static void i801_probe_optional_slaves(struct i801_priv *priv)
1318 {
1319 /* Only register slaves on main SMBus channel */
1320 if (priv->features & FEATURE_IDF)
1321 return;
1322
1323 if (apanel_addr) {
1324 struct i2c_board_info info;
1325
1326 memset(&info, 0, sizeof(struct i2c_board_info));
1327 info.addr = apanel_addr;
1328 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
1329 i2c_new_client_device(&priv->adapter, &info);
1330 }
1331
1332 if (dmi_name_in_vendors("FUJITSU"))
1333 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1334
1335 if (is_dell_system_with_lis3lv02d())
1336 register_dell_lis3lv02d_i2c_device(priv);
1337
1338 /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */
1339 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO)
1340 if (!priv->mux_drvdata)
1341 #endif
1342 i2c_register_spd(&priv->adapter);
1343 }
1344 #else
input_apanel_init(void)1345 static void __init input_apanel_init(void) {}
i801_probe_optional_slaves(struct i801_priv * priv)1346 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1347 #endif /* CONFIG_X86 && CONFIG_DMI */
1348
1349 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1350 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1351 .gpio_chip = "gpio_ich",
1352 .values = { 0x02, 0x03 },
1353 .n_values = 2,
1354 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1355 .gpios = { 52, 53 },
1356 .n_gpios = 2,
1357 };
1358
1359 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1360 .gpio_chip = "gpio_ich",
1361 .values = { 0x02, 0x03, 0x01 },
1362 .n_values = 3,
1363 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1364 .gpios = { 52, 53 },
1365 .n_gpios = 2,
1366 };
1367
1368 static const struct dmi_system_id mux_dmi_table[] = {
1369 {
1370 .matches = {
1371 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1372 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1373 },
1374 .driver_data = &i801_mux_config_asus_z8_d12,
1375 },
1376 {
1377 .matches = {
1378 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1379 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1380 },
1381 .driver_data = &i801_mux_config_asus_z8_d12,
1382 },
1383 {
1384 .matches = {
1385 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1386 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1387 },
1388 .driver_data = &i801_mux_config_asus_z8_d12,
1389 },
1390 {
1391 .matches = {
1392 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1393 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1394 },
1395 .driver_data = &i801_mux_config_asus_z8_d12,
1396 },
1397 {
1398 .matches = {
1399 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1400 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1401 },
1402 .driver_data = &i801_mux_config_asus_z8_d12,
1403 },
1404 {
1405 .matches = {
1406 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1407 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1408 },
1409 .driver_data = &i801_mux_config_asus_z8_d12,
1410 },
1411 {
1412 .matches = {
1413 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1414 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1415 },
1416 .driver_data = &i801_mux_config_asus_z8_d18,
1417 },
1418 {
1419 .matches = {
1420 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1421 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1422 },
1423 .driver_data = &i801_mux_config_asus_z8_d18,
1424 },
1425 {
1426 .matches = {
1427 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1428 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1429 },
1430 .driver_data = &i801_mux_config_asus_z8_d12,
1431 },
1432 { }
1433 };
1434
1435 /* Setup multiplexing if needed */
i801_add_mux(struct i801_priv * priv)1436 static int i801_add_mux(struct i801_priv *priv)
1437 {
1438 struct device *dev = &priv->adapter.dev;
1439 const struct i801_mux_config *mux_config;
1440 struct i2c_mux_gpio_platform_data gpio_data;
1441 struct gpiod_lookup_table *lookup;
1442 int i;
1443
1444 if (!priv->mux_drvdata)
1445 return 0;
1446 mux_config = priv->mux_drvdata;
1447
1448 /* Prepare the platform data */
1449 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1450 gpio_data.parent = priv->adapter.nr;
1451 gpio_data.values = mux_config->values;
1452 gpio_data.n_values = mux_config->n_values;
1453 gpio_data.classes = mux_config->classes;
1454 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1455
1456 /* Register GPIO descriptor lookup table */
1457 lookup = devm_kzalloc(dev,
1458 struct_size(lookup, table, mux_config->n_gpios + 1),
1459 GFP_KERNEL);
1460 if (!lookup)
1461 return -ENOMEM;
1462 lookup->dev_id = "i2c-mux-gpio";
1463 for (i = 0; i < mux_config->n_gpios; i++) {
1464 lookup->table[i] = (struct gpiod_lookup)
1465 GPIO_LOOKUP(mux_config->gpio_chip,
1466 mux_config->gpios[i], "mux", 0);
1467 }
1468 gpiod_add_lookup_table(lookup);
1469 priv->lookup = lookup;
1470
1471 /*
1472 * Register the mux device, we use PLATFORM_DEVID_NONE here
1473 * because since we are referring to the GPIO chip by name we are
1474 * anyways in deep trouble if there is more than one of these
1475 * devices, and there should likely only be one platform controller
1476 * hub.
1477 */
1478 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1479 PLATFORM_DEVID_NONE, &gpio_data,
1480 sizeof(struct i2c_mux_gpio_platform_data));
1481 if (IS_ERR(priv->mux_pdev)) {
1482 gpiod_remove_lookup_table(lookup);
1483 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1484 }
1485
1486 return PTR_ERR_OR_ZERO(priv->mux_pdev);
1487 }
1488
i801_del_mux(struct i801_priv * priv)1489 static void i801_del_mux(struct i801_priv *priv)
1490 {
1491 platform_device_unregister(priv->mux_pdev);
1492 gpiod_remove_lookup_table(priv->lookup);
1493 }
1494
i801_get_adapter_class(struct i801_priv * priv)1495 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1496 {
1497 const struct dmi_system_id *id;
1498 const struct i801_mux_config *mux_config;
1499 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1500 int i;
1501
1502 id = dmi_first_match(mux_dmi_table);
1503 if (id) {
1504 /* Remove branch classes from trunk */
1505 mux_config = id->driver_data;
1506 for (i = 0; i < mux_config->n_values; i++)
1507 class &= ~mux_config->classes[i];
1508
1509 /* Remember for later */
1510 priv->mux_drvdata = mux_config;
1511 }
1512
1513 return class;
1514 }
1515 #else
i801_add_mux(struct i801_priv * priv)1516 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
i801_del_mux(struct i801_priv * priv)1517 static inline void i801_del_mux(struct i801_priv *priv) { }
1518
i801_get_adapter_class(struct i801_priv * priv)1519 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1520 {
1521 return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1522 }
1523 #endif
1524
1525 static const struct itco_wdt_platform_data spt_tco_platform_data = {
1526 .name = "Intel PCH",
1527 .version = 4,
1528 };
1529
1530 static DEFINE_SPINLOCK(p2sb_spinlock);
1531
1532 static struct platform_device *
i801_add_tco_spt(struct i801_priv * priv,struct pci_dev * pci_dev,struct resource * tco_res)1533 i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev,
1534 struct resource *tco_res)
1535 {
1536 struct resource *res;
1537 unsigned int devfn;
1538 u64 base64_addr;
1539 u32 base_addr;
1540 u8 hidden;
1541
1542 /*
1543 * We must access the NO_REBOOT bit over the Primary to Sideband
1544 * bridge (P2SB). The BIOS prevents the P2SB device from being
1545 * enumerated by the PCI subsystem, so we need to unhide/hide it
1546 * to lookup the P2SB BAR.
1547 */
1548 spin_lock(&p2sb_spinlock);
1549
1550 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1551
1552 /* Unhide the P2SB device, if it is hidden */
1553 pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden);
1554 if (hidden)
1555 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1556
1557 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1558 base64_addr = base_addr & 0xfffffff0;
1559
1560 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1561 base64_addr |= (u64)base_addr << 32;
1562
1563 /* Hide the P2SB device, if it was hidden before */
1564 if (hidden)
1565 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden);
1566 spin_unlock(&p2sb_spinlock);
1567
1568 res = &tco_res[1];
1569 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1570 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
1571 else
1572 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1573
1574 res->end = res->start + 3;
1575 res->flags = IORESOURCE_MEM;
1576
1577 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1578 tco_res, 2, &spt_tco_platform_data,
1579 sizeof(spt_tco_platform_data));
1580 }
1581
1582 static const struct itco_wdt_platform_data cnl_tco_platform_data = {
1583 .name = "Intel PCH",
1584 .version = 6,
1585 };
1586
1587 static struct platform_device *
i801_add_tco_cnl(struct i801_priv * priv,struct pci_dev * pci_dev,struct resource * tco_res)1588 i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev,
1589 struct resource *tco_res)
1590 {
1591 return platform_device_register_resndata(&pci_dev->dev,
1592 "iTCO_wdt", -1, tco_res, 1, &cnl_tco_platform_data,
1593 sizeof(cnl_tco_platform_data));
1594 }
1595
i801_add_tco(struct i801_priv * priv)1596 static void i801_add_tco(struct i801_priv *priv)
1597 {
1598 struct pci_dev *pci_dev = priv->pci_dev;
1599 struct resource tco_res[2], *res;
1600 u32 tco_base, tco_ctl;
1601
1602 /* If we have ACPI based watchdog use that instead */
1603 if (acpi_has_watchdog())
1604 return;
1605
1606 if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL)))
1607 return;
1608
1609 pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1610 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1611 if (!(tco_ctl & TCOCTL_EN))
1612 return;
1613
1614 memset(tco_res, 0, sizeof(tco_res));
1615 /*
1616 * Always populate the main iTCO IO resource here. The second entry
1617 * for NO_REBOOT MMIO is filled by the SPT specific function.
1618 */
1619 res = &tco_res[0];
1620 res->start = tco_base & ~1;
1621 res->end = res->start + 32 - 1;
1622 res->flags = IORESOURCE_IO;
1623
1624 if (priv->features & FEATURE_TCO_CNL)
1625 priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res);
1626 else
1627 priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res);
1628
1629 if (IS_ERR(priv->tco_pdev))
1630 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1631 }
1632
1633 #ifdef CONFIG_ACPI
i801_acpi_is_smbus_ioport(const struct i801_priv * priv,acpi_physical_address address)1634 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1635 acpi_physical_address address)
1636 {
1637 return address >= priv->smba &&
1638 address <= pci_resource_end(priv->pci_dev, SMBBAR);
1639 }
1640
1641 static acpi_status
i801_acpi_io_handler(u32 function,acpi_physical_address address,u32 bits,u64 * value,void * handler_context,void * region_context)1642 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1643 u64 *value, void *handler_context, void *region_context)
1644 {
1645 struct i801_priv *priv = handler_context;
1646 struct pci_dev *pdev = priv->pci_dev;
1647 acpi_status status;
1648
1649 /*
1650 * Once BIOS AML code touches the OpRegion we warn and inhibit any
1651 * further access from the driver itself. This device is now owned
1652 * by the system firmware.
1653 */
1654 mutex_lock(&priv->acpi_lock);
1655
1656 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1657 priv->acpi_reserved = true;
1658
1659 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1660 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1661
1662 /*
1663 * BIOS is accessing the host controller so prevent it from
1664 * suspending automatically from now on.
1665 */
1666 pm_runtime_get_sync(&pdev->dev);
1667 }
1668
1669 if ((function & ACPI_IO_MASK) == ACPI_READ)
1670 status = acpi_os_read_port(address, (u32 *)value, bits);
1671 else
1672 status = acpi_os_write_port(address, (u32)*value, bits);
1673
1674 mutex_unlock(&priv->acpi_lock);
1675
1676 return status;
1677 }
1678
i801_acpi_probe(struct i801_priv * priv)1679 static int i801_acpi_probe(struct i801_priv *priv)
1680 {
1681 struct acpi_device *adev;
1682 acpi_status status;
1683
1684 adev = ACPI_COMPANION(&priv->pci_dev->dev);
1685 if (adev) {
1686 status = acpi_install_address_space_handler(adev->handle,
1687 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
1688 NULL, priv);
1689 if (ACPI_SUCCESS(status))
1690 return 0;
1691 }
1692
1693 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1694 }
1695
i801_acpi_remove(struct i801_priv * priv)1696 static void i801_acpi_remove(struct i801_priv *priv)
1697 {
1698 struct acpi_device *adev;
1699
1700 adev = ACPI_COMPANION(&priv->pci_dev->dev);
1701 if (!adev)
1702 return;
1703
1704 acpi_remove_address_space_handler(adev->handle,
1705 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1706
1707 mutex_lock(&priv->acpi_lock);
1708 if (priv->acpi_reserved)
1709 pm_runtime_put(&priv->pci_dev->dev);
1710 mutex_unlock(&priv->acpi_lock);
1711 }
1712 #else
i801_acpi_probe(struct i801_priv * priv)1713 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
i801_acpi_remove(struct i801_priv * priv)1714 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1715 #endif
1716
i801_setup_hstcfg(struct i801_priv * priv)1717 static unsigned char i801_setup_hstcfg(struct i801_priv *priv)
1718 {
1719 unsigned char hstcfg = priv->original_hstcfg;
1720
1721 hstcfg &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1722 hstcfg |= SMBHSTCFG_HST_EN;
1723 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg);
1724 return hstcfg;
1725 }
1726
i801_probe(struct pci_dev * dev,const struct pci_device_id * id)1727 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1728 {
1729 unsigned char temp;
1730 int err, i;
1731 struct i801_priv *priv;
1732
1733 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1734 if (!priv)
1735 return -ENOMEM;
1736
1737 i2c_set_adapdata(&priv->adapter, priv);
1738 priv->adapter.owner = THIS_MODULE;
1739 priv->adapter.class = i801_get_adapter_class(priv);
1740 priv->adapter.algo = &smbus_algorithm;
1741 priv->adapter.dev.parent = &dev->dev;
1742 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1743 priv->adapter.retries = 3;
1744 mutex_init(&priv->acpi_lock);
1745
1746 priv->pci_dev = dev;
1747 switch (dev->device) {
1748 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1749 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1750 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1751 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1752 case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1753 case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS:
1754 case PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS:
1755 priv->features |= FEATURE_BLOCK_PROC;
1756 priv->features |= FEATURE_I2C_BLOCK_READ;
1757 priv->features |= FEATURE_IRQ;
1758 priv->features |= FEATURE_SMBUS_PEC;
1759 priv->features |= FEATURE_BLOCK_BUFFER;
1760 priv->features |= FEATURE_TCO_SPT;
1761 priv->features |= FEATURE_HOST_NOTIFY;
1762 break;
1763
1764 case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS:
1765 case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS:
1766 case PCI_DEVICE_ID_INTEL_CDF_SMBUS:
1767 case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS:
1768 case PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS:
1769 case PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS:
1770 case PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS:
1771 case PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS:
1772 case PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS:
1773 case PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS:
1774 case PCI_DEVICE_ID_INTEL_EBG_SMBUS:
1775 case PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS:
1776 case PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS:
1777 case PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS:
1778 priv->features |= FEATURE_BLOCK_PROC;
1779 priv->features |= FEATURE_I2C_BLOCK_READ;
1780 priv->features |= FEATURE_IRQ;
1781 priv->features |= FEATURE_SMBUS_PEC;
1782 priv->features |= FEATURE_BLOCK_BUFFER;
1783 priv->features |= FEATURE_TCO_CNL;
1784 priv->features |= FEATURE_HOST_NOTIFY;
1785 break;
1786
1787 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1788 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1789 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1790 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1791 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1792 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1793 priv->features |= FEATURE_IDF;
1794 fallthrough;
1795 default:
1796 priv->features |= FEATURE_BLOCK_PROC;
1797 priv->features |= FEATURE_I2C_BLOCK_READ;
1798 priv->features |= FEATURE_IRQ;
1799 fallthrough;
1800 case PCI_DEVICE_ID_INTEL_82801DB_3:
1801 priv->features |= FEATURE_SMBUS_PEC;
1802 priv->features |= FEATURE_BLOCK_BUFFER;
1803 fallthrough;
1804 case PCI_DEVICE_ID_INTEL_82801CA_3:
1805 priv->features |= FEATURE_HOST_NOTIFY;
1806 fallthrough;
1807 case PCI_DEVICE_ID_INTEL_82801BA_2:
1808 case PCI_DEVICE_ID_INTEL_82801AB_3:
1809 case PCI_DEVICE_ID_INTEL_82801AA_3:
1810 break;
1811 }
1812
1813 /* Disable features on user request */
1814 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1815 if (priv->features & disable_features & (1 << i))
1816 dev_notice(&dev->dev, "%s disabled by user\n",
1817 i801_feature_names[i]);
1818 }
1819 priv->features &= ~disable_features;
1820
1821 err = pcim_enable_device(dev);
1822 if (err) {
1823 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1824 err);
1825 return err;
1826 }
1827 pcim_pin_device(dev);
1828
1829 /* Determine the address of the SMBus area */
1830 priv->smba = pci_resource_start(dev, SMBBAR);
1831 if (!priv->smba) {
1832 dev_err(&dev->dev,
1833 "SMBus base address uninitialized, upgrade BIOS\n");
1834 return -ENODEV;
1835 }
1836
1837 if (i801_acpi_probe(priv))
1838 return -ENODEV;
1839
1840 err = pcim_iomap_regions(dev, 1 << SMBBAR,
1841 dev_driver_string(&dev->dev));
1842 if (err) {
1843 dev_err(&dev->dev,
1844 "Failed to request SMBus region 0x%lx-0x%Lx\n",
1845 priv->smba,
1846 (unsigned long long)pci_resource_end(dev, SMBBAR));
1847 i801_acpi_remove(priv);
1848 return err;
1849 }
1850
1851 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg);
1852 temp = i801_setup_hstcfg(priv);
1853 if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN))
1854 dev_info(&dev->dev, "Enabling SMBus device\n");
1855
1856 if (temp & SMBHSTCFG_SMB_SMI_EN) {
1857 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1858 /* Disable SMBus interrupt feature if SMBus using SMI# */
1859 priv->features &= ~FEATURE_IRQ;
1860 }
1861 if (temp & SMBHSTCFG_SPD_WD)
1862 dev_info(&dev->dev, "SPD Write Disable is set\n");
1863
1864 /* Clear special mode bits */
1865 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1866 outb_p(inb_p(SMBAUXCTL(priv)) &
1867 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1868
1869 /* Remember original Host Notify setting */
1870 if (priv->features & FEATURE_HOST_NOTIFY)
1871 priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1872
1873 /* Default timeout in interrupt mode: 200 ms */
1874 priv->adapter.timeout = HZ / 5;
1875
1876 if (dev->irq == IRQ_NOTCONNECTED)
1877 priv->features &= ~FEATURE_IRQ;
1878
1879 if (priv->features & FEATURE_IRQ) {
1880 u16 pcictl, pcists;
1881
1882 /* Complain if an interrupt is already pending */
1883 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1884 if (pcists & SMBPCISTS_INTS)
1885 dev_warn(&dev->dev, "An interrupt is pending!\n");
1886
1887 /* Check if interrupts have been disabled */
1888 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1889 if (pcictl & SMBPCICTL_INTDIS) {
1890 dev_info(&dev->dev, "Interrupts are disabled\n");
1891 priv->features &= ~FEATURE_IRQ;
1892 }
1893 }
1894
1895 if (priv->features & FEATURE_IRQ) {
1896 init_waitqueue_head(&priv->waitq);
1897
1898 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1899 IRQF_SHARED,
1900 dev_driver_string(&dev->dev), priv);
1901 if (err) {
1902 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1903 dev->irq, err);
1904 priv->features &= ~FEATURE_IRQ;
1905 }
1906 }
1907 dev_info(&dev->dev, "SMBus using %s\n",
1908 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1909
1910 i801_add_tco(priv);
1911
1912 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1913 "SMBus I801 adapter at %04lx", priv->smba);
1914 err = i2c_add_adapter(&priv->adapter);
1915 if (err) {
1916 i801_acpi_remove(priv);
1917 return err;
1918 }
1919
1920 i801_enable_host_notify(&priv->adapter);
1921
1922 i801_probe_optional_slaves(priv);
1923 /* We ignore errors - multiplexing is optional */
1924 i801_add_mux(priv);
1925
1926 pci_set_drvdata(dev, priv);
1927
1928 dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
1929 pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1930 pm_runtime_use_autosuspend(&dev->dev);
1931 pm_runtime_put_autosuspend(&dev->dev);
1932 pm_runtime_allow(&dev->dev);
1933
1934 return 0;
1935 }
1936
i801_remove(struct pci_dev * dev)1937 static void i801_remove(struct pci_dev *dev)
1938 {
1939 struct i801_priv *priv = pci_get_drvdata(dev);
1940
1941 pm_runtime_forbid(&dev->dev);
1942 pm_runtime_get_noresume(&dev->dev);
1943
1944 i801_disable_host_notify(priv);
1945 i801_del_mux(priv);
1946 i2c_del_adapter(&priv->adapter);
1947 i801_acpi_remove(priv);
1948 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1949
1950 platform_device_unregister(priv->tco_pdev);
1951
1952 /*
1953 * do not call pci_disable_device(dev) since it can cause hard hangs on
1954 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1955 */
1956 }
1957
i801_shutdown(struct pci_dev * dev)1958 static void i801_shutdown(struct pci_dev *dev)
1959 {
1960 struct i801_priv *priv = pci_get_drvdata(dev);
1961
1962 /* Restore config registers to avoid hard hang on some systems */
1963 i801_disable_host_notify(priv);
1964 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1965 }
1966
1967 #ifdef CONFIG_PM_SLEEP
i801_suspend(struct device * dev)1968 static int i801_suspend(struct device *dev)
1969 {
1970 struct i801_priv *priv = dev_get_drvdata(dev);
1971
1972 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg);
1973 return 0;
1974 }
1975
i801_resume(struct device * dev)1976 static int i801_resume(struct device *dev)
1977 {
1978 struct i801_priv *priv = dev_get_drvdata(dev);
1979
1980 i801_setup_hstcfg(priv);
1981 i801_enable_host_notify(&priv->adapter);
1982
1983 return 0;
1984 }
1985 #endif
1986
1987 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
1988
1989 static struct pci_driver i801_driver = {
1990 .name = "i801_smbus",
1991 .id_table = i801_ids,
1992 .probe = i801_probe,
1993 .remove = i801_remove,
1994 .shutdown = i801_shutdown,
1995 .driver = {
1996 .pm = &i801_pm_ops,
1997 },
1998 };
1999
i2c_i801_init(void)2000 static int __init i2c_i801_init(void)
2001 {
2002 if (dmi_name_in_vendors("FUJITSU"))
2003 input_apanel_init();
2004 return pci_register_driver(&i801_driver);
2005 }
2006
i2c_i801_exit(void)2007 static void __exit i2c_i801_exit(void)
2008 {
2009 pci_unregister_driver(&i801_driver);
2010 }
2011
2012 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>");
2013 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
2014 MODULE_DESCRIPTION("I801 SMBus driver");
2015 MODULE_LICENSE("GPL");
2016
2017 module_init(i2c_i801_init);
2018 module_exit(i2c_i801_exit);
2019