1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Intel IOMMU trace support 4 * 5 * Copyright (C) 2019 Intel Corporation 6 * 7 * Author: Lu Baolu <baolu.lu@linux.intel.com> 8 */ 9 #undef TRACE_SYSTEM 10 #define TRACE_SYSTEM intel_iommu 11 12 #if !defined(_TRACE_INTEL_IOMMU_H) || defined(TRACE_HEADER_MULTI_READ) 13 #define _TRACE_INTEL_IOMMU_H 14 15 #include <linux/tracepoint.h> 16 #include <linux/intel-iommu.h> 17 18 TRACE_EVENT(qi_submit, 19 TP_PROTO(struct intel_iommu *iommu, u64 qw0, u64 qw1, u64 qw2, u64 qw3), 20 21 TP_ARGS(iommu, qw0, qw1, qw2, qw3), 22 23 TP_STRUCT__entry( 24 __field(u64, qw0) 25 __field(u64, qw1) 26 __field(u64, qw2) 27 __field(u64, qw3) 28 __string(iommu, iommu->name) 29 ), 30 31 TP_fast_assign( 32 __assign_str(iommu, iommu->name); 33 __entry->qw0 = qw0; 34 __entry->qw1 = qw1; 35 __entry->qw2 = qw2; 36 __entry->qw3 = qw3; 37 ), 38 39 TP_printk("%s %s: 0x%llx 0x%llx 0x%llx 0x%llx", 40 __print_symbolic(__entry->qw0 & 0xf, 41 { QI_CC_TYPE, "cc_inv" }, 42 { QI_IOTLB_TYPE, "iotlb_inv" }, 43 { QI_DIOTLB_TYPE, "dev_tlb_inv" }, 44 { QI_IEC_TYPE, "iec_inv" }, 45 { QI_IWD_TYPE, "inv_wait" }, 46 { QI_EIOTLB_TYPE, "p_iotlb_inv" }, 47 { QI_PC_TYPE, "pc_inv" }, 48 { QI_DEIOTLB_TYPE, "p_dev_tlb_inv" }, 49 { QI_PGRP_RESP_TYPE, "page_grp_resp" }), 50 __get_str(iommu), 51 __entry->qw0, __entry->qw1, __entry->qw2, __entry->qw3 52 ) 53 ); 54 #endif /* _TRACE_INTEL_IOMMU_H */ 55 56 /* This part must be outside protection */ 57 #include <trace/define_trace.h> 58