1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * Copyright 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 #ifndef __AMDGPU_DRM_H__ 33 #define __AMDGPU_DRM_H__ 34 35 #include "drm.h" 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif 40 41 #define DRM_AMDGPU_GEM_CREATE 0x00 42 #define DRM_AMDGPU_GEM_MMAP 0x01 43 #define DRM_AMDGPU_CTX 0x02 44 #define DRM_AMDGPU_BO_LIST 0x03 45 #define DRM_AMDGPU_CS 0x04 46 #define DRM_AMDGPU_INFO 0x05 47 #define DRM_AMDGPU_GEM_METADATA 0x06 48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 49 #define DRM_AMDGPU_GEM_VA 0x08 50 #define DRM_AMDGPU_WAIT_CS 0x09 51 #define DRM_AMDGPU_GEM_OP 0x10 52 #define DRM_AMDGPU_GEM_USERPTR 0x11 53 #define DRM_AMDGPU_WAIT_FENCES 0x12 54 #define DRM_AMDGPU_VM 0x13 55 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 56 #define DRM_AMDGPU_SCHED 0x15 57 58 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 59 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 60 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 61 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 62 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 63 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 64 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 65 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 66 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 67 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 68 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 69 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 70 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 71 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 72 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 73 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 74 75 /** 76 * DOC: memory domains 77 * 78 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. 79 * Memory in this pool could be swapped out to disk if there is pressure. 80 * 81 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the 82 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous 83 * pages of system memory, allows GPU access system memory in a linezrized 84 * fashion. 85 * 86 * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory 87 * carved out by the BIOS. 88 * 89 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data 90 * across shader threads. 91 * 92 * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the 93 * execution of all the waves on a device. 94 * 95 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines 96 * for appending data. 97 */ 98 #define AMDGPU_GEM_DOMAIN_CPU 0x1 99 #define AMDGPU_GEM_DOMAIN_GTT 0x2 100 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 101 #define AMDGPU_GEM_DOMAIN_GDS 0x8 102 #define AMDGPU_GEM_DOMAIN_GWS 0x10 103 #define AMDGPU_GEM_DOMAIN_OA 0x20 104 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 105 AMDGPU_GEM_DOMAIN_GTT | \ 106 AMDGPU_GEM_DOMAIN_VRAM | \ 107 AMDGPU_GEM_DOMAIN_GDS | \ 108 AMDGPU_GEM_DOMAIN_GWS | \ 109 AMDGPU_GEM_DOMAIN_OA) 110 111 /* Flag that CPU access will be required for the case of VRAM domain */ 112 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 113 /* Flag that CPU access will not work, this VRAM domain is invisible */ 114 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 115 /* Flag that USWC attributes should be used for GTT */ 116 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 117 /* Flag that the memory should be in VRAM and cleared */ 118 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 119 /* Flag that create shadow bo(GTT) while allocating vram bo */ 120 #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) 121 /* Flag that allocating the BO should use linear VRAM */ 122 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 123 /* Flag that BO is always valid in this VM */ 124 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 125 /* Flag that BO sharing will be explicitly synchronized */ 126 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 127 /* Flag that indicates allocating MQD gart on GFX9, where the mtype 128 * for the second page onward should be set to NC. It should never 129 * be used by user space applications. 130 */ 131 #define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) 132 /* Flag that BO may contain sensitive data that must be wiped before 133 * releasing the memory 134 */ 135 #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) 136 /* Flag that BO will be encrypted and that the TMZ bit should be 137 * set in the PTEs when mapping this buffer via GPUVM or 138 * accessing it with various hw blocks 139 */ 140 #define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) 141 142 struct drm_amdgpu_gem_create_in { 143 /** the requested memory size */ 144 uint64_t bo_size; 145 /** physical start_addr alignment in bytes for some HW requirements */ 146 uint64_t alignment; 147 /** the requested memory domains */ 148 uint64_t domains; 149 /** allocation flags */ 150 uint64_t domain_flags; 151 }; 152 153 struct drm_amdgpu_gem_create_out { 154 /** returned GEM object handle */ 155 uint32_t handle; 156 uint32_t _pad; 157 }; 158 159 union drm_amdgpu_gem_create { 160 struct drm_amdgpu_gem_create_in in; 161 struct drm_amdgpu_gem_create_out out; 162 }; 163 164 /** Opcode to create new residency list. */ 165 #define AMDGPU_BO_LIST_OP_CREATE 0 166 /** Opcode to destroy previously created residency list */ 167 #define AMDGPU_BO_LIST_OP_DESTROY 1 168 /** Opcode to update resource information in the list */ 169 #define AMDGPU_BO_LIST_OP_UPDATE 2 170 171 struct drm_amdgpu_bo_list_in { 172 /** Type of operation */ 173 uint32_t operation; 174 /** Handle of list or 0 if we want to create one */ 175 uint32_t list_handle; 176 /** Number of BOs in list */ 177 uint32_t bo_number; 178 /** Size of each element describing BO */ 179 uint32_t bo_info_size; 180 /** Pointer to array describing BOs */ 181 uint64_t bo_info_ptr; 182 }; 183 184 struct drm_amdgpu_bo_list_entry { 185 /** Handle of BO */ 186 uint32_t bo_handle; 187 /** New (if specified) BO priority to be used during migration */ 188 uint32_t bo_priority; 189 }; 190 191 struct drm_amdgpu_bo_list_out { 192 /** Handle of resource list */ 193 uint32_t list_handle; 194 uint32_t _pad; 195 }; 196 197 union drm_amdgpu_bo_list { 198 struct drm_amdgpu_bo_list_in in; 199 struct drm_amdgpu_bo_list_out out; 200 }; 201 202 /* context related */ 203 #define AMDGPU_CTX_OP_ALLOC_CTX 1 204 #define AMDGPU_CTX_OP_FREE_CTX 2 205 #define AMDGPU_CTX_OP_QUERY_STATE 3 206 #define AMDGPU_CTX_OP_QUERY_STATE2 4 207 208 /* GPU reset status */ 209 #define AMDGPU_CTX_NO_RESET 0 210 /* this the context caused it */ 211 #define AMDGPU_CTX_GUILTY_RESET 1 212 /* some other context caused it */ 213 #define AMDGPU_CTX_INNOCENT_RESET 2 214 /* unknown cause */ 215 #define AMDGPU_CTX_UNKNOWN_RESET 3 216 217 /* indicate gpu reset occured after ctx created */ 218 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) 219 /* indicate vram lost occured after ctx created */ 220 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) 221 /* indicate some job from this context once cause gpu hang */ 222 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) 223 /* indicate some errors are detected by RAS */ 224 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3) 225 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4) 226 227 /* Context priority level */ 228 #define AMDGPU_CTX_PRIORITY_UNSET -2048 229 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 230 #define AMDGPU_CTX_PRIORITY_LOW -512 231 #define AMDGPU_CTX_PRIORITY_NORMAL 0 232 /* 233 * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires 234 * CAP_SYS_NICE or DRM_MASTER 235 */ 236 #define AMDGPU_CTX_PRIORITY_HIGH 512 237 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 238 239 struct drm_amdgpu_ctx_in { 240 /** AMDGPU_CTX_OP_* */ 241 uint32_t op; 242 /** For future use, no flags defined so far */ 243 uint32_t flags; 244 uint32_t ctx_id; 245 /** AMDGPU_CTX_PRIORITY_* */ 246 int32_t priority; 247 }; 248 249 union drm_amdgpu_ctx_out { 250 struct { 251 uint32_t ctx_id; 252 uint32_t _pad; 253 } alloc; 254 255 struct { 256 /** For future use, no flags defined so far */ 257 uint64_t flags; 258 /** Number of resets caused by this context so far. */ 259 uint32_t hangs; 260 /** Reset status since the last call of the ioctl. */ 261 uint32_t reset_status; 262 } state; 263 }; 264 265 union drm_amdgpu_ctx { 266 struct drm_amdgpu_ctx_in in; 267 union drm_amdgpu_ctx_out out; 268 }; 269 270 /* vm ioctl */ 271 #define AMDGPU_VM_OP_RESERVE_VMID 1 272 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 273 274 struct drm_amdgpu_vm_in { 275 /** AMDGPU_VM_OP_* */ 276 uint32_t op; 277 uint32_t flags; 278 }; 279 280 struct drm_amdgpu_vm_out { 281 /** For future use, no flags defined so far */ 282 uint64_t flags; 283 }; 284 285 union drm_amdgpu_vm { 286 struct drm_amdgpu_vm_in in; 287 struct drm_amdgpu_vm_out out; 288 }; 289 290 /* sched ioctl */ 291 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 292 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 293 294 struct drm_amdgpu_sched_in { 295 /* AMDGPU_SCHED_OP_* */ 296 uint32_t op; 297 uint32_t fd; 298 /** AMDGPU_CTX_PRIORITY_* */ 299 int32_t priority; 300 uint32_t ctx_id; 301 }; 302 303 union drm_amdgpu_sched { 304 struct drm_amdgpu_sched_in in; 305 }; 306 307 /* 308 * This is not a reliable API and you should expect it to fail for any 309 * number of reasons and have fallback path that do not use userptr to 310 * perform any operation. 311 */ 312 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 313 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 314 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 315 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 316 317 struct drm_amdgpu_gem_userptr { 318 uint64_t addr; 319 uint64_t size; 320 /* AMDGPU_GEM_USERPTR_* */ 321 uint32_t flags; 322 /* Resulting GEM handle */ 323 uint32_t handle; 324 }; 325 326 /* SI-CI-VI: */ 327 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 328 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 329 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 330 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 331 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 332 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 333 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 334 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 335 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 336 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 337 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 338 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 339 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 340 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 341 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 342 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 343 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 344 345 /* GFX9 and later: */ 346 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 347 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 348 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 349 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 350 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 351 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 352 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 353 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 354 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 355 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 356 #define AMDGPU_TILING_SCANOUT_SHIFT 63 357 #define AMDGPU_TILING_SCANOUT_MASK 0x1 358 359 /* Set/Get helpers for tiling flags. */ 360 #define AMDGPU_TILING_SET(field, value) \ 361 (((uint64_t)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 362 #define AMDGPU_TILING_GET(value, field) \ 363 (((uint64_t)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 364 365 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 366 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 367 368 /** The same structure is shared for input/output */ 369 struct drm_amdgpu_gem_metadata { 370 /** GEM Object handle */ 371 uint32_t handle; 372 /** Do we want get or set metadata */ 373 uint32_t op; 374 struct { 375 /** For future use, no flags defined so far */ 376 uint64_t flags; 377 /** family specific tiling info */ 378 uint64_t tiling_info; 379 uint32_t data_size_bytes; 380 uint32_t data[64]; 381 } data; 382 }; 383 384 struct drm_amdgpu_gem_mmap_in { 385 /** the GEM object handle */ 386 uint32_t handle; 387 uint32_t _pad; 388 }; 389 390 struct drm_amdgpu_gem_mmap_out { 391 /** mmap offset from the vma offset manager */ 392 uint64_t addr_ptr; 393 }; 394 395 union drm_amdgpu_gem_mmap { 396 struct drm_amdgpu_gem_mmap_in in; 397 struct drm_amdgpu_gem_mmap_out out; 398 }; 399 400 struct drm_amdgpu_gem_wait_idle_in { 401 /** GEM object handle */ 402 uint32_t handle; 403 /** For future use, no flags defined so far */ 404 uint32_t flags; 405 /** Absolute timeout to wait */ 406 uint64_t timeout; 407 }; 408 409 struct drm_amdgpu_gem_wait_idle_out { 410 /** BO status: 0 - BO is idle, 1 - BO is busy */ 411 uint32_t status; 412 /** Returned current memory domain */ 413 uint32_t domain; 414 }; 415 416 union drm_amdgpu_gem_wait_idle { 417 struct drm_amdgpu_gem_wait_idle_in in; 418 struct drm_amdgpu_gem_wait_idle_out out; 419 }; 420 421 struct drm_amdgpu_wait_cs_in { 422 /* Command submission handle 423 * handle equals 0 means none to wait for 424 * handle equals ~0ull means wait for the latest sequence number 425 */ 426 uint64_t handle; 427 /** Absolute timeout to wait */ 428 uint64_t timeout; 429 uint32_t ip_type; 430 uint32_t ip_instance; 431 uint32_t ring; 432 uint32_t ctx_id; 433 }; 434 435 struct drm_amdgpu_wait_cs_out { 436 /** CS status: 0 - CS completed, 1 - CS still busy */ 437 uint64_t status; 438 }; 439 440 union drm_amdgpu_wait_cs { 441 struct drm_amdgpu_wait_cs_in in; 442 struct drm_amdgpu_wait_cs_out out; 443 }; 444 445 struct drm_amdgpu_fence { 446 uint32_t ctx_id; 447 uint32_t ip_type; 448 uint32_t ip_instance; 449 uint32_t ring; 450 uint64_t seq_no; 451 }; 452 453 struct drm_amdgpu_wait_fences_in { 454 /** This points to uint64_t * which points to fences */ 455 uint64_t fences; 456 uint32_t fence_count; 457 uint32_t wait_all; 458 uint64_t timeout_ns; 459 }; 460 461 struct drm_amdgpu_wait_fences_out { 462 uint32_t status; 463 uint32_t first_signaled; 464 }; 465 466 union drm_amdgpu_wait_fences { 467 struct drm_amdgpu_wait_fences_in in; 468 struct drm_amdgpu_wait_fences_out out; 469 }; 470 471 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 472 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 473 474 /* Sets or returns a value associated with a buffer. */ 475 struct drm_amdgpu_gem_op { 476 /** GEM object handle */ 477 uint32_t handle; 478 /** AMDGPU_GEM_OP_* */ 479 uint32_t op; 480 /** Input or return value */ 481 uint64_t value; 482 }; 483 484 #define AMDGPU_VA_OP_MAP 1 485 #define AMDGPU_VA_OP_UNMAP 2 486 #define AMDGPU_VA_OP_CLEAR 3 487 #define AMDGPU_VA_OP_REPLACE 4 488 489 /* Delay the page table update till the next CS */ 490 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 491 492 /* Mapping flags */ 493 /* readable mapping */ 494 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 495 /* writable mapping */ 496 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 497 /* executable mapping, new for VI */ 498 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 499 /* partially resident texture */ 500 #define AMDGPU_VM_PAGE_PRT (1 << 4) 501 /* MTYPE flags use bit 5 to 8 */ 502 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 503 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 504 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 505 /* Use Non Coherent MTYPE instead of default MTYPE */ 506 #define AMDGPU_VM_MTYPE_NC (1 << 5) 507 /* Use Write Combine MTYPE instead of default MTYPE */ 508 #define AMDGPU_VM_MTYPE_WC (2 << 5) 509 /* Use Cache Coherent MTYPE instead of default MTYPE */ 510 #define AMDGPU_VM_MTYPE_CC (3 << 5) 511 /* Use UnCached MTYPE instead of default MTYPE */ 512 #define AMDGPU_VM_MTYPE_UC (4 << 5) 513 /* Use Read Write MTYPE instead of default MTYPE */ 514 #define AMDGPU_VM_MTYPE_RW (5 << 5) 515 516 struct drm_amdgpu_gem_va { 517 /** GEM object handle */ 518 uint32_t handle; 519 uint32_t _pad; 520 /** AMDGPU_VA_OP_* */ 521 uint32_t operation; 522 /** AMDGPU_VM_PAGE_* */ 523 uint32_t flags; 524 /** va address to assign . Must be correctly aligned.*/ 525 uint64_t va_address; 526 /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 527 uint64_t offset_in_bo; 528 /** Specify mapping size. Must be correctly aligned. */ 529 uint64_t map_size; 530 }; 531 532 #define AMDGPU_HW_IP_GFX 0 533 #define AMDGPU_HW_IP_COMPUTE 1 534 #define AMDGPU_HW_IP_DMA 2 535 #define AMDGPU_HW_IP_UVD 3 536 #define AMDGPU_HW_IP_VCE 4 537 #define AMDGPU_HW_IP_UVD_ENC 5 538 #define AMDGPU_HW_IP_VCN_DEC 6 539 #define AMDGPU_HW_IP_VCN_ENC 7 540 #define AMDGPU_HW_IP_VCN_JPEG 8 541 #define AMDGPU_HW_IP_NUM 9 542 543 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 544 545 #define AMDGPU_CHUNK_ID_IB 0x01 546 #define AMDGPU_CHUNK_ID_FENCE 0x02 547 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 548 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 549 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 550 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 551 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 552 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 553 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 554 555 struct drm_amdgpu_cs_chunk { 556 uint32_t chunk_id; 557 uint32_t length_dw; 558 uint64_t chunk_data; 559 }; 560 561 struct drm_amdgpu_cs_in { 562 /** Rendering context id */ 563 uint32_t ctx_id; 564 /** Handle of resource list associated with CS */ 565 uint32_t bo_list_handle; 566 uint32_t num_chunks; 567 uint32_t flags; 568 /** this points to uint64_t * which point to cs chunks */ 569 uint64_t chunks; 570 }; 571 572 struct drm_amdgpu_cs_out { 573 uint64_t handle; 574 }; 575 576 union drm_amdgpu_cs { 577 struct drm_amdgpu_cs_in in; 578 struct drm_amdgpu_cs_out out; 579 }; 580 581 /* Specify flags to be used for IB */ 582 583 /* This IB should be submitted to CE */ 584 #define AMDGPU_IB_FLAG_CE (1<<0) 585 586 /* Preamble flag, which means the IB could be dropped if no context switch */ 587 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 588 589 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 590 #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 591 592 /* The IB fence should do the L2 writeback but not invalidate any shader 593 * caches (L2/vL1/sL1/I$). */ 594 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 595 596 /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. 597 * This will reset wave ID counters for the IB. 598 */ 599 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 600 601 /* Flag the IB as secure (TMZ) 602 */ 603 #define AMDGPU_IB_FLAGS_SECURE (1 << 5) 604 605 /* Tell KMD to flush and invalidate caches 606 */ 607 #define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6) 608 609 struct drm_amdgpu_cs_chunk_ib { 610 uint32_t _pad; 611 /** AMDGPU_IB_FLAG_* */ 612 uint32_t flags; 613 /** Virtual address to begin IB execution */ 614 uint64_t va_start; 615 /** Size of submission */ 616 uint32_t ib_bytes; 617 /** HW IP to submit to */ 618 uint32_t ip_type; 619 /** HW IP index of the same type to submit to */ 620 uint32_t ip_instance; 621 /** Ring index to submit to */ 622 uint32_t ring; 623 }; 624 625 struct drm_amdgpu_cs_chunk_dep { 626 uint32_t ip_type; 627 uint32_t ip_instance; 628 uint32_t ring; 629 uint32_t ctx_id; 630 uint64_t handle; 631 }; 632 633 struct drm_amdgpu_cs_chunk_fence { 634 uint32_t handle; 635 uint32_t offset; 636 }; 637 638 struct drm_amdgpu_cs_chunk_sem { 639 uint32_t handle; 640 }; 641 642 struct drm_amdgpu_cs_chunk_syncobj { 643 uint32_t handle; 644 uint32_t flags; 645 uint64_t point; 646 }; 647 648 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 649 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 650 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 651 652 union drm_amdgpu_fence_to_handle { 653 struct { 654 struct drm_amdgpu_fence fence; 655 uint32_t what; 656 uint32_t pad; 657 } in; 658 struct { 659 uint32_t handle; 660 } out; 661 }; 662 663 struct drm_amdgpu_cs_chunk_data { 664 union { 665 struct drm_amdgpu_cs_chunk_ib ib_data; 666 struct drm_amdgpu_cs_chunk_fence fence_data; 667 }; 668 }; 669 670 /* 671 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 672 * 673 */ 674 #define AMDGPU_IDS_FLAGS_FUSION 0x1 675 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 676 #define AMDGPU_IDS_FLAGS_TMZ 0x4 677 678 /* indicate if acceleration can be working */ 679 #define AMDGPU_INFO_ACCEL_WORKING 0x00 680 /* get the crtc_id from the mode object id? */ 681 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 682 /* query hw IP info */ 683 #define AMDGPU_INFO_HW_IP_INFO 0x02 684 /* query hw IP instance count for the specified type */ 685 #define AMDGPU_INFO_HW_IP_COUNT 0x03 686 /* timestamp for GL_ARB_timer_query */ 687 #define AMDGPU_INFO_TIMESTAMP 0x05 688 /* Query the firmware version */ 689 #define AMDGPU_INFO_FW_VERSION 0x0e 690 /* Subquery id: Query VCE firmware version */ 691 #define AMDGPU_INFO_FW_VCE 0x1 692 /* Subquery id: Query UVD firmware version */ 693 #define AMDGPU_INFO_FW_UVD 0x2 694 /* Subquery id: Query GMC firmware version */ 695 #define AMDGPU_INFO_FW_GMC 0x03 696 /* Subquery id: Query GFX ME firmware version */ 697 #define AMDGPU_INFO_FW_GFX_ME 0x04 698 /* Subquery id: Query GFX PFP firmware version */ 699 #define AMDGPU_INFO_FW_GFX_PFP 0x05 700 /* Subquery id: Query GFX CE firmware version */ 701 #define AMDGPU_INFO_FW_GFX_CE 0x06 702 /* Subquery id: Query GFX RLC firmware version */ 703 #define AMDGPU_INFO_FW_GFX_RLC 0x07 704 /* Subquery id: Query GFX MEC firmware version */ 705 #define AMDGPU_INFO_FW_GFX_MEC 0x08 706 /* Subquery id: Query SMC firmware version */ 707 #define AMDGPU_INFO_FW_SMC 0x0a 708 /* Subquery id: Query SDMA firmware version */ 709 #define AMDGPU_INFO_FW_SDMA 0x0b 710 /* Subquery id: Query PSP SOS firmware version */ 711 #define AMDGPU_INFO_FW_SOS 0x0c 712 /* Subquery id: Query PSP ASD firmware version */ 713 #define AMDGPU_INFO_FW_ASD 0x0d 714 /* Subquery id: Query VCN firmware version */ 715 #define AMDGPU_INFO_FW_VCN 0x0e 716 /* Subquery id: Query GFX RLC SRLC firmware version */ 717 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 718 /* Subquery id: Query GFX RLC SRLG firmware version */ 719 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 720 /* Subquery id: Query GFX RLC SRLS firmware version */ 721 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 722 /* Subquery id: Query DMCU firmware version */ 723 #define AMDGPU_INFO_FW_DMCU 0x12 724 #define AMDGPU_INFO_FW_TA 0x13 725 /* Subquery id: Query DMCUB firmware version */ 726 #define AMDGPU_INFO_FW_DMCUB 0x14 727 /* Subquery id: Query TOC firmware version */ 728 #define AMDGPU_INFO_FW_TOC 0x15 729 730 /* number of bytes moved for TTM migration */ 731 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 732 /* the used VRAM size */ 733 #define AMDGPU_INFO_VRAM_USAGE 0x10 734 /* the used GTT size */ 735 #define AMDGPU_INFO_GTT_USAGE 0x11 736 /* Information about GDS, etc. resource configuration */ 737 #define AMDGPU_INFO_GDS_CONFIG 0x13 738 /* Query information about VRAM and GTT domains */ 739 #define AMDGPU_INFO_VRAM_GTT 0x14 740 /* Query information about register in MMR address space*/ 741 #define AMDGPU_INFO_READ_MMR_REG 0x15 742 /* Query information about device: rev id, family, etc. */ 743 #define AMDGPU_INFO_DEV_INFO 0x16 744 /* visible vram usage */ 745 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 746 /* number of TTM buffer evictions */ 747 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 748 /* Query memory about VRAM and GTT domains */ 749 #define AMDGPU_INFO_MEMORY 0x19 750 /* Query vce clock table */ 751 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 752 /* Query vbios related information */ 753 #define AMDGPU_INFO_VBIOS 0x1B 754 /* Subquery id: Query vbios size */ 755 #define AMDGPU_INFO_VBIOS_SIZE 0x1 756 /* Subquery id: Query vbios image */ 757 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 758 /* Query UVD handles */ 759 #define AMDGPU_INFO_NUM_HANDLES 0x1C 760 /* Query sensor related information */ 761 #define AMDGPU_INFO_SENSOR 0x1D 762 /* Subquery id: Query GPU shader clock */ 763 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 764 /* Subquery id: Query GPU memory clock */ 765 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 766 /* Subquery id: Query GPU temperature */ 767 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 768 /* Subquery id: Query GPU load */ 769 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 770 /* Subquery id: Query average GPU power */ 771 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 772 /* Subquery id: Query northbridge voltage */ 773 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 774 /* Subquery id: Query graphics voltage */ 775 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 776 /* Subquery id: Query GPU stable pstate shader clock */ 777 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 778 /* Subquery id: Query GPU stable pstate memory clock */ 779 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 780 /* Number of VRAM page faults on CPU access. */ 781 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 782 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 783 /* query ras mask of enabled features*/ 784 #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 785 /* query video encode/decode caps */ 786 #define AMDGPU_INFO_VIDEO_CAPS 0x21 787 /* Subquery id: Decode */ 788 #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 789 /* Subquery id: Encode */ 790 #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 791 792 /* RAS MASK: UMC (VRAM) */ 793 #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 794 /* RAS MASK: SDMA */ 795 #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 796 /* RAS MASK: GFX */ 797 #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 798 /* RAS MASK: MMHUB */ 799 #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 800 /* RAS MASK: ATHUB */ 801 #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 802 /* RAS MASK: PCIE */ 803 #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 804 /* RAS MASK: HDP */ 805 #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 806 /* RAS MASK: XGMI */ 807 #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 808 /* RAS MASK: DF */ 809 #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 810 /* RAS MASK: SMN */ 811 #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 812 /* RAS MASK: SEM */ 813 #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 814 /* RAS MASK: MP0 */ 815 #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 816 /* RAS MASK: MP1 */ 817 #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 818 /* RAS MASK: FUSE */ 819 #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 820 821 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 822 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 823 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 824 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 825 826 struct drm_amdgpu_query_fw { 827 /** AMDGPU_INFO_FW_* */ 828 uint32_t fw_type; 829 /** 830 * Index of the IP if there are more IPs of 831 * the same type. 832 */ 833 uint32_t ip_instance; 834 /** 835 * Index of the engine. Whether this is used depends 836 * on the firmware type. (e.g. MEC, SDMA) 837 */ 838 uint32_t index; 839 uint32_t _pad; 840 }; 841 842 /* Input structure for the INFO ioctl */ 843 struct drm_amdgpu_info { 844 /* Where the return value will be stored */ 845 uint64_t return_pointer; 846 /* The size of the return value. Just like "size" in "snprintf", 847 * it limits how many bytes the kernel can write. */ 848 uint32_t return_size; 849 /* The query request id. */ 850 uint32_t query; 851 852 union { 853 struct { 854 uint32_t id; 855 uint32_t _pad; 856 } mode_crtc; 857 858 struct { 859 /** AMDGPU_HW_IP_* */ 860 uint32_t type; 861 /** 862 * Index of the IP if there are more IPs of the same 863 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 864 */ 865 uint32_t ip_instance; 866 } query_hw_ip; 867 868 struct { 869 uint32_t dword_offset; 870 /** number of registers to read */ 871 uint32_t count; 872 uint32_t instance; 873 /** For future use, no flags defined so far */ 874 uint32_t flags; 875 } read_mmr_reg; 876 877 struct drm_amdgpu_query_fw query_fw; 878 879 struct { 880 uint32_t type; 881 uint32_t offset; 882 } vbios_info; 883 884 struct { 885 uint32_t type; 886 } sensor_info; 887 888 struct { 889 uint32_t type; 890 } video_cap; 891 }; 892 }; 893 894 struct drm_amdgpu_info_gds { 895 /** GDS GFX partition size */ 896 uint32_t gds_gfx_partition_size; 897 /** GDS compute partition size */ 898 uint32_t compute_partition_size; 899 /** total GDS memory size */ 900 uint32_t gds_total_size; 901 /** GWS size per GFX partition */ 902 uint32_t gws_per_gfx_partition; 903 /** GSW size per compute partition */ 904 uint32_t gws_per_compute_partition; 905 /** OA size per GFX partition */ 906 uint32_t oa_per_gfx_partition; 907 /** OA size per compute partition */ 908 uint32_t oa_per_compute_partition; 909 uint32_t _pad; 910 }; 911 912 struct drm_amdgpu_info_vram_gtt { 913 uint64_t vram_size; 914 uint64_t vram_cpu_accessible_size; 915 uint64_t gtt_size; 916 }; 917 918 struct drm_amdgpu_heap_info { 919 /** max. physical memory */ 920 uint64_t total_heap_size; 921 922 /** Theoretical max. available memory in the given heap */ 923 uint64_t usable_heap_size; 924 925 /** 926 * Number of bytes allocated in the heap. This includes all processes 927 * and private allocations in the kernel. It changes when new buffers 928 * are allocated, freed, and moved. It cannot be larger than 929 * heap_size. 930 */ 931 uint64_t heap_usage; 932 933 /** 934 * Theoretical possible max. size of buffer which 935 * could be allocated in the given heap 936 */ 937 uint64_t max_allocation; 938 }; 939 940 struct drm_amdgpu_memory_info { 941 struct drm_amdgpu_heap_info vram; 942 struct drm_amdgpu_heap_info cpu_accessible_vram; 943 struct drm_amdgpu_heap_info gtt; 944 }; 945 946 struct drm_amdgpu_info_firmware { 947 uint32_t ver; 948 uint32_t feature; 949 }; 950 951 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 952 #define AMDGPU_VRAM_TYPE_GDDR1 1 953 #define AMDGPU_VRAM_TYPE_DDR2 2 954 #define AMDGPU_VRAM_TYPE_GDDR3 3 955 #define AMDGPU_VRAM_TYPE_GDDR4 4 956 #define AMDGPU_VRAM_TYPE_GDDR5 5 957 #define AMDGPU_VRAM_TYPE_HBM 6 958 #define AMDGPU_VRAM_TYPE_DDR3 7 959 #define AMDGPU_VRAM_TYPE_DDR4 8 960 #define AMDGPU_VRAM_TYPE_GDDR6 9 961 #define AMDGPU_VRAM_TYPE_DDR5 10 962 963 struct drm_amdgpu_info_device { 964 /** PCI Device ID */ 965 uint32_t device_id; 966 /** Internal chip revision: A0, A1, etc.) */ 967 uint32_t chip_rev; 968 uint32_t external_rev; 969 /** Revision id in PCI Config space */ 970 uint32_t pci_rev; 971 uint32_t family; 972 uint32_t num_shader_engines; 973 uint32_t num_shader_arrays_per_engine; 974 /* in KHz */ 975 uint32_t gpu_counter_freq; 976 uint64_t max_engine_clock; 977 uint64_t max_memory_clock; 978 /* cu information */ 979 uint32_t cu_active_number; 980 /* NOTE: cu_ao_mask is INVALID, DON'T use it */ 981 uint32_t cu_ao_mask; 982 uint32_t cu_bitmap[4][4]; 983 /** Render backend pipe mask. One render backend is CB+DB. */ 984 uint32_t enabled_rb_pipes_mask; 985 uint32_t num_rb_pipes; 986 uint32_t num_hw_gfx_contexts; 987 uint32_t _pad; 988 uint64_t ids_flags; 989 /** Starting virtual address for UMDs. */ 990 uint64_t virtual_address_offset; 991 /** The maximum virtual address */ 992 uint64_t virtual_address_max; 993 /** Required alignment of virtual addresses. */ 994 uint32_t virtual_address_alignment; 995 /** Page table entry - fragment size */ 996 uint32_t pte_fragment_size; 997 uint32_t gart_page_size; 998 /** constant engine ram size*/ 999 uint32_t ce_ram_size; 1000 /** video memory type info*/ 1001 uint32_t vram_type; 1002 /** video memory bit width*/ 1003 uint32_t vram_bit_width; 1004 /* vce harvesting instance */ 1005 uint32_t vce_harvest_config; 1006 /* gfx double offchip LDS buffers */ 1007 uint32_t gc_double_offchip_lds_buf; 1008 /* NGG Primitive Buffer */ 1009 uint64_t prim_buf_gpu_addr; 1010 /* NGG Position Buffer */ 1011 uint64_t pos_buf_gpu_addr; 1012 /* NGG Control Sideband */ 1013 uint64_t cntl_sb_buf_gpu_addr; 1014 /* NGG Parameter Cache */ 1015 uint64_t param_buf_gpu_addr; 1016 uint32_t prim_buf_size; 1017 uint32_t pos_buf_size; 1018 uint32_t cntl_sb_buf_size; 1019 uint32_t param_buf_size; 1020 /* wavefront size*/ 1021 uint32_t wave_front_size; 1022 /* shader visible vgprs*/ 1023 uint32_t num_shader_visible_vgprs; 1024 /* CU per shader array*/ 1025 uint32_t num_cu_per_sh; 1026 /* number of tcc blocks*/ 1027 uint32_t num_tcc_blocks; 1028 /* gs vgt table depth*/ 1029 uint32_t gs_vgt_table_depth; 1030 /* gs primitive buffer depth*/ 1031 uint32_t gs_prim_buffer_depth; 1032 /* max gs wavefront per vgt*/ 1033 uint32_t max_gs_waves_per_vgt; 1034 uint32_t _pad1; 1035 /* always on cu bitmap */ 1036 uint32_t cu_ao_bitmap[4][4]; 1037 /** Starting high virtual address for UMDs. */ 1038 uint64_t high_va_offset; 1039 /** The maximum high virtual address */ 1040 uint64_t high_va_max; 1041 /* gfx10 pa_sc_tile_steering_override */ 1042 uint32_t pa_sc_tile_steering_override; 1043 /* disabled TCCs */ 1044 uint64_t tcc_disabled_mask; 1045 }; 1046 1047 struct drm_amdgpu_info_hw_ip { 1048 /** Version of h/w IP */ 1049 uint32_t hw_ip_version_major; 1050 uint32_t hw_ip_version_minor; 1051 /** Capabilities */ 1052 uint64_t capabilities_flags; 1053 /** command buffer address start alignment*/ 1054 uint32_t ib_start_alignment; 1055 /** command buffer size alignment*/ 1056 uint32_t ib_size_alignment; 1057 /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 1058 uint32_t available_rings; 1059 uint32_t _pad; 1060 }; 1061 1062 struct drm_amdgpu_info_num_handles { 1063 /** Max handles as supported by firmware for UVD */ 1064 uint32_t uvd_max_handles; 1065 /** Handles currently in use for UVD */ 1066 uint32_t uvd_used_handles; 1067 }; 1068 1069 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 1070 1071 struct drm_amdgpu_info_vce_clock_table_entry { 1072 /** System clock */ 1073 uint32_t sclk; 1074 /** Memory clock */ 1075 uint32_t mclk; 1076 /** VCE clock */ 1077 uint32_t eclk; 1078 uint32_t pad; 1079 }; 1080 1081 struct drm_amdgpu_info_vce_clock_table { 1082 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 1083 uint32_t num_valid_entries; 1084 uint32_t pad; 1085 }; 1086 1087 /* query video encode/decode caps */ 1088 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 1089 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 1090 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 1091 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 1092 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 1093 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 1094 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 1095 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 1096 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 1097 1098 struct drm_amdgpu_info_video_codec_info { 1099 uint32_t valid; 1100 uint32_t max_width; 1101 uint32_t max_height; 1102 uint32_t max_pixels_per_frame; 1103 uint32_t max_level; 1104 uint32_t pad; 1105 }; 1106 1107 struct drm_amdgpu_info_video_caps { 1108 struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; 1109 }; 1110 1111 /* 1112 * Supported GPU families 1113 */ 1114 #define AMDGPU_FAMILY_UNKNOWN 0 1115 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 1116 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 1117 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 1118 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 1119 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 1120 #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 1121 #define AMDGPU_FAMILY_RV 142 /* Raven */ 1122 #define AMDGPU_FAMILY_NV 143 /* Navi10 */ 1123 #define AMDGPU_FAMILY_VGH 144 /* Van Gogh */ 1124 1125 #if defined(__cplusplus) 1126 } 1127 #endif 1128 1129 #endif 1130