1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6#include "dra74x.dtsi" 7 8/ { 9 compatible = "ti,dra762", "ti,dra7"; 10 11 ocp { 12 emif1: emif@4c000000 { 13 compatible = "ti,emif-dra7xx"; 14 reg = <0x4c000000 0x200>; 15 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 16 status = "disabled"; 17 }; 18 19 target-module@42c01900 { 20 compatible = "ti,sysc-dra7-mcan", "ti,sysc"; 21 ranges = <0x0 0x42c00000 0x2000>; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 reg = <0x42c01900 0x4>, 25 <0x42c01904 0x4>, 26 <0x42c01908 0x4>; 27 reg-names = "rev", "sysc", "syss"; 28 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET | 29 SYSC_DRA7_MCAN_ENAWAKEUP)>; 30 ti,syss-mask = <1>; 31 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_ADC_CLKCTRL 0>; 32 clock-names = "fck"; 33 34 m_can0: mcan@1a00 { 35 compatible = "bosch,m_can"; 36 reg = <0x1a00 0x4000>, <0x0 0x18FC>; 37 reg-names = "m_can", "message_ram"; 38 interrupt-parent = <&gic>; 39 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 41 interrupt-names = "int0", "int1"; 42 clocks = <&l3_iclk_div>, <&mcan_clk>; 43 clock-names = "hclk", "cclk"; 44 bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>; 45 }; 46 }; 47 }; 48 49}; 50 51&l4_per3 { 52 target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */ 53 compatible = "ti,sysc-omap4", "ti,sysc"; 54 reg = <0x1b0000 0x4>, 55 <0x1b0010 0x4>; 56 reg-names = "rev", "sysc"; 57 ti,sysc-midle = <SYSC_IDLE_FORCE>, 58 <SYSC_IDLE_NO>; 59 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 60 <SYSC_IDLE_NO>; 61 clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>; 62 clock-names = "fck"; 63 #address-cells = <1>; 64 #size-cells = <1>; 65 ranges = <0x0 0x1b0000 0x10000>; 66 67 cal: cal@0 { 68 compatible = "ti,dra76-cal"; 69 reg = <0x0000 0x400>, 70 <0x0800 0x40>, 71 <0x0900 0x40>; 72 reg-names = "cal_top", 73 "cal_rx_core0", 74 "cal_rx_core1"; 75 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 76 ti,camerrx-control = <&scm_conf 0x6dc>; 77 78 ports { 79 #address-cells = <1>; 80 #size-cells = <0>; 81 82 csi2_0: port@0 { 83 reg = <0>; 84 }; 85 csi2_1: port@1 { 86 reg = <1>; 87 }; 88 }; 89 }; 90 }; 91}; 92 93/* MCAN interrupts are hard-wired to irqs 67, 68 */ 94&crossbar_mpu { 95 ti,irqs-skip = <10 67 68 133 139 140>; 96}; 97 98&scm_conf_clocks { 99 dpll_gmac_h14x2_ctrl_ck: dpll_gmac_h14x2_ctrl_ck@3fc { 100 #clock-cells = <0>; 101 compatible = "ti,divider-clock"; 102 clocks = <&dpll_gmac_x2_ck>; 103 ti,max-div = <63>; 104 reg = <0x03fc>; 105 ti,bit-shift=<20>; 106 ti,latch-bit=<26>; 107 assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>; 108 assigned-clock-rates = <80000000>; 109 }; 110 111 dpll_gmac_h14x2_ctrl_mux_ck: dpll_gmac_h14x2_ctrl_mux_ck@3fc { 112 #clock-cells = <0>; 113 compatible = "ti,mux-clock"; 114 clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>; 115 reg = <0x3fc>; 116 ti,bit-shift = <29>; 117 ti,latch-bit=<26>; 118 assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>; 119 assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>; 120 }; 121 122 mcan_clk: mcan_clk@3fc { 123 #clock-cells = <0>; 124 compatible = "ti,gate-clock"; 125 clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>; 126 ti,bit-shift = <27>; 127 reg = <0x3fc>; 128 }; 129}; 130 131&rtctarget { 132 status = "disabled"; 133}; 134 135&usb4_tm { 136 status = "disabled"; 137}; 138 139&mmc3 { 140 /* dra76x is not affected by i887 */ 141 max-frequency = <96000000>; 142}; 143 144&cpu0_opp_table { 145 opp_plus@1800000000 { 146 opp-hz = /bits/ 64 <1800000000>; 147 opp-microvolt = <1250000 950000 1250000>, 148 <1250000 950000 1250000>; 149 opp-supported-hw = <0xFF 0x08>; 150 }; 151}; 152 153&opp_supply_mpu { 154 ti,efuse-settings = < 155 /* uV offset */ 156 1060000 0x0 157 1160000 0x4 158 1210000 0x8 159 1250000 0xC 160 >; 161}; 162 163&abb_mpu { 164 ti,abb_info = < 165 /*uV ABB efuse rbb_m fbb_m vset_m*/ 166 1060000 0 0x0 0 0x02000000 0x01F00000 167 1160000 0 0x4 0 0x02000000 0x01F00000 168 1210000 0 0x8 0 0x02000000 0x01F00000 169 1250000 0 0xC 0 0x02000000 0x01F00000 170 >; 171}; 172