1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/interrupt-controller/irq.h>
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/clock/qcom,gcc-msm8660.h>
7#include <dt-bindings/soc/qcom,gsbi.h>
8
9/ {
10	#address-cells = <1>;
11	#size-cells = <1>;
12	model = "Qualcomm MSM8660";
13	compatible = "qcom,msm8660";
14	interrupt-parent = <&intc>;
15
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19
20		cpu@0 {
21			compatible = "qcom,scorpion";
22			enable-method = "qcom,gcc-msm8660";
23			device_type = "cpu";
24			reg = <0>;
25			next-level-cache = <&L2>;
26		};
27
28		cpu@1 {
29			compatible = "qcom,scorpion";
30			enable-method = "qcom,gcc-msm8660";
31			device_type = "cpu";
32			reg = <1>;
33			next-level-cache = <&L2>;
34		};
35
36		L2: l2-cache {
37			compatible = "cache";
38			cache-level = <2>;
39		};
40	};
41
42	memory {
43		device_type = "memory";
44		reg = <0x0 0x0>;
45	};
46
47	cpu-pmu {
48		compatible = "qcom,scorpion-mp-pmu";
49		interrupts = <1 9 0x304>;
50	};
51
52	clocks {
53		cxo_board {
54			compatible = "fixed-clock";
55			#clock-cells = <0>;
56			clock-frequency = <19200000>;
57		};
58
59		pxo_board {
60			compatible = "fixed-clock";
61			#clock-cells = <0>;
62			clock-frequency = <27000000>;
63		};
64
65		sleep_clk {
66			compatible = "fixed-clock";
67			#clock-cells = <0>;
68			clock-frequency = <32768>;
69		};
70	};
71
72	/*
73	 * These channels from the ADC are simply hardware monitors.
74	 * That is why the ADC is referred to as "HKADC" - HouseKeeping
75	 * ADC.
76	 */
77	iio-hwmon {
78		compatible = "iio-hwmon";
79		io-channels = <&xoadc 0x00 0x01>, /* Battery */
80			    <&xoadc 0x00 0x02>, /* DC in (charger) */
81			    <&xoadc 0x00 0x04>, /* VPH the main system voltage */
82			    <&xoadc 0x00 0x0b>, /* Die temperature */
83			    <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
84			    <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
85			    <&xoadc 0x00 0x0e>; /* Reference voltage 0.325V */
86	};
87
88	soc: soc {
89		#address-cells = <1>;
90		#size-cells = <1>;
91		ranges;
92		compatible = "simple-bus";
93
94		intc: interrupt-controller@2080000 {
95			compatible = "qcom,msm-8660-qgic";
96			interrupt-controller;
97			#interrupt-cells = <3>;
98			reg = < 0x02080000 0x1000 >,
99			      < 0x02081000 0x1000 >;
100		};
101
102		timer@2000000 {
103			compatible = "qcom,scss-timer", "qcom,msm-timer";
104			interrupts = <1 0 0x301>,
105				     <1 1 0x301>,
106				     <1 2 0x301>;
107			reg = <0x02000000 0x100>;
108			clock-frequency = <27000000>,
109					  <32768>;
110			cpu-offset = <0x40000>;
111		};
112
113		tlmm: pinctrl@800000 {
114			compatible = "qcom,msm8660-pinctrl";
115			reg = <0x800000 0x4000>;
116
117			gpio-controller;
118			gpio-ranges = <&tlmm 0 0 173>;
119			#gpio-cells = <2>;
120			interrupts = <0 16 0x4>;
121			interrupt-controller;
122			#interrupt-cells = <2>;
123
124		};
125
126		gcc: clock-controller@900000 {
127			compatible = "qcom,gcc-msm8660";
128			#clock-cells = <1>;
129			#reset-cells = <1>;
130			reg = <0x900000 0x4000>;
131		};
132
133		gsbi6: gsbi@16500000 {
134			compatible = "qcom,gsbi-v1.0.0";
135			cell-index = <12>;
136			reg = <0x16500000 0x100>;
137			clocks = <&gcc GSBI6_H_CLK>;
138			clock-names = "iface";
139			#address-cells = <1>;
140			#size-cells = <1>;
141			ranges;
142			status = "disabled";
143
144			syscon-tcsr = <&tcsr>;
145
146			gsbi6_serial: serial@16540000 {
147				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
148				reg = <0x16540000 0x1000>,
149				      <0x16500000 0x1000>;
150				interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
151				clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
152				clock-names = "core", "iface";
153				status = "disabled";
154			};
155
156			gsbi6_i2c: i2c@16580000 {
157				compatible = "qcom,i2c-qup-v1.1.1";
158				reg = <0x16580000 0x1000>;
159				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
160				clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
161				clock-names = "core", "iface";
162				#address-cells = <1>;
163				#size-cells = <0>;
164				status = "disabled";
165			};
166		};
167
168		gsbi7: gsbi@16600000 {
169			compatible = "qcom,gsbi-v1.0.0";
170			cell-index = <12>;
171			reg = <0x16600000 0x100>;
172			clocks = <&gcc GSBI7_H_CLK>;
173			clock-names = "iface";
174			#address-cells = <1>;
175			#size-cells = <1>;
176			ranges;
177			status = "disabled";
178
179			syscon-tcsr = <&tcsr>;
180
181			gsbi7_serial: serial@16640000 {
182				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
183				reg = <0x16640000 0x1000>,
184				      <0x16600000 0x1000>;
185				interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
186				clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
187				clock-names = "core", "iface";
188				status = "disabled";
189			};
190
191			gsbi7_i2c: i2c@16680000 {
192				compatible = "qcom,i2c-qup-v1.1.1";
193				reg = <0x16680000 0x1000>;
194				interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
195				clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
196				clock-names = "core", "iface";
197				#address-cells = <1>;
198				#size-cells = <0>;
199				status = "disabled";
200			};
201		};
202
203		gsbi8: gsbi@19800000 {
204			compatible = "qcom,gsbi-v1.0.0";
205			cell-index = <12>;
206			reg = <0x19800000 0x100>;
207			clocks = <&gcc GSBI8_H_CLK>;
208			clock-names = "iface";
209			#address-cells = <1>;
210			#size-cells = <1>;
211			ranges;
212
213			syscon-tcsr = <&tcsr>;
214
215			gsbi8_i2c: i2c@19880000 {
216				compatible = "qcom,i2c-qup-v1.1.1";
217				reg = <0x19880000 0x1000>;
218				interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
219				clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>;
220				clock-names = "core", "iface";
221				#address-cells = <1>;
222				#size-cells = <0>;
223				status = "disabled";
224			};
225		};
226
227		gsbi12: gsbi@19c00000 {
228			compatible = "qcom,gsbi-v1.0.0";
229			cell-index = <12>;
230			reg = <0x19c00000 0x100>;
231			clocks = <&gcc GSBI12_H_CLK>;
232			clock-names = "iface";
233			#address-cells = <1>;
234			#size-cells = <1>;
235			ranges;
236
237			syscon-tcsr = <&tcsr>;
238
239			gsbi12_serial: serial@19c40000 {
240				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
241				reg = <0x19c40000 0x1000>,
242				      <0x19c00000 0x1000>;
243				interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>;
244				clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
245				clock-names = "core", "iface";
246				status = "disabled";
247			};
248
249			gsbi12_i2c: i2c@19c80000 {
250				compatible = "qcom,i2c-qup-v1.1.1";
251				reg = <0x19c80000 0x1000>;
252				interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
253				clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
254				clock-names = "core", "iface";
255				#address-cells = <1>;
256				#size-cells = <0>;
257				status = "disabled";
258			};
259		};
260
261		external-bus@1a100000 {
262			compatible = "qcom,msm8660-ebi2";
263			#address-cells = <2>;
264			#size-cells = <1>;
265			ranges = <0 0x0 0x1a800000 0x00800000>,
266				 <1 0x0 0x1b000000 0x00800000>,
267				 <2 0x0 0x1b800000 0x00800000>,
268				 <3 0x0 0x1d000000 0x08000000>,
269				 <4 0x0 0x1c800000 0x00800000>,
270				 <5 0x0 0x1c000000 0x00800000>;
271			reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
272			reg-names = "ebi2", "xmem";
273			clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
274			clock-names = "ebi2x", "ebi2";
275			status = "disabled";
276		};
277
278		qcom,ssbi@500000 {
279			compatible = "qcom,ssbi";
280			reg = <0x500000 0x1000>;
281			qcom,controller-type = "pmic-arbiter";
282
283			pm8058: pmic@0 {
284				compatible = "qcom,pm8058";
285				interrupt-parent = <&tlmm>;
286				interrupts = <88 8>;
287				#interrupt-cells = <2>;
288				interrupt-controller;
289				#address-cells = <1>;
290				#size-cells = <0>;
291
292				pm8058_gpio: gpio@150 {
293					compatible = "qcom,pm8058-gpio",
294						     "qcom,ssbi-gpio";
295					reg = <0x150>;
296					interrupt-controller;
297					#interrupt-cells = <2>;
298					gpio-controller;
299					gpio-ranges = <&pm8058_gpio 0 0 44>;
300					#gpio-cells = <2>;
301
302				};
303
304				pm8058_mpps: mpps@50 {
305					compatible = "qcom,pm8058-mpp",
306						     "qcom,ssbi-mpp";
307					reg = <0x50>;
308					gpio-controller;
309					#gpio-cells = <2>;
310					interrupt-parent = <&pm8058>;
311					interrupts =
312					<128 IRQ_TYPE_NONE>,
313					<129 IRQ_TYPE_NONE>,
314					<130 IRQ_TYPE_NONE>,
315					<131 IRQ_TYPE_NONE>,
316					<132 IRQ_TYPE_NONE>,
317					<133 IRQ_TYPE_NONE>,
318					<134 IRQ_TYPE_NONE>,
319					<135 IRQ_TYPE_NONE>,
320					<136 IRQ_TYPE_NONE>,
321					<137 IRQ_TYPE_NONE>,
322					<138 IRQ_TYPE_NONE>,
323					<139 IRQ_TYPE_NONE>;
324				};
325
326				pwrkey@1c {
327					compatible = "qcom,pm8058-pwrkey";
328					reg = <0x1c>;
329					interrupt-parent = <&pm8058>;
330					interrupts = <50 1>, <51 1>;
331					debounce = <15625>;
332					pull-up;
333				};
334
335				keypad@148 {
336					compatible = "qcom,pm8058-keypad";
337					reg = <0x148>;
338					interrupt-parent = <&pm8058>;
339					interrupts = <74 1>, <75 1>;
340					debounce = <15>;
341					scan-delay = <32>;
342					row-hold = <91500>;
343				};
344
345				xoadc: xoadc@197 {
346					compatible = "qcom,pm8058-adc";
347					reg = <0x197>;
348					interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>;
349					#address-cells = <2>;
350					#size-cells = <0>;
351					#io-channel-cells = <2>;
352
353					vcoin: adc-channel@0 {
354						reg = <0x00 0x00>;
355					};
356					vbat: adc-channel@1 {
357						reg = <0x00 0x01>;
358					};
359					dcin: adc-channel@2 {
360						reg = <0x00 0x02>;
361					};
362					ichg: adc-channel@3 {
363						reg = <0x00 0x03>;
364					};
365					vph_pwr: adc-channel@4 {
366						reg = <0x00 0x04>;
367					};
368					usb_vbus: adc-channel@a {
369						reg = <0x00 0x0a>;
370					};
371					die_temp: adc-channel@b {
372						reg = <0x00 0x0b>;
373					};
374					ref_625mv: adc-channel@c {
375						reg = <0x00 0x0c>;
376					};
377					ref_1250mv: adc-channel@d {
378						reg = <0x00 0x0d>;
379					};
380					ref_325mv: adc-channel@e {
381						reg = <0x00 0x0e>;
382					};
383					ref_muxoff: adc-channel@f {
384						reg = <0x00 0x0f>;
385					};
386				};
387
388				rtc@1e8 {
389					compatible = "qcom,pm8058-rtc";
390					reg = <0x1e8>;
391					interrupt-parent = <&pm8058>;
392					interrupts = <39 1>;
393					allow-set-time;
394				};
395
396				vibrator@4a {
397					compatible = "qcom,pm8058-vib";
398					reg = <0x4a>;
399				};
400			};
401		};
402
403		l2cc: clock-controller@2082000 {
404			compatible	= "syscon";
405			reg		= <0x02082000 0x1000>;
406		};
407
408		rpm: rpm@104000 {
409			compatible	= "qcom,rpm-msm8660";
410			reg		= <0x00104000 0x1000>;
411			qcom,ipc	= <&l2cc 0x8 2>;
412
413			interrupts	= <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
414					  <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
415					  <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
416			interrupt-names	= "ack", "err", "wakeup";
417			clocks = <&gcc RPM_MSG_RAM_H_CLK>;
418			clock-names = "ram";
419
420			rpmcc: clock-controller {
421				compatible	= "qcom,rpmcc-msm8660", "qcom,rpmcc";
422				#clock-cells = <1>;
423			};
424
425			pm8901-regulators {
426				compatible = "qcom,rpm-pm8901-regulators";
427
428				pm8901_l0: l0 {};
429				pm8901_l1: l1 {};
430				pm8901_l2: l2 {};
431				pm8901_l3: l3 {};
432				pm8901_l4: l4 {};
433				pm8901_l5: l5 {};
434				pm8901_l6: l6 {};
435
436				/* S0 and S1 Handled as SAW regulators by SPM */
437				pm8901_s2: s2 {};
438				pm8901_s3: s3 {};
439				pm8901_s4: s4 {};
440
441				pm8901_lvs0: lvs0 {};
442				pm8901_lvs1: lvs1 {};
443				pm8901_lvs2: lvs2 {};
444				pm8901_lvs3: lvs3 {};
445
446				pm8901_mvs: mvs {};
447			};
448
449			pm8058-regulators {
450				compatible = "qcom,rpm-pm8058-regulators";
451
452				pm8058_l0: l0 {};
453				pm8058_l1: l1 {};
454				pm8058_l2: l2 {};
455				pm8058_l3: l3 {};
456				pm8058_l4: l4 {};
457				pm8058_l5: l5 {};
458				pm8058_l6: l6 {};
459				pm8058_l7: l7 {};
460				pm8058_l8: l8 {};
461				pm8058_l9: l9 {};
462				pm8058_l10: l10 {};
463				pm8058_l11: l11 {};
464				pm8058_l12: l12 {};
465				pm8058_l13: l13 {};
466				pm8058_l14: l14 {};
467				pm8058_l15: l15 {};
468				pm8058_l16: l16 {};
469				pm8058_l17: l17 {};
470				pm8058_l18: l18 {};
471				pm8058_l19: l19 {};
472				pm8058_l20: l20 {};
473				pm8058_l21: l21 {};
474				pm8058_l22: l22 {};
475				pm8058_l23: l23 {};
476				pm8058_l24: l24 {};
477				pm8058_l25: l25 {};
478
479				pm8058_s0: s0 {};
480				pm8058_s1: s1 {};
481				pm8058_s2: s2 {};
482				pm8058_s3: s3 {};
483				pm8058_s4: s4 {};
484
485				pm8058_lvs0: lvs0 {};
486				pm8058_lvs1: lvs1 {};
487
488				pm8058_ncp: ncp {};
489			};
490		};
491
492		amba {
493			compatible = "simple-bus";
494			#address-cells = <1>;
495			#size-cells = <1>;
496			ranges;
497			sdcc1: sdcc@12400000 {
498				status		= "disabled";
499				compatible	= "arm,pl18x", "arm,primecell";
500				arm,primecell-periphid = <0x00051180>;
501				reg		= <0x12400000 0x8000>;
502				interrupts	= <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
503				interrupt-names	= "cmd_irq";
504				clocks		= <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
505				clock-names	= "mclk", "apb_pclk";
506				bus-width	= <8>;
507				max-frequency	= <48000000>;
508				non-removable;
509				cap-sd-highspeed;
510				cap-mmc-highspeed;
511			};
512
513			sdcc2: sdcc@12140000 {
514				status		= "disabled";
515				compatible	= "arm,pl18x", "arm,primecell";
516				arm,primecell-periphid = <0x00051180>;
517				reg		= <0x12140000 0x8000>;
518				interrupts	= <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
519				interrupt-names	= "cmd_irq";
520				clocks		= <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
521				clock-names	= "mclk", "apb_pclk";
522				bus-width	= <8>;
523				max-frequency	= <48000000>;
524				cap-sd-highspeed;
525				cap-mmc-highspeed;
526			};
527
528			sdcc3: sdcc@12180000 {
529				compatible	= "arm,pl18x", "arm,primecell";
530				arm,primecell-periphid = <0x00051180>;
531				status		= "disabled";
532				reg		= <0x12180000 0x8000>;
533				interrupts	= <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
534				interrupt-names	= "cmd_irq";
535				clocks		= <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
536				clock-names	= "mclk", "apb_pclk";
537				bus-width	= <4>;
538				cap-sd-highspeed;
539				cap-mmc-highspeed;
540				max-frequency	= <48000000>;
541				no-1-8-v;
542			};
543
544			sdcc4: sdcc@121c0000 {
545				compatible	= "arm,pl18x", "arm,primecell";
546				arm,primecell-periphid = <0x00051180>;
547				status		= "disabled";
548				reg		= <0x121c0000 0x8000>;
549				interrupts	= <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
550				interrupt-names	= "cmd_irq";
551				clocks		= <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
552				clock-names	= "mclk", "apb_pclk";
553				bus-width	= <4>;
554				max-frequency	= <48000000>;
555				cap-sd-highspeed;
556				cap-mmc-highspeed;
557			};
558
559			sdcc5: sdcc@12200000 {
560				compatible	= "arm,pl18x", "arm,primecell";
561				arm,primecell-periphid = <0x00051180>;
562				status		= "disabled";
563				reg		= <0x12200000 0x8000>;
564				interrupts	= <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
565				interrupt-names	= "cmd_irq";
566				clocks		= <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
567				clock-names	= "mclk", "apb_pclk";
568				bus-width	= <4>;
569				cap-sd-highspeed;
570				cap-mmc-highspeed;
571				max-frequency	= <48000000>;
572			};
573		};
574
575		tcsr: syscon@1a400000 {
576			compatible = "qcom,tcsr-msm8660", "syscon";
577			reg = <0x1a400000 0x100>;
578		};
579	};
580
581};
582