1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * File: mca.c
4 * Purpose: Generic MCA handling layer
5 *
6 * Copyright (C) 2003 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
8 *
9 * Copyright (C) 2002 Dell Inc.
10 * Copyright (C) Matt Domsch <Matt_Domsch@dell.com>
11 *
12 * Copyright (C) 2002 Intel
13 * Copyright (C) Jenna Hall <jenna.s.hall@intel.com>
14 *
15 * Copyright (C) 2001 Intel
16 * Copyright (C) Fred Lewis <frederick.v.lewis@intel.com>
17 *
18 * Copyright (C) 2000 Intel
19 * Copyright (C) Chuck Fleckenstein <cfleck@co.intel.com>
20 *
21 * Copyright (C) 1999, 2004-2008 Silicon Graphics, Inc.
22 * Copyright (C) Vijay Chander <vijay@engr.sgi.com>
23 *
24 * Copyright (C) 2006 FUJITSU LIMITED
25 * Copyright (C) Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
26 *
27 * 2000-03-29 Chuck Fleckenstein <cfleck@co.intel.com>
28 * Fixed PAL/SAL update issues, began MCA bug fixes, logging issues,
29 * added min save state dump, added INIT handler.
30 *
31 * 2001-01-03 Fred Lewis <frederick.v.lewis@intel.com>
32 * Added setup of CMCI and CPEI IRQs, logging of corrected platform
33 * errors, completed code for logging of corrected & uncorrected
34 * machine check errors, and updated for conformance with Nov. 2000
35 * revision of the SAL 3.0 spec.
36 *
37 * 2002-01-04 Jenna Hall <jenna.s.hall@intel.com>
38 * Aligned MCA stack to 16 bytes, added platform vs. CPU error flag,
39 * set SAL default return values, changed error record structure to
40 * linked list, added init call to sal_get_state_info_size().
41 *
42 * 2002-03-25 Matt Domsch <Matt_Domsch@dell.com>
43 * GUID cleanups.
44 *
45 * 2003-04-15 David Mosberger-Tang <davidm@hpl.hp.com>
46 * Added INIT backtrace support.
47 *
48 * 2003-12-08 Keith Owens <kaos@sgi.com>
49 * smp_call_function() must not be called from interrupt context
50 * (can deadlock on tasklist_lock).
51 * Use keventd to call smp_call_function().
52 *
53 * 2004-02-01 Keith Owens <kaos@sgi.com>
54 * Avoid deadlock when using printk() for MCA and INIT records.
55 * Delete all record printing code, moved to salinfo_decode in user
56 * space. Mark variables and functions static where possible.
57 * Delete dead variables and functions. Reorder to remove the need
58 * for forward declarations and to consolidate related code.
59 *
60 * 2005-08-12 Keith Owens <kaos@sgi.com>
61 * Convert MCA/INIT handlers to use per event stacks and SAL/OS
62 * state.
63 *
64 * 2005-10-07 Keith Owens <kaos@sgi.com>
65 * Add notify_die() hooks.
66 *
67 * 2006-09-15 Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
68 * Add printing support for MCA/INIT.
69 *
70 * 2007-04-27 Russ Anderson <rja@sgi.com>
71 * Support multiple cpus going through OS_MCA in the same event.
72 */
73 #include <linux/jiffies.h>
74 #include <linux/types.h>
75 #include <linux/init.h>
76 #include <linux/sched/signal.h>
77 #include <linux/sched/debug.h>
78 #include <linux/sched/task.h>
79 #include <linux/interrupt.h>
80 #include <linux/irq.h>
81 #include <linux/memblock.h>
82 #include <linux/acpi.h>
83 #include <linux/timer.h>
84 #include <linux/module.h>
85 #include <linux/kernel.h>
86 #include <linux/smp.h>
87 #include <linux/workqueue.h>
88 #include <linux/cpumask.h>
89 #include <linux/kdebug.h>
90 #include <linux/cpu.h>
91 #include <linux/gfp.h>
92
93 #include <asm/delay.h>
94 #include <asm/efi.h>
95 #include <asm/meminit.h>
96 #include <asm/page.h>
97 #include <asm/ptrace.h>
98 #include <asm/sal.h>
99 #include <asm/mca.h>
100 #include <asm/mca_asm.h>
101 #include <asm/kexec.h>
102
103 #include <asm/irq.h>
104 #include <asm/hw_irq.h>
105 #include <asm/tlb.h>
106
107 #include "mca_drv.h"
108 #include "entry.h"
109 #include "irq.h"
110
111 #if defined(IA64_MCA_DEBUG_INFO)
112 # define IA64_MCA_DEBUG(fmt...) printk(fmt)
113 #else
114 # define IA64_MCA_DEBUG(fmt...) do {} while (0)
115 #endif
116
117 #define NOTIFY_INIT(event, regs, arg, spin) \
118 do { \
119 if ((notify_die((event), "INIT", (regs), (arg), 0, 0) \
120 == NOTIFY_STOP) && ((spin) == 1)) \
121 ia64_mca_spin(__func__); \
122 } while (0)
123
124 #define NOTIFY_MCA(event, regs, arg, spin) \
125 do { \
126 if ((notify_die((event), "MCA", (regs), (arg), 0, 0) \
127 == NOTIFY_STOP) && ((spin) == 1)) \
128 ia64_mca_spin(__func__); \
129 } while (0)
130
131 /* Used by mca_asm.S */
132 DEFINE_PER_CPU(u64, ia64_mca_data); /* == __per_cpu_mca[smp_processor_id()] */
133 DEFINE_PER_CPU(u64, ia64_mca_per_cpu_pte); /* PTE to map per-CPU area */
134 DEFINE_PER_CPU(u64, ia64_mca_pal_pte); /* PTE to map PAL code */
135 DEFINE_PER_CPU(u64, ia64_mca_pal_base); /* vaddr PAL code granule */
136 DEFINE_PER_CPU(u64, ia64_mca_tr_reload); /* Flag for TR reload */
137
138 unsigned long __per_cpu_mca[NR_CPUS];
139
140 /* In mca_asm.S */
141 extern void ia64_os_init_dispatch_monarch (void);
142 extern void ia64_os_init_dispatch_slave (void);
143
144 static int monarch_cpu = -1;
145
146 static ia64_mc_info_t ia64_mc_info;
147
148 #define MAX_CPE_POLL_INTERVAL (15*60*HZ) /* 15 minutes */
149 #define MIN_CPE_POLL_INTERVAL (2*60*HZ) /* 2 minutes */
150 #define CMC_POLL_INTERVAL (1*60*HZ) /* 1 minute */
151 #define CPE_HISTORY_LENGTH 5
152 #define CMC_HISTORY_LENGTH 5
153
154 static struct timer_list cpe_poll_timer;
155 static struct timer_list cmc_poll_timer;
156 /*
157 * This variable tells whether we are currently in polling mode.
158 * Start with this in the wrong state so we won't play w/ timers
159 * before the system is ready.
160 */
161 static int cmc_polling_enabled = 1;
162
163 /*
164 * Clearing this variable prevents CPE polling from getting activated
165 * in mca_late_init. Use it if your system doesn't provide a CPEI,
166 * but encounters problems retrieving CPE logs. This should only be
167 * necessary for debugging.
168 */
169 static int cpe_poll_enabled = 1;
170
171 extern void salinfo_log_wakeup(int type, u8 *buffer, u64 size, int irqsafe);
172
173 static int mca_init __initdata;
174
175 /*
176 * limited & delayed printing support for MCA/INIT handler
177 */
178
179 #define mprintk(fmt...) ia64_mca_printk(fmt)
180
181 #define MLOGBUF_SIZE (512+256*NR_CPUS)
182 #define MLOGBUF_MSGMAX 256
183 static char mlogbuf[MLOGBUF_SIZE];
184 static DEFINE_SPINLOCK(mlogbuf_wlock); /* mca context only */
185 static DEFINE_SPINLOCK(mlogbuf_rlock); /* normal context only */
186 static unsigned long mlogbuf_start;
187 static unsigned long mlogbuf_end;
188 static unsigned int mlogbuf_finished = 0;
189 static unsigned long mlogbuf_timestamp = 0;
190
191 static int loglevel_save = -1;
192 #define BREAK_LOGLEVEL(__console_loglevel) \
193 oops_in_progress = 1; \
194 if (loglevel_save < 0) \
195 loglevel_save = __console_loglevel; \
196 __console_loglevel = 15;
197
198 #define RESTORE_LOGLEVEL(__console_loglevel) \
199 if (loglevel_save >= 0) { \
200 __console_loglevel = loglevel_save; \
201 loglevel_save = -1; \
202 } \
203 mlogbuf_finished = 0; \
204 oops_in_progress = 0;
205
206 /*
207 * Push messages into buffer, print them later if not urgent.
208 */
ia64_mca_printk(const char * fmt,...)209 void ia64_mca_printk(const char *fmt, ...)
210 {
211 va_list args;
212 int printed_len;
213 char temp_buf[MLOGBUF_MSGMAX];
214 char *p;
215
216 va_start(args, fmt);
217 printed_len = vscnprintf(temp_buf, sizeof(temp_buf), fmt, args);
218 va_end(args);
219
220 /* Copy the output into mlogbuf */
221 if (oops_in_progress) {
222 /* mlogbuf was abandoned, use printk directly instead. */
223 printk("%s", temp_buf);
224 } else {
225 spin_lock(&mlogbuf_wlock);
226 for (p = temp_buf; *p; p++) {
227 unsigned long next = (mlogbuf_end + 1) % MLOGBUF_SIZE;
228 if (next != mlogbuf_start) {
229 mlogbuf[mlogbuf_end] = *p;
230 mlogbuf_end = next;
231 } else {
232 /* buffer full */
233 break;
234 }
235 }
236 mlogbuf[mlogbuf_end] = '\0';
237 spin_unlock(&mlogbuf_wlock);
238 }
239 }
240 EXPORT_SYMBOL(ia64_mca_printk);
241
242 /*
243 * Print buffered messages.
244 * NOTE: call this after returning normal context. (ex. from salinfod)
245 */
ia64_mlogbuf_dump(void)246 void ia64_mlogbuf_dump(void)
247 {
248 char temp_buf[MLOGBUF_MSGMAX];
249 char *p;
250 unsigned long index;
251 unsigned long flags;
252 unsigned int printed_len;
253
254 /* Get output from mlogbuf */
255 while (mlogbuf_start != mlogbuf_end) {
256 temp_buf[0] = '\0';
257 p = temp_buf;
258 printed_len = 0;
259
260 spin_lock_irqsave(&mlogbuf_rlock, flags);
261
262 index = mlogbuf_start;
263 while (index != mlogbuf_end) {
264 *p = mlogbuf[index];
265 index = (index + 1) % MLOGBUF_SIZE;
266 if (!*p)
267 break;
268 p++;
269 if (++printed_len >= MLOGBUF_MSGMAX - 1)
270 break;
271 }
272 *p = '\0';
273 if (temp_buf[0])
274 printk("%s", temp_buf);
275 mlogbuf_start = index;
276
277 mlogbuf_timestamp = 0;
278 spin_unlock_irqrestore(&mlogbuf_rlock, flags);
279 }
280 }
281 EXPORT_SYMBOL(ia64_mlogbuf_dump);
282
283 /*
284 * Call this if system is going to down or if immediate flushing messages to
285 * console is required. (ex. recovery was failed, crash dump is going to be
286 * invoked, long-wait rendezvous etc.)
287 * NOTE: this should be called from monarch.
288 */
ia64_mlogbuf_finish(int wait)289 static void ia64_mlogbuf_finish(int wait)
290 {
291 BREAK_LOGLEVEL(console_loglevel);
292
293 spin_lock_init(&mlogbuf_rlock);
294 ia64_mlogbuf_dump();
295 printk(KERN_EMERG "mlogbuf_finish: printing switched to urgent mode, "
296 "MCA/INIT might be dodgy or fail.\n");
297
298 if (!wait)
299 return;
300
301 /* wait for console */
302 printk("Delaying for 5 seconds...\n");
303 udelay(5*1000000);
304
305 mlogbuf_finished = 1;
306 }
307
308 /*
309 * Print buffered messages from INIT context.
310 */
ia64_mlogbuf_dump_from_init(void)311 static void ia64_mlogbuf_dump_from_init(void)
312 {
313 if (mlogbuf_finished)
314 return;
315
316 if (mlogbuf_timestamp &&
317 time_before(jiffies, mlogbuf_timestamp + 30 * HZ)) {
318 printk(KERN_ERR "INIT: mlogbuf_dump is interrupted by INIT "
319 " and the system seems to be messed up.\n");
320 ia64_mlogbuf_finish(0);
321 return;
322 }
323
324 if (!spin_trylock(&mlogbuf_rlock)) {
325 printk(KERN_ERR "INIT: mlogbuf_dump is interrupted by INIT. "
326 "Generated messages other than stack dump will be "
327 "buffered to mlogbuf and will be printed later.\n");
328 printk(KERN_ERR "INIT: If messages would not printed after "
329 "this INIT, wait 30sec and assert INIT again.\n");
330 if (!mlogbuf_timestamp)
331 mlogbuf_timestamp = jiffies;
332 return;
333 }
334 spin_unlock(&mlogbuf_rlock);
335 ia64_mlogbuf_dump();
336 }
337
338 static inline void
ia64_mca_spin(const char * func)339 ia64_mca_spin(const char *func)
340 {
341 if (monarch_cpu == smp_processor_id())
342 ia64_mlogbuf_finish(0);
343 mprintk(KERN_EMERG "%s: spinning here, not returning to SAL\n", func);
344 while (1)
345 cpu_relax();
346 }
347 /*
348 * IA64_MCA log support
349 */
350 #define IA64_MAX_LOGS 2 /* Double-buffering for nested MCAs */
351 #define IA64_MAX_LOG_TYPES 4 /* MCA, INIT, CMC, CPE */
352
353 typedef struct ia64_state_log_s
354 {
355 spinlock_t isl_lock;
356 int isl_index;
357 unsigned long isl_count;
358 ia64_err_rec_t *isl_log[IA64_MAX_LOGS]; /* need space to store header + error log */
359 } ia64_state_log_t;
360
361 static ia64_state_log_t ia64_state_log[IA64_MAX_LOG_TYPES];
362
363 #define IA64_LOG_LOCK_INIT(it) spin_lock_init(&ia64_state_log[it].isl_lock)
364 #define IA64_LOG_LOCK(it) spin_lock_irqsave(&ia64_state_log[it].isl_lock, s)
365 #define IA64_LOG_UNLOCK(it) spin_unlock_irqrestore(&ia64_state_log[it].isl_lock,s)
366 #define IA64_LOG_NEXT_INDEX(it) ia64_state_log[it].isl_index
367 #define IA64_LOG_CURR_INDEX(it) 1 - ia64_state_log[it].isl_index
368 #define IA64_LOG_INDEX_INC(it) \
369 {ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index; \
370 ia64_state_log[it].isl_count++;}
371 #define IA64_LOG_INDEX_DEC(it) \
372 ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index
373 #define IA64_LOG_NEXT_BUFFER(it) (void *)((ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)]))
374 #define IA64_LOG_CURR_BUFFER(it) (void *)((ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)]))
375 #define IA64_LOG_COUNT(it) ia64_state_log[it].isl_count
376
ia64_log_allocate(int it,u64 size)377 static inline void ia64_log_allocate(int it, u64 size)
378 {
379 ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)] =
380 (ia64_err_rec_t *)memblock_alloc(size, SMP_CACHE_BYTES);
381 if (!ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)])
382 panic("%s: Failed to allocate %llu bytes\n", __func__, size);
383
384 ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)] =
385 (ia64_err_rec_t *)memblock_alloc(size, SMP_CACHE_BYTES);
386 if (!ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)])
387 panic("%s: Failed to allocate %llu bytes\n", __func__, size);
388 }
389
390 /*
391 * ia64_log_init
392 * Reset the OS ia64 log buffer
393 * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
394 * Outputs : None
395 */
396 static void __init
ia64_log_init(int sal_info_type)397 ia64_log_init(int sal_info_type)
398 {
399 u64 max_size = 0;
400
401 IA64_LOG_NEXT_INDEX(sal_info_type) = 0;
402 IA64_LOG_LOCK_INIT(sal_info_type);
403
404 // SAL will tell us the maximum size of any error record of this type
405 max_size = ia64_sal_get_state_info_size(sal_info_type);
406 if (!max_size)
407 /* alloc_bootmem() doesn't like zero-sized allocations! */
408 return;
409
410 // set up OS data structures to hold error info
411 ia64_log_allocate(sal_info_type, max_size);
412 }
413
414 /*
415 * ia64_log_get
416 *
417 * Get the current MCA log from SAL and copy it into the OS log buffer.
418 *
419 * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
420 * irq_safe whether you can use printk at this point
421 * Outputs : size (total record length)
422 * *buffer (ptr to error record)
423 *
424 */
425 static u64
ia64_log_get(int sal_info_type,u8 ** buffer,int irq_safe)426 ia64_log_get(int sal_info_type, u8 **buffer, int irq_safe)
427 {
428 sal_log_record_header_t *log_buffer;
429 u64 total_len = 0;
430 unsigned long s;
431
432 IA64_LOG_LOCK(sal_info_type);
433
434 /* Get the process state information */
435 log_buffer = IA64_LOG_NEXT_BUFFER(sal_info_type);
436
437 total_len = ia64_sal_get_state_info(sal_info_type, (u64 *)log_buffer);
438
439 if (total_len) {
440 IA64_LOG_INDEX_INC(sal_info_type);
441 IA64_LOG_UNLOCK(sal_info_type);
442 if (irq_safe) {
443 IA64_MCA_DEBUG("%s: SAL error record type %d retrieved. Record length = %ld\n",
444 __func__, sal_info_type, total_len);
445 }
446 *buffer = (u8 *) log_buffer;
447 return total_len;
448 } else {
449 IA64_LOG_UNLOCK(sal_info_type);
450 return 0;
451 }
452 }
453
454 /*
455 * ia64_mca_log_sal_error_record
456 *
457 * This function retrieves a specified error record type from SAL
458 * and wakes up any processes waiting for error records.
459 *
460 * Inputs : sal_info_type (Type of error record MCA/CMC/CPE)
461 * FIXME: remove MCA and irq_safe.
462 */
463 static void
ia64_mca_log_sal_error_record(int sal_info_type)464 ia64_mca_log_sal_error_record(int sal_info_type)
465 {
466 u8 *buffer;
467 sal_log_record_header_t *rh;
468 u64 size;
469 int irq_safe = sal_info_type != SAL_INFO_TYPE_MCA;
470 #ifdef IA64_MCA_DEBUG_INFO
471 static const char * const rec_name[] = { "MCA", "INIT", "CMC", "CPE" };
472 #endif
473
474 size = ia64_log_get(sal_info_type, &buffer, irq_safe);
475 if (!size)
476 return;
477
478 salinfo_log_wakeup(sal_info_type, buffer, size, irq_safe);
479
480 if (irq_safe)
481 IA64_MCA_DEBUG("CPU %d: SAL log contains %s error record\n",
482 smp_processor_id(),
483 sal_info_type < ARRAY_SIZE(rec_name) ? rec_name[sal_info_type] : "UNKNOWN");
484
485 /* Clear logs from corrected errors in case there's no user-level logger */
486 rh = (sal_log_record_header_t *)buffer;
487 if (rh->severity == sal_log_severity_corrected)
488 ia64_sal_clear_state_info(sal_info_type);
489 }
490
491 /*
492 * search_mca_table
493 * See if the MCA surfaced in an instruction range
494 * that has been tagged as recoverable.
495 *
496 * Inputs
497 * first First address range to check
498 * last Last address range to check
499 * ip Instruction pointer, address we are looking for
500 *
501 * Return value:
502 * 1 on Success (in the table)/ 0 on Failure (not in the table)
503 */
504 int
search_mca_table(const struct mca_table_entry * first,const struct mca_table_entry * last,unsigned long ip)505 search_mca_table (const struct mca_table_entry *first,
506 const struct mca_table_entry *last,
507 unsigned long ip)
508 {
509 const struct mca_table_entry *curr;
510 u64 curr_start, curr_end;
511
512 curr = first;
513 while (curr <= last) {
514 curr_start = (u64) &curr->start_addr + curr->start_addr;
515 curr_end = (u64) &curr->end_addr + curr->end_addr;
516
517 if ((ip >= curr_start) && (ip <= curr_end)) {
518 return 1;
519 }
520 curr++;
521 }
522 return 0;
523 }
524
525 /* Given an address, look for it in the mca tables. */
mca_recover_range(unsigned long addr)526 int mca_recover_range(unsigned long addr)
527 {
528 extern struct mca_table_entry __start___mca_table[];
529 extern struct mca_table_entry __stop___mca_table[];
530
531 return search_mca_table(__start___mca_table, __stop___mca_table-1, addr);
532 }
533 EXPORT_SYMBOL_GPL(mca_recover_range);
534
535 int cpe_vector = -1;
536 int ia64_cpe_irq = -1;
537
538 static irqreturn_t
ia64_mca_cpe_int_handler(int cpe_irq,void * arg)539 ia64_mca_cpe_int_handler (int cpe_irq, void *arg)
540 {
541 static unsigned long cpe_history[CPE_HISTORY_LENGTH];
542 static int index;
543 static DEFINE_SPINLOCK(cpe_history_lock);
544
545 IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
546 __func__, cpe_irq, smp_processor_id());
547
548 /* SAL spec states this should run w/ interrupts enabled */
549 local_irq_enable();
550
551 spin_lock(&cpe_history_lock);
552 if (!cpe_poll_enabled && cpe_vector >= 0) {
553
554 int i, count = 1; /* we know 1 happened now */
555 unsigned long now = jiffies;
556
557 for (i = 0; i < CPE_HISTORY_LENGTH; i++) {
558 if (now - cpe_history[i] <= HZ)
559 count++;
560 }
561
562 IA64_MCA_DEBUG(KERN_INFO "CPE threshold %d/%d\n", count, CPE_HISTORY_LENGTH);
563 if (count >= CPE_HISTORY_LENGTH) {
564
565 cpe_poll_enabled = 1;
566 spin_unlock(&cpe_history_lock);
567 disable_irq_nosync(local_vector_to_irq(IA64_CPE_VECTOR));
568
569 /*
570 * Corrected errors will still be corrected, but
571 * make sure there's a log somewhere that indicates
572 * something is generating more than we can handle.
573 */
574 printk(KERN_WARNING "WARNING: Switching to polling CPE handler; error records may be lost\n");
575
576 mod_timer(&cpe_poll_timer, jiffies + MIN_CPE_POLL_INTERVAL);
577
578 /* lock already released, get out now */
579 goto out;
580 } else {
581 cpe_history[index++] = now;
582 if (index == CPE_HISTORY_LENGTH)
583 index = 0;
584 }
585 }
586 spin_unlock(&cpe_history_lock);
587 out:
588 /* Get the CPE error record and log it */
589 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CPE);
590
591 local_irq_disable();
592
593 return IRQ_HANDLED;
594 }
595
596 /*
597 * ia64_mca_register_cpev
598 *
599 * Register the corrected platform error vector with SAL.
600 *
601 * Inputs
602 * cpev Corrected Platform Error Vector number
603 *
604 * Outputs
605 * None
606 */
607 void
ia64_mca_register_cpev(int cpev)608 ia64_mca_register_cpev (int cpev)
609 {
610 /* Register the CPE interrupt vector with SAL */
611 struct ia64_sal_retval isrv;
612
613 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_CPE_INT, SAL_MC_PARAM_MECHANISM_INT, cpev, 0, 0);
614 if (isrv.status) {
615 printk(KERN_ERR "Failed to register Corrected Platform "
616 "Error interrupt vector with SAL (status %ld)\n", isrv.status);
617 return;
618 }
619
620 IA64_MCA_DEBUG("%s: corrected platform error "
621 "vector %#x registered\n", __func__, cpev);
622 }
623
624 /*
625 * ia64_mca_cmc_vector_setup
626 *
627 * Setup the corrected machine check vector register in the processor.
628 * (The interrupt is masked on boot. ia64_mca_late_init unmask this.)
629 * This function is invoked on a per-processor basis.
630 *
631 * Inputs
632 * None
633 *
634 * Outputs
635 * None
636 */
637 void
ia64_mca_cmc_vector_setup(void)638 ia64_mca_cmc_vector_setup (void)
639 {
640 cmcv_reg_t cmcv;
641
642 cmcv.cmcv_regval = 0;
643 cmcv.cmcv_mask = 1; /* Mask/disable interrupt at first */
644 cmcv.cmcv_vector = IA64_CMC_VECTOR;
645 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
646
647 IA64_MCA_DEBUG("%s: CPU %d corrected machine check vector %#x registered.\n",
648 __func__, smp_processor_id(), IA64_CMC_VECTOR);
649
650 IA64_MCA_DEBUG("%s: CPU %d CMCV = %#016lx\n",
651 __func__, smp_processor_id(), ia64_getreg(_IA64_REG_CR_CMCV));
652 }
653
654 /*
655 * ia64_mca_cmc_vector_disable
656 *
657 * Mask the corrected machine check vector register in the processor.
658 * This function is invoked on a per-processor basis.
659 *
660 * Inputs
661 * dummy(unused)
662 *
663 * Outputs
664 * None
665 */
666 static void
ia64_mca_cmc_vector_disable(void * dummy)667 ia64_mca_cmc_vector_disable (void *dummy)
668 {
669 cmcv_reg_t cmcv;
670
671 cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
672
673 cmcv.cmcv_mask = 1; /* Mask/disable interrupt */
674 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
675
676 IA64_MCA_DEBUG("%s: CPU %d corrected machine check vector %#x disabled.\n",
677 __func__, smp_processor_id(), cmcv.cmcv_vector);
678 }
679
680 /*
681 * ia64_mca_cmc_vector_enable
682 *
683 * Unmask the corrected machine check vector register in the processor.
684 * This function is invoked on a per-processor basis.
685 *
686 * Inputs
687 * dummy(unused)
688 *
689 * Outputs
690 * None
691 */
692 static void
ia64_mca_cmc_vector_enable(void * dummy)693 ia64_mca_cmc_vector_enable (void *dummy)
694 {
695 cmcv_reg_t cmcv;
696
697 cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
698
699 cmcv.cmcv_mask = 0; /* Unmask/enable interrupt */
700 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
701
702 IA64_MCA_DEBUG("%s: CPU %d corrected machine check vector %#x enabled.\n",
703 __func__, smp_processor_id(), cmcv.cmcv_vector);
704 }
705
706 /*
707 * ia64_mca_cmc_vector_disable_keventd
708 *
709 * Called via keventd (smp_call_function() is not safe in interrupt context) to
710 * disable the cmc interrupt vector.
711 */
712 static void
ia64_mca_cmc_vector_disable_keventd(struct work_struct * unused)713 ia64_mca_cmc_vector_disable_keventd(struct work_struct *unused)
714 {
715 on_each_cpu(ia64_mca_cmc_vector_disable, NULL, 0);
716 }
717
718 /*
719 * ia64_mca_cmc_vector_enable_keventd
720 *
721 * Called via keventd (smp_call_function() is not safe in interrupt context) to
722 * enable the cmc interrupt vector.
723 */
724 static void
ia64_mca_cmc_vector_enable_keventd(struct work_struct * unused)725 ia64_mca_cmc_vector_enable_keventd(struct work_struct *unused)
726 {
727 on_each_cpu(ia64_mca_cmc_vector_enable, NULL, 0);
728 }
729
730 /*
731 * ia64_mca_wakeup
732 *
733 * Send an inter-cpu interrupt to wake-up a particular cpu.
734 *
735 * Inputs : cpuid
736 * Outputs : None
737 */
738 static void
ia64_mca_wakeup(int cpu)739 ia64_mca_wakeup(int cpu)
740 {
741 ia64_send_ipi(cpu, IA64_MCA_WAKEUP_VECTOR, IA64_IPI_DM_INT, 0);
742 }
743
744 /*
745 * ia64_mca_wakeup_all
746 *
747 * Wakeup all the slave cpus which have rendez'ed previously.
748 *
749 * Inputs : None
750 * Outputs : None
751 */
752 static void
ia64_mca_wakeup_all(void)753 ia64_mca_wakeup_all(void)
754 {
755 int cpu;
756
757 /* Clear the Rendez checkin flag for all cpus */
758 for_each_online_cpu(cpu) {
759 if (ia64_mc_info.imi_rendez_checkin[cpu] == IA64_MCA_RENDEZ_CHECKIN_DONE)
760 ia64_mca_wakeup(cpu);
761 }
762
763 }
764
765 /*
766 * ia64_mca_rendez_interrupt_handler
767 *
768 * This is handler used to put slave processors into spinloop
769 * while the monarch processor does the mca handling and later
770 * wake each slave up once the monarch is done. The state
771 * IA64_MCA_RENDEZ_CHECKIN_DONE indicates the cpu is rendez'ed
772 * in SAL. The state IA64_MCA_RENDEZ_CHECKIN_NOTDONE indicates
773 * the cpu has come out of OS rendezvous.
774 *
775 * Inputs : None
776 * Outputs : None
777 */
778 static irqreturn_t
ia64_mca_rendez_int_handler(int rendez_irq,void * arg)779 ia64_mca_rendez_int_handler(int rendez_irq, void *arg)
780 {
781 unsigned long flags;
782 int cpu = smp_processor_id();
783 struct ia64_mca_notify_die nd =
784 { .sos = NULL, .monarch_cpu = &monarch_cpu };
785
786 /* Mask all interrupts */
787 local_irq_save(flags);
788
789 NOTIFY_MCA(DIE_MCA_RENDZVOUS_ENTER, get_irq_regs(), (long)&nd, 1);
790
791 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_DONE;
792 /* Register with the SAL monarch that the slave has
793 * reached SAL
794 */
795 ia64_sal_mc_rendez();
796
797 NOTIFY_MCA(DIE_MCA_RENDZVOUS_PROCESS, get_irq_regs(), (long)&nd, 1);
798
799 /* Wait for the monarch cpu to exit. */
800 while (monarch_cpu != -1)
801 cpu_relax(); /* spin until monarch leaves */
802
803 NOTIFY_MCA(DIE_MCA_RENDZVOUS_LEAVE, get_irq_regs(), (long)&nd, 1);
804
805 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
806 /* Enable all interrupts */
807 local_irq_restore(flags);
808 return IRQ_HANDLED;
809 }
810
811 /*
812 * ia64_mca_wakeup_int_handler
813 *
814 * The interrupt handler for processing the inter-cpu interrupt to the
815 * slave cpu which was spinning in the rendez loop.
816 * Since this spinning is done by turning off the interrupts and
817 * polling on the wakeup-interrupt bit in the IRR, there is
818 * nothing useful to be done in the handler.
819 *
820 * Inputs : wakeup_irq (Wakeup-interrupt bit)
821 * arg (Interrupt handler specific argument)
822 * Outputs : None
823 *
824 */
825 static irqreturn_t
ia64_mca_wakeup_int_handler(int wakeup_irq,void * arg)826 ia64_mca_wakeup_int_handler(int wakeup_irq, void *arg)
827 {
828 return IRQ_HANDLED;
829 }
830
831 /* Function pointer for extra MCA recovery */
832 int (*ia64_mca_ucmc_extension)
833 (void*,struct ia64_sal_os_state*)
834 = NULL;
835
836 int
ia64_reg_MCA_extension(int (* fn)(void *,struct ia64_sal_os_state *))837 ia64_reg_MCA_extension(int (*fn)(void *, struct ia64_sal_os_state *))
838 {
839 if (ia64_mca_ucmc_extension)
840 return 1;
841
842 ia64_mca_ucmc_extension = fn;
843 return 0;
844 }
845
846 void
ia64_unreg_MCA_extension(void)847 ia64_unreg_MCA_extension(void)
848 {
849 if (ia64_mca_ucmc_extension)
850 ia64_mca_ucmc_extension = NULL;
851 }
852
853 EXPORT_SYMBOL(ia64_reg_MCA_extension);
854 EXPORT_SYMBOL(ia64_unreg_MCA_extension);
855
856
857 static inline void
copy_reg(const u64 * fr,u64 fnat,unsigned long * tr,unsigned long * tnat)858 copy_reg(const u64 *fr, u64 fnat, unsigned long *tr, unsigned long *tnat)
859 {
860 u64 fslot, tslot, nat;
861 *tr = *fr;
862 fslot = ((unsigned long)fr >> 3) & 63;
863 tslot = ((unsigned long)tr >> 3) & 63;
864 *tnat &= ~(1UL << tslot);
865 nat = (fnat >> fslot) & 1;
866 *tnat |= (nat << tslot);
867 }
868
869 /* Change the comm field on the MCA/INT task to include the pid that
870 * was interrupted, it makes for easier debugging. If that pid was 0
871 * (swapper or nested MCA/INIT) then use the start of the previous comm
872 * field suffixed with its cpu.
873 */
874
875 static void
ia64_mca_modify_comm(const struct task_struct * previous_current)876 ia64_mca_modify_comm(const struct task_struct *previous_current)
877 {
878 char *p, comm[sizeof(current->comm)];
879 if (previous_current->pid)
880 snprintf(comm, sizeof(comm), "%s %d",
881 current->comm, previous_current->pid);
882 else {
883 int l;
884 if ((p = strchr(previous_current->comm, ' ')))
885 l = p - previous_current->comm;
886 else
887 l = strlen(previous_current->comm);
888 snprintf(comm, sizeof(comm), "%s %*s %d",
889 current->comm, l, previous_current->comm,
890 task_thread_info(previous_current)->cpu);
891 }
892 memcpy(current->comm, comm, sizeof(current->comm));
893 }
894
895 static void
finish_pt_regs(struct pt_regs * regs,struct ia64_sal_os_state * sos,unsigned long * nat)896 finish_pt_regs(struct pt_regs *regs, struct ia64_sal_os_state *sos,
897 unsigned long *nat)
898 {
899 const struct pal_min_state_area *ms = sos->pal_min_state;
900 const u64 *bank;
901
902 /* If ipsr.ic then use pmsa_{iip,ipsr,ifs}, else use
903 * pmsa_{xip,xpsr,xfs}
904 */
905 if (ia64_psr(regs)->ic) {
906 regs->cr_iip = ms->pmsa_iip;
907 regs->cr_ipsr = ms->pmsa_ipsr;
908 regs->cr_ifs = ms->pmsa_ifs;
909 } else {
910 regs->cr_iip = ms->pmsa_xip;
911 regs->cr_ipsr = ms->pmsa_xpsr;
912 regs->cr_ifs = ms->pmsa_xfs;
913
914 sos->iip = ms->pmsa_iip;
915 sos->ipsr = ms->pmsa_ipsr;
916 sos->ifs = ms->pmsa_ifs;
917 }
918 regs->pr = ms->pmsa_pr;
919 regs->b0 = ms->pmsa_br0;
920 regs->ar_rsc = ms->pmsa_rsc;
921 copy_reg(&ms->pmsa_gr[1-1], ms->pmsa_nat_bits, ®s->r1, nat);
922 copy_reg(&ms->pmsa_gr[2-1], ms->pmsa_nat_bits, ®s->r2, nat);
923 copy_reg(&ms->pmsa_gr[3-1], ms->pmsa_nat_bits, ®s->r3, nat);
924 copy_reg(&ms->pmsa_gr[8-1], ms->pmsa_nat_bits, ®s->r8, nat);
925 copy_reg(&ms->pmsa_gr[9-1], ms->pmsa_nat_bits, ®s->r9, nat);
926 copy_reg(&ms->pmsa_gr[10-1], ms->pmsa_nat_bits, ®s->r10, nat);
927 copy_reg(&ms->pmsa_gr[11-1], ms->pmsa_nat_bits, ®s->r11, nat);
928 copy_reg(&ms->pmsa_gr[12-1], ms->pmsa_nat_bits, ®s->r12, nat);
929 copy_reg(&ms->pmsa_gr[13-1], ms->pmsa_nat_bits, ®s->r13, nat);
930 copy_reg(&ms->pmsa_gr[14-1], ms->pmsa_nat_bits, ®s->r14, nat);
931 copy_reg(&ms->pmsa_gr[15-1], ms->pmsa_nat_bits, ®s->r15, nat);
932 if (ia64_psr(regs)->bn)
933 bank = ms->pmsa_bank1_gr;
934 else
935 bank = ms->pmsa_bank0_gr;
936 copy_reg(&bank[16-16], ms->pmsa_nat_bits, ®s->r16, nat);
937 copy_reg(&bank[17-16], ms->pmsa_nat_bits, ®s->r17, nat);
938 copy_reg(&bank[18-16], ms->pmsa_nat_bits, ®s->r18, nat);
939 copy_reg(&bank[19-16], ms->pmsa_nat_bits, ®s->r19, nat);
940 copy_reg(&bank[20-16], ms->pmsa_nat_bits, ®s->r20, nat);
941 copy_reg(&bank[21-16], ms->pmsa_nat_bits, ®s->r21, nat);
942 copy_reg(&bank[22-16], ms->pmsa_nat_bits, ®s->r22, nat);
943 copy_reg(&bank[23-16], ms->pmsa_nat_bits, ®s->r23, nat);
944 copy_reg(&bank[24-16], ms->pmsa_nat_bits, ®s->r24, nat);
945 copy_reg(&bank[25-16], ms->pmsa_nat_bits, ®s->r25, nat);
946 copy_reg(&bank[26-16], ms->pmsa_nat_bits, ®s->r26, nat);
947 copy_reg(&bank[27-16], ms->pmsa_nat_bits, ®s->r27, nat);
948 copy_reg(&bank[28-16], ms->pmsa_nat_bits, ®s->r28, nat);
949 copy_reg(&bank[29-16], ms->pmsa_nat_bits, ®s->r29, nat);
950 copy_reg(&bank[30-16], ms->pmsa_nat_bits, ®s->r30, nat);
951 copy_reg(&bank[31-16], ms->pmsa_nat_bits, ®s->r31, nat);
952 }
953
954 /* On entry to this routine, we are running on the per cpu stack, see
955 * mca_asm.h. The original stack has not been touched by this event. Some of
956 * the original stack's registers will be in the RBS on this stack. This stack
957 * also contains a partial pt_regs and switch_stack, the rest of the data is in
958 * PAL minstate.
959 *
960 * The first thing to do is modify the original stack to look like a blocked
961 * task so we can run backtrace on the original task. Also mark the per cpu
962 * stack as current to ensure that we use the correct task state, it also means
963 * that we can do backtrace on the MCA/INIT handler code itself.
964 */
965
966 static struct task_struct *
ia64_mca_modify_original_stack(struct pt_regs * regs,const struct switch_stack * sw,struct ia64_sal_os_state * sos,const char * type)967 ia64_mca_modify_original_stack(struct pt_regs *regs,
968 const struct switch_stack *sw,
969 struct ia64_sal_os_state *sos,
970 const char *type)
971 {
972 char *p;
973 ia64_va va;
974 extern char ia64_leave_kernel[]; /* Need asm address, not function descriptor */
975 const struct pal_min_state_area *ms = sos->pal_min_state;
976 struct task_struct *previous_current;
977 struct pt_regs *old_regs;
978 struct switch_stack *old_sw;
979 unsigned size = sizeof(struct pt_regs) +
980 sizeof(struct switch_stack) + 16;
981 unsigned long *old_bspstore, *old_bsp;
982 unsigned long *new_bspstore, *new_bsp;
983 unsigned long old_unat, old_rnat, new_rnat, nat;
984 u64 slots, loadrs = regs->loadrs;
985 u64 r12 = ms->pmsa_gr[12-1], r13 = ms->pmsa_gr[13-1];
986 u64 ar_bspstore = regs->ar_bspstore;
987 u64 ar_bsp = regs->ar_bspstore + (loadrs >> 16);
988 const char *msg;
989 int cpu = smp_processor_id();
990
991 previous_current = curr_task(cpu);
992 ia64_set_curr_task(cpu, current);
993 if ((p = strchr(current->comm, ' ')))
994 *p = '\0';
995
996 /* Best effort attempt to cope with MCA/INIT delivered while in
997 * physical mode.
998 */
999 regs->cr_ipsr = ms->pmsa_ipsr;
1000 if (ia64_psr(regs)->dt == 0) {
1001 va.l = r12;
1002 if (va.f.reg == 0) {
1003 va.f.reg = 7;
1004 r12 = va.l;
1005 }
1006 va.l = r13;
1007 if (va.f.reg == 0) {
1008 va.f.reg = 7;
1009 r13 = va.l;
1010 }
1011 }
1012 if (ia64_psr(regs)->rt == 0) {
1013 va.l = ar_bspstore;
1014 if (va.f.reg == 0) {
1015 va.f.reg = 7;
1016 ar_bspstore = va.l;
1017 }
1018 va.l = ar_bsp;
1019 if (va.f.reg == 0) {
1020 va.f.reg = 7;
1021 ar_bsp = va.l;
1022 }
1023 }
1024
1025 /* mca_asm.S ia64_old_stack() cannot assume that the dirty registers
1026 * have been copied to the old stack, the old stack may fail the
1027 * validation tests below. So ia64_old_stack() must restore the dirty
1028 * registers from the new stack. The old and new bspstore probably
1029 * have different alignments, so loadrs calculated on the old bsp
1030 * cannot be used to restore from the new bsp. Calculate a suitable
1031 * loadrs for the new stack and save it in the new pt_regs, where
1032 * ia64_old_stack() can get it.
1033 */
1034 old_bspstore = (unsigned long *)ar_bspstore;
1035 old_bsp = (unsigned long *)ar_bsp;
1036 slots = ia64_rse_num_regs(old_bspstore, old_bsp);
1037 new_bspstore = (unsigned long *)((u64)current + IA64_RBS_OFFSET);
1038 new_bsp = ia64_rse_skip_regs(new_bspstore, slots);
1039 regs->loadrs = (new_bsp - new_bspstore) * 8 << 16;
1040
1041 /* Verify the previous stack state before we change it */
1042 if (user_mode(regs)) {
1043 msg = "occurred in user space";
1044 /* previous_current is guaranteed to be valid when the task was
1045 * in user space, so ...
1046 */
1047 ia64_mca_modify_comm(previous_current);
1048 goto no_mod;
1049 }
1050
1051 if (r13 != sos->prev_IA64_KR_CURRENT) {
1052 msg = "inconsistent previous current and r13";
1053 goto no_mod;
1054 }
1055
1056 if (!mca_recover_range(ms->pmsa_iip)) {
1057 if ((r12 - r13) >= KERNEL_STACK_SIZE) {
1058 msg = "inconsistent r12 and r13";
1059 goto no_mod;
1060 }
1061 if ((ar_bspstore - r13) >= KERNEL_STACK_SIZE) {
1062 msg = "inconsistent ar.bspstore and r13";
1063 goto no_mod;
1064 }
1065 va.p = old_bspstore;
1066 if (va.f.reg < 5) {
1067 msg = "old_bspstore is in the wrong region";
1068 goto no_mod;
1069 }
1070 if ((ar_bsp - r13) >= KERNEL_STACK_SIZE) {
1071 msg = "inconsistent ar.bsp and r13";
1072 goto no_mod;
1073 }
1074 size += (ia64_rse_skip_regs(old_bspstore, slots) - old_bspstore) * 8;
1075 if (ar_bspstore + size > r12) {
1076 msg = "no room for blocked state";
1077 goto no_mod;
1078 }
1079 }
1080
1081 ia64_mca_modify_comm(previous_current);
1082
1083 /* Make the original task look blocked. First stack a struct pt_regs,
1084 * describing the state at the time of interrupt. mca_asm.S built a
1085 * partial pt_regs, copy it and fill in the blanks using minstate.
1086 */
1087 p = (char *)r12 - sizeof(*regs);
1088 old_regs = (struct pt_regs *)p;
1089 memcpy(old_regs, regs, sizeof(*regs));
1090 old_regs->loadrs = loadrs;
1091 old_unat = old_regs->ar_unat;
1092 finish_pt_regs(old_regs, sos, &old_unat);
1093
1094 /* Next stack a struct switch_stack. mca_asm.S built a partial
1095 * switch_stack, copy it and fill in the blanks using pt_regs and
1096 * minstate.
1097 *
1098 * In the synthesized switch_stack, b0 points to ia64_leave_kernel,
1099 * ar.pfs is set to 0.
1100 *
1101 * unwind.c::unw_unwind() does special processing for interrupt frames.
1102 * It checks if the PRED_NON_SYSCALL predicate is set, if the predicate
1103 * is clear then unw_unwind() does _not_ adjust bsp over pt_regs. Not
1104 * that this is documented, of course. Set PRED_NON_SYSCALL in the
1105 * switch_stack on the original stack so it will unwind correctly when
1106 * unwind.c reads pt_regs.
1107 *
1108 * thread.ksp is updated to point to the synthesized switch_stack.
1109 */
1110 p -= sizeof(struct switch_stack);
1111 old_sw = (struct switch_stack *)p;
1112 memcpy(old_sw, sw, sizeof(*sw));
1113 old_sw->caller_unat = old_unat;
1114 old_sw->ar_fpsr = old_regs->ar_fpsr;
1115 copy_reg(&ms->pmsa_gr[4-1], ms->pmsa_nat_bits, &old_sw->r4, &old_unat);
1116 copy_reg(&ms->pmsa_gr[5-1], ms->pmsa_nat_bits, &old_sw->r5, &old_unat);
1117 copy_reg(&ms->pmsa_gr[6-1], ms->pmsa_nat_bits, &old_sw->r6, &old_unat);
1118 copy_reg(&ms->pmsa_gr[7-1], ms->pmsa_nat_bits, &old_sw->r7, &old_unat);
1119 old_sw->b0 = (u64)ia64_leave_kernel;
1120 old_sw->b1 = ms->pmsa_br1;
1121 old_sw->ar_pfs = 0;
1122 old_sw->ar_unat = old_unat;
1123 old_sw->pr = old_regs->pr | (1UL << PRED_NON_SYSCALL);
1124 previous_current->thread.ksp = (u64)p - 16;
1125
1126 /* Finally copy the original stack's registers back to its RBS.
1127 * Registers from ar.bspstore through ar.bsp at the time of the event
1128 * are in the current RBS, copy them back to the original stack. The
1129 * copy must be done register by register because the original bspstore
1130 * and the current one have different alignments, so the saved RNAT
1131 * data occurs at different places.
1132 *
1133 * mca_asm does cover, so the old_bsp already includes all registers at
1134 * the time of MCA/INIT. It also does flushrs, so all registers before
1135 * this function have been written to backing store on the MCA/INIT
1136 * stack.
1137 */
1138 new_rnat = ia64_get_rnat(ia64_rse_rnat_addr(new_bspstore));
1139 old_rnat = regs->ar_rnat;
1140 while (slots--) {
1141 if (ia64_rse_is_rnat_slot(new_bspstore)) {
1142 new_rnat = ia64_get_rnat(new_bspstore++);
1143 }
1144 if (ia64_rse_is_rnat_slot(old_bspstore)) {
1145 *old_bspstore++ = old_rnat;
1146 old_rnat = 0;
1147 }
1148 nat = (new_rnat >> ia64_rse_slot_num(new_bspstore)) & 1UL;
1149 old_rnat &= ~(1UL << ia64_rse_slot_num(old_bspstore));
1150 old_rnat |= (nat << ia64_rse_slot_num(old_bspstore));
1151 *old_bspstore++ = *new_bspstore++;
1152 }
1153 old_sw->ar_bspstore = (unsigned long)old_bspstore;
1154 old_sw->ar_rnat = old_rnat;
1155
1156 sos->prev_task = previous_current;
1157 return previous_current;
1158
1159 no_mod:
1160 mprintk(KERN_INFO "cpu %d, %s %s, original stack not modified\n",
1161 smp_processor_id(), type, msg);
1162 old_unat = regs->ar_unat;
1163 finish_pt_regs(regs, sos, &old_unat);
1164 return previous_current;
1165 }
1166
1167 /* The monarch/slave interaction is based on monarch_cpu and requires that all
1168 * slaves have entered rendezvous before the monarch leaves. If any cpu has
1169 * not entered rendezvous yet then wait a bit. The assumption is that any
1170 * slave that has not rendezvoused after a reasonable time is never going to do
1171 * so. In this context, slave includes cpus that respond to the MCA rendezvous
1172 * interrupt, as well as cpus that receive the INIT slave event.
1173 */
1174
1175 static void
ia64_wait_for_slaves(int monarch,const char * type)1176 ia64_wait_for_slaves(int monarch, const char *type)
1177 {
1178 int c, i , wait;
1179
1180 /*
1181 * wait 5 seconds total for slaves (arbitrary)
1182 */
1183 for (i = 0; i < 5000; i++) {
1184 wait = 0;
1185 for_each_online_cpu(c) {
1186 if (c == monarch)
1187 continue;
1188 if (ia64_mc_info.imi_rendez_checkin[c]
1189 == IA64_MCA_RENDEZ_CHECKIN_NOTDONE) {
1190 udelay(1000); /* short wait */
1191 wait = 1;
1192 break;
1193 }
1194 }
1195 if (!wait)
1196 goto all_in;
1197 }
1198
1199 /*
1200 * Maybe slave(s) dead. Print buffered messages immediately.
1201 */
1202 ia64_mlogbuf_finish(0);
1203 mprintk(KERN_INFO "OS %s slave did not rendezvous on cpu", type);
1204 for_each_online_cpu(c) {
1205 if (c == monarch)
1206 continue;
1207 if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE)
1208 mprintk(" %d", c);
1209 }
1210 mprintk("\n");
1211 return;
1212
1213 all_in:
1214 mprintk(KERN_INFO "All OS %s slaves have reached rendezvous\n", type);
1215 return;
1216 }
1217
1218 /* mca_insert_tr
1219 *
1220 * Switch rid when TR reload and needed!
1221 * iord: 1: itr, 2: itr;
1222 *
1223 */
mca_insert_tr(u64 iord)1224 static void mca_insert_tr(u64 iord)
1225 {
1226
1227 int i;
1228 u64 old_rr;
1229 struct ia64_tr_entry *p;
1230 unsigned long psr;
1231 int cpu = smp_processor_id();
1232
1233 if (!ia64_idtrs[cpu])
1234 return;
1235
1236 psr = ia64_clear_ic();
1237 for (i = IA64_TR_ALLOC_BASE; i < IA64_TR_ALLOC_MAX; i++) {
1238 p = ia64_idtrs[cpu] + (iord - 1) * IA64_TR_ALLOC_MAX;
1239 if (p->pte & 0x1) {
1240 old_rr = ia64_get_rr(p->ifa);
1241 if (old_rr != p->rr) {
1242 ia64_set_rr(p->ifa, p->rr);
1243 ia64_srlz_d();
1244 }
1245 ia64_ptr(iord, p->ifa, p->itir >> 2);
1246 ia64_srlz_i();
1247 if (iord & 0x1) {
1248 ia64_itr(0x1, i, p->ifa, p->pte, p->itir >> 2);
1249 ia64_srlz_i();
1250 }
1251 if (iord & 0x2) {
1252 ia64_itr(0x2, i, p->ifa, p->pte, p->itir >> 2);
1253 ia64_srlz_i();
1254 }
1255 if (old_rr != p->rr) {
1256 ia64_set_rr(p->ifa, old_rr);
1257 ia64_srlz_d();
1258 }
1259 }
1260 }
1261 ia64_set_psr(psr);
1262 }
1263
1264 /*
1265 * ia64_mca_handler
1266 *
1267 * This is uncorrectable machine check handler called from OS_MCA
1268 * dispatch code which is in turn called from SAL_CHECK().
1269 * This is the place where the core of OS MCA handling is done.
1270 * Right now the logs are extracted and displayed in a well-defined
1271 * format. This handler code is supposed to be run only on the
1272 * monarch processor. Once the monarch is done with MCA handling
1273 * further MCA logging is enabled by clearing logs.
1274 * Monarch also has the duty of sending wakeup-IPIs to pull the
1275 * slave processors out of rendezvous spinloop.
1276 *
1277 * If multiple processors call into OS_MCA, the first will become
1278 * the monarch. Subsequent cpus will be recorded in the mca_cpu
1279 * bitmask. After the first monarch has processed its MCA, it
1280 * will wake up the next cpu in the mca_cpu bitmask and then go
1281 * into the rendezvous loop. When all processors have serviced
1282 * their MCA, the last monarch frees up the rest of the processors.
1283 */
1284 void
ia64_mca_handler(struct pt_regs * regs,struct switch_stack * sw,struct ia64_sal_os_state * sos)1285 ia64_mca_handler(struct pt_regs *regs, struct switch_stack *sw,
1286 struct ia64_sal_os_state *sos)
1287 {
1288 int recover, cpu = smp_processor_id();
1289 struct task_struct *previous_current;
1290 struct ia64_mca_notify_die nd =
1291 { .sos = sos, .monarch_cpu = &monarch_cpu, .data = &recover };
1292 static atomic_t mca_count;
1293 static cpumask_t mca_cpu;
1294
1295 if (atomic_add_return(1, &mca_count) == 1) {
1296 monarch_cpu = cpu;
1297 sos->monarch = 1;
1298 } else {
1299 cpumask_set_cpu(cpu, &mca_cpu);
1300 sos->monarch = 0;
1301 }
1302 mprintk(KERN_INFO "Entered OS MCA handler. PSP=%lx cpu=%d "
1303 "monarch=%ld\n", sos->proc_state_param, cpu, sos->monarch);
1304
1305 previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "MCA");
1306
1307 NOTIFY_MCA(DIE_MCA_MONARCH_ENTER, regs, (long)&nd, 1);
1308
1309 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_CONCURRENT_MCA;
1310 if (sos->monarch) {
1311 ia64_wait_for_slaves(cpu, "MCA");
1312
1313 /* Wakeup all the processors which are spinning in the
1314 * rendezvous loop. They will leave SAL, then spin in the OS
1315 * with interrupts disabled until this monarch cpu leaves the
1316 * MCA handler. That gets control back to the OS so we can
1317 * backtrace the other cpus, backtrace when spinning in SAL
1318 * does not work.
1319 */
1320 ia64_mca_wakeup_all();
1321 } else {
1322 while (cpumask_test_cpu(cpu, &mca_cpu))
1323 cpu_relax(); /* spin until monarch wakes us */
1324 }
1325
1326 NOTIFY_MCA(DIE_MCA_MONARCH_PROCESS, regs, (long)&nd, 1);
1327
1328 /* Get the MCA error record and log it */
1329 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA);
1330
1331 /* MCA error recovery */
1332 recover = (ia64_mca_ucmc_extension
1333 && ia64_mca_ucmc_extension(
1334 IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA),
1335 sos));
1336
1337 if (recover) {
1338 sal_log_record_header_t *rh = IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA);
1339 rh->severity = sal_log_severity_corrected;
1340 ia64_sal_clear_state_info(SAL_INFO_TYPE_MCA);
1341 sos->os_status = IA64_MCA_CORRECTED;
1342 } else {
1343 /* Dump buffered message to console */
1344 ia64_mlogbuf_finish(1);
1345 }
1346
1347 if (__this_cpu_read(ia64_mca_tr_reload)) {
1348 mca_insert_tr(0x1); /*Reload dynamic itrs*/
1349 mca_insert_tr(0x2); /*Reload dynamic itrs*/
1350 }
1351
1352 NOTIFY_MCA(DIE_MCA_MONARCH_LEAVE, regs, (long)&nd, 1);
1353
1354 if (atomic_dec_return(&mca_count) > 0) {
1355 int i;
1356
1357 /* wake up the next monarch cpu,
1358 * and put this cpu in the rendez loop.
1359 */
1360 for_each_online_cpu(i) {
1361 if (cpumask_test_cpu(i, &mca_cpu)) {
1362 monarch_cpu = i;
1363 cpumask_clear_cpu(i, &mca_cpu); /* wake next cpu */
1364 while (monarch_cpu != -1)
1365 cpu_relax(); /* spin until last cpu leaves */
1366 ia64_set_curr_task(cpu, previous_current);
1367 ia64_mc_info.imi_rendez_checkin[cpu]
1368 = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1369 return;
1370 }
1371 }
1372 }
1373 ia64_set_curr_task(cpu, previous_current);
1374 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1375 monarch_cpu = -1; /* This frees the slaves and previous monarchs */
1376 }
1377
1378 static DECLARE_WORK(cmc_disable_work, ia64_mca_cmc_vector_disable_keventd);
1379 static DECLARE_WORK(cmc_enable_work, ia64_mca_cmc_vector_enable_keventd);
1380
1381 /*
1382 * ia64_mca_cmc_int_handler
1383 *
1384 * This is corrected machine check interrupt handler.
1385 * Right now the logs are extracted and displayed in a well-defined
1386 * format.
1387 *
1388 * Inputs
1389 * interrupt number
1390 * client data arg ptr
1391 *
1392 * Outputs
1393 * None
1394 */
1395 static irqreturn_t
ia64_mca_cmc_int_handler(int cmc_irq,void * arg)1396 ia64_mca_cmc_int_handler(int cmc_irq, void *arg)
1397 {
1398 static unsigned long cmc_history[CMC_HISTORY_LENGTH];
1399 static int index;
1400 static DEFINE_SPINLOCK(cmc_history_lock);
1401
1402 IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
1403 __func__, cmc_irq, smp_processor_id());
1404
1405 /* SAL spec states this should run w/ interrupts enabled */
1406 local_irq_enable();
1407
1408 spin_lock(&cmc_history_lock);
1409 if (!cmc_polling_enabled) {
1410 int i, count = 1; /* we know 1 happened now */
1411 unsigned long now = jiffies;
1412
1413 for (i = 0; i < CMC_HISTORY_LENGTH; i++) {
1414 if (now - cmc_history[i] <= HZ)
1415 count++;
1416 }
1417
1418 IA64_MCA_DEBUG(KERN_INFO "CMC threshold %d/%d\n", count, CMC_HISTORY_LENGTH);
1419 if (count >= CMC_HISTORY_LENGTH) {
1420
1421 cmc_polling_enabled = 1;
1422 spin_unlock(&cmc_history_lock);
1423 /* If we're being hit with CMC interrupts, we won't
1424 * ever execute the schedule_work() below. Need to
1425 * disable CMC interrupts on this processor now.
1426 */
1427 ia64_mca_cmc_vector_disable(NULL);
1428 schedule_work(&cmc_disable_work);
1429
1430 /*
1431 * Corrected errors will still be corrected, but
1432 * make sure there's a log somewhere that indicates
1433 * something is generating more than we can handle.
1434 */
1435 printk(KERN_WARNING "WARNING: Switching to polling CMC handler; error records may be lost\n");
1436
1437 mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
1438
1439 /* lock already released, get out now */
1440 goto out;
1441 } else {
1442 cmc_history[index++] = now;
1443 if (index == CMC_HISTORY_LENGTH)
1444 index = 0;
1445 }
1446 }
1447 spin_unlock(&cmc_history_lock);
1448 out:
1449 /* Get the CMC error record and log it */
1450 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CMC);
1451
1452 local_irq_disable();
1453
1454 return IRQ_HANDLED;
1455 }
1456
1457 /*
1458 * ia64_mca_cmc_int_caller
1459 *
1460 * Triggered by sw interrupt from CMC polling routine. Calls
1461 * real interrupt handler and either triggers a sw interrupt
1462 * on the next cpu or does cleanup at the end.
1463 *
1464 * Inputs
1465 * interrupt number
1466 * client data arg ptr
1467 * Outputs
1468 * handled
1469 */
1470 static irqreturn_t
ia64_mca_cmc_int_caller(int cmc_irq,void * arg)1471 ia64_mca_cmc_int_caller(int cmc_irq, void *arg)
1472 {
1473 static int start_count = -1;
1474 unsigned int cpuid;
1475
1476 cpuid = smp_processor_id();
1477
1478 /* If first cpu, update count */
1479 if (start_count == -1)
1480 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CMC);
1481
1482 ia64_mca_cmc_int_handler(cmc_irq, arg);
1483
1484 cpuid = cpumask_next(cpuid+1, cpu_online_mask);
1485
1486 if (cpuid < nr_cpu_ids) {
1487 ia64_send_ipi(cpuid, IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
1488 } else {
1489 /* If no log record, switch out of polling mode */
1490 if (start_count == IA64_LOG_COUNT(SAL_INFO_TYPE_CMC)) {
1491
1492 printk(KERN_WARNING "Returning to interrupt driven CMC handler\n");
1493 schedule_work(&cmc_enable_work);
1494 cmc_polling_enabled = 0;
1495
1496 } else {
1497
1498 mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
1499 }
1500
1501 start_count = -1;
1502 }
1503
1504 return IRQ_HANDLED;
1505 }
1506
1507 /*
1508 * ia64_mca_cmc_poll
1509 *
1510 * Poll for Corrected Machine Checks (CMCs)
1511 *
1512 * Inputs : dummy(unused)
1513 * Outputs : None
1514 *
1515 */
1516 static void
ia64_mca_cmc_poll(struct timer_list * unused)1517 ia64_mca_cmc_poll (struct timer_list *unused)
1518 {
1519 /* Trigger a CMC interrupt cascade */
1520 ia64_send_ipi(cpumask_first(cpu_online_mask), IA64_CMCP_VECTOR,
1521 IA64_IPI_DM_INT, 0);
1522 }
1523
1524 /*
1525 * ia64_mca_cpe_int_caller
1526 *
1527 * Triggered by sw interrupt from CPE polling routine. Calls
1528 * real interrupt handler and either triggers a sw interrupt
1529 * on the next cpu or does cleanup at the end.
1530 *
1531 * Inputs
1532 * interrupt number
1533 * client data arg ptr
1534 * Outputs
1535 * handled
1536 */
1537 static irqreturn_t
ia64_mca_cpe_int_caller(int cpe_irq,void * arg)1538 ia64_mca_cpe_int_caller(int cpe_irq, void *arg)
1539 {
1540 static int start_count = -1;
1541 static int poll_time = MIN_CPE_POLL_INTERVAL;
1542 unsigned int cpuid;
1543
1544 cpuid = smp_processor_id();
1545
1546 /* If first cpu, update count */
1547 if (start_count == -1)
1548 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CPE);
1549
1550 ia64_mca_cpe_int_handler(cpe_irq, arg);
1551
1552 cpuid = cpumask_next(cpuid+1, cpu_online_mask);
1553
1554 if (cpuid < NR_CPUS) {
1555 ia64_send_ipi(cpuid, IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1556 } else {
1557 /*
1558 * If a log was recorded, increase our polling frequency,
1559 * otherwise, backoff or return to interrupt mode.
1560 */
1561 if (start_count != IA64_LOG_COUNT(SAL_INFO_TYPE_CPE)) {
1562 poll_time = max(MIN_CPE_POLL_INTERVAL, poll_time / 2);
1563 } else if (cpe_vector < 0) {
1564 poll_time = min(MAX_CPE_POLL_INTERVAL, poll_time * 2);
1565 } else {
1566 poll_time = MIN_CPE_POLL_INTERVAL;
1567
1568 printk(KERN_WARNING "Returning to interrupt driven CPE handler\n");
1569 enable_irq(local_vector_to_irq(IA64_CPE_VECTOR));
1570 cpe_poll_enabled = 0;
1571 }
1572
1573 if (cpe_poll_enabled)
1574 mod_timer(&cpe_poll_timer, jiffies + poll_time);
1575 start_count = -1;
1576 }
1577
1578 return IRQ_HANDLED;
1579 }
1580
1581 /*
1582 * ia64_mca_cpe_poll
1583 *
1584 * Poll for Corrected Platform Errors (CPEs), trigger interrupt
1585 * on first cpu, from there it will trickle through all the cpus.
1586 *
1587 * Inputs : dummy(unused)
1588 * Outputs : None
1589 *
1590 */
1591 static void
ia64_mca_cpe_poll(struct timer_list * unused)1592 ia64_mca_cpe_poll (struct timer_list *unused)
1593 {
1594 /* Trigger a CPE interrupt cascade */
1595 ia64_send_ipi(cpumask_first(cpu_online_mask), IA64_CPEP_VECTOR,
1596 IA64_IPI_DM_INT, 0);
1597 }
1598
1599 static int
default_monarch_init_process(struct notifier_block * self,unsigned long val,void * data)1600 default_monarch_init_process(struct notifier_block *self, unsigned long val, void *data)
1601 {
1602 int c;
1603 struct task_struct *g, *t;
1604 if (val != DIE_INIT_MONARCH_PROCESS)
1605 return NOTIFY_DONE;
1606 #ifdef CONFIG_KEXEC
1607 if (atomic_read(&kdump_in_progress))
1608 return NOTIFY_DONE;
1609 #endif
1610
1611 /*
1612 * FIXME: mlogbuf will brim over with INIT stack dumps.
1613 * To enable show_stack from INIT, we use oops_in_progress which should
1614 * be used in real oops. This would cause something wrong after INIT.
1615 */
1616 BREAK_LOGLEVEL(console_loglevel);
1617 ia64_mlogbuf_dump_from_init();
1618
1619 printk(KERN_ERR "Processes interrupted by INIT -");
1620 for_each_online_cpu(c) {
1621 struct ia64_sal_os_state *s;
1622 t = __va(__per_cpu_mca[c] + IA64_MCA_CPU_INIT_STACK_OFFSET);
1623 s = (struct ia64_sal_os_state *)((char *)t + MCA_SOS_OFFSET);
1624 g = s->prev_task;
1625 if (g) {
1626 if (g->pid)
1627 printk(" %d", g->pid);
1628 else
1629 printk(" %d (cpu %d task 0x%p)", g->pid, task_cpu(g), g);
1630 }
1631 }
1632 printk("\n\n");
1633 if (read_trylock(&tasklist_lock)) {
1634 do_each_thread (g, t) {
1635 printk("\nBacktrace of pid %d (%s)\n", t->pid, t->comm);
1636 show_stack(t, NULL, KERN_DEFAULT);
1637 } while_each_thread (g, t);
1638 read_unlock(&tasklist_lock);
1639 }
1640 /* FIXME: This will not restore zapped printk locks. */
1641 RESTORE_LOGLEVEL(console_loglevel);
1642 return NOTIFY_DONE;
1643 }
1644
1645 /*
1646 * C portion of the OS INIT handler
1647 *
1648 * Called from ia64_os_init_dispatch
1649 *
1650 * Inputs: pointer to pt_regs where processor info was saved. SAL/OS state for
1651 * this event. This code is used for both monarch and slave INIT events, see
1652 * sos->monarch.
1653 *
1654 * All INIT events switch to the INIT stack and change the previous process to
1655 * blocked status. If one of the INIT events is the monarch then we are
1656 * probably processing the nmi button/command. Use the monarch cpu to dump all
1657 * the processes. The slave INIT events all spin until the monarch cpu
1658 * returns. We can also get INIT slave events for MCA, in which case the MCA
1659 * process is the monarch.
1660 */
1661
1662 void
ia64_init_handler(struct pt_regs * regs,struct switch_stack * sw,struct ia64_sal_os_state * sos)1663 ia64_init_handler(struct pt_regs *regs, struct switch_stack *sw,
1664 struct ia64_sal_os_state *sos)
1665 {
1666 static atomic_t slaves;
1667 static atomic_t monarchs;
1668 struct task_struct *previous_current;
1669 int cpu = smp_processor_id();
1670 struct ia64_mca_notify_die nd =
1671 { .sos = sos, .monarch_cpu = &monarch_cpu };
1672
1673 NOTIFY_INIT(DIE_INIT_ENTER, regs, (long)&nd, 0);
1674
1675 mprintk(KERN_INFO "Entered OS INIT handler. PSP=%lx cpu=%d monarch=%ld\n",
1676 sos->proc_state_param, cpu, sos->monarch);
1677 salinfo_log_wakeup(SAL_INFO_TYPE_INIT, NULL, 0, 0);
1678
1679 previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "INIT");
1680 sos->os_status = IA64_INIT_RESUME;
1681
1682 /* FIXME: Workaround for broken proms that drive all INIT events as
1683 * slaves. The last slave that enters is promoted to be a monarch.
1684 * Remove this code in September 2006, that gives platforms a year to
1685 * fix their proms and get their customers updated.
1686 */
1687 if (!sos->monarch && atomic_add_return(1, &slaves) == num_online_cpus()) {
1688 mprintk(KERN_WARNING "%s: Promoting cpu %d to monarch.\n",
1689 __func__, cpu);
1690 atomic_dec(&slaves);
1691 sos->monarch = 1;
1692 }
1693
1694 /* FIXME: Workaround for broken proms that drive all INIT events as
1695 * monarchs. Second and subsequent monarchs are demoted to slaves.
1696 * Remove this code in September 2006, that gives platforms a year to
1697 * fix their proms and get their customers updated.
1698 */
1699 if (sos->monarch && atomic_add_return(1, &monarchs) > 1) {
1700 mprintk(KERN_WARNING "%s: Demoting cpu %d to slave.\n",
1701 __func__, cpu);
1702 atomic_dec(&monarchs);
1703 sos->monarch = 0;
1704 }
1705
1706 if (!sos->monarch) {
1707 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_INIT;
1708
1709 #ifdef CONFIG_KEXEC
1710 while (monarch_cpu == -1 && !atomic_read(&kdump_in_progress))
1711 udelay(1000);
1712 #else
1713 while (monarch_cpu == -1)
1714 cpu_relax(); /* spin until monarch enters */
1715 #endif
1716
1717 NOTIFY_INIT(DIE_INIT_SLAVE_ENTER, regs, (long)&nd, 1);
1718 NOTIFY_INIT(DIE_INIT_SLAVE_PROCESS, regs, (long)&nd, 1);
1719
1720 #ifdef CONFIG_KEXEC
1721 while (monarch_cpu != -1 && !atomic_read(&kdump_in_progress))
1722 udelay(1000);
1723 #else
1724 while (monarch_cpu != -1)
1725 cpu_relax(); /* spin until monarch leaves */
1726 #endif
1727
1728 NOTIFY_INIT(DIE_INIT_SLAVE_LEAVE, regs, (long)&nd, 1);
1729
1730 mprintk("Slave on cpu %d returning to normal service.\n", cpu);
1731 ia64_set_curr_task(cpu, previous_current);
1732 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1733 atomic_dec(&slaves);
1734 return;
1735 }
1736
1737 monarch_cpu = cpu;
1738 NOTIFY_INIT(DIE_INIT_MONARCH_ENTER, regs, (long)&nd, 1);
1739
1740 /*
1741 * Wait for a bit. On some machines (e.g., HP's zx2000 and zx6000, INIT can be
1742 * generated via the BMC's command-line interface, but since the console is on the
1743 * same serial line, the user will need some time to switch out of the BMC before
1744 * the dump begins.
1745 */
1746 mprintk("Delaying for 5 seconds...\n");
1747 udelay(5*1000000);
1748 ia64_wait_for_slaves(cpu, "INIT");
1749 /* If nobody intercepts DIE_INIT_MONARCH_PROCESS then we drop through
1750 * to default_monarch_init_process() above and just print all the
1751 * tasks.
1752 */
1753 NOTIFY_INIT(DIE_INIT_MONARCH_PROCESS, regs, (long)&nd, 1);
1754 NOTIFY_INIT(DIE_INIT_MONARCH_LEAVE, regs, (long)&nd, 1);
1755
1756 mprintk("\nINIT dump complete. Monarch on cpu %d returning to normal service.\n", cpu);
1757 atomic_dec(&monarchs);
1758 ia64_set_curr_task(cpu, previous_current);
1759 monarch_cpu = -1;
1760 return;
1761 }
1762
1763 static int __init
ia64_mca_disable_cpe_polling(char * str)1764 ia64_mca_disable_cpe_polling(char *str)
1765 {
1766 cpe_poll_enabled = 0;
1767 return 1;
1768 }
1769
1770 __setup("disable_cpe_poll", ia64_mca_disable_cpe_polling);
1771
1772 /* Minimal format of the MCA/INIT stacks. The pseudo processes that run on
1773 * these stacks can never sleep, they cannot return from the kernel to user
1774 * space, they do not appear in a normal ps listing. So there is no need to
1775 * format most of the fields.
1776 */
1777
1778 static void
format_mca_init_stack(void * mca_data,unsigned long offset,const char * type,int cpu)1779 format_mca_init_stack(void *mca_data, unsigned long offset,
1780 const char *type, int cpu)
1781 {
1782 struct task_struct *p = (struct task_struct *)((char *)mca_data + offset);
1783 struct thread_info *ti;
1784 memset(p, 0, KERNEL_STACK_SIZE);
1785 ti = task_thread_info(p);
1786 ti->flags = _TIF_MCA_INIT;
1787 ti->preempt_count = 1;
1788 ti->task = p;
1789 ti->cpu = cpu;
1790 p->stack = ti;
1791 p->state = TASK_UNINTERRUPTIBLE;
1792 cpumask_set_cpu(cpu, &p->cpus_mask);
1793 INIT_LIST_HEAD(&p->tasks);
1794 p->parent = p->real_parent = p->group_leader = p;
1795 INIT_LIST_HEAD(&p->children);
1796 INIT_LIST_HEAD(&p->sibling);
1797 strncpy(p->comm, type, sizeof(p->comm)-1);
1798 }
1799
1800 /* Caller prevents this from being called after init */
mca_bootmem(void)1801 static void * __ref mca_bootmem(void)
1802 {
1803 return memblock_alloc(sizeof(struct ia64_mca_cpu), KERNEL_STACK_SIZE);
1804 }
1805
1806 /* Do per-CPU MCA-related initialization. */
1807 void
ia64_mca_cpu_init(void * cpu_data)1808 ia64_mca_cpu_init(void *cpu_data)
1809 {
1810 void *pal_vaddr;
1811 void *data;
1812 long sz = sizeof(struct ia64_mca_cpu);
1813 int cpu = smp_processor_id();
1814 static int first_time = 1;
1815
1816 /*
1817 * Structure will already be allocated if cpu has been online,
1818 * then offlined.
1819 */
1820 if (__per_cpu_mca[cpu]) {
1821 data = __va(__per_cpu_mca[cpu]);
1822 } else {
1823 if (first_time) {
1824 data = mca_bootmem();
1825 first_time = 0;
1826 } else
1827 data = (void *)__get_free_pages(GFP_ATOMIC,
1828 get_order(sz));
1829 if (!data)
1830 panic("Could not allocate MCA memory for cpu %d\n",
1831 cpu);
1832 }
1833 format_mca_init_stack(data, offsetof(struct ia64_mca_cpu, mca_stack),
1834 "MCA", cpu);
1835 format_mca_init_stack(data, offsetof(struct ia64_mca_cpu, init_stack),
1836 "INIT", cpu);
1837 __this_cpu_write(ia64_mca_data, (__per_cpu_mca[cpu] = __pa(data)));
1838
1839 /*
1840 * Stash away a copy of the PTE needed to map the per-CPU page.
1841 * We may need it during MCA recovery.
1842 */
1843 __this_cpu_write(ia64_mca_per_cpu_pte,
1844 pte_val(mk_pte_phys(__pa(cpu_data), PAGE_KERNEL)));
1845
1846 /*
1847 * Also, stash away a copy of the PAL address and the PTE
1848 * needed to map it.
1849 */
1850 pal_vaddr = efi_get_pal_addr();
1851 if (!pal_vaddr)
1852 return;
1853 __this_cpu_write(ia64_mca_pal_base,
1854 GRANULEROUNDDOWN((unsigned long) pal_vaddr));
1855 __this_cpu_write(ia64_mca_pal_pte, pte_val(mk_pte_phys(__pa(pal_vaddr),
1856 PAGE_KERNEL)));
1857 }
1858
ia64_mca_cpu_online(unsigned int cpu)1859 static int ia64_mca_cpu_online(unsigned int cpu)
1860 {
1861 unsigned long flags;
1862
1863 local_irq_save(flags);
1864 if (!cmc_polling_enabled)
1865 ia64_mca_cmc_vector_enable(NULL);
1866 local_irq_restore(flags);
1867 return 0;
1868 }
1869
1870 /*
1871 * ia64_mca_init
1872 *
1873 * Do all the system level mca specific initialization.
1874 *
1875 * 1. Register spinloop and wakeup request interrupt vectors
1876 *
1877 * 2. Register OS_MCA handler entry point
1878 *
1879 * 3. Register OS_INIT handler entry point
1880 *
1881 * 4. Initialize MCA/CMC/INIT related log buffers maintained by the OS.
1882 *
1883 * Note that this initialization is done very early before some kernel
1884 * services are available.
1885 *
1886 * Inputs : None
1887 *
1888 * Outputs : None
1889 */
1890 void __init
ia64_mca_init(void)1891 ia64_mca_init(void)
1892 {
1893 ia64_fptr_t *init_hldlr_ptr_monarch = (ia64_fptr_t *)ia64_os_init_dispatch_monarch;
1894 ia64_fptr_t *init_hldlr_ptr_slave = (ia64_fptr_t *)ia64_os_init_dispatch_slave;
1895 ia64_fptr_t *mca_hldlr_ptr = (ia64_fptr_t *)ia64_os_mca_dispatch;
1896 int i;
1897 long rc;
1898 struct ia64_sal_retval isrv;
1899 unsigned long timeout = IA64_MCA_RENDEZ_TIMEOUT; /* platform specific */
1900 static struct notifier_block default_init_monarch_nb = {
1901 .notifier_call = default_monarch_init_process,
1902 .priority = 0/* we need to notified last */
1903 };
1904
1905 IA64_MCA_DEBUG("%s: begin\n", __func__);
1906
1907 /* Clear the Rendez checkin flag for all cpus */
1908 for(i = 0 ; i < NR_CPUS; i++)
1909 ia64_mc_info.imi_rendez_checkin[i] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1910
1911 /*
1912 * Register the rendezvous spinloop and wakeup mechanism with SAL
1913 */
1914
1915 /* Register the rendezvous interrupt vector with SAL */
1916 while (1) {
1917 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_INT,
1918 SAL_MC_PARAM_MECHANISM_INT,
1919 IA64_MCA_RENDEZ_VECTOR,
1920 timeout,
1921 SAL_MC_PARAM_RZ_ALWAYS);
1922 rc = isrv.status;
1923 if (rc == 0)
1924 break;
1925 if (rc == -2) {
1926 printk(KERN_INFO "Increasing MCA rendezvous timeout from "
1927 "%ld to %ld milliseconds\n", timeout, isrv.v0);
1928 timeout = isrv.v0;
1929 NOTIFY_MCA(DIE_MCA_NEW_TIMEOUT, NULL, timeout, 0);
1930 continue;
1931 }
1932 printk(KERN_ERR "Failed to register rendezvous interrupt "
1933 "with SAL (status %ld)\n", rc);
1934 return;
1935 }
1936
1937 /* Register the wakeup interrupt vector with SAL */
1938 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_WAKEUP,
1939 SAL_MC_PARAM_MECHANISM_INT,
1940 IA64_MCA_WAKEUP_VECTOR,
1941 0, 0);
1942 rc = isrv.status;
1943 if (rc) {
1944 printk(KERN_ERR "Failed to register wakeup interrupt with SAL "
1945 "(status %ld)\n", rc);
1946 return;
1947 }
1948
1949 IA64_MCA_DEBUG("%s: registered MCA rendezvous spinloop and wakeup mech.\n", __func__);
1950
1951 ia64_mc_info.imi_mca_handler = ia64_tpa(mca_hldlr_ptr->fp);
1952 /*
1953 * XXX - disable SAL checksum by setting size to 0; should be
1954 * ia64_tpa(ia64_os_mca_dispatch_end) - ia64_tpa(ia64_os_mca_dispatch);
1955 */
1956 ia64_mc_info.imi_mca_handler_size = 0;
1957
1958 /* Register the os mca handler with SAL */
1959 if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_MCA,
1960 ia64_mc_info.imi_mca_handler,
1961 ia64_tpa(mca_hldlr_ptr->gp),
1962 ia64_mc_info.imi_mca_handler_size,
1963 0, 0, 0)))
1964 {
1965 printk(KERN_ERR "Failed to register OS MCA handler with SAL "
1966 "(status %ld)\n", rc);
1967 return;
1968 }
1969
1970 IA64_MCA_DEBUG("%s: registered OS MCA handler with SAL at 0x%lx, gp = 0x%lx\n", __func__,
1971 ia64_mc_info.imi_mca_handler, ia64_tpa(mca_hldlr_ptr->gp));
1972
1973 /*
1974 * XXX - disable SAL checksum by setting size to 0, should be
1975 * size of the actual init handler in mca_asm.S.
1976 */
1977 ia64_mc_info.imi_monarch_init_handler = ia64_tpa(init_hldlr_ptr_monarch->fp);
1978 ia64_mc_info.imi_monarch_init_handler_size = 0;
1979 ia64_mc_info.imi_slave_init_handler = ia64_tpa(init_hldlr_ptr_slave->fp);
1980 ia64_mc_info.imi_slave_init_handler_size = 0;
1981
1982 IA64_MCA_DEBUG("%s: OS INIT handler at %lx\n", __func__,
1983 ia64_mc_info.imi_monarch_init_handler);
1984
1985 /* Register the os init handler with SAL */
1986 if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_INIT,
1987 ia64_mc_info.imi_monarch_init_handler,
1988 ia64_tpa(ia64_getreg(_IA64_REG_GP)),
1989 ia64_mc_info.imi_monarch_init_handler_size,
1990 ia64_mc_info.imi_slave_init_handler,
1991 ia64_tpa(ia64_getreg(_IA64_REG_GP)),
1992 ia64_mc_info.imi_slave_init_handler_size)))
1993 {
1994 printk(KERN_ERR "Failed to register m/s INIT handlers with SAL "
1995 "(status %ld)\n", rc);
1996 return;
1997 }
1998 if (register_die_notifier(&default_init_monarch_nb)) {
1999 printk(KERN_ERR "Failed to register default monarch INIT process\n");
2000 return;
2001 }
2002
2003 IA64_MCA_DEBUG("%s: registered OS INIT handler with SAL\n", __func__);
2004
2005 /* Initialize the areas set aside by the OS to buffer the
2006 * platform/processor error states for MCA/INIT/CMC
2007 * handling.
2008 */
2009 ia64_log_init(SAL_INFO_TYPE_MCA);
2010 ia64_log_init(SAL_INFO_TYPE_INIT);
2011 ia64_log_init(SAL_INFO_TYPE_CMC);
2012 ia64_log_init(SAL_INFO_TYPE_CPE);
2013
2014 mca_init = 1;
2015 printk(KERN_INFO "MCA related initialization done\n");
2016 }
2017
2018
2019 /*
2020 * These pieces cannot be done in ia64_mca_init() because it is called before
2021 * early_irq_init() which would wipe out our percpu irq registrations. But we
2022 * cannot leave them until ia64_mca_late_init() because by then all the other
2023 * processors have been brought online and have set their own CMC vectors to
2024 * point at a non-existant action. Called from arch_early_irq_init().
2025 */
ia64_mca_irq_init(void)2026 void __init ia64_mca_irq_init(void)
2027 {
2028 /*
2029 * Configure the CMCI/P vector and handler. Interrupts for CMC are
2030 * per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c).
2031 */
2032 register_percpu_irq(IA64_CMC_VECTOR, ia64_mca_cmc_int_handler, 0,
2033 "cmc_hndlr");
2034 register_percpu_irq(IA64_CMCP_VECTOR, ia64_mca_cmc_int_caller, 0,
2035 "cmc_poll");
2036 ia64_mca_cmc_vector_setup(); /* Setup vector on BSP */
2037
2038 /* Setup the MCA rendezvous interrupt vector */
2039 register_percpu_irq(IA64_MCA_RENDEZ_VECTOR, ia64_mca_rendez_int_handler,
2040 0, "mca_rdzv");
2041
2042 /* Setup the MCA wakeup interrupt vector */
2043 register_percpu_irq(IA64_MCA_WAKEUP_VECTOR, ia64_mca_wakeup_int_handler,
2044 0, "mca_wkup");
2045
2046 /* Setup the CPEI/P handler */
2047 register_percpu_irq(IA64_CPEP_VECTOR, ia64_mca_cpe_int_caller, 0,
2048 "cpe_poll");
2049 }
2050
2051 /*
2052 * ia64_mca_late_init
2053 *
2054 * Opportunity to setup things that require initialization later
2055 * than ia64_mca_init. Setup a timer to poll for CPEs if the
2056 * platform doesn't support an interrupt driven mechanism.
2057 *
2058 * Inputs : None
2059 * Outputs : Status
2060 */
2061 static int __init
ia64_mca_late_init(void)2062 ia64_mca_late_init(void)
2063 {
2064 if (!mca_init)
2065 return 0;
2066
2067 /* Setup the CMCI/P vector and handler */
2068 timer_setup(&cmc_poll_timer, ia64_mca_cmc_poll, 0);
2069
2070 /* Unmask/enable the vector */
2071 cmc_polling_enabled = 0;
2072 cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "ia64/mca:online",
2073 ia64_mca_cpu_online, NULL);
2074 IA64_MCA_DEBUG("%s: CMCI/P setup and enabled.\n", __func__);
2075
2076 /* Setup the CPEI/P vector and handler */
2077 cpe_vector = acpi_request_vector(ACPI_INTERRUPT_CPEI);
2078 timer_setup(&cpe_poll_timer, ia64_mca_cpe_poll, 0);
2079
2080 {
2081 unsigned int irq;
2082
2083 if (cpe_vector >= 0) {
2084 /* If platform supports CPEI, enable the irq. */
2085 irq = local_vector_to_irq(cpe_vector);
2086 if (irq > 0) {
2087 cpe_poll_enabled = 0;
2088 irq_set_status_flags(irq, IRQ_PER_CPU);
2089 if (request_irq(irq, ia64_mca_cpe_int_handler,
2090 0, "cpe_hndlr", NULL))
2091 pr_err("Failed to register cpe_hndlr interrupt\n");
2092 ia64_cpe_irq = irq;
2093 ia64_mca_register_cpev(cpe_vector);
2094 IA64_MCA_DEBUG("%s: CPEI/P setup and enabled.\n",
2095 __func__);
2096 return 0;
2097 }
2098 printk(KERN_ERR "%s: Failed to find irq for CPE "
2099 "interrupt handler, vector %d\n",
2100 __func__, cpe_vector);
2101 }
2102 /* If platform doesn't support CPEI, get the timer going. */
2103 if (cpe_poll_enabled) {
2104 ia64_mca_cpe_poll(0UL);
2105 IA64_MCA_DEBUG("%s: CPEP setup and enabled.\n", __func__);
2106 }
2107 }
2108
2109 return 0;
2110 }
2111
2112 device_initcall(ia64_mca_late_init);
2113