1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _PARISC_PGTABLE_H
3 #define _PARISC_PGTABLE_H
4
5 #include <asm/page.h>
6
7 #if CONFIG_PGTABLE_LEVELS == 3
8 #include <asm-generic/pgtable-nopud.h>
9 #elif CONFIG_PGTABLE_LEVELS == 2
10 #include <asm-generic/pgtable-nopmd.h>
11 #endif
12
13 #include <asm/fixmap.h>
14
15 #ifndef __ASSEMBLY__
16 /*
17 * we simulate an x86-style page table for the linux mm code
18 */
19
20 #include <linux/bitops.h>
21 #include <linux/spinlock.h>
22 #include <linux/mm_types.h>
23 #include <asm/processor.h>
24 #include <asm/cache.h>
25
26 /*
27 * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel
28 * memory. For the return value to be meaningful, ADDR must be >=
29 * PAGE_OFFSET. This operation can be relatively expensive (e.g.,
30 * require a hash-, or multi-level tree-lookup or something of that
31 * sort) but it guarantees to return TRUE only if accessing the page
32 * at that address does not cause an error. Note that there may be
33 * addresses for which kern_addr_valid() returns FALSE even though an
34 * access would not cause an error (e.g., this is typically true for
35 * memory mapped I/O regions.
36 *
37 * XXX Need to implement this for parisc.
38 */
39 #define kern_addr_valid(addr) (1)
40
41 /* This is for the serialization of PxTLB broadcasts. At least on the N class
42 * systems, only one PxTLB inter processor broadcast can be active at any one
43 * time on the Merced bus. */
44 extern spinlock_t pa_tlb_flush_lock;
45 #if defined(CONFIG_64BIT) && defined(CONFIG_SMP)
46 extern int pa_serialize_tlb_flushes;
47 #else
48 #define pa_serialize_tlb_flushes (0)
49 #endif
50
51 #define purge_tlb_start(flags) do { \
52 if (pa_serialize_tlb_flushes) \
53 spin_lock_irqsave(&pa_tlb_flush_lock, flags); \
54 else \
55 local_irq_save(flags); \
56 } while (0)
57 #define purge_tlb_end(flags) do { \
58 if (pa_serialize_tlb_flushes) \
59 spin_unlock_irqrestore(&pa_tlb_flush_lock, flags); \
60 else \
61 local_irq_restore(flags); \
62 } while (0)
63
64 /* Purge data and instruction TLB entries. The TLB purge instructions
65 * are slow on SMP machines since the purge must be broadcast to all CPUs.
66 */
67
purge_tlb_entries(struct mm_struct * mm,unsigned long addr)68 static inline void purge_tlb_entries(struct mm_struct *mm, unsigned long addr)
69 {
70 unsigned long flags;
71
72 purge_tlb_start(flags);
73 mtsp(mm->context, 1);
74 pdtlb(addr);
75 pitlb(addr);
76 purge_tlb_end(flags);
77 }
78
79 /* Certain architectures need to do special things when PTEs
80 * within a page table are directly modified. Thus, the following
81 * hook is made available.
82 */
83 #define set_pte(pteptr, pteval) \
84 do { \
85 *(pteptr) = (pteval); \
86 barrier(); \
87 } while(0)
88
89 #define set_pte_at(mm, addr, pteptr, pteval) \
90 do { \
91 *(pteptr) = (pteval); \
92 purge_tlb_entries(mm, addr); \
93 } while (0)
94
95 #endif /* !__ASSEMBLY__ */
96
97 #define pte_ERROR(e) \
98 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
99 #if CONFIG_PGTABLE_LEVELS == 3
100 #define pmd_ERROR(e) \
101 printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, (unsigned long)pmd_val(e))
102 #endif
103 #define pgd_ERROR(e) \
104 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, (unsigned long)pgd_val(e))
105
106 /* This is the size of the initially mapped kernel memory */
107 #if defined(CONFIG_64BIT)
108 #define KERNEL_INITIAL_ORDER 26 /* 1<<26 = 64MB */
109 #else
110 #define KERNEL_INITIAL_ORDER 25 /* 1<<25 = 32MB */
111 #endif
112 #define KERNEL_INITIAL_SIZE (1 << KERNEL_INITIAL_ORDER)
113
114 #if CONFIG_PGTABLE_LEVELS == 3
115 #define PMD_ORDER 1
116 #define PGD_ORDER 0
117 #else
118 #define PGD_ORDER 1
119 #endif
120
121 /* Definitions for 3rd level (we use PLD here for Page Lower directory
122 * because PTE_SHIFT is used lower down to mean shift that has to be
123 * done to get usable bits out of the PTE) */
124 #define PLD_SHIFT PAGE_SHIFT
125 #define PLD_SIZE PAGE_SIZE
126 #define BITS_PER_PTE (PAGE_SHIFT - BITS_PER_PTE_ENTRY)
127 #define PTRS_PER_PTE (1UL << BITS_PER_PTE)
128
129 /* Definitions for 2nd level */
130 #if CONFIG_PGTABLE_LEVELS == 3
131 #define PMD_SHIFT (PLD_SHIFT + BITS_PER_PTE)
132 #define PMD_SIZE (1UL << PMD_SHIFT)
133 #define PMD_MASK (~(PMD_SIZE-1))
134 #define BITS_PER_PMD (PAGE_SHIFT + PMD_ORDER - BITS_PER_PMD_ENTRY)
135 #define PTRS_PER_PMD (1UL << BITS_PER_PMD)
136 #else
137 #define BITS_PER_PMD 0
138 #endif
139
140 /* Definitions for 1st level */
141 #define PGDIR_SHIFT (PLD_SHIFT + BITS_PER_PTE + BITS_PER_PMD)
142 #if (PGDIR_SHIFT + PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY) > BITS_PER_LONG
143 #define BITS_PER_PGD (BITS_PER_LONG - PGDIR_SHIFT)
144 #else
145 #define BITS_PER_PGD (PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY)
146 #endif
147 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
148 #define PGDIR_MASK (~(PGDIR_SIZE-1))
149 #define PTRS_PER_PGD (1UL << BITS_PER_PGD)
150 #define USER_PTRS_PER_PGD PTRS_PER_PGD
151
152 #ifdef CONFIG_64BIT
153 #define MAX_ADDRBITS (PGDIR_SHIFT + BITS_PER_PGD)
154 #define MAX_ADDRESS (1UL << MAX_ADDRBITS)
155 #define SPACEID_SHIFT (MAX_ADDRBITS - 32)
156 #else
157 #define MAX_ADDRBITS (BITS_PER_LONG)
158 #define MAX_ADDRESS (1UL << MAX_ADDRBITS)
159 #define SPACEID_SHIFT 0
160 #endif
161
162 /* This calculates the number of initial pages we need for the initial
163 * page tables */
164 #if (KERNEL_INITIAL_ORDER) >= (PMD_SHIFT)
165 # define PT_INITIAL (1 << (KERNEL_INITIAL_ORDER - PMD_SHIFT))
166 #else
167 # define PT_INITIAL (1) /* all initial PTEs fit into one page */
168 #endif
169
170 /*
171 * pgd entries used up by user/kernel:
172 */
173
174 #define FIRST_USER_ADDRESS 0UL
175
176 /* NB: The tlb miss handlers make certain assumptions about the order */
177 /* of the following bits, so be careful (One example, bits 25-31 */
178 /* are moved together in one instruction). */
179
180 #define _PAGE_READ_BIT 31 /* (0x001) read access allowed */
181 #define _PAGE_WRITE_BIT 30 /* (0x002) write access allowed */
182 #define _PAGE_EXEC_BIT 29 /* (0x004) execute access allowed */
183 #define _PAGE_GATEWAY_BIT 28 /* (0x008) privilege promotion allowed */
184 #define _PAGE_DMB_BIT 27 /* (0x010) Data Memory Break enable (B bit) */
185 #define _PAGE_DIRTY_BIT 26 /* (0x020) Page Dirty (D bit) */
186 #define _PAGE_REFTRAP_BIT 25 /* (0x040) Page Ref. Trap enable (T bit) */
187 #define _PAGE_NO_CACHE_BIT 24 /* (0x080) Uncached Page (U bit) */
188 #define _PAGE_ACCESSED_BIT 23 /* (0x100) Software: Page Accessed */
189 #define _PAGE_PRESENT_BIT 22 /* (0x200) Software: translation valid */
190 #define _PAGE_HPAGE_BIT 21 /* (0x400) Software: Huge Page */
191 #define _PAGE_USER_BIT 20 /* (0x800) Software: User accessible page */
192
193 /* N.B. The bits are defined in terms of a 32 bit word above, so the */
194 /* following macro is ok for both 32 and 64 bit. */
195
196 #define xlate_pabit(x) (31 - x)
197
198 /* this defines the shift to the usable bits in the PTE it is set so
199 * that the valid bits _PAGE_PRESENT_BIT and _PAGE_USER_BIT are set
200 * to zero */
201 #define PTE_SHIFT xlate_pabit(_PAGE_USER_BIT)
202
203 /* PFN_PTE_SHIFT defines the shift of a PTE value to access the PFN field */
204 #define PFN_PTE_SHIFT 12
205
206 #define _PAGE_READ (1 << xlate_pabit(_PAGE_READ_BIT))
207 #define _PAGE_WRITE (1 << xlate_pabit(_PAGE_WRITE_BIT))
208 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)
209 #define _PAGE_EXEC (1 << xlate_pabit(_PAGE_EXEC_BIT))
210 #define _PAGE_GATEWAY (1 << xlate_pabit(_PAGE_GATEWAY_BIT))
211 #define _PAGE_DMB (1 << xlate_pabit(_PAGE_DMB_BIT))
212 #define _PAGE_DIRTY (1 << xlate_pabit(_PAGE_DIRTY_BIT))
213 #define _PAGE_REFTRAP (1 << xlate_pabit(_PAGE_REFTRAP_BIT))
214 #define _PAGE_NO_CACHE (1 << xlate_pabit(_PAGE_NO_CACHE_BIT))
215 #define _PAGE_ACCESSED (1 << xlate_pabit(_PAGE_ACCESSED_BIT))
216 #define _PAGE_PRESENT (1 << xlate_pabit(_PAGE_PRESENT_BIT))
217 #define _PAGE_HUGE (1 << xlate_pabit(_PAGE_HPAGE_BIT))
218 #define _PAGE_USER (1 << xlate_pabit(_PAGE_USER_BIT))
219
220 #define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_ACCESSED)
221 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
222 #define _PAGE_KERNEL_RO (_PAGE_PRESENT | _PAGE_READ | _PAGE_DIRTY | _PAGE_ACCESSED)
223 #define _PAGE_KERNEL_EXEC (_PAGE_KERNEL_RO | _PAGE_EXEC)
224 #define _PAGE_KERNEL_RWX (_PAGE_KERNEL_EXEC | _PAGE_WRITE)
225 #define _PAGE_KERNEL (_PAGE_KERNEL_RO | _PAGE_WRITE)
226
227 /* The pgd/pmd contains a ptr (in phys addr space); since all pgds/pmds
228 * are page-aligned, we don't care about the PAGE_OFFSET bits, except
229 * for a few meta-information bits, so we shift the address to be
230 * able to effectively address 40/42/44-bits of physical address space
231 * depending on 4k/16k/64k PAGE_SIZE */
232 #define _PxD_PRESENT_BIT 31
233 #define _PxD_VALID_BIT 30
234
235 #define PxD_FLAG_PRESENT (1 << xlate_pabit(_PxD_PRESENT_BIT))
236 #define PxD_FLAG_VALID (1 << xlate_pabit(_PxD_VALID_BIT))
237 #define PxD_FLAG_MASK (0xf)
238 #define PxD_FLAG_SHIFT (4)
239 #define PxD_VALUE_SHIFT (PFN_PTE_SHIFT-PxD_FLAG_SHIFT)
240
241 #ifndef __ASSEMBLY__
242
243 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_USER)
244 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE)
245 /* Others seem to make this executable, I don't know if that's correct
246 or not. The stack is mapped this way though so this is necessary
247 in the short term - dhd@linuxcare.com, 2000-08-08 */
248 #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ)
249 #define PAGE_WRITEONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITE)
250 #define PAGE_EXECREAD __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_EXEC)
251 #define PAGE_COPY PAGE_EXECREAD
252 #define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)
253 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL)
254 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL_EXEC)
255 #define PAGE_KERNEL_RWX __pgprot(_PAGE_KERNEL_RWX)
256 #define PAGE_KERNEL_RO __pgprot(_PAGE_KERNEL_RO)
257 #define PAGE_KERNEL_UNC __pgprot(_PAGE_KERNEL | _PAGE_NO_CACHE)
258 #define PAGE_GATEWAY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_GATEWAY| _PAGE_READ)
259
260
261 /*
262 * We could have an execute only page using "gateway - promote to priv
263 * level 3", but that is kind of silly. So, the way things are defined
264 * now, we must always have read permission for pages with execute
265 * permission. For the fun of it we'll go ahead and support write only
266 * pages.
267 */
268
269 /*xwr*/
270 #define __P000 PAGE_NONE
271 #define __P001 PAGE_READONLY
272 #define __P010 __P000 /* copy on write */
273 #define __P011 __P001 /* copy on write */
274 #define __P100 PAGE_EXECREAD
275 #define __P101 PAGE_EXECREAD
276 #define __P110 __P100 /* copy on write */
277 #define __P111 __P101 /* copy on write */
278
279 #define __S000 PAGE_NONE
280 #define __S001 PAGE_READONLY
281 #define __S010 PAGE_WRITEONLY
282 #define __S011 PAGE_SHARED
283 #define __S100 PAGE_EXECREAD
284 #define __S101 PAGE_EXECREAD
285 #define __S110 PAGE_RWX
286 #define __S111 PAGE_RWX
287
288
289 extern pgd_t swapper_pg_dir[]; /* declared in init_task.c */
290
291 /* initial page tables for 0-8MB for kernel */
292
293 extern pte_t pg0[];
294
295 /* zero page used for uninitialized stuff */
296
297 extern unsigned long *empty_zero_page;
298
299 /*
300 * ZERO_PAGE is a global shared page that is always zero: used
301 * for zero-mapped memory areas etc..
302 */
303
304 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
305
306 #define pte_none(x) (pte_val(x) == 0)
307 #define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
308 #define pte_clear(mm, addr, xp) set_pte_at(mm, addr, xp, __pte(0))
309
310 #define pmd_flag(x) (pmd_val(x) & PxD_FLAG_MASK)
311 #define pmd_address(x) ((unsigned long)(pmd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
312 #define pud_flag(x) (pud_val(x) & PxD_FLAG_MASK)
313 #define pud_address(x) ((unsigned long)(pud_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
314 #define pgd_flag(x) (pgd_val(x) & PxD_FLAG_MASK)
315 #define pgd_address(x) ((unsigned long)(pgd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
316
317 #define pmd_none(x) (!pmd_val(x))
318 #define pmd_bad(x) (!(pmd_flag(x) & PxD_FLAG_VALID))
319 #define pmd_present(x) (pmd_flag(x) & PxD_FLAG_PRESENT)
pmd_clear(pmd_t * pmd)320 static inline void pmd_clear(pmd_t *pmd) {
321 set_pmd(pmd, __pmd(0));
322 }
323
324
325
326 #if CONFIG_PGTABLE_LEVELS == 3
327 #define pud_page_vaddr(pud) ((unsigned long) __va(pud_address(pud)))
328 #define pud_page(pud) virt_to_page((void *)pud_page_vaddr(pud))
329
330 /* For 64 bit we have three level tables */
331
332 #define pud_none(x) (!pud_val(x))
333 #define pud_bad(x) (!(pud_flag(x) & PxD_FLAG_VALID))
334 #define pud_present(x) (pud_flag(x) & PxD_FLAG_PRESENT)
pud_clear(pud_t * pud)335 static inline void pud_clear(pud_t *pud) {
336 set_pud(pud, __pud(0));
337 }
338 #endif
339
340 /*
341 * The following only work if pte_present() is true.
342 * Undefined behaviour if not..
343 */
pte_dirty(pte_t pte)344 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
pte_young(pte_t pte)345 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
pte_write(pte_t pte)346 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
347
pte_mkclean(pte_t pte)348 static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
pte_mkold(pte_t pte)349 static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
pte_wrprotect(pte_t pte)350 static inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= ~_PAGE_WRITE; return pte; }
pte_mkdirty(pte_t pte)351 static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; }
pte_mkyoung(pte_t pte)352 static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
pte_mkwrite(pte_t pte)353 static inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= _PAGE_WRITE; return pte; }
354
355 /*
356 * Huge pte definitions.
357 */
358 #ifdef CONFIG_HUGETLB_PAGE
359 #define pte_huge(pte) (pte_val(pte) & _PAGE_HUGE)
360 #define pte_mkhuge(pte) (__pte(pte_val(pte) | \
361 (parisc_requires_coherency() ? 0 : _PAGE_HUGE)))
362 #else
363 #define pte_huge(pte) (0)
364 #define pte_mkhuge(pte) (pte)
365 #endif
366
367
368 /*
369 * Conversion functions: convert a page and protection to a page entry,
370 * and a page entry and page directory to the page they refer to.
371 */
372 #define __mk_pte(addr,pgprot) \
373 ({ \
374 pte_t __pte; \
375 \
376 pte_val(__pte) = ((((addr)>>PAGE_SHIFT)<<PFN_PTE_SHIFT) + pgprot_val(pgprot)); \
377 \
378 __pte; \
379 })
380
381 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
382
pfn_pte(unsigned long pfn,pgprot_t pgprot)383 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
384 {
385 pte_t pte;
386 pte_val(pte) = (pfn << PFN_PTE_SHIFT) | pgprot_val(pgprot);
387 return pte;
388 }
389
pte_modify(pte_t pte,pgprot_t newprot)390 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
391 { pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
392
393 /* Permanent address of a page. On parisc we don't have highmem. */
394
395 #define pte_pfn(x) (pte_val(x) >> PFN_PTE_SHIFT)
396
397 #define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
398
pmd_page_vaddr(pmd_t pmd)399 static inline unsigned long pmd_page_vaddr(pmd_t pmd)
400 {
401 return ((unsigned long) __va(pmd_address(pmd)));
402 }
403
404 #define __pmd_page(pmd) ((unsigned long) __va(pmd_address(pmd)))
405 #define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd))
406
407 /* Find an entry in the second-level page table.. */
408
409 extern void paging_init (void);
410
411 /* Used for deferring calls to flush_dcache_page() */
412
413 #define PG_dcache_dirty PG_arch_1
414
415 extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
416
417 /* Encode and de-code a swap entry */
418
419 #define __swp_type(x) ((x).val & 0x1f)
420 #define __swp_offset(x) ( (((x).val >> 6) & 0x7) | \
421 (((x).val >> 8) & ~0x7) )
422 #define __swp_entry(type, offset) ((swp_entry_t) { (type) | \
423 ((offset & 0x7) << 6) | \
424 ((offset & ~0x7) << 8) })
425 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
426 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
427
ptep_test_and_clear_young(struct vm_area_struct * vma,unsigned long addr,pte_t * ptep)428 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
429 {
430 pte_t pte;
431
432 if (!pte_young(*ptep))
433 return 0;
434
435 pte = *ptep;
436 if (!pte_young(pte)) {
437 return 0;
438 }
439 set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte));
440 return 1;
441 }
442
443 struct mm_struct;
ptep_get_and_clear(struct mm_struct * mm,unsigned long addr,pte_t * ptep)444 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
445 {
446 pte_t old_pte;
447
448 old_pte = *ptep;
449 set_pte_at(mm, addr, ptep, __pte(0));
450
451 return old_pte;
452 }
453
ptep_set_wrprotect(struct mm_struct * mm,unsigned long addr,pte_t * ptep)454 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
455 {
456 set_pte_at(mm, addr, ptep, pte_wrprotect(*ptep));
457 }
458
459 #define pte_same(A,B) (pte_val(A) == pte_val(B))
460
461 struct seq_file;
462 extern void arch_report_meminfo(struct seq_file *m);
463
464 #endif /* !__ASSEMBLY__ */
465
466
467 /* TLB page size encoding - see table 3-1 in parisc20.pdf */
468 #define _PAGE_SIZE_ENCODING_4K 0
469 #define _PAGE_SIZE_ENCODING_16K 1
470 #define _PAGE_SIZE_ENCODING_64K 2
471 #define _PAGE_SIZE_ENCODING_256K 3
472 #define _PAGE_SIZE_ENCODING_1M 4
473 #define _PAGE_SIZE_ENCODING_4M 5
474 #define _PAGE_SIZE_ENCODING_16M 6
475 #define _PAGE_SIZE_ENCODING_64M 7
476
477 #if defined(CONFIG_PARISC_PAGE_SIZE_4KB)
478 # define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_4K
479 #elif defined(CONFIG_PARISC_PAGE_SIZE_16KB)
480 # define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_16K
481 #elif defined(CONFIG_PARISC_PAGE_SIZE_64KB)
482 # define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_64K
483 #endif
484
485
486 #define pgprot_noncached(prot) __pgprot(pgprot_val(prot) | _PAGE_NO_CACHE)
487
488 /* We provide our own get_unmapped_area to provide cache coherency */
489
490 #define HAVE_ARCH_UNMAPPED_AREA
491 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
492
493 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
494 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
495 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
496 #define __HAVE_ARCH_PTE_SAME
497
498 #endif /* _PARISC_PGTABLE_H */
499