1 /* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2017 Broadcom Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
9 */
10
11 #include <linux/ctype.h>
12 #include <linux/stringify.h>
13 #include <linux/ethtool.h>
14 #include <linux/linkmode.h>
15 #include <linux/interrupt.h>
16 #include <linux/pci.h>
17 #include <linux/etherdevice.h>
18 #include <linux/crc32.h>
19 #include <linux/firmware.h>
20 #include <linux/utsname.h>
21 #include <linux/time.h>
22 #include "bnxt_hsi.h"
23 #include "bnxt.h"
24 #include "bnxt_xdp.h"
25 #include "bnxt_ethtool.h"
26 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */
27 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */
28 #include "bnxt_coredump.h"
29 #define FLASH_NVRAM_TIMEOUT ((HWRM_CMD_TIMEOUT) * 100)
30 #define FLASH_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200)
31 #define INSTALL_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200)
32
bnxt_get_msglevel(struct net_device * dev)33 static u32 bnxt_get_msglevel(struct net_device *dev)
34 {
35 struct bnxt *bp = netdev_priv(dev);
36
37 return bp->msg_enable;
38 }
39
bnxt_set_msglevel(struct net_device * dev,u32 value)40 static void bnxt_set_msglevel(struct net_device *dev, u32 value)
41 {
42 struct bnxt *bp = netdev_priv(dev);
43
44 bp->msg_enable = value;
45 }
46
bnxt_get_coalesce(struct net_device * dev,struct ethtool_coalesce * coal)47 static int bnxt_get_coalesce(struct net_device *dev,
48 struct ethtool_coalesce *coal)
49 {
50 struct bnxt *bp = netdev_priv(dev);
51 struct bnxt_coal *hw_coal;
52 u16 mult;
53
54 memset(coal, 0, sizeof(*coal));
55
56 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM;
57
58 hw_coal = &bp->rx_coal;
59 mult = hw_coal->bufs_per_record;
60 coal->rx_coalesce_usecs = hw_coal->coal_ticks;
61 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult;
62 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq;
63 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult;
64
65 hw_coal = &bp->tx_coal;
66 mult = hw_coal->bufs_per_record;
67 coal->tx_coalesce_usecs = hw_coal->coal_ticks;
68 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult;
69 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq;
70 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult;
71
72 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks;
73
74 return 0;
75 }
76
bnxt_set_coalesce(struct net_device * dev,struct ethtool_coalesce * coal)77 static int bnxt_set_coalesce(struct net_device *dev,
78 struct ethtool_coalesce *coal)
79 {
80 struct bnxt *bp = netdev_priv(dev);
81 bool update_stats = false;
82 struct bnxt_coal *hw_coal;
83 int rc = 0;
84 u16 mult;
85
86 if (coal->use_adaptive_rx_coalesce) {
87 bp->flags |= BNXT_FLAG_DIM;
88 } else {
89 if (bp->flags & BNXT_FLAG_DIM) {
90 bp->flags &= ~(BNXT_FLAG_DIM);
91 goto reset_coalesce;
92 }
93 }
94
95 hw_coal = &bp->rx_coal;
96 mult = hw_coal->bufs_per_record;
97 hw_coal->coal_ticks = coal->rx_coalesce_usecs;
98 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult;
99 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq;
100 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult;
101
102 hw_coal = &bp->tx_coal;
103 mult = hw_coal->bufs_per_record;
104 hw_coal->coal_ticks = coal->tx_coalesce_usecs;
105 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult;
106 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq;
107 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult;
108
109 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) {
110 u32 stats_ticks = coal->stats_block_coalesce_usecs;
111
112 /* Allow 0, which means disable. */
113 if (stats_ticks)
114 stats_ticks = clamp_t(u32, stats_ticks,
115 BNXT_MIN_STATS_COAL_TICKS,
116 BNXT_MAX_STATS_COAL_TICKS);
117 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS);
118 bp->stats_coal_ticks = stats_ticks;
119 if (bp->stats_coal_ticks)
120 bp->current_interval =
121 bp->stats_coal_ticks * HZ / 1000000;
122 else
123 bp->current_interval = BNXT_TIMER_INTERVAL;
124 update_stats = true;
125 }
126
127 reset_coalesce:
128 if (netif_running(dev)) {
129 if (update_stats) {
130 rc = bnxt_close_nic(bp, true, false);
131 if (!rc)
132 rc = bnxt_open_nic(bp, true, false);
133 } else {
134 rc = bnxt_hwrm_set_coal(bp);
135 }
136 }
137
138 return rc;
139 }
140
141 static const char * const bnxt_ring_rx_stats_str[] = {
142 "rx_ucast_packets",
143 "rx_mcast_packets",
144 "rx_bcast_packets",
145 "rx_discards",
146 "rx_errors",
147 "rx_ucast_bytes",
148 "rx_mcast_bytes",
149 "rx_bcast_bytes",
150 };
151
152 static const char * const bnxt_ring_tx_stats_str[] = {
153 "tx_ucast_packets",
154 "tx_mcast_packets",
155 "tx_bcast_packets",
156 "tx_errors",
157 "tx_discards",
158 "tx_ucast_bytes",
159 "tx_mcast_bytes",
160 "tx_bcast_bytes",
161 };
162
163 static const char * const bnxt_ring_tpa_stats_str[] = {
164 "tpa_packets",
165 "tpa_bytes",
166 "tpa_events",
167 "tpa_aborts",
168 };
169
170 static const char * const bnxt_ring_tpa2_stats_str[] = {
171 "rx_tpa_eligible_pkt",
172 "rx_tpa_eligible_bytes",
173 "rx_tpa_pkt",
174 "rx_tpa_bytes",
175 "rx_tpa_errors",
176 "rx_tpa_events",
177 };
178
179 static const char * const bnxt_rx_sw_stats_str[] = {
180 "rx_l4_csum_errors",
181 "rx_resets",
182 "rx_buf_errors",
183 };
184
185 static const char * const bnxt_cmn_sw_stats_str[] = {
186 "missed_irqs",
187 };
188
189 #define BNXT_RX_STATS_ENTRY(counter) \
190 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) }
191
192 #define BNXT_TX_STATS_ENTRY(counter) \
193 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) }
194
195 #define BNXT_RX_STATS_EXT_ENTRY(counter) \
196 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) }
197
198 #define BNXT_TX_STATS_EXT_ENTRY(counter) \
199 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) }
200
201 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \
202 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \
203 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions)
204
205 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \
206 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \
207 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions)
208
209 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \
210 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \
211 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \
212 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \
213 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \
214 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \
215 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \
216 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \
217 BNXT_RX_STATS_EXT_PFC_ENTRY(7)
218
219 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \
220 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \
221 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \
222 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \
223 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \
224 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \
225 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \
226 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \
227 BNXT_TX_STATS_EXT_PFC_ENTRY(7)
228
229 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \
230 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \
231 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n)
232
233 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \
234 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \
235 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n)
236
237 #define BNXT_RX_STATS_EXT_COS_ENTRIES \
238 BNXT_RX_STATS_EXT_COS_ENTRY(0), \
239 BNXT_RX_STATS_EXT_COS_ENTRY(1), \
240 BNXT_RX_STATS_EXT_COS_ENTRY(2), \
241 BNXT_RX_STATS_EXT_COS_ENTRY(3), \
242 BNXT_RX_STATS_EXT_COS_ENTRY(4), \
243 BNXT_RX_STATS_EXT_COS_ENTRY(5), \
244 BNXT_RX_STATS_EXT_COS_ENTRY(6), \
245 BNXT_RX_STATS_EXT_COS_ENTRY(7) \
246
247 #define BNXT_TX_STATS_EXT_COS_ENTRIES \
248 BNXT_TX_STATS_EXT_COS_ENTRY(0), \
249 BNXT_TX_STATS_EXT_COS_ENTRY(1), \
250 BNXT_TX_STATS_EXT_COS_ENTRY(2), \
251 BNXT_TX_STATS_EXT_COS_ENTRY(3), \
252 BNXT_TX_STATS_EXT_COS_ENTRY(4), \
253 BNXT_TX_STATS_EXT_COS_ENTRY(5), \
254 BNXT_TX_STATS_EXT_COS_ENTRY(6), \
255 BNXT_TX_STATS_EXT_COS_ENTRY(7) \
256
257 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \
258 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \
259 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n)
260
261 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \
262 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \
263 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \
264 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \
265 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \
266 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \
267 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \
268 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \
269 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7)
270
271 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \
272 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \
273 __stringify(counter##_pri##n) }
274
275 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \
276 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \
277 __stringify(counter##_pri##n) }
278
279 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \
280 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \
281 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \
282 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \
283 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \
284 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \
285 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \
286 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \
287 BNXT_RX_STATS_PRI_ENTRY(counter, 7)
288
289 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \
290 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \
291 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \
292 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \
293 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \
294 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \
295 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \
296 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \
297 BNXT_TX_STATS_PRI_ENTRY(counter, 7)
298
299 enum {
300 RX_TOTAL_DISCARDS,
301 TX_TOTAL_DISCARDS,
302 };
303
304 static struct {
305 u64 counter;
306 char string[ETH_GSTRING_LEN];
307 } bnxt_sw_func_stats[] = {
308 {0, "rx_total_discard_pkts"},
309 {0, "tx_total_discard_pkts"},
310 };
311
312 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str)
313 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str)
314 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str)
315 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str)
316
317 static const struct {
318 long offset;
319 char string[ETH_GSTRING_LEN];
320 } bnxt_port_stats_arr[] = {
321 BNXT_RX_STATS_ENTRY(rx_64b_frames),
322 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames),
323 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames),
324 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames),
325 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames),
326 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames),
327 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames),
328 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames),
329 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames),
330 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames),
331 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames),
332 BNXT_RX_STATS_ENTRY(rx_total_frames),
333 BNXT_RX_STATS_ENTRY(rx_ucast_frames),
334 BNXT_RX_STATS_ENTRY(rx_mcast_frames),
335 BNXT_RX_STATS_ENTRY(rx_bcast_frames),
336 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames),
337 BNXT_RX_STATS_ENTRY(rx_ctrl_frames),
338 BNXT_RX_STATS_ENTRY(rx_pause_frames),
339 BNXT_RX_STATS_ENTRY(rx_pfc_frames),
340 BNXT_RX_STATS_ENTRY(rx_align_err_frames),
341 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames),
342 BNXT_RX_STATS_ENTRY(rx_jbr_frames),
343 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames),
344 BNXT_RX_STATS_ENTRY(rx_tagged_frames),
345 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames),
346 BNXT_RX_STATS_ENTRY(rx_good_frames),
347 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0),
348 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1),
349 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2),
350 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3),
351 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4),
352 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5),
353 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6),
354 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7),
355 BNXT_RX_STATS_ENTRY(rx_undrsz_frames),
356 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events),
357 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration),
358 BNXT_RX_STATS_ENTRY(rx_bytes),
359 BNXT_RX_STATS_ENTRY(rx_runt_bytes),
360 BNXT_RX_STATS_ENTRY(rx_runt_frames),
361 BNXT_RX_STATS_ENTRY(rx_stat_discard),
362 BNXT_RX_STATS_ENTRY(rx_stat_err),
363
364 BNXT_TX_STATS_ENTRY(tx_64b_frames),
365 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames),
366 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames),
367 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames),
368 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames),
369 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames),
370 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames),
371 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames),
372 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames),
373 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames),
374 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames),
375 BNXT_TX_STATS_ENTRY(tx_good_frames),
376 BNXT_TX_STATS_ENTRY(tx_total_frames),
377 BNXT_TX_STATS_ENTRY(tx_ucast_frames),
378 BNXT_TX_STATS_ENTRY(tx_mcast_frames),
379 BNXT_TX_STATS_ENTRY(tx_bcast_frames),
380 BNXT_TX_STATS_ENTRY(tx_pause_frames),
381 BNXT_TX_STATS_ENTRY(tx_pfc_frames),
382 BNXT_TX_STATS_ENTRY(tx_jabber_frames),
383 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames),
384 BNXT_TX_STATS_ENTRY(tx_err),
385 BNXT_TX_STATS_ENTRY(tx_fifo_underruns),
386 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0),
387 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1),
388 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2),
389 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3),
390 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4),
391 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5),
392 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6),
393 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7),
394 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events),
395 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration),
396 BNXT_TX_STATS_ENTRY(tx_total_collisions),
397 BNXT_TX_STATS_ENTRY(tx_bytes),
398 BNXT_TX_STATS_ENTRY(tx_xthol_frames),
399 BNXT_TX_STATS_ENTRY(tx_stat_discard),
400 BNXT_TX_STATS_ENTRY(tx_stat_error),
401 };
402
403 static const struct {
404 long offset;
405 char string[ETH_GSTRING_LEN];
406 } bnxt_port_stats_ext_arr[] = {
407 BNXT_RX_STATS_EXT_ENTRY(link_down_events),
408 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events),
409 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events),
410 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events),
411 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events),
412 BNXT_RX_STATS_EXT_COS_ENTRIES,
413 BNXT_RX_STATS_EXT_PFC_ENTRIES,
414 BNXT_RX_STATS_EXT_ENTRY(rx_bits),
415 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold),
416 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err),
417 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits),
418 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES,
419 };
420
421 static const struct {
422 long offset;
423 char string[ETH_GSTRING_LEN];
424 } bnxt_tx_port_stats_ext_arr[] = {
425 BNXT_TX_STATS_EXT_COS_ENTRIES,
426 BNXT_TX_STATS_EXT_PFC_ENTRIES,
427 };
428
429 static const struct {
430 long base_off;
431 char string[ETH_GSTRING_LEN];
432 } bnxt_rx_bytes_pri_arr[] = {
433 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes),
434 };
435
436 static const struct {
437 long base_off;
438 char string[ETH_GSTRING_LEN];
439 } bnxt_rx_pkts_pri_arr[] = {
440 BNXT_RX_STATS_PRI_ENTRIES(rx_packets),
441 };
442
443 static const struct {
444 long base_off;
445 char string[ETH_GSTRING_LEN];
446 } bnxt_tx_bytes_pri_arr[] = {
447 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes),
448 };
449
450 static const struct {
451 long base_off;
452 char string[ETH_GSTRING_LEN];
453 } bnxt_tx_pkts_pri_arr[] = {
454 BNXT_TX_STATS_PRI_ENTRIES(tx_packets),
455 };
456
457 #define BNXT_NUM_SW_FUNC_STATS ARRAY_SIZE(bnxt_sw_func_stats)
458 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr)
459 #define BNXT_NUM_STATS_PRI \
460 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \
461 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \
462 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \
463 ARRAY_SIZE(bnxt_tx_pkts_pri_arr))
464
bnxt_get_num_tpa_ring_stats(struct bnxt * bp)465 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp)
466 {
467 if (BNXT_SUPPORTS_TPA(bp)) {
468 if (bp->max_tpa_v2) {
469 if (BNXT_CHIP_P5_THOR(bp))
470 return BNXT_NUM_TPA_RING_STATS_P5;
471 return BNXT_NUM_TPA_RING_STATS_P5_SR2;
472 }
473 return BNXT_NUM_TPA_RING_STATS;
474 }
475 return 0;
476 }
477
bnxt_get_num_ring_stats(struct bnxt * bp)478 static int bnxt_get_num_ring_stats(struct bnxt *bp)
479 {
480 int rx, tx, cmn;
481
482 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS +
483 bnxt_get_num_tpa_ring_stats(bp);
484 tx = NUM_RING_TX_HW_STATS;
485 cmn = NUM_RING_CMN_SW_STATS;
486 return rx * bp->rx_nr_rings + tx * bp->tx_nr_rings +
487 cmn * bp->cp_nr_rings;
488 }
489
bnxt_get_num_stats(struct bnxt * bp)490 static int bnxt_get_num_stats(struct bnxt *bp)
491 {
492 int num_stats = bnxt_get_num_ring_stats(bp);
493
494 num_stats += BNXT_NUM_SW_FUNC_STATS;
495
496 if (bp->flags & BNXT_FLAG_PORT_STATS)
497 num_stats += BNXT_NUM_PORT_STATS;
498
499 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
500 num_stats += bp->fw_rx_stats_ext_size +
501 bp->fw_tx_stats_ext_size;
502 if (bp->pri2cos_valid)
503 num_stats += BNXT_NUM_STATS_PRI;
504 }
505
506 return num_stats;
507 }
508
bnxt_get_sset_count(struct net_device * dev,int sset)509 static int bnxt_get_sset_count(struct net_device *dev, int sset)
510 {
511 struct bnxt *bp = netdev_priv(dev);
512
513 switch (sset) {
514 case ETH_SS_STATS:
515 return bnxt_get_num_stats(bp);
516 case ETH_SS_TEST:
517 if (!bp->num_tests)
518 return -EOPNOTSUPP;
519 return bp->num_tests;
520 default:
521 return -EOPNOTSUPP;
522 }
523 }
524
is_rx_ring(struct bnxt * bp,int ring_num)525 static bool is_rx_ring(struct bnxt *bp, int ring_num)
526 {
527 return ring_num < bp->rx_nr_rings;
528 }
529
is_tx_ring(struct bnxt * bp,int ring_num)530 static bool is_tx_ring(struct bnxt *bp, int ring_num)
531 {
532 int tx_base = 0;
533
534 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
535 tx_base = bp->rx_nr_rings;
536
537 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings))
538 return true;
539 return false;
540 }
541
bnxt_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * buf)542 static void bnxt_get_ethtool_stats(struct net_device *dev,
543 struct ethtool_stats *stats, u64 *buf)
544 {
545 u32 i, j = 0;
546 struct bnxt *bp = netdev_priv(dev);
547 u32 tpa_stats;
548
549 if (!bp->bnapi) {
550 j += bnxt_get_num_ring_stats(bp) + BNXT_NUM_SW_FUNC_STATS;
551 goto skip_ring_stats;
552 }
553
554 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++)
555 bnxt_sw_func_stats[i].counter = 0;
556
557 tpa_stats = bnxt_get_num_tpa_ring_stats(bp);
558 for (i = 0; i < bp->cp_nr_rings; i++) {
559 struct bnxt_napi *bnapi = bp->bnapi[i];
560 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
561 u64 *sw_stats = cpr->stats.sw_stats;
562 u64 *sw;
563 int k;
564
565 if (is_rx_ring(bp, i)) {
566 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++)
567 buf[j] = sw_stats[k];
568 }
569 if (is_tx_ring(bp, i)) {
570 k = NUM_RING_RX_HW_STATS;
571 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS;
572 j++, k++)
573 buf[j] = sw_stats[k];
574 }
575 if (!tpa_stats || !is_rx_ring(bp, i))
576 goto skip_tpa_ring_stats;
577
578 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS;
579 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS +
580 tpa_stats; j++, k++)
581 buf[j] = sw_stats[k];
582
583 skip_tpa_ring_stats:
584 sw = (u64 *)&cpr->sw_stats.rx;
585 if (is_rx_ring(bp, i)) {
586 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++)
587 buf[j] = sw[k];
588 }
589
590 sw = (u64 *)&cpr->sw_stats.cmn;
591 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++)
592 buf[j] = sw[k];
593
594 bnxt_sw_func_stats[RX_TOTAL_DISCARDS].counter +=
595 BNXT_GET_RING_STATS64(sw_stats, rx_discard_pkts);
596 bnxt_sw_func_stats[TX_TOTAL_DISCARDS].counter +=
597 BNXT_GET_RING_STATS64(sw_stats, tx_discard_pkts);
598 }
599
600 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++, j++)
601 buf[j] = bnxt_sw_func_stats[i].counter;
602
603 skip_ring_stats:
604 if (bp->flags & BNXT_FLAG_PORT_STATS) {
605 u64 *port_stats = bp->port_stats.sw_stats;
606
607 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++)
608 buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset);
609 }
610 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
611 u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats;
612 u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats;
613
614 for (i = 0; i < bp->fw_rx_stats_ext_size; i++, j++) {
615 buf[j] = *(rx_port_stats_ext +
616 bnxt_port_stats_ext_arr[i].offset);
617 }
618 for (i = 0; i < bp->fw_tx_stats_ext_size; i++, j++) {
619 buf[j] = *(tx_port_stats_ext +
620 bnxt_tx_port_stats_ext_arr[i].offset);
621 }
622 if (bp->pri2cos_valid) {
623 for (i = 0; i < 8; i++, j++) {
624 long n = bnxt_rx_bytes_pri_arr[i].base_off +
625 bp->pri2cos_idx[i];
626
627 buf[j] = *(rx_port_stats_ext + n);
628 }
629 for (i = 0; i < 8; i++, j++) {
630 long n = bnxt_rx_pkts_pri_arr[i].base_off +
631 bp->pri2cos_idx[i];
632
633 buf[j] = *(rx_port_stats_ext + n);
634 }
635 for (i = 0; i < 8; i++, j++) {
636 long n = bnxt_tx_bytes_pri_arr[i].base_off +
637 bp->pri2cos_idx[i];
638
639 buf[j] = *(tx_port_stats_ext + n);
640 }
641 for (i = 0; i < 8; i++, j++) {
642 long n = bnxt_tx_pkts_pri_arr[i].base_off +
643 bp->pri2cos_idx[i];
644
645 buf[j] = *(tx_port_stats_ext + n);
646 }
647 }
648 }
649 }
650
bnxt_get_strings(struct net_device * dev,u32 stringset,u8 * buf)651 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
652 {
653 struct bnxt *bp = netdev_priv(dev);
654 static const char * const *str;
655 u32 i, j, num_str;
656
657 switch (stringset) {
658 case ETH_SS_STATS:
659 for (i = 0; i < bp->cp_nr_rings; i++) {
660 if (is_rx_ring(bp, i)) {
661 num_str = NUM_RING_RX_HW_STATS;
662 for (j = 0; j < num_str; j++) {
663 sprintf(buf, "[%d]: %s", i,
664 bnxt_ring_rx_stats_str[j]);
665 buf += ETH_GSTRING_LEN;
666 }
667 }
668 if (is_tx_ring(bp, i)) {
669 num_str = NUM_RING_TX_HW_STATS;
670 for (j = 0; j < num_str; j++) {
671 sprintf(buf, "[%d]: %s", i,
672 bnxt_ring_tx_stats_str[j]);
673 buf += ETH_GSTRING_LEN;
674 }
675 }
676 num_str = bnxt_get_num_tpa_ring_stats(bp);
677 if (!num_str || !is_rx_ring(bp, i))
678 goto skip_tpa_stats;
679
680 if (bp->max_tpa_v2)
681 str = bnxt_ring_tpa2_stats_str;
682 else
683 str = bnxt_ring_tpa_stats_str;
684
685 for (j = 0; j < num_str; j++) {
686 sprintf(buf, "[%d]: %s", i, str[j]);
687 buf += ETH_GSTRING_LEN;
688 }
689 skip_tpa_stats:
690 if (is_rx_ring(bp, i)) {
691 num_str = NUM_RING_RX_SW_STATS;
692 for (j = 0; j < num_str; j++) {
693 sprintf(buf, "[%d]: %s", i,
694 bnxt_rx_sw_stats_str[j]);
695 buf += ETH_GSTRING_LEN;
696 }
697 }
698 num_str = NUM_RING_CMN_SW_STATS;
699 for (j = 0; j < num_str; j++) {
700 sprintf(buf, "[%d]: %s", i,
701 bnxt_cmn_sw_stats_str[j]);
702 buf += ETH_GSTRING_LEN;
703 }
704 }
705 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) {
706 strcpy(buf, bnxt_sw_func_stats[i].string);
707 buf += ETH_GSTRING_LEN;
708 }
709
710 if (bp->flags & BNXT_FLAG_PORT_STATS) {
711 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) {
712 strcpy(buf, bnxt_port_stats_arr[i].string);
713 buf += ETH_GSTRING_LEN;
714 }
715 }
716 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
717 for (i = 0; i < bp->fw_rx_stats_ext_size; i++) {
718 strcpy(buf, bnxt_port_stats_ext_arr[i].string);
719 buf += ETH_GSTRING_LEN;
720 }
721 for (i = 0; i < bp->fw_tx_stats_ext_size; i++) {
722 strcpy(buf,
723 bnxt_tx_port_stats_ext_arr[i].string);
724 buf += ETH_GSTRING_LEN;
725 }
726 if (bp->pri2cos_valid) {
727 for (i = 0; i < 8; i++) {
728 strcpy(buf,
729 bnxt_rx_bytes_pri_arr[i].string);
730 buf += ETH_GSTRING_LEN;
731 }
732 for (i = 0; i < 8; i++) {
733 strcpy(buf,
734 bnxt_rx_pkts_pri_arr[i].string);
735 buf += ETH_GSTRING_LEN;
736 }
737 for (i = 0; i < 8; i++) {
738 strcpy(buf,
739 bnxt_tx_bytes_pri_arr[i].string);
740 buf += ETH_GSTRING_LEN;
741 }
742 for (i = 0; i < 8; i++) {
743 strcpy(buf,
744 bnxt_tx_pkts_pri_arr[i].string);
745 buf += ETH_GSTRING_LEN;
746 }
747 }
748 }
749 break;
750 case ETH_SS_TEST:
751 if (bp->num_tests)
752 memcpy(buf, bp->test_info->string,
753 bp->num_tests * ETH_GSTRING_LEN);
754 break;
755 default:
756 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n",
757 stringset);
758 break;
759 }
760 }
761
bnxt_get_ringparam(struct net_device * dev,struct ethtool_ringparam * ering)762 static void bnxt_get_ringparam(struct net_device *dev,
763 struct ethtool_ringparam *ering)
764 {
765 struct bnxt *bp = netdev_priv(dev);
766
767 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT;
768 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT;
769 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT;
770
771 ering->rx_pending = bp->rx_ring_size;
772 ering->rx_jumbo_pending = bp->rx_agg_ring_size;
773 ering->tx_pending = bp->tx_ring_size;
774 }
775
bnxt_set_ringparam(struct net_device * dev,struct ethtool_ringparam * ering)776 static int bnxt_set_ringparam(struct net_device *dev,
777 struct ethtool_ringparam *ering)
778 {
779 struct bnxt *bp = netdev_priv(dev);
780
781 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) ||
782 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) ||
783 (ering->tx_pending <= MAX_SKB_FRAGS))
784 return -EINVAL;
785
786 if (netif_running(dev))
787 bnxt_close_nic(bp, false, false);
788
789 bp->rx_ring_size = ering->rx_pending;
790 bp->tx_ring_size = ering->tx_pending;
791 bnxt_set_ring_params(bp);
792
793 if (netif_running(dev))
794 return bnxt_open_nic(bp, false, false);
795
796 return 0;
797 }
798
bnxt_get_channels(struct net_device * dev,struct ethtool_channels * channel)799 static void bnxt_get_channels(struct net_device *dev,
800 struct ethtool_channels *channel)
801 {
802 struct bnxt *bp = netdev_priv(dev);
803 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
804 int max_rx_rings, max_tx_rings, tcs;
805 int max_tx_sch_inputs, tx_grps;
806
807 /* Get the most up-to-date max_tx_sch_inputs. */
808 if (netif_running(dev) && BNXT_NEW_RM(bp))
809 bnxt_hwrm_func_resc_qcaps(bp, false);
810 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs;
811
812 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true);
813 if (max_tx_sch_inputs)
814 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs);
815
816 tcs = netdev_get_num_tc(dev);
817 tx_grps = max(tcs, 1);
818 if (bp->tx_nr_rings_xdp)
819 tx_grps++;
820 max_tx_rings /= tx_grps;
821 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings);
822
823 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) {
824 max_rx_rings = 0;
825 max_tx_rings = 0;
826 }
827 if (max_tx_sch_inputs)
828 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs);
829
830 if (tcs > 1)
831 max_tx_rings /= tcs;
832
833 channel->max_rx = max_rx_rings;
834 channel->max_tx = max_tx_rings;
835 channel->max_other = 0;
836 if (bp->flags & BNXT_FLAG_SHARED_RINGS) {
837 channel->combined_count = bp->rx_nr_rings;
838 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
839 channel->combined_count--;
840 } else {
841 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) {
842 channel->rx_count = bp->rx_nr_rings;
843 channel->tx_count = bp->tx_nr_rings_per_tc;
844 }
845 }
846 }
847
bnxt_set_channels(struct net_device * dev,struct ethtool_channels * channel)848 static int bnxt_set_channels(struct net_device *dev,
849 struct ethtool_channels *channel)
850 {
851 struct bnxt *bp = netdev_priv(dev);
852 int req_tx_rings, req_rx_rings, tcs;
853 bool sh = false;
854 int tx_xdp = 0;
855 int rc = 0;
856
857 if (channel->other_count)
858 return -EINVAL;
859
860 if (!channel->combined_count &&
861 (!channel->rx_count || !channel->tx_count))
862 return -EINVAL;
863
864 if (channel->combined_count &&
865 (channel->rx_count || channel->tx_count))
866 return -EINVAL;
867
868 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count ||
869 channel->tx_count))
870 return -EINVAL;
871
872 if (channel->combined_count)
873 sh = true;
874
875 tcs = netdev_get_num_tc(dev);
876
877 req_tx_rings = sh ? channel->combined_count : channel->tx_count;
878 req_rx_rings = sh ? channel->combined_count : channel->rx_count;
879 if (bp->tx_nr_rings_xdp) {
880 if (!sh) {
881 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n");
882 return -EINVAL;
883 }
884 tx_xdp = req_rx_rings;
885 }
886 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp);
887 if (rc) {
888 netdev_warn(dev, "Unable to allocate the requested rings\n");
889 return rc;
890 }
891
892 if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) !=
893 bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) &&
894 (dev->priv_flags & IFF_RXFH_CONFIGURED)) {
895 netdev_warn(dev, "RSS table size change required, RSS table entries must be default to proceed\n");
896 return -EINVAL;
897 }
898
899 if (netif_running(dev)) {
900 if (BNXT_PF(bp)) {
901 /* TODO CHIMP_FW: Send message to all VF's
902 * before PF unload
903 */
904 }
905 rc = bnxt_close_nic(bp, true, false);
906 if (rc) {
907 netdev_err(bp->dev, "Set channel failure rc :%x\n",
908 rc);
909 return rc;
910 }
911 }
912
913 if (sh) {
914 bp->flags |= BNXT_FLAG_SHARED_RINGS;
915 bp->rx_nr_rings = channel->combined_count;
916 bp->tx_nr_rings_per_tc = channel->combined_count;
917 } else {
918 bp->flags &= ~BNXT_FLAG_SHARED_RINGS;
919 bp->rx_nr_rings = channel->rx_count;
920 bp->tx_nr_rings_per_tc = channel->tx_count;
921 }
922 bp->tx_nr_rings_xdp = tx_xdp;
923 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp;
924 if (tcs > 1)
925 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp;
926
927 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
928 bp->tx_nr_rings + bp->rx_nr_rings;
929
930 /* After changing number of rx channels, update NTUPLE feature. */
931 netdev_update_features(dev);
932 if (netif_running(dev)) {
933 rc = bnxt_open_nic(bp, true, false);
934 if ((!rc) && BNXT_PF(bp)) {
935 /* TODO CHIMP_FW: Send message to all VF's
936 * to renable
937 */
938 }
939 } else {
940 rc = bnxt_reserve_rings(bp, true);
941 }
942
943 return rc;
944 }
945
946 #ifdef CONFIG_RFS_ACCEL
bnxt_grxclsrlall(struct bnxt * bp,struct ethtool_rxnfc * cmd,u32 * rule_locs)947 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd,
948 u32 *rule_locs)
949 {
950 int i, j = 0;
951
952 cmd->data = bp->ntp_fltr_count;
953 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
954 struct hlist_head *head;
955 struct bnxt_ntuple_filter *fltr;
956
957 head = &bp->ntp_fltr_hash_tbl[i];
958 rcu_read_lock();
959 hlist_for_each_entry_rcu(fltr, head, hash) {
960 if (j == cmd->rule_cnt)
961 break;
962 rule_locs[j++] = fltr->sw_id;
963 }
964 rcu_read_unlock();
965 if (j == cmd->rule_cnt)
966 break;
967 }
968 cmd->rule_cnt = j;
969 return 0;
970 }
971
bnxt_grxclsrule(struct bnxt * bp,struct ethtool_rxnfc * cmd)972 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd)
973 {
974 struct ethtool_rx_flow_spec *fs =
975 (struct ethtool_rx_flow_spec *)&cmd->fs;
976 struct bnxt_ntuple_filter *fltr;
977 struct flow_keys *fkeys;
978 int i, rc = -EINVAL;
979
980 if (fs->location >= BNXT_NTP_FLTR_MAX_FLTR)
981 return rc;
982
983 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
984 struct hlist_head *head;
985
986 head = &bp->ntp_fltr_hash_tbl[i];
987 rcu_read_lock();
988 hlist_for_each_entry_rcu(fltr, head, hash) {
989 if (fltr->sw_id == fs->location)
990 goto fltr_found;
991 }
992 rcu_read_unlock();
993 }
994 return rc;
995
996 fltr_found:
997 fkeys = &fltr->fkeys;
998 if (fkeys->basic.n_proto == htons(ETH_P_IP)) {
999 if (fkeys->basic.ip_proto == IPPROTO_TCP)
1000 fs->flow_type = TCP_V4_FLOW;
1001 else if (fkeys->basic.ip_proto == IPPROTO_UDP)
1002 fs->flow_type = UDP_V4_FLOW;
1003 else
1004 goto fltr_err;
1005
1006 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src;
1007 fs->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(~0);
1008
1009 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst;
1010 fs->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(~0);
1011
1012 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src;
1013 fs->m_u.tcp_ip4_spec.psrc = cpu_to_be16(~0);
1014
1015 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst;
1016 fs->m_u.tcp_ip4_spec.pdst = cpu_to_be16(~0);
1017 } else {
1018 int i;
1019
1020 if (fkeys->basic.ip_proto == IPPROTO_TCP)
1021 fs->flow_type = TCP_V6_FLOW;
1022 else if (fkeys->basic.ip_proto == IPPROTO_UDP)
1023 fs->flow_type = UDP_V6_FLOW;
1024 else
1025 goto fltr_err;
1026
1027 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] =
1028 fkeys->addrs.v6addrs.src;
1029 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] =
1030 fkeys->addrs.v6addrs.dst;
1031 for (i = 0; i < 4; i++) {
1032 fs->m_u.tcp_ip6_spec.ip6src[i] = cpu_to_be32(~0);
1033 fs->m_u.tcp_ip6_spec.ip6dst[i] = cpu_to_be32(~0);
1034 }
1035 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src;
1036 fs->m_u.tcp_ip6_spec.psrc = cpu_to_be16(~0);
1037
1038 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst;
1039 fs->m_u.tcp_ip6_spec.pdst = cpu_to_be16(~0);
1040 }
1041
1042 fs->ring_cookie = fltr->rxq;
1043 rc = 0;
1044
1045 fltr_err:
1046 rcu_read_unlock();
1047
1048 return rc;
1049 }
1050 #endif
1051
get_ethtool_ipv4_rss(struct bnxt * bp)1052 static u64 get_ethtool_ipv4_rss(struct bnxt *bp)
1053 {
1054 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4)
1055 return RXH_IP_SRC | RXH_IP_DST;
1056 return 0;
1057 }
1058
get_ethtool_ipv6_rss(struct bnxt * bp)1059 static u64 get_ethtool_ipv6_rss(struct bnxt *bp)
1060 {
1061 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6)
1062 return RXH_IP_SRC | RXH_IP_DST;
1063 return 0;
1064 }
1065
bnxt_grxfh(struct bnxt * bp,struct ethtool_rxnfc * cmd)1066 static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1067 {
1068 cmd->data = 0;
1069 switch (cmd->flow_type) {
1070 case TCP_V4_FLOW:
1071 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4)
1072 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1073 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1074 cmd->data |= get_ethtool_ipv4_rss(bp);
1075 break;
1076 case UDP_V4_FLOW:
1077 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4)
1078 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1079 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1080 fallthrough;
1081 case SCTP_V4_FLOW:
1082 case AH_ESP_V4_FLOW:
1083 case AH_V4_FLOW:
1084 case ESP_V4_FLOW:
1085 case IPV4_FLOW:
1086 cmd->data |= get_ethtool_ipv4_rss(bp);
1087 break;
1088
1089 case TCP_V6_FLOW:
1090 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6)
1091 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1092 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1093 cmd->data |= get_ethtool_ipv6_rss(bp);
1094 break;
1095 case UDP_V6_FLOW:
1096 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6)
1097 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1098 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1099 fallthrough;
1100 case SCTP_V6_FLOW:
1101 case AH_ESP_V6_FLOW:
1102 case AH_V6_FLOW:
1103 case ESP_V6_FLOW:
1104 case IPV6_FLOW:
1105 cmd->data |= get_ethtool_ipv6_rss(bp);
1106 break;
1107 }
1108 return 0;
1109 }
1110
1111 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)
1112 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST)
1113
bnxt_srxfh(struct bnxt * bp,struct ethtool_rxnfc * cmd)1114 static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1115 {
1116 u32 rss_hash_cfg = bp->rss_hash_cfg;
1117 int tuple, rc = 0;
1118
1119 if (cmd->data == RXH_4TUPLE)
1120 tuple = 4;
1121 else if (cmd->data == RXH_2TUPLE)
1122 tuple = 2;
1123 else if (!cmd->data)
1124 tuple = 0;
1125 else
1126 return -EINVAL;
1127
1128 if (cmd->flow_type == TCP_V4_FLOW) {
1129 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4;
1130 if (tuple == 4)
1131 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4;
1132 } else if (cmd->flow_type == UDP_V4_FLOW) {
1133 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP))
1134 return -EINVAL;
1135 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4;
1136 if (tuple == 4)
1137 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4;
1138 } else if (cmd->flow_type == TCP_V6_FLOW) {
1139 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
1140 if (tuple == 4)
1141 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
1142 } else if (cmd->flow_type == UDP_V6_FLOW) {
1143 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP))
1144 return -EINVAL;
1145 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
1146 if (tuple == 4)
1147 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
1148 } else if (tuple == 4) {
1149 return -EINVAL;
1150 }
1151
1152 switch (cmd->flow_type) {
1153 case TCP_V4_FLOW:
1154 case UDP_V4_FLOW:
1155 case SCTP_V4_FLOW:
1156 case AH_ESP_V4_FLOW:
1157 case AH_V4_FLOW:
1158 case ESP_V4_FLOW:
1159 case IPV4_FLOW:
1160 if (tuple == 2)
1161 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4;
1162 else if (!tuple)
1163 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4;
1164 break;
1165
1166 case TCP_V6_FLOW:
1167 case UDP_V6_FLOW:
1168 case SCTP_V6_FLOW:
1169 case AH_ESP_V6_FLOW:
1170 case AH_V6_FLOW:
1171 case ESP_V6_FLOW:
1172 case IPV6_FLOW:
1173 if (tuple == 2)
1174 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6;
1175 else if (!tuple)
1176 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6;
1177 break;
1178 }
1179
1180 if (bp->rss_hash_cfg == rss_hash_cfg)
1181 return 0;
1182
1183 bp->rss_hash_cfg = rss_hash_cfg;
1184 if (netif_running(bp->dev)) {
1185 bnxt_close_nic(bp, false, false);
1186 rc = bnxt_open_nic(bp, false, false);
1187 }
1188 return rc;
1189 }
1190
bnxt_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd,u32 * rule_locs)1191 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1192 u32 *rule_locs)
1193 {
1194 struct bnxt *bp = netdev_priv(dev);
1195 int rc = 0;
1196
1197 switch (cmd->cmd) {
1198 #ifdef CONFIG_RFS_ACCEL
1199 case ETHTOOL_GRXRINGS:
1200 cmd->data = bp->rx_nr_rings;
1201 break;
1202
1203 case ETHTOOL_GRXCLSRLCNT:
1204 cmd->rule_cnt = bp->ntp_fltr_count;
1205 cmd->data = BNXT_NTP_FLTR_MAX_FLTR;
1206 break;
1207
1208 case ETHTOOL_GRXCLSRLALL:
1209 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs);
1210 break;
1211
1212 case ETHTOOL_GRXCLSRULE:
1213 rc = bnxt_grxclsrule(bp, cmd);
1214 break;
1215 #endif
1216
1217 case ETHTOOL_GRXFH:
1218 rc = bnxt_grxfh(bp, cmd);
1219 break;
1220
1221 default:
1222 rc = -EOPNOTSUPP;
1223 break;
1224 }
1225
1226 return rc;
1227 }
1228
bnxt_set_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd)1229 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1230 {
1231 struct bnxt *bp = netdev_priv(dev);
1232 int rc;
1233
1234 switch (cmd->cmd) {
1235 case ETHTOOL_SRXFH:
1236 rc = bnxt_srxfh(bp, cmd);
1237 break;
1238
1239 default:
1240 rc = -EOPNOTSUPP;
1241 break;
1242 }
1243 return rc;
1244 }
1245
bnxt_get_rxfh_indir_size(struct net_device * dev)1246 u32 bnxt_get_rxfh_indir_size(struct net_device *dev)
1247 {
1248 struct bnxt *bp = netdev_priv(dev);
1249
1250 if (bp->flags & BNXT_FLAG_CHIP_P5)
1251 return ALIGN(bp->rx_nr_rings, BNXT_RSS_TABLE_ENTRIES_P5);
1252 return HW_HASH_INDEX_SIZE;
1253 }
1254
bnxt_get_rxfh_key_size(struct net_device * dev)1255 static u32 bnxt_get_rxfh_key_size(struct net_device *dev)
1256 {
1257 return HW_HASH_KEY_SIZE;
1258 }
1259
bnxt_get_rxfh(struct net_device * dev,u32 * indir,u8 * key,u8 * hfunc)1260 static int bnxt_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
1261 u8 *hfunc)
1262 {
1263 struct bnxt *bp = netdev_priv(dev);
1264 struct bnxt_vnic_info *vnic;
1265 u32 i, tbl_size;
1266
1267 if (hfunc)
1268 *hfunc = ETH_RSS_HASH_TOP;
1269
1270 if (!bp->vnic_info)
1271 return 0;
1272
1273 vnic = &bp->vnic_info[0];
1274 if (indir && bp->rss_indir_tbl) {
1275 tbl_size = bnxt_get_rxfh_indir_size(dev);
1276 for (i = 0; i < tbl_size; i++)
1277 indir[i] = bp->rss_indir_tbl[i];
1278 }
1279
1280 if (key && vnic->rss_hash_key)
1281 memcpy(key, vnic->rss_hash_key, HW_HASH_KEY_SIZE);
1282
1283 return 0;
1284 }
1285
bnxt_set_rxfh(struct net_device * dev,const u32 * indir,const u8 * key,const u8 hfunc)1286 static int bnxt_set_rxfh(struct net_device *dev, const u32 *indir,
1287 const u8 *key, const u8 hfunc)
1288 {
1289 struct bnxt *bp = netdev_priv(dev);
1290 int rc = 0;
1291
1292 if (hfunc && hfunc != ETH_RSS_HASH_TOP)
1293 return -EOPNOTSUPP;
1294
1295 if (key)
1296 return -EOPNOTSUPP;
1297
1298 if (indir) {
1299 u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(dev);
1300
1301 for (i = 0; i < tbl_size; i++)
1302 bp->rss_indir_tbl[i] = indir[i];
1303 pad = bp->rss_indir_tbl_entries - tbl_size;
1304 if (pad)
1305 memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16));
1306 }
1307
1308 if (netif_running(bp->dev)) {
1309 bnxt_close_nic(bp, false, false);
1310 rc = bnxt_open_nic(bp, false, false);
1311 }
1312 return rc;
1313 }
1314
bnxt_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)1315 static void bnxt_get_drvinfo(struct net_device *dev,
1316 struct ethtool_drvinfo *info)
1317 {
1318 struct bnxt *bp = netdev_priv(dev);
1319
1320 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1321 strlcpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version));
1322 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
1323 info->n_stats = bnxt_get_num_stats(bp);
1324 info->testinfo_len = bp->num_tests;
1325 /* TODO CHIMP_FW: eeprom dump details */
1326 info->eedump_len = 0;
1327 /* TODO CHIMP FW: reg dump details */
1328 info->regdump_len = 0;
1329 }
1330
bnxt_get_regs_len(struct net_device * dev)1331 static int bnxt_get_regs_len(struct net_device *dev)
1332 {
1333 struct bnxt *bp = netdev_priv(dev);
1334 int reg_len;
1335
1336 if (!BNXT_PF(bp))
1337 return -EOPNOTSUPP;
1338
1339 reg_len = BNXT_PXP_REG_LEN;
1340
1341 if (bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)
1342 reg_len += sizeof(struct pcie_ctx_hw_stats);
1343
1344 return reg_len;
1345 }
1346
bnxt_get_regs(struct net_device * dev,struct ethtool_regs * regs,void * _p)1347 static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1348 void *_p)
1349 {
1350 struct pcie_ctx_hw_stats *hw_pcie_stats;
1351 struct hwrm_pcie_qstats_input req = {0};
1352 struct bnxt *bp = netdev_priv(dev);
1353 dma_addr_t hw_pcie_stats_addr;
1354 int rc;
1355
1356 regs->version = 0;
1357 bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p);
1358
1359 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED))
1360 return;
1361
1362 hw_pcie_stats = dma_alloc_coherent(&bp->pdev->dev,
1363 sizeof(*hw_pcie_stats),
1364 &hw_pcie_stats_addr, GFP_KERNEL);
1365 if (!hw_pcie_stats)
1366 return;
1367
1368 regs->version = 1;
1369 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PCIE_QSTATS, -1, -1);
1370 req.pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats));
1371 req.pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr);
1372 mutex_lock(&bp->hwrm_cmd_lock);
1373 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
1374 if (!rc) {
1375 __le64 *src = (__le64 *)hw_pcie_stats;
1376 u64 *dst = (u64 *)(_p + BNXT_PXP_REG_LEN);
1377 int i;
1378
1379 for (i = 0; i < sizeof(*hw_pcie_stats) / sizeof(__le64); i++)
1380 dst[i] = le64_to_cpu(src[i]);
1381 }
1382 mutex_unlock(&bp->hwrm_cmd_lock);
1383 dma_free_coherent(&bp->pdev->dev, sizeof(*hw_pcie_stats), hw_pcie_stats,
1384 hw_pcie_stats_addr);
1385 }
1386
bnxt_get_wol(struct net_device * dev,struct ethtool_wolinfo * wol)1387 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1388 {
1389 struct bnxt *bp = netdev_priv(dev);
1390
1391 wol->supported = 0;
1392 wol->wolopts = 0;
1393 memset(&wol->sopass, 0, sizeof(wol->sopass));
1394 if (bp->flags & BNXT_FLAG_WOL_CAP) {
1395 wol->supported = WAKE_MAGIC;
1396 if (bp->wol)
1397 wol->wolopts = WAKE_MAGIC;
1398 }
1399 }
1400
bnxt_set_wol(struct net_device * dev,struct ethtool_wolinfo * wol)1401 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1402 {
1403 struct bnxt *bp = netdev_priv(dev);
1404
1405 if (wol->wolopts & ~WAKE_MAGIC)
1406 return -EINVAL;
1407
1408 if (wol->wolopts & WAKE_MAGIC) {
1409 if (!(bp->flags & BNXT_FLAG_WOL_CAP))
1410 return -EINVAL;
1411 if (!bp->wol) {
1412 if (bnxt_hwrm_alloc_wol_fltr(bp))
1413 return -EBUSY;
1414 bp->wol = 1;
1415 }
1416 } else {
1417 if (bp->wol) {
1418 if (bnxt_hwrm_free_wol_fltr(bp))
1419 return -EBUSY;
1420 bp->wol = 0;
1421 }
1422 }
1423 return 0;
1424 }
1425
_bnxt_fw_to_ethtool_adv_spds(u16 fw_speeds,u8 fw_pause)1426 u32 _bnxt_fw_to_ethtool_adv_spds(u16 fw_speeds, u8 fw_pause)
1427 {
1428 u32 speed_mask = 0;
1429
1430 /* TODO: support 25GB, 40GB, 50GB with different cable type */
1431 /* set the advertised speeds */
1432 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB)
1433 speed_mask |= ADVERTISED_100baseT_Full;
1434 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB)
1435 speed_mask |= ADVERTISED_1000baseT_Full;
1436 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB)
1437 speed_mask |= ADVERTISED_2500baseX_Full;
1438 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB)
1439 speed_mask |= ADVERTISED_10000baseT_Full;
1440 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB)
1441 speed_mask |= ADVERTISED_40000baseCR4_Full;
1442
1443 if ((fw_pause & BNXT_LINK_PAUSE_BOTH) == BNXT_LINK_PAUSE_BOTH)
1444 speed_mask |= ADVERTISED_Pause;
1445 else if (fw_pause & BNXT_LINK_PAUSE_TX)
1446 speed_mask |= ADVERTISED_Asym_Pause;
1447 else if (fw_pause & BNXT_LINK_PAUSE_RX)
1448 speed_mask |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1449
1450 return speed_mask;
1451 }
1452
1453 #define BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, name)\
1454 { \
1455 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100MB) \
1456 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1457 100baseT_Full); \
1458 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_1GB) \
1459 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1460 1000baseT_Full); \
1461 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_10GB) \
1462 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1463 10000baseT_Full); \
1464 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_25GB) \
1465 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1466 25000baseCR_Full); \
1467 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_40GB) \
1468 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1469 40000baseCR4_Full);\
1470 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_50GB) \
1471 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1472 50000baseCR2_Full);\
1473 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100GB) \
1474 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1475 100000baseCR4_Full);\
1476 if ((fw_pause) & BNXT_LINK_PAUSE_RX) { \
1477 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1478 Pause); \
1479 if (!((fw_pause) & BNXT_LINK_PAUSE_TX)) \
1480 ethtool_link_ksettings_add_link_mode( \
1481 lk_ksettings, name, Asym_Pause);\
1482 } else if ((fw_pause) & BNXT_LINK_PAUSE_TX) { \
1483 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1484 Asym_Pause); \
1485 } \
1486 }
1487
1488 #define BNXT_ETHTOOL_TO_FW_SPDS(fw_speeds, lk_ksettings, name) \
1489 { \
1490 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1491 100baseT_Full) || \
1492 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1493 100baseT_Half)) \
1494 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100MB; \
1495 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1496 1000baseT_Full) || \
1497 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1498 1000baseT_Half)) \
1499 (fw_speeds) |= BNXT_LINK_SPEED_MSK_1GB; \
1500 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1501 10000baseT_Full)) \
1502 (fw_speeds) |= BNXT_LINK_SPEED_MSK_10GB; \
1503 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1504 25000baseCR_Full)) \
1505 (fw_speeds) |= BNXT_LINK_SPEED_MSK_25GB; \
1506 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1507 40000baseCR4_Full)) \
1508 (fw_speeds) |= BNXT_LINK_SPEED_MSK_40GB; \
1509 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1510 50000baseCR2_Full)) \
1511 (fw_speeds) |= BNXT_LINK_SPEED_MSK_50GB; \
1512 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1513 100000baseCR4_Full)) \
1514 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100GB; \
1515 }
1516
1517 #define BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, name) \
1518 { \
1519 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_50GB) \
1520 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1521 50000baseCR_Full); \
1522 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_100GB) \
1523 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1524 100000baseCR2_Full);\
1525 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_200GB) \
1526 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1527 200000baseCR4_Full);\
1528 }
1529
1530 #define BNXT_ETHTOOL_TO_FW_PAM4_SPDS(fw_speeds, lk_ksettings, name) \
1531 { \
1532 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1533 50000baseCR_Full)) \
1534 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_50GB; \
1535 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1536 100000baseCR2_Full)) \
1537 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_100GB; \
1538 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1539 200000baseCR4_Full)) \
1540 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_200GB; \
1541 }
1542
bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info * link_info,struct ethtool_link_ksettings * lk_ksettings)1543 static void bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info *link_info,
1544 struct ethtool_link_ksettings *lk_ksettings)
1545 {
1546 u16 fec_cfg = link_info->fec_cfg;
1547
1548 if ((fec_cfg & BNXT_FEC_NONE) || !(fec_cfg & BNXT_FEC_AUTONEG)) {
1549 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
1550 lk_ksettings->link_modes.advertising);
1551 return;
1552 }
1553 if (fec_cfg & BNXT_FEC_ENC_BASE_R)
1554 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
1555 lk_ksettings->link_modes.advertising);
1556 if (fec_cfg & BNXT_FEC_ENC_RS)
1557 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
1558 lk_ksettings->link_modes.advertising);
1559 if (fec_cfg & BNXT_FEC_ENC_LLRS)
1560 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
1561 lk_ksettings->link_modes.advertising);
1562 }
1563
bnxt_fw_to_ethtool_advertised_spds(struct bnxt_link_info * link_info,struct ethtool_link_ksettings * lk_ksettings)1564 static void bnxt_fw_to_ethtool_advertised_spds(struct bnxt_link_info *link_info,
1565 struct ethtool_link_ksettings *lk_ksettings)
1566 {
1567 u16 fw_speeds = link_info->advertising;
1568 u8 fw_pause = 0;
1569
1570 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
1571 fw_pause = link_info->auto_pause_setting;
1572
1573 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, advertising);
1574 fw_speeds = link_info->advertising_pam4;
1575 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, advertising);
1576 bnxt_fw_to_ethtool_advertised_fec(link_info, lk_ksettings);
1577 }
1578
bnxt_fw_to_ethtool_lp_adv(struct bnxt_link_info * link_info,struct ethtool_link_ksettings * lk_ksettings)1579 static void bnxt_fw_to_ethtool_lp_adv(struct bnxt_link_info *link_info,
1580 struct ethtool_link_ksettings *lk_ksettings)
1581 {
1582 u16 fw_speeds = link_info->lp_auto_link_speeds;
1583 u8 fw_pause = 0;
1584
1585 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
1586 fw_pause = link_info->lp_pause;
1587
1588 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings,
1589 lp_advertising);
1590 fw_speeds = link_info->lp_auto_pam4_link_speeds;
1591 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, lp_advertising);
1592 }
1593
bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info * link_info,struct ethtool_link_ksettings * lk_ksettings)1594 static void bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info *link_info,
1595 struct ethtool_link_ksettings *lk_ksettings)
1596 {
1597 u16 fec_cfg = link_info->fec_cfg;
1598
1599 if (fec_cfg & BNXT_FEC_NONE) {
1600 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
1601 lk_ksettings->link_modes.supported);
1602 return;
1603 }
1604 if (fec_cfg & BNXT_FEC_ENC_BASE_R_CAP)
1605 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
1606 lk_ksettings->link_modes.supported);
1607 if (fec_cfg & BNXT_FEC_ENC_RS_CAP)
1608 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
1609 lk_ksettings->link_modes.supported);
1610 if (fec_cfg & BNXT_FEC_ENC_LLRS_CAP)
1611 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
1612 lk_ksettings->link_modes.supported);
1613 }
1614
bnxt_fw_to_ethtool_support_spds(struct bnxt_link_info * link_info,struct ethtool_link_ksettings * lk_ksettings)1615 static void bnxt_fw_to_ethtool_support_spds(struct bnxt_link_info *link_info,
1616 struct ethtool_link_ksettings *lk_ksettings)
1617 {
1618 u16 fw_speeds = link_info->support_speeds;
1619
1620 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, 0, lk_ksettings, supported);
1621 fw_speeds = link_info->support_pam4_speeds;
1622 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, supported);
1623
1624 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, Pause);
1625 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1626 Asym_Pause);
1627
1628 if (link_info->support_auto_speeds ||
1629 link_info->support_pam4_auto_speeds)
1630 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1631 Autoneg);
1632 bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings);
1633 }
1634
bnxt_fw_to_ethtool_speed(u16 fw_link_speed)1635 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed)
1636 {
1637 switch (fw_link_speed) {
1638 case BNXT_LINK_SPEED_100MB:
1639 return SPEED_100;
1640 case BNXT_LINK_SPEED_1GB:
1641 return SPEED_1000;
1642 case BNXT_LINK_SPEED_2_5GB:
1643 return SPEED_2500;
1644 case BNXT_LINK_SPEED_10GB:
1645 return SPEED_10000;
1646 case BNXT_LINK_SPEED_20GB:
1647 return SPEED_20000;
1648 case BNXT_LINK_SPEED_25GB:
1649 return SPEED_25000;
1650 case BNXT_LINK_SPEED_40GB:
1651 return SPEED_40000;
1652 case BNXT_LINK_SPEED_50GB:
1653 return SPEED_50000;
1654 case BNXT_LINK_SPEED_100GB:
1655 return SPEED_100000;
1656 default:
1657 return SPEED_UNKNOWN;
1658 }
1659 }
1660
bnxt_get_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * lk_ksettings)1661 static int bnxt_get_link_ksettings(struct net_device *dev,
1662 struct ethtool_link_ksettings *lk_ksettings)
1663 {
1664 struct bnxt *bp = netdev_priv(dev);
1665 struct bnxt_link_info *link_info = &bp->link_info;
1666 struct ethtool_link_settings *base = &lk_ksettings->base;
1667 u32 ethtool_speed;
1668
1669 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported);
1670 mutex_lock(&bp->link_lock);
1671 bnxt_fw_to_ethtool_support_spds(link_info, lk_ksettings);
1672
1673 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising);
1674 if (link_info->autoneg) {
1675 bnxt_fw_to_ethtool_advertised_spds(link_info, lk_ksettings);
1676 ethtool_link_ksettings_add_link_mode(lk_ksettings,
1677 advertising, Autoneg);
1678 base->autoneg = AUTONEG_ENABLE;
1679 base->duplex = DUPLEX_UNKNOWN;
1680 if (link_info->phy_link_status == BNXT_LINK_LINK) {
1681 bnxt_fw_to_ethtool_lp_adv(link_info, lk_ksettings);
1682 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL)
1683 base->duplex = DUPLEX_FULL;
1684 else
1685 base->duplex = DUPLEX_HALF;
1686 }
1687 ethtool_speed = bnxt_fw_to_ethtool_speed(link_info->link_speed);
1688 } else {
1689 base->autoneg = AUTONEG_DISABLE;
1690 ethtool_speed =
1691 bnxt_fw_to_ethtool_speed(link_info->req_link_speed);
1692 base->duplex = DUPLEX_HALF;
1693 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL)
1694 base->duplex = DUPLEX_FULL;
1695 }
1696 base->speed = ethtool_speed;
1697
1698 base->port = PORT_NONE;
1699 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) {
1700 base->port = PORT_TP;
1701 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1702 TP);
1703 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising,
1704 TP);
1705 } else {
1706 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1707 FIBRE);
1708 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising,
1709 FIBRE);
1710
1711 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC)
1712 base->port = PORT_DA;
1713 else if (link_info->media_type ==
1714 PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE)
1715 base->port = PORT_FIBRE;
1716 }
1717 base->phy_address = link_info->phy_addr;
1718 mutex_unlock(&bp->link_lock);
1719
1720 return 0;
1721 }
1722
bnxt_force_link_speed(struct net_device * dev,u32 ethtool_speed)1723 static int bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed)
1724 {
1725 struct bnxt *bp = netdev_priv(dev);
1726 struct bnxt_link_info *link_info = &bp->link_info;
1727 u16 support_pam4_spds = link_info->support_pam4_speeds;
1728 u16 support_spds = link_info->support_speeds;
1729 u8 sig_mode = BNXT_SIG_MODE_NRZ;
1730 u16 fw_speed = 0;
1731
1732 switch (ethtool_speed) {
1733 case SPEED_100:
1734 if (support_spds & BNXT_LINK_SPEED_MSK_100MB)
1735 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB;
1736 break;
1737 case SPEED_1000:
1738 if (support_spds & BNXT_LINK_SPEED_MSK_1GB)
1739 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB;
1740 break;
1741 case SPEED_2500:
1742 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB)
1743 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB;
1744 break;
1745 case SPEED_10000:
1746 if (support_spds & BNXT_LINK_SPEED_MSK_10GB)
1747 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB;
1748 break;
1749 case SPEED_20000:
1750 if (support_spds & BNXT_LINK_SPEED_MSK_20GB)
1751 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB;
1752 break;
1753 case SPEED_25000:
1754 if (support_spds & BNXT_LINK_SPEED_MSK_25GB)
1755 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB;
1756 break;
1757 case SPEED_40000:
1758 if (support_spds & BNXT_LINK_SPEED_MSK_40GB)
1759 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB;
1760 break;
1761 case SPEED_50000:
1762 if (support_spds & BNXT_LINK_SPEED_MSK_50GB) {
1763 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB;
1764 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_50GB) {
1765 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB;
1766 sig_mode = BNXT_SIG_MODE_PAM4;
1767 }
1768 break;
1769 case SPEED_100000:
1770 if (support_spds & BNXT_LINK_SPEED_MSK_100GB) {
1771 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB;
1772 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_100GB) {
1773 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB;
1774 sig_mode = BNXT_SIG_MODE_PAM4;
1775 }
1776 break;
1777 case SPEED_200000:
1778 if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_200GB) {
1779 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB;
1780 sig_mode = BNXT_SIG_MODE_PAM4;
1781 }
1782 break;
1783 }
1784
1785 if (!fw_speed) {
1786 netdev_err(dev, "unsupported speed!\n");
1787 return -EINVAL;
1788 }
1789
1790 if (link_info->req_link_speed == fw_speed &&
1791 link_info->req_signal_mode == sig_mode &&
1792 link_info->autoneg == 0)
1793 return -EALREADY;
1794
1795 link_info->req_link_speed = fw_speed;
1796 link_info->req_signal_mode = sig_mode;
1797 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL;
1798 link_info->autoneg = 0;
1799 link_info->advertising = 0;
1800 link_info->advertising_pam4 = 0;
1801
1802 return 0;
1803 }
1804
bnxt_get_fw_auto_link_speeds(u32 advertising)1805 u16 bnxt_get_fw_auto_link_speeds(u32 advertising)
1806 {
1807 u16 fw_speed_mask = 0;
1808
1809 /* only support autoneg at speed 100, 1000, and 10000 */
1810 if (advertising & (ADVERTISED_100baseT_Full |
1811 ADVERTISED_100baseT_Half)) {
1812 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB;
1813 }
1814 if (advertising & (ADVERTISED_1000baseT_Full |
1815 ADVERTISED_1000baseT_Half)) {
1816 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB;
1817 }
1818 if (advertising & ADVERTISED_10000baseT_Full)
1819 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB;
1820
1821 if (advertising & ADVERTISED_40000baseCR4_Full)
1822 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB;
1823
1824 return fw_speed_mask;
1825 }
1826
bnxt_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * lk_ksettings)1827 static int bnxt_set_link_ksettings(struct net_device *dev,
1828 const struct ethtool_link_ksettings *lk_ksettings)
1829 {
1830 struct bnxt *bp = netdev_priv(dev);
1831 struct bnxt_link_info *link_info = &bp->link_info;
1832 const struct ethtool_link_settings *base = &lk_ksettings->base;
1833 bool set_pause = false;
1834 u32 speed;
1835 int rc = 0;
1836
1837 if (!BNXT_PHY_CFG_ABLE(bp))
1838 return -EOPNOTSUPP;
1839
1840 mutex_lock(&bp->link_lock);
1841 if (base->autoneg == AUTONEG_ENABLE) {
1842 link_info->advertising = 0;
1843 link_info->advertising_pam4 = 0;
1844 BNXT_ETHTOOL_TO_FW_SPDS(link_info->advertising, lk_ksettings,
1845 advertising);
1846 BNXT_ETHTOOL_TO_FW_PAM4_SPDS(link_info->advertising_pam4,
1847 lk_ksettings, advertising);
1848 link_info->autoneg |= BNXT_AUTONEG_SPEED;
1849 if (!link_info->advertising && !link_info->advertising_pam4) {
1850 link_info->advertising = link_info->support_auto_speeds;
1851 link_info->advertising_pam4 =
1852 link_info->support_pam4_auto_speeds;
1853 }
1854 /* any change to autoneg will cause link change, therefore the
1855 * driver should put back the original pause setting in autoneg
1856 */
1857 set_pause = true;
1858 } else {
1859 u8 phy_type = link_info->phy_type;
1860
1861 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET ||
1862 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE ||
1863 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) {
1864 netdev_err(dev, "10GBase-T devices must autoneg\n");
1865 rc = -EINVAL;
1866 goto set_setting_exit;
1867 }
1868 if (base->duplex == DUPLEX_HALF) {
1869 netdev_err(dev, "HALF DUPLEX is not supported!\n");
1870 rc = -EINVAL;
1871 goto set_setting_exit;
1872 }
1873 speed = base->speed;
1874 rc = bnxt_force_link_speed(dev, speed);
1875 if (rc) {
1876 if (rc == -EALREADY)
1877 rc = 0;
1878 goto set_setting_exit;
1879 }
1880 }
1881
1882 if (netif_running(dev))
1883 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false);
1884
1885 set_setting_exit:
1886 mutex_unlock(&bp->link_lock);
1887 return rc;
1888 }
1889
bnxt_get_fecparam(struct net_device * dev,struct ethtool_fecparam * fec)1890 static int bnxt_get_fecparam(struct net_device *dev,
1891 struct ethtool_fecparam *fec)
1892 {
1893 struct bnxt *bp = netdev_priv(dev);
1894 struct bnxt_link_info *link_info;
1895 u8 active_fec;
1896 u16 fec_cfg;
1897
1898 link_info = &bp->link_info;
1899 fec_cfg = link_info->fec_cfg;
1900 active_fec = link_info->active_fec_sig_mode &
1901 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK;
1902 if (fec_cfg & BNXT_FEC_NONE) {
1903 fec->fec = ETHTOOL_FEC_NONE;
1904 fec->active_fec = ETHTOOL_FEC_NONE;
1905 return 0;
1906 }
1907 if (fec_cfg & BNXT_FEC_AUTONEG)
1908 fec->fec |= ETHTOOL_FEC_AUTO;
1909 if (fec_cfg & BNXT_FEC_ENC_BASE_R)
1910 fec->fec |= ETHTOOL_FEC_BASER;
1911 if (fec_cfg & BNXT_FEC_ENC_RS)
1912 fec->fec |= ETHTOOL_FEC_RS;
1913 if (fec_cfg & BNXT_FEC_ENC_LLRS)
1914 fec->fec |= ETHTOOL_FEC_LLRS;
1915
1916 switch (active_fec) {
1917 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE:
1918 fec->active_fec |= ETHTOOL_FEC_BASER;
1919 break;
1920 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE:
1921 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE:
1922 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE:
1923 fec->active_fec |= ETHTOOL_FEC_RS;
1924 break;
1925 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE:
1926 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE:
1927 fec->active_fec |= ETHTOOL_FEC_LLRS;
1928 break;
1929 }
1930 return 0;
1931 }
1932
bnxt_get_fec_stats(struct net_device * dev,struct ethtool_fec_stats * fec_stats)1933 static void bnxt_get_fec_stats(struct net_device *dev,
1934 struct ethtool_fec_stats *fec_stats)
1935 {
1936 struct bnxt *bp = netdev_priv(dev);
1937 u64 *rx;
1938
1939 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
1940 return;
1941
1942 rx = bp->rx_port_stats_ext.sw_stats;
1943 fec_stats->corrected_bits.total =
1944 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_corrected_bits));
1945 }
1946
bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info * link_info,u32 fec)1947 static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info,
1948 u32 fec)
1949 {
1950 u32 fw_fec = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE;
1951
1952 if (fec & ETHTOOL_FEC_BASER)
1953 fw_fec |= BNXT_FEC_BASE_R_ON(link_info);
1954 else if (fec & ETHTOOL_FEC_RS)
1955 fw_fec |= BNXT_FEC_RS_ON(link_info);
1956 else if (fec & ETHTOOL_FEC_LLRS)
1957 fw_fec |= BNXT_FEC_LLRS_ON;
1958 return fw_fec;
1959 }
1960
bnxt_set_fecparam(struct net_device * dev,struct ethtool_fecparam * fecparam)1961 static int bnxt_set_fecparam(struct net_device *dev,
1962 struct ethtool_fecparam *fecparam)
1963 {
1964 struct hwrm_port_phy_cfg_input req = {0};
1965 struct bnxt *bp = netdev_priv(dev);
1966 struct bnxt_link_info *link_info;
1967 u32 new_cfg, fec = fecparam->fec;
1968 u16 fec_cfg;
1969 int rc;
1970
1971 link_info = &bp->link_info;
1972 fec_cfg = link_info->fec_cfg;
1973 if (fec_cfg & BNXT_FEC_NONE)
1974 return -EOPNOTSUPP;
1975
1976 if (fec & ETHTOOL_FEC_OFF) {
1977 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE |
1978 BNXT_FEC_ALL_OFF(link_info);
1979 goto apply_fec;
1980 }
1981 if (((fec & ETHTOOL_FEC_AUTO) && !(fec_cfg & BNXT_FEC_AUTONEG_CAP)) ||
1982 ((fec & ETHTOOL_FEC_RS) && !(fec_cfg & BNXT_FEC_ENC_RS_CAP)) ||
1983 ((fec & ETHTOOL_FEC_LLRS) && !(fec_cfg & BNXT_FEC_ENC_LLRS_CAP)) ||
1984 ((fec & ETHTOOL_FEC_BASER) && !(fec_cfg & BNXT_FEC_ENC_BASE_R_CAP)))
1985 return -EINVAL;
1986
1987 if (fec & ETHTOOL_FEC_AUTO) {
1988 if (!link_info->autoneg)
1989 return -EINVAL;
1990 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE;
1991 } else {
1992 new_cfg = bnxt_ethtool_forced_fec_to_fw(link_info, fec);
1993 }
1994
1995 apply_fec:
1996 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
1997 req.flags = cpu_to_le32(new_cfg | PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
1998 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
1999 /* update current settings */
2000 if (!rc) {
2001 mutex_lock(&bp->link_lock);
2002 bnxt_update_link(bp, false);
2003 mutex_unlock(&bp->link_lock);
2004 }
2005 return rc;
2006 }
2007
bnxt_get_pauseparam(struct net_device * dev,struct ethtool_pauseparam * epause)2008 static void bnxt_get_pauseparam(struct net_device *dev,
2009 struct ethtool_pauseparam *epause)
2010 {
2011 struct bnxt *bp = netdev_priv(dev);
2012 struct bnxt_link_info *link_info = &bp->link_info;
2013
2014 if (BNXT_VF(bp))
2015 return;
2016 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL);
2017 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX);
2018 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX);
2019 }
2020
bnxt_get_pause_stats(struct net_device * dev,struct ethtool_pause_stats * epstat)2021 static void bnxt_get_pause_stats(struct net_device *dev,
2022 struct ethtool_pause_stats *epstat)
2023 {
2024 struct bnxt *bp = netdev_priv(dev);
2025 u64 *rx, *tx;
2026
2027 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
2028 return;
2029
2030 rx = bp->port_stats.sw_stats;
2031 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
2032
2033 epstat->rx_pause_frames = BNXT_GET_RX_PORT_STATS64(rx, rx_pause_frames);
2034 epstat->tx_pause_frames = BNXT_GET_TX_PORT_STATS64(tx, tx_pause_frames);
2035 }
2036
bnxt_set_pauseparam(struct net_device * dev,struct ethtool_pauseparam * epause)2037 static int bnxt_set_pauseparam(struct net_device *dev,
2038 struct ethtool_pauseparam *epause)
2039 {
2040 int rc = 0;
2041 struct bnxt *bp = netdev_priv(dev);
2042 struct bnxt_link_info *link_info = &bp->link_info;
2043
2044 if (!BNXT_PHY_CFG_ABLE(bp))
2045 return -EOPNOTSUPP;
2046
2047 mutex_lock(&bp->link_lock);
2048 if (epause->autoneg) {
2049 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
2050 rc = -EINVAL;
2051 goto pause_exit;
2052 }
2053
2054 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
2055 if (bp->hwrm_spec_code >= 0x10201)
2056 link_info->req_flow_ctrl =
2057 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
2058 } else {
2059 /* when transition from auto pause to force pause,
2060 * force a link change
2061 */
2062 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
2063 link_info->force_link_chng = true;
2064 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL;
2065 link_info->req_flow_ctrl = 0;
2066 }
2067 if (epause->rx_pause)
2068 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX;
2069
2070 if (epause->tx_pause)
2071 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX;
2072
2073 if (netif_running(dev))
2074 rc = bnxt_hwrm_set_pause(bp);
2075
2076 pause_exit:
2077 mutex_unlock(&bp->link_lock);
2078 return rc;
2079 }
2080
bnxt_get_link(struct net_device * dev)2081 static u32 bnxt_get_link(struct net_device *dev)
2082 {
2083 struct bnxt *bp = netdev_priv(dev);
2084
2085 /* TODO: handle MF, VF, driver close case */
2086 return bp->link_info.link_up;
2087 }
2088
bnxt_hwrm_nvm_get_dev_info(struct bnxt * bp,struct hwrm_nvm_get_dev_info_output * nvm_dev_info)2089 int bnxt_hwrm_nvm_get_dev_info(struct bnxt *bp,
2090 struct hwrm_nvm_get_dev_info_output *nvm_dev_info)
2091 {
2092 struct hwrm_nvm_get_dev_info_output *resp = bp->hwrm_cmd_resp_addr;
2093 struct hwrm_nvm_get_dev_info_input req = {0};
2094 int rc;
2095
2096 if (BNXT_VF(bp))
2097 return -EOPNOTSUPP;
2098
2099 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DEV_INFO, -1, -1);
2100 mutex_lock(&bp->hwrm_cmd_lock);
2101 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2102 if (!rc)
2103 memcpy(nvm_dev_info, resp, sizeof(*resp));
2104 mutex_unlock(&bp->hwrm_cmd_lock);
2105 return rc;
2106 }
2107
bnxt_print_admin_err(struct bnxt * bp)2108 static void bnxt_print_admin_err(struct bnxt *bp)
2109 {
2110 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n");
2111 }
2112
2113 static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal,
2114 u16 ext, u16 *index, u32 *item_length,
2115 u32 *data_length);
2116
__bnxt_flash_nvram(struct net_device * dev,u16 dir_type,u16 dir_ordinal,u16 dir_ext,u16 dir_attr,u32 dir_item_len,const u8 * data,size_t data_len)2117 static int __bnxt_flash_nvram(struct net_device *dev, u16 dir_type,
2118 u16 dir_ordinal, u16 dir_ext, u16 dir_attr,
2119 u32 dir_item_len, const u8 *data,
2120 size_t data_len)
2121 {
2122 struct bnxt *bp = netdev_priv(dev);
2123 int rc;
2124 struct hwrm_nvm_write_input req = {0};
2125 dma_addr_t dma_handle;
2126 u8 *kmem = NULL;
2127
2128 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_WRITE, -1, -1);
2129
2130 req.dir_type = cpu_to_le16(dir_type);
2131 req.dir_ordinal = cpu_to_le16(dir_ordinal);
2132 req.dir_ext = cpu_to_le16(dir_ext);
2133 req.dir_attr = cpu_to_le16(dir_attr);
2134 req.dir_item_length = cpu_to_le32(dir_item_len);
2135 if (data_len && data) {
2136 req.dir_data_length = cpu_to_le32(data_len);
2137
2138 kmem = dma_alloc_coherent(&bp->pdev->dev, data_len, &dma_handle,
2139 GFP_KERNEL);
2140 if (!kmem)
2141 return -ENOMEM;
2142
2143 memcpy(kmem, data, data_len);
2144 req.host_src_addr = cpu_to_le64(dma_handle);
2145 }
2146
2147 rc = _hwrm_send_message(bp, &req, sizeof(req), FLASH_NVRAM_TIMEOUT);
2148 if (kmem)
2149 dma_free_coherent(&bp->pdev->dev, data_len, kmem, dma_handle);
2150
2151 if (rc == -EACCES)
2152 bnxt_print_admin_err(bp);
2153 return rc;
2154 }
2155
bnxt_flash_nvram(struct net_device * dev,u16 dir_type,u16 dir_ordinal,u16 dir_ext,u16 dir_attr,const u8 * data,size_t data_len)2156 static int bnxt_flash_nvram(struct net_device *dev, u16 dir_type,
2157 u16 dir_ordinal, u16 dir_ext, u16 dir_attr,
2158 const u8 *data, size_t data_len)
2159 {
2160 struct bnxt *bp = netdev_priv(dev);
2161 int rc;
2162
2163 mutex_lock(&bp->hwrm_cmd_lock);
2164 rc = __bnxt_flash_nvram(dev, dir_type, dir_ordinal, dir_ext, dir_attr,
2165 0, data, data_len);
2166 mutex_unlock(&bp->hwrm_cmd_lock);
2167 return rc;
2168 }
2169
bnxt_hwrm_firmware_reset(struct net_device * dev,u8 proc_type,u8 self_reset,u8 flags)2170 static int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type,
2171 u8 self_reset, u8 flags)
2172 {
2173 struct hwrm_fw_reset_input req = {0};
2174 struct bnxt *bp = netdev_priv(dev);
2175 int rc;
2176
2177 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET, -1, -1);
2178
2179 req.embedded_proc_type = proc_type;
2180 req.selfrst_status = self_reset;
2181 req.flags = flags;
2182
2183 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) {
2184 rc = hwrm_send_message_silent(bp, &req, sizeof(req),
2185 HWRM_CMD_TIMEOUT);
2186 } else {
2187 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2188 if (rc == -EACCES)
2189 bnxt_print_admin_err(bp);
2190 }
2191 return rc;
2192 }
2193
bnxt_firmware_reset(struct net_device * dev,enum bnxt_nvm_directory_type dir_type)2194 static int bnxt_firmware_reset(struct net_device *dev,
2195 enum bnxt_nvm_directory_type dir_type)
2196 {
2197 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE;
2198 u8 proc_type, flags = 0;
2199
2200 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */
2201 /* (e.g. when firmware isn't already running) */
2202 switch (dir_type) {
2203 case BNX_DIR_TYPE_CHIMP_PATCH:
2204 case BNX_DIR_TYPE_BOOTCODE:
2205 case BNX_DIR_TYPE_BOOTCODE_2:
2206 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT;
2207 /* Self-reset ChiMP upon next PCIe reset: */
2208 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST;
2209 break;
2210 case BNX_DIR_TYPE_APE_FW:
2211 case BNX_DIR_TYPE_APE_PATCH:
2212 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT;
2213 /* Self-reset APE upon next PCIe reset: */
2214 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST;
2215 break;
2216 case BNX_DIR_TYPE_KONG_FW:
2217 case BNX_DIR_TYPE_KONG_PATCH:
2218 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL;
2219 break;
2220 case BNX_DIR_TYPE_BONO_FW:
2221 case BNX_DIR_TYPE_BONO_PATCH:
2222 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE;
2223 break;
2224 default:
2225 return -EINVAL;
2226 }
2227
2228 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags);
2229 }
2230
bnxt_firmware_reset_chip(struct net_device * dev)2231 static int bnxt_firmware_reset_chip(struct net_device *dev)
2232 {
2233 struct bnxt *bp = netdev_priv(dev);
2234 u8 flags = 0;
2235
2236 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
2237 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL;
2238
2239 return bnxt_hwrm_firmware_reset(dev,
2240 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP,
2241 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP,
2242 flags);
2243 }
2244
bnxt_firmware_reset_ap(struct net_device * dev)2245 static int bnxt_firmware_reset_ap(struct net_device *dev)
2246 {
2247 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP,
2248 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE,
2249 0);
2250 }
2251
bnxt_flash_firmware(struct net_device * dev,u16 dir_type,const u8 * fw_data,size_t fw_size)2252 static int bnxt_flash_firmware(struct net_device *dev,
2253 u16 dir_type,
2254 const u8 *fw_data,
2255 size_t fw_size)
2256 {
2257 int rc = 0;
2258 u16 code_type;
2259 u32 stored_crc;
2260 u32 calculated_crc;
2261 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data;
2262
2263 switch (dir_type) {
2264 case BNX_DIR_TYPE_BOOTCODE:
2265 case BNX_DIR_TYPE_BOOTCODE_2:
2266 code_type = CODE_BOOT;
2267 break;
2268 case BNX_DIR_TYPE_CHIMP_PATCH:
2269 code_type = CODE_CHIMP_PATCH;
2270 break;
2271 case BNX_DIR_TYPE_APE_FW:
2272 code_type = CODE_MCTP_PASSTHRU;
2273 break;
2274 case BNX_DIR_TYPE_APE_PATCH:
2275 code_type = CODE_APE_PATCH;
2276 break;
2277 case BNX_DIR_TYPE_KONG_FW:
2278 code_type = CODE_KONG_FW;
2279 break;
2280 case BNX_DIR_TYPE_KONG_PATCH:
2281 code_type = CODE_KONG_PATCH;
2282 break;
2283 case BNX_DIR_TYPE_BONO_FW:
2284 code_type = CODE_BONO_FW;
2285 break;
2286 case BNX_DIR_TYPE_BONO_PATCH:
2287 code_type = CODE_BONO_PATCH;
2288 break;
2289 default:
2290 netdev_err(dev, "Unsupported directory entry type: %u\n",
2291 dir_type);
2292 return -EINVAL;
2293 }
2294 if (fw_size < sizeof(struct bnxt_fw_header)) {
2295 netdev_err(dev, "Invalid firmware file size: %u\n",
2296 (unsigned int)fw_size);
2297 return -EINVAL;
2298 }
2299 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) {
2300 netdev_err(dev, "Invalid firmware signature: %08X\n",
2301 le32_to_cpu(header->signature));
2302 return -EINVAL;
2303 }
2304 if (header->code_type != code_type) {
2305 netdev_err(dev, "Expected firmware type: %d, read: %d\n",
2306 code_type, header->code_type);
2307 return -EINVAL;
2308 }
2309 if (header->device != DEVICE_CUMULUS_FAMILY) {
2310 netdev_err(dev, "Expected firmware device family %d, read: %d\n",
2311 DEVICE_CUMULUS_FAMILY, header->device);
2312 return -EINVAL;
2313 }
2314 /* Confirm the CRC32 checksum of the file: */
2315 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size -
2316 sizeof(stored_crc)));
2317 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc));
2318 if (calculated_crc != stored_crc) {
2319 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n",
2320 (unsigned long)stored_crc,
2321 (unsigned long)calculated_crc);
2322 return -EINVAL;
2323 }
2324 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
2325 0, 0, fw_data, fw_size);
2326 if (rc == 0) /* Firmware update successful */
2327 rc = bnxt_firmware_reset(dev, dir_type);
2328
2329 return rc;
2330 }
2331
bnxt_flash_microcode(struct net_device * dev,u16 dir_type,const u8 * fw_data,size_t fw_size)2332 static int bnxt_flash_microcode(struct net_device *dev,
2333 u16 dir_type,
2334 const u8 *fw_data,
2335 size_t fw_size)
2336 {
2337 struct bnxt_ucode_trailer *trailer;
2338 u32 calculated_crc;
2339 u32 stored_crc;
2340 int rc = 0;
2341
2342 if (fw_size < sizeof(struct bnxt_ucode_trailer)) {
2343 netdev_err(dev, "Invalid microcode file size: %u\n",
2344 (unsigned int)fw_size);
2345 return -EINVAL;
2346 }
2347 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size -
2348 sizeof(*trailer)));
2349 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) {
2350 netdev_err(dev, "Invalid microcode trailer signature: %08X\n",
2351 le32_to_cpu(trailer->sig));
2352 return -EINVAL;
2353 }
2354 if (le16_to_cpu(trailer->dir_type) != dir_type) {
2355 netdev_err(dev, "Expected microcode type: %d, read: %d\n",
2356 dir_type, le16_to_cpu(trailer->dir_type));
2357 return -EINVAL;
2358 }
2359 if (le16_to_cpu(trailer->trailer_length) <
2360 sizeof(struct bnxt_ucode_trailer)) {
2361 netdev_err(dev, "Invalid microcode trailer length: %d\n",
2362 le16_to_cpu(trailer->trailer_length));
2363 return -EINVAL;
2364 }
2365
2366 /* Confirm the CRC32 checksum of the file: */
2367 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size -
2368 sizeof(stored_crc)));
2369 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc));
2370 if (calculated_crc != stored_crc) {
2371 netdev_err(dev,
2372 "CRC32 (%08lX) does not match calculated: %08lX\n",
2373 (unsigned long)stored_crc,
2374 (unsigned long)calculated_crc);
2375 return -EINVAL;
2376 }
2377 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
2378 0, 0, fw_data, fw_size);
2379
2380 return rc;
2381 }
2382
bnxt_dir_type_is_ape_bin_format(u16 dir_type)2383 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type)
2384 {
2385 switch (dir_type) {
2386 case BNX_DIR_TYPE_CHIMP_PATCH:
2387 case BNX_DIR_TYPE_BOOTCODE:
2388 case BNX_DIR_TYPE_BOOTCODE_2:
2389 case BNX_DIR_TYPE_APE_FW:
2390 case BNX_DIR_TYPE_APE_PATCH:
2391 case BNX_DIR_TYPE_KONG_FW:
2392 case BNX_DIR_TYPE_KONG_PATCH:
2393 case BNX_DIR_TYPE_BONO_FW:
2394 case BNX_DIR_TYPE_BONO_PATCH:
2395 return true;
2396 }
2397
2398 return false;
2399 }
2400
bnxt_dir_type_is_other_exec_format(u16 dir_type)2401 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type)
2402 {
2403 switch (dir_type) {
2404 case BNX_DIR_TYPE_AVS:
2405 case BNX_DIR_TYPE_EXP_ROM_MBA:
2406 case BNX_DIR_TYPE_PCIE:
2407 case BNX_DIR_TYPE_TSCF_UCODE:
2408 case BNX_DIR_TYPE_EXT_PHY:
2409 case BNX_DIR_TYPE_CCM:
2410 case BNX_DIR_TYPE_ISCSI_BOOT:
2411 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
2412 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
2413 return true;
2414 }
2415
2416 return false;
2417 }
2418
bnxt_dir_type_is_executable(u16 dir_type)2419 static bool bnxt_dir_type_is_executable(u16 dir_type)
2420 {
2421 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
2422 bnxt_dir_type_is_other_exec_format(dir_type);
2423 }
2424
bnxt_flash_firmware_from_file(struct net_device * dev,u16 dir_type,const char * filename)2425 static int bnxt_flash_firmware_from_file(struct net_device *dev,
2426 u16 dir_type,
2427 const char *filename)
2428 {
2429 const struct firmware *fw;
2430 int rc;
2431
2432 rc = request_firmware(&fw, filename, &dev->dev);
2433 if (rc != 0) {
2434 netdev_err(dev, "Error %d requesting firmware file: %s\n",
2435 rc, filename);
2436 return rc;
2437 }
2438 if (bnxt_dir_type_is_ape_bin_format(dir_type))
2439 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size);
2440 else if (bnxt_dir_type_is_other_exec_format(dir_type))
2441 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size);
2442 else
2443 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
2444 0, 0, fw->data, fw->size);
2445 release_firmware(fw);
2446 return rc;
2447 }
2448
2449 #define BNXT_PKG_DMA_SIZE 0x40000
2450 #define BNXT_NVM_MORE_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_MODE))
2451 #define BNXT_NVM_LAST_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_LAST))
2452
bnxt_flash_package_from_fw_obj(struct net_device * dev,const struct firmware * fw,u32 install_type)2453 int bnxt_flash_package_from_fw_obj(struct net_device *dev, const struct firmware *fw,
2454 u32 install_type)
2455 {
2456 struct hwrm_nvm_install_update_input install = {0};
2457 struct hwrm_nvm_install_update_output resp = {0};
2458 struct hwrm_nvm_modify_input modify = {0};
2459 struct bnxt *bp = netdev_priv(dev);
2460 bool defrag_attempted = false;
2461 dma_addr_t dma_handle;
2462 u8 *kmem = NULL;
2463 u32 modify_len;
2464 u32 item_len;
2465 int rc = 0;
2466 u16 index;
2467
2468 bnxt_hwrm_fw_set_time(bp);
2469
2470 bnxt_hwrm_cmd_hdr_init(bp, &modify, HWRM_NVM_MODIFY, -1, -1);
2471
2472 /* Try allocating a large DMA buffer first. Older fw will
2473 * cause excessive NVRAM erases when using small blocks.
2474 */
2475 modify_len = roundup_pow_of_two(fw->size);
2476 modify_len = min_t(u32, modify_len, BNXT_PKG_DMA_SIZE);
2477 while (1) {
2478 kmem = dma_alloc_coherent(&bp->pdev->dev, modify_len,
2479 &dma_handle, GFP_KERNEL);
2480 if (!kmem && modify_len > PAGE_SIZE)
2481 modify_len /= 2;
2482 else
2483 break;
2484 }
2485 if (!kmem)
2486 return -ENOMEM;
2487
2488 modify.host_src_addr = cpu_to_le64(dma_handle);
2489
2490 bnxt_hwrm_cmd_hdr_init(bp, &install, HWRM_NVM_INSTALL_UPDATE, -1, -1);
2491 if ((install_type & 0xffff) == 0)
2492 install_type >>= 16;
2493 install.install_type = cpu_to_le32(install_type);
2494
2495 do {
2496 u32 copied = 0, len = modify_len;
2497
2498 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE,
2499 BNX_DIR_ORDINAL_FIRST,
2500 BNX_DIR_EXT_NONE,
2501 &index, &item_len, NULL);
2502 if (rc) {
2503 netdev_err(dev, "PKG update area not created in nvram\n");
2504 break;
2505 }
2506 if (fw->size > item_len) {
2507 netdev_err(dev, "PKG insufficient update area in nvram: %lu\n",
2508 (unsigned long)fw->size);
2509 rc = -EFBIG;
2510 break;
2511 }
2512
2513 modify.dir_idx = cpu_to_le16(index);
2514
2515 if (fw->size > modify_len)
2516 modify.flags = BNXT_NVM_MORE_FLAG;
2517 while (copied < fw->size) {
2518 u32 balance = fw->size - copied;
2519
2520 if (balance <= modify_len) {
2521 len = balance;
2522 if (copied)
2523 modify.flags |= BNXT_NVM_LAST_FLAG;
2524 }
2525 memcpy(kmem, fw->data + copied, len);
2526 modify.len = cpu_to_le32(len);
2527 modify.offset = cpu_to_le32(copied);
2528 rc = hwrm_send_message(bp, &modify, sizeof(modify),
2529 FLASH_PACKAGE_TIMEOUT);
2530 if (rc)
2531 goto pkg_abort;
2532 copied += len;
2533 }
2534 mutex_lock(&bp->hwrm_cmd_lock);
2535 rc = _hwrm_send_message_silent(bp, &install, sizeof(install),
2536 INSTALL_PACKAGE_TIMEOUT);
2537 memcpy(&resp, bp->hwrm_cmd_resp_addr, sizeof(resp));
2538
2539 if (defrag_attempted) {
2540 /* We have tried to defragment already in the previous
2541 * iteration. Return with the result for INSTALL_UPDATE
2542 */
2543 mutex_unlock(&bp->hwrm_cmd_lock);
2544 break;
2545 }
2546
2547 if (rc && ((struct hwrm_err_output *)&resp)->cmd_err ==
2548 NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR) {
2549 install.flags =
2550 cpu_to_le16(NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG);
2551
2552 rc = _hwrm_send_message_silent(bp, &install,
2553 sizeof(install),
2554 INSTALL_PACKAGE_TIMEOUT);
2555 memcpy(&resp, bp->hwrm_cmd_resp_addr, sizeof(resp));
2556
2557 if (rc && ((struct hwrm_err_output *)&resp)->cmd_err ==
2558 NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE) {
2559 /* FW has cleared NVM area, driver will create
2560 * UPDATE directory and try the flash again
2561 */
2562 defrag_attempted = true;
2563 install.flags = 0;
2564 rc = __bnxt_flash_nvram(bp->dev,
2565 BNX_DIR_TYPE_UPDATE,
2566 BNX_DIR_ORDINAL_FIRST,
2567 0, 0, item_len, NULL,
2568 0);
2569 } else if (rc) {
2570 netdev_err(dev, "HWRM_NVM_INSTALL_UPDATE failure rc :%x\n", rc);
2571 }
2572 } else if (rc) {
2573 netdev_err(dev, "HWRM_NVM_INSTALL_UPDATE failure rc :%x\n", rc);
2574 }
2575 mutex_unlock(&bp->hwrm_cmd_lock);
2576 } while (defrag_attempted && !rc);
2577
2578 pkg_abort:
2579 dma_free_coherent(&bp->pdev->dev, modify_len, kmem, dma_handle);
2580 if (resp.result) {
2581 netdev_err(dev, "PKG install error = %d, problem_item = %d\n",
2582 (s8)resp.result, (int)resp.problem_item);
2583 rc = -ENOPKG;
2584 }
2585 if (rc == -EACCES)
2586 bnxt_print_admin_err(bp);
2587 return rc;
2588 }
2589
bnxt_flash_package_from_file(struct net_device * dev,const char * filename,u32 install_type)2590 static int bnxt_flash_package_from_file(struct net_device *dev, const char *filename,
2591 u32 install_type)
2592 {
2593 const struct firmware *fw;
2594 int rc;
2595
2596 rc = request_firmware(&fw, filename, &dev->dev);
2597 if (rc != 0) {
2598 netdev_err(dev, "PKG error %d requesting file: %s\n",
2599 rc, filename);
2600 return rc;
2601 }
2602
2603 rc = bnxt_flash_package_from_fw_obj(dev, fw, install_type);
2604
2605 release_firmware(fw);
2606
2607 return rc;
2608 }
2609
bnxt_flash_device(struct net_device * dev,struct ethtool_flash * flash)2610 static int bnxt_flash_device(struct net_device *dev,
2611 struct ethtool_flash *flash)
2612 {
2613 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) {
2614 netdev_err(dev, "flashdev not supported from a virtual function\n");
2615 return -EINVAL;
2616 }
2617
2618 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS ||
2619 flash->region > 0xffff)
2620 return bnxt_flash_package_from_file(dev, flash->data,
2621 flash->region);
2622
2623 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data);
2624 }
2625
nvm_get_dir_info(struct net_device * dev,u32 * entries,u32 * length)2626 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length)
2627 {
2628 struct bnxt *bp = netdev_priv(dev);
2629 int rc;
2630 struct hwrm_nvm_get_dir_info_input req = {0};
2631 struct hwrm_nvm_get_dir_info_output *output = bp->hwrm_cmd_resp_addr;
2632
2633 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DIR_INFO, -1, -1);
2634
2635 mutex_lock(&bp->hwrm_cmd_lock);
2636 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2637 if (!rc) {
2638 *entries = le32_to_cpu(output->entries);
2639 *length = le32_to_cpu(output->entry_length);
2640 }
2641 mutex_unlock(&bp->hwrm_cmd_lock);
2642 return rc;
2643 }
2644
bnxt_get_eeprom_len(struct net_device * dev)2645 static int bnxt_get_eeprom_len(struct net_device *dev)
2646 {
2647 struct bnxt *bp = netdev_priv(dev);
2648
2649 if (BNXT_VF(bp))
2650 return 0;
2651
2652 /* The -1 return value allows the entire 32-bit range of offsets to be
2653 * passed via the ethtool command-line utility.
2654 */
2655 return -1;
2656 }
2657
bnxt_get_nvram_directory(struct net_device * dev,u32 len,u8 * data)2658 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data)
2659 {
2660 struct bnxt *bp = netdev_priv(dev);
2661 int rc;
2662 u32 dir_entries;
2663 u32 entry_length;
2664 u8 *buf;
2665 size_t buflen;
2666 dma_addr_t dma_handle;
2667 struct hwrm_nvm_get_dir_entries_input req = {0};
2668
2669 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length);
2670 if (rc != 0)
2671 return rc;
2672
2673 if (!dir_entries || !entry_length)
2674 return -EIO;
2675
2676 /* Insert 2 bytes of directory info (count and size of entries) */
2677 if (len < 2)
2678 return -EINVAL;
2679
2680 *data++ = dir_entries;
2681 *data++ = entry_length;
2682 len -= 2;
2683 memset(data, 0xff, len);
2684
2685 buflen = dir_entries * entry_length;
2686 buf = dma_alloc_coherent(&bp->pdev->dev, buflen, &dma_handle,
2687 GFP_KERNEL);
2688 if (!buf) {
2689 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n",
2690 (unsigned)buflen);
2691 return -ENOMEM;
2692 }
2693 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DIR_ENTRIES, -1, -1);
2694 req.host_dest_addr = cpu_to_le64(dma_handle);
2695 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2696 if (rc == 0)
2697 memcpy(data, buf, len > buflen ? buflen : len);
2698 dma_free_coherent(&bp->pdev->dev, buflen, buf, dma_handle);
2699 return rc;
2700 }
2701
bnxt_get_nvram_item(struct net_device * dev,u32 index,u32 offset,u32 length,u8 * data)2702 static int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset,
2703 u32 length, u8 *data)
2704 {
2705 struct bnxt *bp = netdev_priv(dev);
2706 int rc;
2707 u8 *buf;
2708 dma_addr_t dma_handle;
2709 struct hwrm_nvm_read_input req = {0};
2710
2711 if (!length)
2712 return -EINVAL;
2713
2714 buf = dma_alloc_coherent(&bp->pdev->dev, length, &dma_handle,
2715 GFP_KERNEL);
2716 if (!buf) {
2717 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n",
2718 (unsigned)length);
2719 return -ENOMEM;
2720 }
2721 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_READ, -1, -1);
2722 req.host_dest_addr = cpu_to_le64(dma_handle);
2723 req.dir_idx = cpu_to_le16(index);
2724 req.offset = cpu_to_le32(offset);
2725 req.len = cpu_to_le32(length);
2726
2727 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2728 if (rc == 0)
2729 memcpy(data, buf, length);
2730 dma_free_coherent(&bp->pdev->dev, length, buf, dma_handle);
2731 return rc;
2732 }
2733
bnxt_find_nvram_item(struct net_device * dev,u16 type,u16 ordinal,u16 ext,u16 * index,u32 * item_length,u32 * data_length)2734 static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal,
2735 u16 ext, u16 *index, u32 *item_length,
2736 u32 *data_length)
2737 {
2738 struct bnxt *bp = netdev_priv(dev);
2739 int rc;
2740 struct hwrm_nvm_find_dir_entry_input req = {0};
2741 struct hwrm_nvm_find_dir_entry_output *output = bp->hwrm_cmd_resp_addr;
2742
2743 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_FIND_DIR_ENTRY, -1, -1);
2744 req.enables = 0;
2745 req.dir_idx = 0;
2746 req.dir_type = cpu_to_le16(type);
2747 req.dir_ordinal = cpu_to_le16(ordinal);
2748 req.dir_ext = cpu_to_le16(ext);
2749 req.opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ;
2750 mutex_lock(&bp->hwrm_cmd_lock);
2751 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2752 if (rc == 0) {
2753 if (index)
2754 *index = le16_to_cpu(output->dir_idx);
2755 if (item_length)
2756 *item_length = le32_to_cpu(output->dir_item_length);
2757 if (data_length)
2758 *data_length = le32_to_cpu(output->dir_data_length);
2759 }
2760 mutex_unlock(&bp->hwrm_cmd_lock);
2761 return rc;
2762 }
2763
bnxt_parse_pkglog(int desired_field,u8 * data,size_t datalen)2764 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen)
2765 {
2766 char *retval = NULL;
2767 char *p;
2768 char *value;
2769 int field = 0;
2770
2771 if (datalen < 1)
2772 return NULL;
2773 /* null-terminate the log data (removing last '\n'): */
2774 data[datalen - 1] = 0;
2775 for (p = data; *p != 0; p++) {
2776 field = 0;
2777 retval = NULL;
2778 while (*p != 0 && *p != '\n') {
2779 value = p;
2780 while (*p != 0 && *p != '\t' && *p != '\n')
2781 p++;
2782 if (field == desired_field)
2783 retval = value;
2784 if (*p != '\t')
2785 break;
2786 *p = 0;
2787 field++;
2788 p++;
2789 }
2790 if (*p == 0)
2791 break;
2792 *p = 0;
2793 }
2794 return retval;
2795 }
2796
bnxt_get_pkgver(struct net_device * dev)2797 static void bnxt_get_pkgver(struct net_device *dev)
2798 {
2799 struct bnxt *bp = netdev_priv(dev);
2800 u16 index = 0;
2801 char *pkgver;
2802 u32 pkglen;
2803 u8 *pkgbuf;
2804 int len;
2805
2806 if (bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG,
2807 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE,
2808 &index, NULL, &pkglen) != 0)
2809 return;
2810
2811 pkgbuf = kzalloc(pkglen, GFP_KERNEL);
2812 if (!pkgbuf) {
2813 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n",
2814 pkglen);
2815 return;
2816 }
2817
2818 if (bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf))
2819 goto err;
2820
2821 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf,
2822 pkglen);
2823 if (pkgver && *pkgver != 0 && isdigit(*pkgver)) {
2824 len = strlen(bp->fw_ver_str);
2825 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len - 1,
2826 "/pkg %s", pkgver);
2827 }
2828 err:
2829 kfree(pkgbuf);
2830 }
2831
bnxt_get_eeprom(struct net_device * dev,struct ethtool_eeprom * eeprom,u8 * data)2832 static int bnxt_get_eeprom(struct net_device *dev,
2833 struct ethtool_eeprom *eeprom,
2834 u8 *data)
2835 {
2836 u32 index;
2837 u32 offset;
2838
2839 if (eeprom->offset == 0) /* special offset value to get directory */
2840 return bnxt_get_nvram_directory(dev, eeprom->len, data);
2841
2842 index = eeprom->offset >> 24;
2843 offset = eeprom->offset & 0xffffff;
2844
2845 if (index == 0) {
2846 netdev_err(dev, "unsupported index value: %d\n", index);
2847 return -EINVAL;
2848 }
2849
2850 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data);
2851 }
2852
bnxt_erase_nvram_directory(struct net_device * dev,u8 index)2853 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index)
2854 {
2855 struct bnxt *bp = netdev_priv(dev);
2856 struct hwrm_nvm_erase_dir_entry_input req = {0};
2857
2858 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_ERASE_DIR_ENTRY, -1, -1);
2859 req.dir_idx = cpu_to_le16(index);
2860 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2861 }
2862
bnxt_set_eeprom(struct net_device * dev,struct ethtool_eeprom * eeprom,u8 * data)2863 static int bnxt_set_eeprom(struct net_device *dev,
2864 struct ethtool_eeprom *eeprom,
2865 u8 *data)
2866 {
2867 struct bnxt *bp = netdev_priv(dev);
2868 u8 index, dir_op;
2869 u16 type, ext, ordinal, attr;
2870
2871 if (!BNXT_PF(bp)) {
2872 netdev_err(dev, "NVM write not supported from a virtual function\n");
2873 return -EINVAL;
2874 }
2875
2876 type = eeprom->magic >> 16;
2877
2878 if (type == 0xffff) { /* special value for directory operations */
2879 index = eeprom->magic & 0xff;
2880 dir_op = eeprom->magic >> 8;
2881 if (index == 0)
2882 return -EINVAL;
2883 switch (dir_op) {
2884 case 0x0e: /* erase */
2885 if (eeprom->offset != ~eeprom->magic)
2886 return -EINVAL;
2887 return bnxt_erase_nvram_directory(dev, index - 1);
2888 default:
2889 return -EINVAL;
2890 }
2891 }
2892
2893 /* Create or re-write an NVM item: */
2894 if (bnxt_dir_type_is_executable(type))
2895 return -EOPNOTSUPP;
2896 ext = eeprom->magic & 0xffff;
2897 ordinal = eeprom->offset >> 16;
2898 attr = eeprom->offset & 0xffff;
2899
2900 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, data,
2901 eeprom->len);
2902 }
2903
bnxt_set_eee(struct net_device * dev,struct ethtool_eee * edata)2904 static int bnxt_set_eee(struct net_device *dev, struct ethtool_eee *edata)
2905 {
2906 struct bnxt *bp = netdev_priv(dev);
2907 struct ethtool_eee *eee = &bp->eee;
2908 struct bnxt_link_info *link_info = &bp->link_info;
2909 u32 advertising;
2910 int rc = 0;
2911
2912 if (!BNXT_PHY_CFG_ABLE(bp))
2913 return -EOPNOTSUPP;
2914
2915 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP))
2916 return -EOPNOTSUPP;
2917
2918 mutex_lock(&bp->link_lock);
2919 advertising = _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
2920 if (!edata->eee_enabled)
2921 goto eee_ok;
2922
2923 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
2924 netdev_warn(dev, "EEE requires autoneg\n");
2925 rc = -EINVAL;
2926 goto eee_exit;
2927 }
2928 if (edata->tx_lpi_enabled) {
2929 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi ||
2930 edata->tx_lpi_timer < bp->lpi_tmr_lo)) {
2931 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n",
2932 bp->lpi_tmr_lo, bp->lpi_tmr_hi);
2933 rc = -EINVAL;
2934 goto eee_exit;
2935 } else if (!bp->lpi_tmr_hi) {
2936 edata->tx_lpi_timer = eee->tx_lpi_timer;
2937 }
2938 }
2939 if (!edata->advertised) {
2940 edata->advertised = advertising & eee->supported;
2941 } else if (edata->advertised & ~advertising) {
2942 netdev_warn(dev, "EEE advertised %x must be a subset of autoneg advertised speeds %x\n",
2943 edata->advertised, advertising);
2944 rc = -EINVAL;
2945 goto eee_exit;
2946 }
2947
2948 eee->advertised = edata->advertised;
2949 eee->tx_lpi_enabled = edata->tx_lpi_enabled;
2950 eee->tx_lpi_timer = edata->tx_lpi_timer;
2951 eee_ok:
2952 eee->eee_enabled = edata->eee_enabled;
2953
2954 if (netif_running(dev))
2955 rc = bnxt_hwrm_set_link_setting(bp, false, true);
2956
2957 eee_exit:
2958 mutex_unlock(&bp->link_lock);
2959 return rc;
2960 }
2961
bnxt_get_eee(struct net_device * dev,struct ethtool_eee * edata)2962 static int bnxt_get_eee(struct net_device *dev, struct ethtool_eee *edata)
2963 {
2964 struct bnxt *bp = netdev_priv(dev);
2965
2966 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP))
2967 return -EOPNOTSUPP;
2968
2969 *edata = bp->eee;
2970 if (!bp->eee.eee_enabled) {
2971 /* Preserve tx_lpi_timer so that the last value will be used
2972 * by default when it is re-enabled.
2973 */
2974 edata->advertised = 0;
2975 edata->tx_lpi_enabled = 0;
2976 }
2977
2978 if (!bp->eee.eee_active)
2979 edata->lp_advertised = 0;
2980
2981 return 0;
2982 }
2983
bnxt_read_sfp_module_eeprom_info(struct bnxt * bp,u16 i2c_addr,u16 page_number,u16 start_addr,u16 data_length,u8 * buf)2984 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr,
2985 u16 page_number, u16 start_addr,
2986 u16 data_length, u8 *buf)
2987 {
2988 struct hwrm_port_phy_i2c_read_input req = {0};
2989 struct hwrm_port_phy_i2c_read_output *output = bp->hwrm_cmd_resp_addr;
2990 int rc, byte_offset = 0;
2991
2992 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_I2C_READ, -1, -1);
2993 req.i2c_slave_addr = i2c_addr;
2994 req.page_number = cpu_to_le16(page_number);
2995 req.port_id = cpu_to_le16(bp->pf.port_id);
2996 do {
2997 u16 xfer_size;
2998
2999 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE);
3000 data_length -= xfer_size;
3001 req.page_offset = cpu_to_le16(start_addr + byte_offset);
3002 req.data_length = xfer_size;
3003 req.enables = cpu_to_le32(start_addr + byte_offset ?
3004 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 0);
3005 mutex_lock(&bp->hwrm_cmd_lock);
3006 rc = _hwrm_send_message(bp, &req, sizeof(req),
3007 HWRM_CMD_TIMEOUT);
3008 if (!rc)
3009 memcpy(buf + byte_offset, output->data, xfer_size);
3010 mutex_unlock(&bp->hwrm_cmd_lock);
3011 byte_offset += xfer_size;
3012 } while (!rc && data_length > 0);
3013
3014 return rc;
3015 }
3016
bnxt_get_module_info(struct net_device * dev,struct ethtool_modinfo * modinfo)3017 static int bnxt_get_module_info(struct net_device *dev,
3018 struct ethtool_modinfo *modinfo)
3019 {
3020 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1];
3021 struct bnxt *bp = netdev_priv(dev);
3022 int rc;
3023
3024 /* No point in going further if phy status indicates
3025 * module is not inserted or if it is powered down or
3026 * if it is of type 10GBase-T
3027 */
3028 if (bp->link_info.module_status >
3029 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG)
3030 return -EOPNOTSUPP;
3031
3032 /* This feature is not supported in older firmware versions */
3033 if (bp->hwrm_spec_code < 0x10202)
3034 return -EOPNOTSUPP;
3035
3036 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3037 SFF_DIAG_SUPPORT_OFFSET + 1,
3038 data);
3039 if (!rc) {
3040 u8 module_id = data[0];
3041 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET];
3042
3043 switch (module_id) {
3044 case SFF_MODULE_ID_SFP:
3045 modinfo->type = ETH_MODULE_SFF_8472;
3046 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
3047 if (!diag_supported)
3048 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
3049 break;
3050 case SFF_MODULE_ID_QSFP:
3051 case SFF_MODULE_ID_QSFP_PLUS:
3052 modinfo->type = ETH_MODULE_SFF_8436;
3053 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
3054 break;
3055 case SFF_MODULE_ID_QSFP28:
3056 modinfo->type = ETH_MODULE_SFF_8636;
3057 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
3058 break;
3059 default:
3060 rc = -EOPNOTSUPP;
3061 break;
3062 }
3063 }
3064 return rc;
3065 }
3066
bnxt_get_module_eeprom(struct net_device * dev,struct ethtool_eeprom * eeprom,u8 * data)3067 static int bnxt_get_module_eeprom(struct net_device *dev,
3068 struct ethtool_eeprom *eeprom,
3069 u8 *data)
3070 {
3071 struct bnxt *bp = netdev_priv(dev);
3072 u16 start = eeprom->offset, length = eeprom->len;
3073 int rc = 0;
3074
3075 memset(data, 0, eeprom->len);
3076
3077 /* Read A0 portion of the EEPROM */
3078 if (start < ETH_MODULE_SFF_8436_LEN) {
3079 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN)
3080 length = ETH_MODULE_SFF_8436_LEN - start;
3081 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0,
3082 start, length, data);
3083 if (rc)
3084 return rc;
3085 start += length;
3086 data += length;
3087 length = eeprom->len - length;
3088 }
3089
3090 /* Read A2 portion of the EEPROM */
3091 if (length) {
3092 start -= ETH_MODULE_SFF_8436_LEN;
3093 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 0,
3094 start, length, data);
3095 }
3096 return rc;
3097 }
3098
bnxt_nway_reset(struct net_device * dev)3099 static int bnxt_nway_reset(struct net_device *dev)
3100 {
3101 int rc = 0;
3102
3103 struct bnxt *bp = netdev_priv(dev);
3104 struct bnxt_link_info *link_info = &bp->link_info;
3105
3106 if (!BNXT_PHY_CFG_ABLE(bp))
3107 return -EOPNOTSUPP;
3108
3109 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED))
3110 return -EINVAL;
3111
3112 if (netif_running(dev))
3113 rc = bnxt_hwrm_set_link_setting(bp, true, false);
3114
3115 return rc;
3116 }
3117
bnxt_set_phys_id(struct net_device * dev,enum ethtool_phys_id_state state)3118 static int bnxt_set_phys_id(struct net_device *dev,
3119 enum ethtool_phys_id_state state)
3120 {
3121 struct hwrm_port_led_cfg_input req = {0};
3122 struct bnxt *bp = netdev_priv(dev);
3123 struct bnxt_pf_info *pf = &bp->pf;
3124 struct bnxt_led_cfg *led_cfg;
3125 u8 led_state;
3126 __le16 duration;
3127 int i;
3128
3129 if (!bp->num_leds || BNXT_VF(bp))
3130 return -EOPNOTSUPP;
3131
3132 if (state == ETHTOOL_ID_ACTIVE) {
3133 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT;
3134 duration = cpu_to_le16(500);
3135 } else if (state == ETHTOOL_ID_INACTIVE) {
3136 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT;
3137 duration = cpu_to_le16(0);
3138 } else {
3139 return -EINVAL;
3140 }
3141 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_CFG, -1, -1);
3142 req.port_id = cpu_to_le16(pf->port_id);
3143 req.num_leds = bp->num_leds;
3144 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3145 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3146 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3147 led_cfg->led_id = bp->leds[i].led_id;
3148 led_cfg->led_state = led_state;
3149 led_cfg->led_blink_on = duration;
3150 led_cfg->led_blink_off = duration;
3151 led_cfg->led_group_id = bp->leds[i].led_group_id;
3152 }
3153 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3154 }
3155
bnxt_hwrm_selftest_irq(struct bnxt * bp,u16 cmpl_ring)3156 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring)
3157 {
3158 struct hwrm_selftest_irq_input req = {0};
3159
3160 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_IRQ, cmpl_ring, -1);
3161 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3162 }
3163
bnxt_test_irq(struct bnxt * bp)3164 static int bnxt_test_irq(struct bnxt *bp)
3165 {
3166 int i;
3167
3168 for (i = 0; i < bp->cp_nr_rings; i++) {
3169 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id;
3170 int rc;
3171
3172 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring);
3173 if (rc)
3174 return rc;
3175 }
3176 return 0;
3177 }
3178
bnxt_hwrm_mac_loopback(struct bnxt * bp,bool enable)3179 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable)
3180 {
3181 struct hwrm_port_mac_cfg_input req = {0};
3182
3183 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_MAC_CFG, -1, -1);
3184
3185 req.enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK);
3186 if (enable)
3187 req.lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL;
3188 else
3189 req.lpbk = PORT_MAC_CFG_REQ_LPBK_NONE;
3190 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3191 }
3192
bnxt_query_force_speeds(struct bnxt * bp,u16 * force_speeds)3193 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds)
3194 {
3195 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3196 struct hwrm_port_phy_qcaps_input req = {0};
3197 int rc;
3198
3199 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
3200 mutex_lock(&bp->hwrm_cmd_lock);
3201 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3202 if (!rc)
3203 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode);
3204
3205 mutex_unlock(&bp->hwrm_cmd_lock);
3206 return rc;
3207 }
3208
bnxt_disable_an_for_lpbk(struct bnxt * bp,struct hwrm_port_phy_cfg_input * req)3209 static int bnxt_disable_an_for_lpbk(struct bnxt *bp,
3210 struct hwrm_port_phy_cfg_input *req)
3211 {
3212 struct bnxt_link_info *link_info = &bp->link_info;
3213 u16 fw_advertising;
3214 u16 fw_speed;
3215 int rc;
3216
3217 if (!link_info->autoneg ||
3218 (bp->phy_flags & BNXT_PHY_FL_AN_PHY_LPBK))
3219 return 0;
3220
3221 rc = bnxt_query_force_speeds(bp, &fw_advertising);
3222 if (rc)
3223 return rc;
3224
3225 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB;
3226 if (bp->link_info.link_up)
3227 fw_speed = bp->link_info.link_speed;
3228 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB)
3229 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB;
3230 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB)
3231 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB;
3232 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB)
3233 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB;
3234 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB)
3235 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB;
3236
3237 req->force_link_speed = cpu_to_le16(fw_speed);
3238 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE |
3239 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
3240 rc = hwrm_send_message(bp, req, sizeof(*req), HWRM_CMD_TIMEOUT);
3241 req->flags = 0;
3242 req->force_link_speed = cpu_to_le16(0);
3243 return rc;
3244 }
3245
bnxt_hwrm_phy_loopback(struct bnxt * bp,bool enable,bool ext)3246 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext)
3247 {
3248 struct hwrm_port_phy_cfg_input req = {0};
3249
3250 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
3251
3252 if (enable) {
3253 bnxt_disable_an_for_lpbk(bp, &req);
3254 if (ext)
3255 req.lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL;
3256 else
3257 req.lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL;
3258 } else {
3259 req.lpbk = PORT_PHY_CFG_REQ_LPBK_NONE;
3260 }
3261 req.enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK);
3262 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3263 }
3264
bnxt_rx_loopback(struct bnxt * bp,struct bnxt_cp_ring_info * cpr,u32 raw_cons,int pkt_size)3265 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
3266 u32 raw_cons, int pkt_size)
3267 {
3268 struct bnxt_napi *bnapi = cpr->bnapi;
3269 struct bnxt_rx_ring_info *rxr;
3270 struct bnxt_sw_rx_bd *rx_buf;
3271 struct rx_cmp *rxcmp;
3272 u16 cp_cons, cons;
3273 u8 *data;
3274 u32 len;
3275 int i;
3276
3277 rxr = bnapi->rx_ring;
3278 cp_cons = RING_CMP(raw_cons);
3279 rxcmp = (struct rx_cmp *)
3280 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
3281 cons = rxcmp->rx_cmp_opaque;
3282 rx_buf = &rxr->rx_buf_ring[cons];
3283 data = rx_buf->data_ptr;
3284 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
3285 if (len != pkt_size)
3286 return -EIO;
3287 i = ETH_ALEN;
3288 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr))
3289 return -EIO;
3290 i += ETH_ALEN;
3291 for ( ; i < pkt_size; i++) {
3292 if (data[i] != (u8)(i & 0xff))
3293 return -EIO;
3294 }
3295 return 0;
3296 }
3297
bnxt_poll_loopback(struct bnxt * bp,struct bnxt_cp_ring_info * cpr,int pkt_size)3298 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
3299 int pkt_size)
3300 {
3301 struct tx_cmp *txcmp;
3302 int rc = -EIO;
3303 u32 raw_cons;
3304 u32 cons;
3305 int i;
3306
3307 raw_cons = cpr->cp_raw_cons;
3308 for (i = 0; i < 200; i++) {
3309 cons = RING_CMP(raw_cons);
3310 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
3311
3312 if (!TX_CMP_VALID(txcmp, raw_cons)) {
3313 udelay(5);
3314 continue;
3315 }
3316
3317 /* The valid test of the entry must be done first before
3318 * reading any further.
3319 */
3320 dma_rmb();
3321 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP) {
3322 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size);
3323 raw_cons = NEXT_RAW_CMP(raw_cons);
3324 raw_cons = NEXT_RAW_CMP(raw_cons);
3325 break;
3326 }
3327 raw_cons = NEXT_RAW_CMP(raw_cons);
3328 }
3329 cpr->cp_raw_cons = raw_cons;
3330 return rc;
3331 }
3332
bnxt_run_loopback(struct bnxt * bp)3333 static int bnxt_run_loopback(struct bnxt *bp)
3334 {
3335 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0];
3336 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
3337 struct bnxt_cp_ring_info *cpr;
3338 int pkt_size, i = 0;
3339 struct sk_buff *skb;
3340 dma_addr_t map;
3341 u8 *data;
3342 int rc;
3343
3344 cpr = &rxr->bnapi->cp_ring;
3345 if (bp->flags & BNXT_FLAG_CHIP_P5)
3346 cpr = cpr->cp_ring_arr[BNXT_RX_HDL];
3347 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh);
3348 skb = netdev_alloc_skb(bp->dev, pkt_size);
3349 if (!skb)
3350 return -ENOMEM;
3351 data = skb_put(skb, pkt_size);
3352 eth_broadcast_addr(data);
3353 i += ETH_ALEN;
3354 ether_addr_copy(&data[i], bp->dev->dev_addr);
3355 i += ETH_ALEN;
3356 for ( ; i < pkt_size; i++)
3357 data[i] = (u8)(i & 0xff);
3358
3359 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,
3360 PCI_DMA_TODEVICE);
3361 if (dma_mapping_error(&bp->pdev->dev, map)) {
3362 dev_kfree_skb(skb);
3363 return -EIO;
3364 }
3365 bnxt_xmit_bd(bp, txr, map, pkt_size);
3366
3367 /* Sync BD data before updating doorbell */
3368 wmb();
3369
3370 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod);
3371 rc = bnxt_poll_loopback(bp, cpr, pkt_size);
3372
3373 dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE);
3374 dev_kfree_skb(skb);
3375 return rc;
3376 }
3377
bnxt_run_fw_tests(struct bnxt * bp,u8 test_mask,u8 * test_results)3378 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results)
3379 {
3380 struct hwrm_selftest_exec_output *resp = bp->hwrm_cmd_resp_addr;
3381 struct hwrm_selftest_exec_input req = {0};
3382 int rc;
3383
3384 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_EXEC, -1, -1);
3385 mutex_lock(&bp->hwrm_cmd_lock);
3386 resp->test_success = 0;
3387 req.flags = test_mask;
3388 rc = _hwrm_send_message(bp, &req, sizeof(req), bp->test_info->timeout);
3389 *test_results = resp->test_success;
3390 mutex_unlock(&bp->hwrm_cmd_lock);
3391 return rc;
3392 }
3393
3394 #define BNXT_DRV_TESTS 4
3395 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS)
3396 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1)
3397 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2)
3398 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3)
3399
bnxt_self_test(struct net_device * dev,struct ethtool_test * etest,u64 * buf)3400 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest,
3401 u64 *buf)
3402 {
3403 struct bnxt *bp = netdev_priv(dev);
3404 bool do_ext_lpbk = false;
3405 bool offline = false;
3406 u8 test_results = 0;
3407 u8 test_mask = 0;
3408 int rc = 0, i;
3409
3410 if (!bp->num_tests || !BNXT_PF(bp))
3411 return;
3412 memset(buf, 0, sizeof(u64) * bp->num_tests);
3413 if (!netif_running(dev)) {
3414 etest->flags |= ETH_TEST_FL_FAILED;
3415 return;
3416 }
3417
3418 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) &&
3419 (bp->phy_flags & BNXT_PHY_FL_EXT_LPBK))
3420 do_ext_lpbk = true;
3421
3422 if (etest->flags & ETH_TEST_FL_OFFLINE) {
3423 if (bp->pf.active_vfs || !BNXT_SINGLE_PF(bp)) {
3424 etest->flags |= ETH_TEST_FL_FAILED;
3425 netdev_warn(dev, "Offline tests cannot be run with active VFs or on shared PF\n");
3426 return;
3427 }
3428 offline = true;
3429 }
3430
3431 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) {
3432 u8 bit_val = 1 << i;
3433
3434 if (!(bp->test_info->offline_mask & bit_val))
3435 test_mask |= bit_val;
3436 else if (offline)
3437 test_mask |= bit_val;
3438 }
3439 if (!offline) {
3440 bnxt_run_fw_tests(bp, test_mask, &test_results);
3441 } else {
3442 rc = bnxt_close_nic(bp, false, false);
3443 if (rc)
3444 return;
3445 bnxt_run_fw_tests(bp, test_mask, &test_results);
3446
3447 buf[BNXT_MACLPBK_TEST_IDX] = 1;
3448 bnxt_hwrm_mac_loopback(bp, true);
3449 msleep(250);
3450 rc = bnxt_half_open_nic(bp);
3451 if (rc) {
3452 bnxt_hwrm_mac_loopback(bp, false);
3453 etest->flags |= ETH_TEST_FL_FAILED;
3454 return;
3455 }
3456 if (bnxt_run_loopback(bp))
3457 etest->flags |= ETH_TEST_FL_FAILED;
3458 else
3459 buf[BNXT_MACLPBK_TEST_IDX] = 0;
3460
3461 bnxt_hwrm_mac_loopback(bp, false);
3462 bnxt_hwrm_phy_loopback(bp, true, false);
3463 msleep(1000);
3464 if (bnxt_run_loopback(bp)) {
3465 buf[BNXT_PHYLPBK_TEST_IDX] = 1;
3466 etest->flags |= ETH_TEST_FL_FAILED;
3467 }
3468 if (do_ext_lpbk) {
3469 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
3470 bnxt_hwrm_phy_loopback(bp, true, true);
3471 msleep(1000);
3472 if (bnxt_run_loopback(bp)) {
3473 buf[BNXT_EXTLPBK_TEST_IDX] = 1;
3474 etest->flags |= ETH_TEST_FL_FAILED;
3475 }
3476 }
3477 bnxt_hwrm_phy_loopback(bp, false, false);
3478 bnxt_half_close_nic(bp);
3479 rc = bnxt_open_nic(bp, false, true);
3480 }
3481 if (rc || bnxt_test_irq(bp)) {
3482 buf[BNXT_IRQ_TEST_IDX] = 1;
3483 etest->flags |= ETH_TEST_FL_FAILED;
3484 }
3485 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) {
3486 u8 bit_val = 1 << i;
3487
3488 if ((test_mask & bit_val) && !(test_results & bit_val)) {
3489 buf[i] = 1;
3490 etest->flags |= ETH_TEST_FL_FAILED;
3491 }
3492 }
3493 }
3494
bnxt_reset(struct net_device * dev,u32 * flags)3495 static int bnxt_reset(struct net_device *dev, u32 *flags)
3496 {
3497 struct bnxt *bp = netdev_priv(dev);
3498 bool reload = false;
3499 u32 req = *flags;
3500
3501 if (!req)
3502 return -EINVAL;
3503
3504 if (!BNXT_PF(bp)) {
3505 netdev_err(dev, "Reset is not supported from a VF\n");
3506 return -EOPNOTSUPP;
3507 }
3508
3509 if (pci_vfs_assigned(bp->pdev) &&
3510 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) {
3511 netdev_err(dev,
3512 "Reset not allowed when VFs are assigned to VMs\n");
3513 return -EBUSY;
3514 }
3515
3516 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) {
3517 /* This feature is not supported in older firmware versions */
3518 if (bp->hwrm_spec_code >= 0x10803) {
3519 if (!bnxt_firmware_reset_chip(dev)) {
3520 netdev_info(dev, "Firmware reset request successful.\n");
3521 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET))
3522 reload = true;
3523 *flags &= ~BNXT_FW_RESET_CHIP;
3524 }
3525 } else if (req == BNXT_FW_RESET_CHIP) {
3526 return -EOPNOTSUPP; /* only request, fail hard */
3527 }
3528 }
3529
3530 if (req & BNXT_FW_RESET_AP) {
3531 /* This feature is not supported in older firmware versions */
3532 if (bp->hwrm_spec_code >= 0x10803) {
3533 if (!bnxt_firmware_reset_ap(dev)) {
3534 netdev_info(dev, "Reset application processor successful.\n");
3535 reload = true;
3536 *flags &= ~BNXT_FW_RESET_AP;
3537 }
3538 } else if (req == BNXT_FW_RESET_AP) {
3539 return -EOPNOTSUPP; /* only request, fail hard */
3540 }
3541 }
3542
3543 if (reload)
3544 netdev_info(dev, "Reload driver to complete reset\n");
3545
3546 return 0;
3547 }
3548
bnxt_hwrm_dbg_dma_data(struct bnxt * bp,void * msg,int msg_len,struct bnxt_hwrm_dbg_dma_info * info)3549 static int bnxt_hwrm_dbg_dma_data(struct bnxt *bp, void *msg, int msg_len,
3550 struct bnxt_hwrm_dbg_dma_info *info)
3551 {
3552 struct hwrm_dbg_cmn_output *cmn_resp = bp->hwrm_cmd_resp_addr;
3553 struct hwrm_dbg_cmn_input *cmn_req = msg;
3554 __le16 *seq_ptr = msg + info->seq_off;
3555 u16 seq = 0, len, segs_off;
3556 void *resp = cmn_resp;
3557 dma_addr_t dma_handle;
3558 int rc, off = 0;
3559 void *dma_buf;
3560
3561 dma_buf = dma_alloc_coherent(&bp->pdev->dev, info->dma_len, &dma_handle,
3562 GFP_KERNEL);
3563 if (!dma_buf)
3564 return -ENOMEM;
3565
3566 segs_off = offsetof(struct hwrm_dbg_coredump_list_output,
3567 total_segments);
3568 cmn_req->host_dest_addr = cpu_to_le64(dma_handle);
3569 cmn_req->host_buf_len = cpu_to_le32(info->dma_len);
3570 mutex_lock(&bp->hwrm_cmd_lock);
3571 while (1) {
3572 *seq_ptr = cpu_to_le16(seq);
3573 rc = _hwrm_send_message(bp, msg, msg_len,
3574 HWRM_COREDUMP_TIMEOUT);
3575 if (rc)
3576 break;
3577
3578 len = le16_to_cpu(*((__le16 *)(resp + info->data_len_off)));
3579 if (!seq &&
3580 cmn_req->req_type == cpu_to_le16(HWRM_DBG_COREDUMP_LIST)) {
3581 info->segs = le16_to_cpu(*((__le16 *)(resp +
3582 segs_off)));
3583 if (!info->segs) {
3584 rc = -EIO;
3585 break;
3586 }
3587
3588 info->dest_buf_size = info->segs *
3589 sizeof(struct coredump_segment_record);
3590 info->dest_buf = kmalloc(info->dest_buf_size,
3591 GFP_KERNEL);
3592 if (!info->dest_buf) {
3593 rc = -ENOMEM;
3594 break;
3595 }
3596 }
3597
3598 if (info->dest_buf) {
3599 if ((info->seg_start + off + len) <=
3600 BNXT_COREDUMP_BUF_LEN(info->buf_len)) {
3601 memcpy(info->dest_buf + off, dma_buf, len);
3602 } else {
3603 rc = -ENOBUFS;
3604 break;
3605 }
3606 }
3607
3608 if (cmn_req->req_type ==
3609 cpu_to_le16(HWRM_DBG_COREDUMP_RETRIEVE))
3610 info->dest_buf_size += len;
3611
3612 if (!(cmn_resp->flags & HWRM_DBG_CMN_FLAGS_MORE))
3613 break;
3614
3615 seq++;
3616 off += len;
3617 }
3618 mutex_unlock(&bp->hwrm_cmd_lock);
3619 dma_free_coherent(&bp->pdev->dev, info->dma_len, dma_buf, dma_handle);
3620 return rc;
3621 }
3622
bnxt_hwrm_dbg_coredump_list(struct bnxt * bp,struct bnxt_coredump * coredump)3623 static int bnxt_hwrm_dbg_coredump_list(struct bnxt *bp,
3624 struct bnxt_coredump *coredump)
3625 {
3626 struct hwrm_dbg_coredump_list_input req = {0};
3627 struct bnxt_hwrm_dbg_dma_info info = {NULL};
3628 int rc;
3629
3630 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_LIST, -1, -1);
3631
3632 info.dma_len = COREDUMP_LIST_BUF_LEN;
3633 info.seq_off = offsetof(struct hwrm_dbg_coredump_list_input, seq_no);
3634 info.data_len_off = offsetof(struct hwrm_dbg_coredump_list_output,
3635 data_len);
3636
3637 rc = bnxt_hwrm_dbg_dma_data(bp, &req, sizeof(req), &info);
3638 if (!rc) {
3639 coredump->data = info.dest_buf;
3640 coredump->data_size = info.dest_buf_size;
3641 coredump->total_segs = info.segs;
3642 }
3643 return rc;
3644 }
3645
bnxt_hwrm_dbg_coredump_initiate(struct bnxt * bp,u16 component_id,u16 segment_id)3646 static int bnxt_hwrm_dbg_coredump_initiate(struct bnxt *bp, u16 component_id,
3647 u16 segment_id)
3648 {
3649 struct hwrm_dbg_coredump_initiate_input req = {0};
3650
3651 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_INITIATE, -1, -1);
3652 req.component_id = cpu_to_le16(component_id);
3653 req.segment_id = cpu_to_le16(segment_id);
3654
3655 return hwrm_send_message(bp, &req, sizeof(req), HWRM_COREDUMP_TIMEOUT);
3656 }
3657
bnxt_hwrm_dbg_coredump_retrieve(struct bnxt * bp,u16 component_id,u16 segment_id,u32 * seg_len,void * buf,u32 buf_len,u32 offset)3658 static int bnxt_hwrm_dbg_coredump_retrieve(struct bnxt *bp, u16 component_id,
3659 u16 segment_id, u32 *seg_len,
3660 void *buf, u32 buf_len, u32 offset)
3661 {
3662 struct hwrm_dbg_coredump_retrieve_input req = {0};
3663 struct bnxt_hwrm_dbg_dma_info info = {NULL};
3664 int rc;
3665
3666 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_RETRIEVE, -1, -1);
3667 req.component_id = cpu_to_le16(component_id);
3668 req.segment_id = cpu_to_le16(segment_id);
3669
3670 info.dma_len = COREDUMP_RETRIEVE_BUF_LEN;
3671 info.seq_off = offsetof(struct hwrm_dbg_coredump_retrieve_input,
3672 seq_no);
3673 info.data_len_off = offsetof(struct hwrm_dbg_coredump_retrieve_output,
3674 data_len);
3675 if (buf) {
3676 info.dest_buf = buf + offset;
3677 info.buf_len = buf_len;
3678 info.seg_start = offset;
3679 }
3680
3681 rc = bnxt_hwrm_dbg_dma_data(bp, &req, sizeof(req), &info);
3682 if (!rc)
3683 *seg_len = info.dest_buf_size;
3684
3685 return rc;
3686 }
3687
3688 static void
bnxt_fill_coredump_seg_hdr(struct bnxt * bp,struct bnxt_coredump_segment_hdr * seg_hdr,struct coredump_segment_record * seg_rec,u32 seg_len,int status,u32 duration,u32 instance)3689 bnxt_fill_coredump_seg_hdr(struct bnxt *bp,
3690 struct bnxt_coredump_segment_hdr *seg_hdr,
3691 struct coredump_segment_record *seg_rec, u32 seg_len,
3692 int status, u32 duration, u32 instance)
3693 {
3694 memset(seg_hdr, 0, sizeof(*seg_hdr));
3695 memcpy(seg_hdr->signature, "sEgM", 4);
3696 if (seg_rec) {
3697 seg_hdr->component_id = (__force __le32)seg_rec->component_id;
3698 seg_hdr->segment_id = (__force __le32)seg_rec->segment_id;
3699 seg_hdr->low_version = seg_rec->version_low;
3700 seg_hdr->high_version = seg_rec->version_hi;
3701 } else {
3702 /* For hwrm_ver_get response Component id = 2
3703 * and Segment id = 0
3704 */
3705 seg_hdr->component_id = cpu_to_le32(2);
3706 seg_hdr->segment_id = 0;
3707 }
3708 seg_hdr->function_id = cpu_to_le16(bp->pdev->devfn);
3709 seg_hdr->length = cpu_to_le32(seg_len);
3710 seg_hdr->status = cpu_to_le32(status);
3711 seg_hdr->duration = cpu_to_le32(duration);
3712 seg_hdr->data_offset = cpu_to_le32(sizeof(*seg_hdr));
3713 seg_hdr->instance = cpu_to_le32(instance);
3714 }
3715
3716 static void
bnxt_fill_coredump_record(struct bnxt * bp,struct bnxt_coredump_record * record,time64_t start,s16 start_utc,u16 total_segs,int status)3717 bnxt_fill_coredump_record(struct bnxt *bp, struct bnxt_coredump_record *record,
3718 time64_t start, s16 start_utc, u16 total_segs,
3719 int status)
3720 {
3721 time64_t end = ktime_get_real_seconds();
3722 u32 os_ver_major = 0, os_ver_minor = 0;
3723 struct tm tm;
3724
3725 time64_to_tm(start, 0, &tm);
3726 memset(record, 0, sizeof(*record));
3727 memcpy(record->signature, "cOrE", 4);
3728 record->flags = 0;
3729 record->low_version = 0;
3730 record->high_version = 1;
3731 record->asic_state = 0;
3732 strlcpy(record->system_name, utsname()->nodename,
3733 sizeof(record->system_name));
3734 record->year = cpu_to_le16(tm.tm_year + 1900);
3735 record->month = cpu_to_le16(tm.tm_mon + 1);
3736 record->day = cpu_to_le16(tm.tm_mday);
3737 record->hour = cpu_to_le16(tm.tm_hour);
3738 record->minute = cpu_to_le16(tm.tm_min);
3739 record->second = cpu_to_le16(tm.tm_sec);
3740 record->utc_bias = cpu_to_le16(start_utc);
3741 strcpy(record->commandline, "ethtool -w");
3742 record->total_segments = cpu_to_le32(total_segs);
3743
3744 sscanf(utsname()->release, "%u.%u", &os_ver_major, &os_ver_minor);
3745 record->os_ver_major = cpu_to_le32(os_ver_major);
3746 record->os_ver_minor = cpu_to_le32(os_ver_minor);
3747
3748 strlcpy(record->os_name, utsname()->sysname, 32);
3749 time64_to_tm(end, 0, &tm);
3750 record->end_year = cpu_to_le16(tm.tm_year + 1900);
3751 record->end_month = cpu_to_le16(tm.tm_mon + 1);
3752 record->end_day = cpu_to_le16(tm.tm_mday);
3753 record->end_hour = cpu_to_le16(tm.tm_hour);
3754 record->end_minute = cpu_to_le16(tm.tm_min);
3755 record->end_second = cpu_to_le16(tm.tm_sec);
3756 record->end_utc_bias = cpu_to_le16(sys_tz.tz_minuteswest * 60);
3757 record->asic_id1 = cpu_to_le32(bp->chip_num << 16 |
3758 bp->ver_resp.chip_rev << 8 |
3759 bp->ver_resp.chip_metal);
3760 record->asic_id2 = 0;
3761 record->coredump_status = cpu_to_le32(status);
3762 record->ioctl_low_version = 0;
3763 record->ioctl_high_version = 0;
3764 }
3765
bnxt_get_coredump(struct bnxt * bp,void * buf,u32 * dump_len)3766 static int bnxt_get_coredump(struct bnxt *bp, void *buf, u32 *dump_len)
3767 {
3768 u32 ver_get_resp_len = sizeof(struct hwrm_ver_get_output);
3769 u32 offset = 0, seg_hdr_len, seg_record_len, buf_len = 0;
3770 struct coredump_segment_record *seg_record = NULL;
3771 struct bnxt_coredump_segment_hdr seg_hdr;
3772 struct bnxt_coredump coredump = {NULL};
3773 time64_t start_time;
3774 u16 start_utc;
3775 int rc = 0, i;
3776
3777 if (buf)
3778 buf_len = *dump_len;
3779
3780 start_time = ktime_get_real_seconds();
3781 start_utc = sys_tz.tz_minuteswest * 60;
3782 seg_hdr_len = sizeof(seg_hdr);
3783
3784 /* First segment should be hwrm_ver_get response */
3785 *dump_len = seg_hdr_len + ver_get_resp_len;
3786 if (buf) {
3787 bnxt_fill_coredump_seg_hdr(bp, &seg_hdr, NULL, ver_get_resp_len,
3788 0, 0, 0);
3789 memcpy(buf + offset, &seg_hdr, seg_hdr_len);
3790 offset += seg_hdr_len;
3791 memcpy(buf + offset, &bp->ver_resp, ver_get_resp_len);
3792 offset += ver_get_resp_len;
3793 }
3794
3795 rc = bnxt_hwrm_dbg_coredump_list(bp, &coredump);
3796 if (rc) {
3797 netdev_err(bp->dev, "Failed to get coredump segment list\n");
3798 goto err;
3799 }
3800
3801 *dump_len += seg_hdr_len * coredump.total_segs;
3802
3803 seg_record = (struct coredump_segment_record *)coredump.data;
3804 seg_record_len = sizeof(*seg_record);
3805
3806 for (i = 0; i < coredump.total_segs; i++) {
3807 u16 comp_id = le16_to_cpu(seg_record->component_id);
3808 u16 seg_id = le16_to_cpu(seg_record->segment_id);
3809 u32 duration = 0, seg_len = 0;
3810 unsigned long start, end;
3811
3812 if (buf && ((offset + seg_hdr_len) >
3813 BNXT_COREDUMP_BUF_LEN(buf_len))) {
3814 rc = -ENOBUFS;
3815 goto err;
3816 }
3817
3818 start = jiffies;
3819
3820 rc = bnxt_hwrm_dbg_coredump_initiate(bp, comp_id, seg_id);
3821 if (rc) {
3822 netdev_err(bp->dev,
3823 "Failed to initiate coredump for seg = %d\n",
3824 seg_record->segment_id);
3825 goto next_seg;
3826 }
3827
3828 /* Write segment data into the buffer */
3829 rc = bnxt_hwrm_dbg_coredump_retrieve(bp, comp_id, seg_id,
3830 &seg_len, buf, buf_len,
3831 offset + seg_hdr_len);
3832 if (rc && rc == -ENOBUFS)
3833 goto err;
3834 else if (rc)
3835 netdev_err(bp->dev,
3836 "Failed to retrieve coredump for seg = %d\n",
3837 seg_record->segment_id);
3838
3839 next_seg:
3840 end = jiffies;
3841 duration = jiffies_to_msecs(end - start);
3842 bnxt_fill_coredump_seg_hdr(bp, &seg_hdr, seg_record, seg_len,
3843 rc, duration, 0);
3844
3845 if (buf) {
3846 /* Write segment header into the buffer */
3847 memcpy(buf + offset, &seg_hdr, seg_hdr_len);
3848 offset += seg_hdr_len + seg_len;
3849 }
3850
3851 *dump_len += seg_len;
3852 seg_record =
3853 (struct coredump_segment_record *)((u8 *)seg_record +
3854 seg_record_len);
3855 }
3856
3857 err:
3858 if (buf)
3859 bnxt_fill_coredump_record(bp, buf + offset, start_time,
3860 start_utc, coredump.total_segs + 1,
3861 rc);
3862 kfree(coredump.data);
3863 *dump_len += sizeof(struct bnxt_coredump_record);
3864 if (rc == -ENOBUFS)
3865 netdev_err(bp->dev, "Firmware returned large coredump buffer\n");
3866 return rc;
3867 }
3868
bnxt_set_dump(struct net_device * dev,struct ethtool_dump * dump)3869 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump)
3870 {
3871 struct bnxt *bp = netdev_priv(dev);
3872
3873 if (dump->flag > BNXT_DUMP_CRASH) {
3874 netdev_info(dev, "Supports only Live(0) and Crash(1) dumps.\n");
3875 return -EINVAL;
3876 }
3877
3878 if (!IS_ENABLED(CONFIG_TEE_BNXT_FW) && dump->flag == BNXT_DUMP_CRASH) {
3879 netdev_info(dev, "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n");
3880 return -EOPNOTSUPP;
3881 }
3882
3883 bp->dump_flag = dump->flag;
3884 return 0;
3885 }
3886
bnxt_get_dump_flag(struct net_device * dev,struct ethtool_dump * dump)3887 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump)
3888 {
3889 struct bnxt *bp = netdev_priv(dev);
3890
3891 if (bp->hwrm_spec_code < 0x10801)
3892 return -EOPNOTSUPP;
3893
3894 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 |
3895 bp->ver_resp.hwrm_fw_min_8b << 16 |
3896 bp->ver_resp.hwrm_fw_bld_8b << 8 |
3897 bp->ver_resp.hwrm_fw_rsvd_8b;
3898
3899 dump->flag = bp->dump_flag;
3900 if (bp->dump_flag == BNXT_DUMP_CRASH)
3901 dump->len = BNXT_CRASH_DUMP_LEN;
3902 else
3903 bnxt_get_coredump(bp, NULL, &dump->len);
3904 return 0;
3905 }
3906
bnxt_get_dump_data(struct net_device * dev,struct ethtool_dump * dump,void * buf)3907 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump,
3908 void *buf)
3909 {
3910 struct bnxt *bp = netdev_priv(dev);
3911
3912 if (bp->hwrm_spec_code < 0x10801)
3913 return -EOPNOTSUPP;
3914
3915 memset(buf, 0, dump->len);
3916
3917 dump->flag = bp->dump_flag;
3918 if (dump->flag == BNXT_DUMP_CRASH) {
3919 #ifdef CONFIG_TEE_BNXT_FW
3920 return tee_bnxt_copy_coredump(buf, 0, dump->len);
3921 #endif
3922 } else {
3923 return bnxt_get_coredump(bp, buf, &dump->len);
3924 }
3925
3926 return 0;
3927 }
3928
bnxt_ethtool_init(struct bnxt * bp)3929 void bnxt_ethtool_init(struct bnxt *bp)
3930 {
3931 struct hwrm_selftest_qlist_output *resp = bp->hwrm_cmd_resp_addr;
3932 struct hwrm_selftest_qlist_input req = {0};
3933 struct bnxt_test_info *test_info;
3934 struct net_device *dev = bp->dev;
3935 int i, rc;
3936
3937 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER))
3938 bnxt_get_pkgver(dev);
3939
3940 bp->num_tests = 0;
3941 if (bp->hwrm_spec_code < 0x10704 || !BNXT_PF(bp))
3942 return;
3943
3944 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_QLIST, -1, -1);
3945 mutex_lock(&bp->hwrm_cmd_lock);
3946 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3947 if (rc)
3948 goto ethtool_init_exit;
3949
3950 test_info = bp->test_info;
3951 if (!test_info)
3952 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL);
3953 if (!test_info)
3954 goto ethtool_init_exit;
3955
3956 bp->test_info = test_info;
3957 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS;
3958 if (bp->num_tests > BNXT_MAX_TEST)
3959 bp->num_tests = BNXT_MAX_TEST;
3960
3961 test_info->offline_mask = resp->offline_tests;
3962 test_info->timeout = le16_to_cpu(resp->test_timeout);
3963 if (!test_info->timeout)
3964 test_info->timeout = HWRM_CMD_TIMEOUT;
3965 for (i = 0; i < bp->num_tests; i++) {
3966 char *str = test_info->string[i];
3967 char *fw_str = resp->test0_name + i * 32;
3968
3969 if (i == BNXT_MACLPBK_TEST_IDX) {
3970 strcpy(str, "Mac loopback test (offline)");
3971 } else if (i == BNXT_PHYLPBK_TEST_IDX) {
3972 strcpy(str, "Phy loopback test (offline)");
3973 } else if (i == BNXT_EXTLPBK_TEST_IDX) {
3974 strcpy(str, "Ext loopback test (offline)");
3975 } else if (i == BNXT_IRQ_TEST_IDX) {
3976 strcpy(str, "Interrupt_test (offline)");
3977 } else {
3978 strlcpy(str, fw_str, ETH_GSTRING_LEN);
3979 strncat(str, " test", ETH_GSTRING_LEN - strlen(str));
3980 if (test_info->offline_mask & (1 << i))
3981 strncat(str, " (offline)",
3982 ETH_GSTRING_LEN - strlen(str));
3983 else
3984 strncat(str, " (online)",
3985 ETH_GSTRING_LEN - strlen(str));
3986 }
3987 }
3988
3989 ethtool_init_exit:
3990 mutex_unlock(&bp->hwrm_cmd_lock);
3991 }
3992
bnxt_get_eth_phy_stats(struct net_device * dev,struct ethtool_eth_phy_stats * phy_stats)3993 static void bnxt_get_eth_phy_stats(struct net_device *dev,
3994 struct ethtool_eth_phy_stats *phy_stats)
3995 {
3996 struct bnxt *bp = netdev_priv(dev);
3997 u64 *rx;
3998
3999 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
4000 return;
4001
4002 rx = bp->rx_port_stats_ext.sw_stats;
4003 phy_stats->SymbolErrorDuringCarrier =
4004 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_pcs_symbol_err));
4005 }
4006
bnxt_get_eth_mac_stats(struct net_device * dev,struct ethtool_eth_mac_stats * mac_stats)4007 static void bnxt_get_eth_mac_stats(struct net_device *dev,
4008 struct ethtool_eth_mac_stats *mac_stats)
4009 {
4010 struct bnxt *bp = netdev_priv(dev);
4011 u64 *rx, *tx;
4012
4013 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
4014 return;
4015
4016 rx = bp->port_stats.sw_stats;
4017 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
4018
4019 mac_stats->FramesReceivedOK =
4020 BNXT_GET_RX_PORT_STATS64(rx, rx_good_frames);
4021 mac_stats->FramesTransmittedOK =
4022 BNXT_GET_TX_PORT_STATS64(tx, tx_good_frames);
4023 mac_stats->FrameCheckSequenceErrors =
4024 BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames);
4025 mac_stats->AlignmentErrors =
4026 BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames);
4027 mac_stats->OutOfRangeLengthField =
4028 BNXT_GET_RX_PORT_STATS64(rx, rx_oor_len_frames);
4029 }
4030
bnxt_get_eth_ctrl_stats(struct net_device * dev,struct ethtool_eth_ctrl_stats * ctrl_stats)4031 static void bnxt_get_eth_ctrl_stats(struct net_device *dev,
4032 struct ethtool_eth_ctrl_stats *ctrl_stats)
4033 {
4034 struct bnxt *bp = netdev_priv(dev);
4035 u64 *rx;
4036
4037 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
4038 return;
4039
4040 rx = bp->port_stats.sw_stats;
4041 ctrl_stats->MACControlFramesReceived =
4042 BNXT_GET_RX_PORT_STATS64(rx, rx_ctrl_frames);
4043 }
4044
4045 static const struct ethtool_rmon_hist_range bnxt_rmon_ranges[] = {
4046 { 0, 64 },
4047 { 65, 127 },
4048 { 128, 255 },
4049 { 256, 511 },
4050 { 512, 1023 },
4051 { 1024, 1518 },
4052 { 1519, 2047 },
4053 { 2048, 4095 },
4054 { 4096, 9216 },
4055 { 9217, 16383 },
4056 {}
4057 };
4058
bnxt_get_rmon_stats(struct net_device * dev,struct ethtool_rmon_stats * rmon_stats,const struct ethtool_rmon_hist_range ** ranges)4059 static void bnxt_get_rmon_stats(struct net_device *dev,
4060 struct ethtool_rmon_stats *rmon_stats,
4061 const struct ethtool_rmon_hist_range **ranges)
4062 {
4063 struct bnxt *bp = netdev_priv(dev);
4064 u64 *rx, *tx;
4065
4066 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
4067 return;
4068
4069 rx = bp->port_stats.sw_stats;
4070 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
4071
4072 rmon_stats->jabbers =
4073 BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames);
4074 rmon_stats->oversize_pkts =
4075 BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames);
4076 rmon_stats->undersize_pkts =
4077 BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames);
4078
4079 rmon_stats->hist[0] = BNXT_GET_RX_PORT_STATS64(rx, rx_64b_frames);
4080 rmon_stats->hist[1] = BNXT_GET_RX_PORT_STATS64(rx, rx_65b_127b_frames);
4081 rmon_stats->hist[2] = BNXT_GET_RX_PORT_STATS64(rx, rx_128b_255b_frames);
4082 rmon_stats->hist[3] = BNXT_GET_RX_PORT_STATS64(rx, rx_256b_511b_frames);
4083 rmon_stats->hist[4] =
4084 BNXT_GET_RX_PORT_STATS64(rx, rx_512b_1023b_frames);
4085 rmon_stats->hist[5] =
4086 BNXT_GET_RX_PORT_STATS64(rx, rx_1024b_1518b_frames);
4087 rmon_stats->hist[6] =
4088 BNXT_GET_RX_PORT_STATS64(rx, rx_1519b_2047b_frames);
4089 rmon_stats->hist[7] =
4090 BNXT_GET_RX_PORT_STATS64(rx, rx_2048b_4095b_frames);
4091 rmon_stats->hist[8] =
4092 BNXT_GET_RX_PORT_STATS64(rx, rx_4096b_9216b_frames);
4093 rmon_stats->hist[9] =
4094 BNXT_GET_RX_PORT_STATS64(rx, rx_9217b_16383b_frames);
4095
4096 rmon_stats->hist_tx[0] =
4097 BNXT_GET_TX_PORT_STATS64(tx, tx_64b_frames);
4098 rmon_stats->hist_tx[1] =
4099 BNXT_GET_TX_PORT_STATS64(tx, tx_65b_127b_frames);
4100 rmon_stats->hist_tx[2] =
4101 BNXT_GET_TX_PORT_STATS64(tx, tx_128b_255b_frames);
4102 rmon_stats->hist_tx[3] =
4103 BNXT_GET_TX_PORT_STATS64(tx, tx_256b_511b_frames);
4104 rmon_stats->hist_tx[4] =
4105 BNXT_GET_TX_PORT_STATS64(tx, tx_512b_1023b_frames);
4106 rmon_stats->hist_tx[5] =
4107 BNXT_GET_TX_PORT_STATS64(tx, tx_1024b_1518b_frames);
4108 rmon_stats->hist_tx[6] =
4109 BNXT_GET_TX_PORT_STATS64(tx, tx_1519b_2047b_frames);
4110 rmon_stats->hist_tx[7] =
4111 BNXT_GET_TX_PORT_STATS64(tx, tx_2048b_4095b_frames);
4112 rmon_stats->hist_tx[8] =
4113 BNXT_GET_TX_PORT_STATS64(tx, tx_4096b_9216b_frames);
4114 rmon_stats->hist_tx[9] =
4115 BNXT_GET_TX_PORT_STATS64(tx, tx_9217b_16383b_frames);
4116
4117 *ranges = bnxt_rmon_ranges;
4118 }
4119
bnxt_ethtool_free(struct bnxt * bp)4120 void bnxt_ethtool_free(struct bnxt *bp)
4121 {
4122 kfree(bp->test_info);
4123 bp->test_info = NULL;
4124 }
4125
4126 const struct ethtool_ops bnxt_ethtool_ops = {
4127 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
4128 ETHTOOL_COALESCE_MAX_FRAMES |
4129 ETHTOOL_COALESCE_USECS_IRQ |
4130 ETHTOOL_COALESCE_MAX_FRAMES_IRQ |
4131 ETHTOOL_COALESCE_STATS_BLOCK_USECS |
4132 ETHTOOL_COALESCE_USE_ADAPTIVE_RX,
4133 .get_link_ksettings = bnxt_get_link_ksettings,
4134 .set_link_ksettings = bnxt_set_link_ksettings,
4135 .get_fec_stats = bnxt_get_fec_stats,
4136 .get_fecparam = bnxt_get_fecparam,
4137 .set_fecparam = bnxt_set_fecparam,
4138 .get_pause_stats = bnxt_get_pause_stats,
4139 .get_pauseparam = bnxt_get_pauseparam,
4140 .set_pauseparam = bnxt_set_pauseparam,
4141 .get_drvinfo = bnxt_get_drvinfo,
4142 .get_regs_len = bnxt_get_regs_len,
4143 .get_regs = bnxt_get_regs,
4144 .get_wol = bnxt_get_wol,
4145 .set_wol = bnxt_set_wol,
4146 .get_coalesce = bnxt_get_coalesce,
4147 .set_coalesce = bnxt_set_coalesce,
4148 .get_msglevel = bnxt_get_msglevel,
4149 .set_msglevel = bnxt_set_msglevel,
4150 .get_sset_count = bnxt_get_sset_count,
4151 .get_strings = bnxt_get_strings,
4152 .get_ethtool_stats = bnxt_get_ethtool_stats,
4153 .set_ringparam = bnxt_set_ringparam,
4154 .get_ringparam = bnxt_get_ringparam,
4155 .get_channels = bnxt_get_channels,
4156 .set_channels = bnxt_set_channels,
4157 .get_rxnfc = bnxt_get_rxnfc,
4158 .set_rxnfc = bnxt_set_rxnfc,
4159 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size,
4160 .get_rxfh_key_size = bnxt_get_rxfh_key_size,
4161 .get_rxfh = bnxt_get_rxfh,
4162 .set_rxfh = bnxt_set_rxfh,
4163 .flash_device = bnxt_flash_device,
4164 .get_eeprom_len = bnxt_get_eeprom_len,
4165 .get_eeprom = bnxt_get_eeprom,
4166 .set_eeprom = bnxt_set_eeprom,
4167 .get_link = bnxt_get_link,
4168 .get_eee = bnxt_get_eee,
4169 .set_eee = bnxt_set_eee,
4170 .get_module_info = bnxt_get_module_info,
4171 .get_module_eeprom = bnxt_get_module_eeprom,
4172 .nway_reset = bnxt_nway_reset,
4173 .set_phys_id = bnxt_set_phys_id,
4174 .self_test = bnxt_self_test,
4175 .reset = bnxt_reset,
4176 .set_dump = bnxt_set_dump,
4177 .get_dump_flag = bnxt_get_dump_flag,
4178 .get_dump_data = bnxt_get_dump_data,
4179 .get_eth_phy_stats = bnxt_get_eth_phy_stats,
4180 .get_eth_mac_stats = bnxt_get_eth_mac_stats,
4181 .get_eth_ctrl_stats = bnxt_get_eth_ctrl_stats,
4182 .get_rmon_stats = bnxt_get_rmon_stats,
4183 };
4184