1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /************************************************************************
3  * Copyright 2003 Digi International (www.digi.com)
4  *
5  * Copyright (C) 2004 IBM Corporation. All rights reserved.
6  *
7  * Contact Information:
8  * Scott H Kilau <Scott_Kilau@digi.com>
9  * Wendy Xiong   <wendyx@us.ibm.com>
10  *
11  ***********************************************************************/
12 
13 #ifndef __JSM_DRIVER_H
14 #define __JSM_DRIVER_H
15 
16 #include <linux/kernel.h>
17 #include <linux/types.h>	/* To pick up the varions Linux types */
18 #include <linux/tty.h>
19 #include <linux/serial_core.h>
20 #include <linux/device.h>
21 
22 /*
23  * Debugging levels can be set using debug insmod variable
24  * They can also be compiled out completely.
25  */
26 enum {
27 	DBG_INIT	= 0x01,
28 	DBG_BASIC	= 0x02,
29 	DBG_CORE	= 0x04,
30 	DBG_OPEN	= 0x08,
31 	DBG_CLOSE	= 0x10,
32 	DBG_READ	= 0x20,
33 	DBG_WRITE	= 0x40,
34 	DBG_IOCTL	= 0x80,
35 	DBG_PROC	= 0x100,
36 	DBG_PARAM	= 0x200,
37 	DBG_PSCAN	= 0x400,
38 	DBG_EVENT	= 0x800,
39 	DBG_DRAIN	= 0x1000,
40 	DBG_MSIGS	= 0x2000,
41 	DBG_MGMT	= 0x4000,
42 	DBG_INTR	= 0x8000,
43 	DBG_CARR	= 0x10000,
44 };
45 
46 #define jsm_dbg(nlevel, pdev, fmt, ...)				\
47 do {								\
48 	if (DBG_##nlevel & jsm_debug)				\
49 		dev_dbg(pdev->dev, fmt, ##__VA_ARGS__);		\
50 } while (0)
51 
52 #define	MAXLINES	256
53 #define MAXPORTS	8
54 #define MAX_STOPS_SENT	5
55 
56 /* Board ids */
57 #define PCI_DEVICE_ID_CLASSIC_4		0x0028
58 #define PCI_DEVICE_ID_CLASSIC_8		0x0029
59 #define PCI_DEVICE_ID_CLASSIC_4_422	0x00D0
60 #define PCI_DEVICE_ID_CLASSIC_8_422	0x00D1
61 #define PCI_DEVICE_ID_NEO_4             0x00B0
62 #define PCI_DEVICE_ID_NEO_1_422         0x00CC
63 #define PCI_DEVICE_ID_NEO_1_422_485     0x00CD
64 #define PCI_DEVICE_ID_NEO_2_422_485     0x00CE
65 #define PCIE_DEVICE_ID_NEO_8            0x00F0
66 #define PCIE_DEVICE_ID_NEO_4            0x00F1
67 #define PCIE_DEVICE_ID_NEO_4RJ45        0x00F2
68 #define PCIE_DEVICE_ID_NEO_8RJ45        0x00F3
69 
70 /* Board type definitions */
71 
72 #define T_NEO		0000
73 #define T_CLASSIC	0001
74 #define T_PCIBUS	0400
75 
76 /* Board State Definitions */
77 
78 #define BD_RUNNING	0x0
79 #define BD_REASON	0x7f
80 #define BD_NOTFOUND	0x1
81 #define BD_NOIOPORT	0x2
82 #define BD_NOMEM	0x3
83 #define BD_NOBIOS	0x4
84 #define BD_NOFEP	0x5
85 #define BD_FAILED	0x6
86 #define BD_ALLOCATED	0x7
87 #define BD_TRIBOOT	0x8
88 #define BD_BADKME	0x80
89 
90 
91 /* 4 extra for alignment play space */
92 #define WRITEBUFLEN	((4096) + 4)
93 
94 #define JSM_VERSION	"jsm: 1.2-1-INKERNEL"
95 #define JSM_PARTNUM	"40002438_A-INKERNEL"
96 
97 struct jsm_board;
98 struct jsm_channel;
99 
100 /************************************************************************
101  * Per board operations structure					*
102  ************************************************************************/
103 struct board_ops {
104 	irq_handler_t intr;
105 	void (*uart_init)(struct jsm_channel *ch);
106 	void (*uart_off)(struct jsm_channel *ch);
107 	void (*param)(struct jsm_channel *ch);
108 	void (*assert_modem_signals)(struct jsm_channel *ch);
109 	void (*flush_uart_write)(struct jsm_channel *ch);
110 	void (*flush_uart_read)(struct jsm_channel *ch);
111 	void (*disable_receiver)(struct jsm_channel *ch);
112 	void (*enable_receiver)(struct jsm_channel *ch);
113 	void (*send_break)(struct jsm_channel *ch);
114 	void (*clear_break)(struct jsm_channel *ch);
115 	void (*send_start_character)(struct jsm_channel *ch);
116 	void (*send_stop_character)(struct jsm_channel *ch);
117 	void (*copy_data_from_queue_to_uart)(struct jsm_channel *ch);
118 	u32 (*get_uart_bytes_left)(struct jsm_channel *ch);
119 	void (*send_immediate_char)(struct jsm_channel *ch, unsigned char);
120 };
121 
122 
123 /*
124  *	Per-board information
125  */
126 struct jsm_board
127 {
128 	int		boardnum;	/* Board number: 0-32 */
129 
130 	int		type;		/* Type of board */
131 	u8		rev;		/* PCI revision ID */
132 	struct pci_dev	*pci_dev;
133 	u32		maxports;	/* MAX ports this board can handle */
134 
135 	spinlock_t	bd_intr_lock;	/* Used to protect the poller tasklet and
136 					 * the interrupt routine from each other.
137 					 */
138 
139 	u32		nasync;		/* Number of ports on card */
140 
141 	u32		irq;		/* Interrupt request number */
142 
143 	u64		membase;	/* Start of base memory of the card */
144 	u64		membase_end;	/* End of base memory of the card */
145 
146 	u8	__iomem *re_map_membase;/* Remapped memory of the card */
147 
148 	u64		iobase;		/* Start of io base of the card */
149 	u64		iobase_end;	/* End of io base of the card */
150 
151 	u32		bd_uart_offset;	/* Space between each UART */
152 
153 	struct jsm_channel *channels[MAXPORTS]; /* array of pointers to our channels. */
154 
155 	u32		bd_dividend;	/* Board/UARTs specific dividend */
156 
157 	struct board_ops *bd_ops;
158 
159 	struct list_head jsm_board_entry;
160 };
161 
162 /************************************************************************
163  * Device flag definitions for ch_flags.
164  ************************************************************************/
165 #define CH_PRON		0x0001		/* Printer on string		*/
166 #define CH_STOP		0x0002		/* Output is stopped		*/
167 #define CH_STOPI	0x0004		/* Input is stopped		*/
168 #define CH_CD		0x0008		/* Carrier is present		*/
169 #define CH_FCAR		0x0010		/* Carrier forced on		*/
170 #define CH_HANGUP	0x0020		/* Hangup received		*/
171 
172 #define CH_RECEIVER_OFF	0x0040		/* Receiver is off		*/
173 #define CH_OPENING	0x0080		/* Port in fragile open state	*/
174 #define CH_CLOSING	0x0100		/* Port in fragile close state	*/
175 #define CH_FIFO_ENABLED 0x0200		/* Port has FIFOs enabled	*/
176 #define CH_TX_FIFO_EMPTY 0x0400		/* TX Fifo is completely empty	*/
177 #define CH_TX_FIFO_LWM	0x0800		/* TX Fifo is below Low Water	*/
178 #define CH_BREAK_SENDING 0x1000		/* Break is being sent		*/
179 #define CH_LOOPBACK 0x2000		/* Channel is in lookback mode	*/
180 #define CH_BAUD0	0x08000		/* Used for checking B0 transitions */
181 
182 /* Our Read/Error queue sizes */
183 #define RQUEUEMASK	0x1FFF		/* 8 K - 1 */
184 #define EQUEUEMASK	0x1FFF		/* 8 K - 1 */
185 #define RQUEUESIZE	(RQUEUEMASK + 1)
186 #define EQUEUESIZE	RQUEUESIZE
187 
188 
189 /************************************************************************
190  * Channel information structure.
191  ************************************************************************/
192 struct jsm_channel {
193 	struct uart_port uart_port;
194 	struct jsm_board	*ch_bd;		/* Board structure pointer	*/
195 
196 	spinlock_t	ch_lock;	/* provide for serialization */
197 	wait_queue_head_t ch_flags_wait;
198 
199 	u32		ch_portnum;	/* Port number, 0 offset.	*/
200 	u32		ch_open_count;	/* open count			*/
201 	u32		ch_flags;	/* Channel flags		*/
202 
203 	u64		ch_close_delay;	/* How long we should drop RTS/DTR for */
204 
205 	tcflag_t	ch_c_iflag;	/* channel iflags		*/
206 	tcflag_t	ch_c_cflag;	/* channel cflags		*/
207 	tcflag_t	ch_c_oflag;	/* channel oflags		*/
208 	tcflag_t	ch_c_lflag;	/* channel lflags		*/
209 	u8		ch_stopc;	/* Stop character		*/
210 	u8		ch_startc;	/* Start character		*/
211 
212 	u8		ch_mostat;	/* FEP output modem status	*/
213 	u8		ch_mistat;	/* FEP input modem status	*/
214 
215 	/* Pointers to the "mapped" UART structs */
216 	struct neo_uart_struct __iomem *ch_neo_uart; /* NEO card */
217 	struct cls_uart_struct __iomem *ch_cls_uart; /* Classic card */
218 
219 	u8		ch_cached_lsr;	/* Cached value of the LSR register */
220 
221 	u8		*ch_rqueue;	/* Our read queue buffer - malloc'ed */
222 	u16		ch_r_head;	/* Head location of the read queue */
223 	u16		ch_r_tail;	/* Tail location of the read queue */
224 
225 	u8		*ch_equeue;	/* Our error queue buffer - malloc'ed */
226 	u16		ch_e_head;	/* Head location of the error queue */
227 	u16		ch_e_tail;	/* Tail location of the error queue */
228 
229 	u64		ch_rxcount;	/* total of data received so far */
230 	u64		ch_txcount;	/* total of data transmitted so far */
231 
232 	u8		ch_r_tlevel;	/* Receive Trigger level */
233 	u8		ch_t_tlevel;	/* Transmit Trigger level */
234 
235 	u8		ch_r_watermark;	/* Receive Watermark */
236 
237 
238 	u32		ch_stops_sent;	/* How many times I have sent a stop character
239 					 * to try to stop the other guy sending.
240 					 */
241 	u64		ch_err_parity;	/* Count of parity errors on channel */
242 	u64		ch_err_frame;	/* Count of framing errors on channel */
243 	u64		ch_err_break;	/* Count of breaks on channel */
244 	u64		ch_err_overrun; /* Count of overruns on channel */
245 
246 	u64		ch_xon_sends;	/* Count of xons transmitted */
247 	u64		ch_xoff_sends;	/* Count of xoffs transmitted */
248 };
249 
250 /************************************************************************
251  * Per channel/port Classic UART structures				*
252  ************************************************************************
253  *		Base Structure Entries Usage Meanings to Host		*
254  *									*
255  *	W = read write		R = read only				*
256  *			U = Unused.					*
257  ************************************************************************/
258 
259 struct cls_uart_struct {
260 	u8 txrx;	/* WR  RHR/THR - Holding Reg */
261 	u8 ier;		/* WR  IER - Interrupt Enable Reg */
262 	u8 isr_fcr;	/* WR  ISR/FCR - Interrupt Status Reg/Fifo Control Reg*/
263 	u8 lcr;		/* WR  LCR - Line Control Reg */
264 	u8 mcr;		/* WR  MCR - Modem Control Reg */
265 	u8 lsr;		/* WR  LSR - Line Status Reg */
266 	u8 msr;		/* WR  MSR - Modem Status Reg */
267 	u8 spr;		/* WR  SPR - Scratch Pad Reg */
268 };
269 
270 /* Where to read the interrupt register (8bits) */
271 #define UART_CLASSIC_POLL_ADDR_OFFSET	0x40
272 
273 #define UART_EXAR654_ENHANCED_REGISTER_SET 0xBF
274 
275 #define UART_16654_FCR_TXTRIGGER_8	0x0
276 #define UART_16654_FCR_TXTRIGGER_16	0x10
277 #define UART_16654_FCR_TXTRIGGER_32	0x20
278 #define UART_16654_FCR_TXTRIGGER_56	0x30
279 
280 #define UART_16654_FCR_RXTRIGGER_8	0x0
281 #define UART_16654_FCR_RXTRIGGER_16	0x40
282 #define UART_16654_FCR_RXTRIGGER_56	0x80
283 #define UART_16654_FCR_RXTRIGGER_60	0xC0
284 
285 #define UART_IIR_CTSRTS			0x20	/* Received CTS/RTS change of state */
286 #define UART_IIR_RDI_TIMEOUT		0x0C    /* Receiver data TIMEOUT */
287 
288 /*
289  * These are the EXTENDED definitions for the Exar 654's Interrupt
290  * Enable Register.
291  */
292 #define UART_EXAR654_EFR_ECB      0x10    /* Enhanced control bit */
293 #define UART_EXAR654_EFR_IXON     0x2     /* Receiver compares Xon1/Xoff1 */
294 #define UART_EXAR654_EFR_IXOFF    0x8     /* Transmit Xon1/Xoff1 */
295 #define UART_EXAR654_EFR_RTSDTR   0x40    /* Auto RTS/DTR Flow Control Enable */
296 #define UART_EXAR654_EFR_CTSDSR   0x80    /* Auto CTS/DSR Flow COntrol Enable */
297 
298 #define UART_EXAR654_XOFF_DETECT  0x1     /* Indicates whether chip saw an incoming XOFF char  */
299 #define UART_EXAR654_XON_DETECT   0x2     /* Indicates whether chip saw an incoming XON char */
300 
301 #define UART_EXAR654_IER_XOFF     0x20    /* Xoff Interrupt Enable */
302 #define UART_EXAR654_IER_RTSDTR   0x40    /* Output Interrupt Enable */
303 #define UART_EXAR654_IER_CTSDSR   0x80    /* Input Interrupt Enable */
304 
305 /************************************************************************
306  * Per channel/port NEO UART structure					*
307  ************************************************************************
308  *		Base Structure Entries Usage Meanings to Host		*
309  *									*
310  *	W = read write		R = read only				*
311  *			U = Unused.					*
312  ************************************************************************/
313 
314 struct neo_uart_struct {
315 	 u8 txrx;		/* WR	RHR/THR - Holding Reg */
316 	 u8 ier;		/* WR	IER - Interrupt Enable Reg */
317 	 u8 isr_fcr;		/* WR	ISR/FCR - Interrupt Status Reg/Fifo Control Reg */
318 	 u8 lcr;		/* WR	LCR - Line Control Reg */
319 	 u8 mcr;		/* WR	MCR - Modem Control Reg */
320 	 u8 lsr;		/* WR	LSR - Line Status Reg */
321 	 u8 msr;		/* WR	MSR - Modem Status Reg */
322 	 u8 spr;		/* WR	SPR - Scratch Pad Reg */
323 	 u8 fctr;		/* WR	FCTR - Feature Control Reg */
324 	 u8 efr;		/* WR	EFR - Enhanced Function Reg */
325 	 u8 tfifo;		/* WR	TXCNT/TXTRG - Transmit FIFO Reg */
326 	 u8 rfifo;		/* WR	RXCNT/RXTRG - Receive FIFO Reg */
327 	 u8 xoffchar1;	/* WR	XOFF 1 - XOff Character 1 Reg */
328 	 u8 xoffchar2;	/* WR	XOFF 2 - XOff Character 2 Reg */
329 	 u8 xonchar1;	/* WR	XON 1 - Xon Character 1 Reg */
330 	 u8 xonchar2;	/* WR	XON 2 - XOn Character 2 Reg */
331 
332 	 u8 reserved1[0x2ff - 0x200]; /* U	Reserved by Exar */
333 	 u8 txrxburst[64];	/* RW	64 bytes of RX/TX FIFO Data */
334 	 u8 reserved2[0x37f - 0x340]; /* U	Reserved by Exar */
335 	 u8 rxburst_with_errors[64];	/* R	64 bytes of RX FIFO Data + LSR */
336 };
337 
338 /* Where to read the extended interrupt register (32bits instead of 8bits) */
339 #define	UART_17158_POLL_ADDR_OFFSET	0x80
340 
341 /*
342  * These are the redefinitions for the FCTR on the XR17C158, since
343  * Exar made them different than their earlier design. (XR16C854)
344  */
345 
346 /* These are only applicable when table D is selected */
347 #define UART_17158_FCTR_RTS_NODELAY	0x00
348 #define UART_17158_FCTR_RTS_4DELAY	0x01
349 #define UART_17158_FCTR_RTS_6DELAY	0x02
350 #define UART_17158_FCTR_RTS_8DELAY	0x03
351 #define UART_17158_FCTR_RTS_12DELAY	0x12
352 #define UART_17158_FCTR_RTS_16DELAY	0x05
353 #define UART_17158_FCTR_RTS_20DELAY	0x13
354 #define UART_17158_FCTR_RTS_24DELAY	0x06
355 #define UART_17158_FCTR_RTS_28DELAY	0x14
356 #define UART_17158_FCTR_RTS_32DELAY	0x07
357 #define UART_17158_FCTR_RTS_36DELAY	0x16
358 #define UART_17158_FCTR_RTS_40DELAY	0x08
359 #define UART_17158_FCTR_RTS_44DELAY	0x09
360 #define UART_17158_FCTR_RTS_48DELAY	0x10
361 #define UART_17158_FCTR_RTS_52DELAY	0x11
362 
363 #define UART_17158_FCTR_RTS_IRDA	0x10
364 #define UART_17158_FCTR_RS485		0x20
365 #define UART_17158_FCTR_TRGA		0x00
366 #define UART_17158_FCTR_TRGB		0x40
367 #define UART_17158_FCTR_TRGC		0x80
368 #define UART_17158_FCTR_TRGD		0xC0
369 
370 /* 17158 trigger table selects.. */
371 #define UART_17158_FCTR_BIT6		0x40
372 #define UART_17158_FCTR_BIT7		0x80
373 
374 /* 17158 TX/RX memmapped buffer offsets */
375 #define UART_17158_RX_FIFOSIZE		64
376 #define UART_17158_TX_FIFOSIZE		64
377 
378 /* 17158 Extended IIR's */
379 #define UART_17158_IIR_RDI_TIMEOUT	0x0C	/* Receiver data TIMEOUT */
380 #define UART_17158_IIR_XONXOFF		0x10	/* Received an XON/XOFF char */
381 #define UART_17158_IIR_HWFLOW_STATE_CHANGE 0x20	/* CTS/DSR or RTS/DTR state change */
382 #define UART_17158_IIR_FIFO_ENABLED	0xC0	/* 16550 FIFOs are Enabled */
383 
384 /*
385  * These are the extended interrupts that get sent
386  * back to us from the UART's 32bit interrupt register
387  */
388 #define UART_17158_RX_LINE_STATUS	0x1	/* RX Ready */
389 #define UART_17158_RXRDY_TIMEOUT	0x2	/* RX Ready Timeout */
390 #define UART_17158_TXRDY		0x3	/* TX Ready */
391 #define UART_17158_MSR			0x4	/* Modem State Change */
392 #define UART_17158_TX_AND_FIFO_CLR	0x40	/* Transmitter Holding Reg Empty */
393 #define UART_17158_RX_FIFO_DATA_ERROR	0x80	/* UART detected an RX FIFO Data error */
394 
395 /*
396  * These are the EXTENDED definitions for the 17C158's Interrupt
397  * Enable Register.
398  */
399 #define UART_17158_EFR_ECB	0x10	/* Enhanced control bit */
400 #define UART_17158_EFR_IXON	0x2	/* Receiver compares Xon1/Xoff1 */
401 #define UART_17158_EFR_IXOFF	0x8	/* Transmit Xon1/Xoff1 */
402 #define UART_17158_EFR_RTSDTR	0x40	/* Auto RTS/DTR Flow Control Enable */
403 #define UART_17158_EFR_CTSDSR	0x80	/* Auto CTS/DSR Flow COntrol Enable */
404 
405 #define UART_17158_XOFF_DETECT	0x1	/* Indicates whether chip saw an incoming XOFF char */
406 #define UART_17158_XON_DETECT	0x2	/* Indicates whether chip saw an incoming XON char */
407 
408 #define UART_17158_IER_RSVD1	0x10	/* Reserved by Exar */
409 #define UART_17158_IER_XOFF	0x20	/* Xoff Interrupt Enable */
410 #define UART_17158_IER_RTSDTR	0x40	/* Output Interrupt Enable */
411 #define UART_17158_IER_CTSDSR	0x80	/* Input Interrupt Enable */
412 
413 #define PCI_DEVICE_NEO_2DB9_PCI_NAME		"Neo 2 - DB9 Universal PCI"
414 #define PCI_DEVICE_NEO_2DB9PRI_PCI_NAME		"Neo 2 - DB9 Universal PCI - Powered Ring Indicator"
415 #define PCI_DEVICE_NEO_2RJ45_PCI_NAME		"Neo 2 - RJ45 Universal PCI"
416 #define PCI_DEVICE_NEO_2RJ45PRI_PCI_NAME	"Neo 2 - RJ45 Universal PCI - Powered Ring Indicator"
417 #define PCIE_DEVICE_NEO_IBM_PCI_NAME		"Neo 4 - PCI Express - IBM"
418 
419 /*
420  * Our Global Variables.
421  */
422 extern struct	uart_driver jsm_uart_driver;
423 extern struct	board_ops jsm_neo_ops;
424 extern struct	board_ops jsm_cls_ops;
425 extern int	jsm_debug;
426 
427 /*************************************************************************
428  *
429  * Prototypes for non-static functions used in more than one module
430  *
431  *************************************************************************/
432 int jsm_tty_init(struct jsm_board *);
433 int jsm_uart_port_init(struct jsm_board *);
434 int jsm_remove_uart_port(struct jsm_board *);
435 void jsm_input(struct jsm_channel *ch);
436 void jsm_check_queue_flow_control(struct jsm_channel *ch);
437 
438 #endif
439