1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright (c) 2001-2002 by David Brownell
4 */
5
6 #ifndef __LINUX_EHCI_HCD_H
7 #define __LINUX_EHCI_HCD_H
8
9 /* definitions used for the EHCI driver */
10
11 /*
12 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
13 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
14 * the host controller implementation.
15 *
16 * To facilitate the strongest possible byte-order checking from "sparse"
17 * and so on, we use __leXX unless that's not practical.
18 */
19 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
20 typedef __u32 __bitwise __hc32;
21 typedef __u16 __bitwise __hc16;
22 #else
23 #define __hc32 __le32
24 #define __hc16 __le16
25 #endif
26
27 /* statistics can be kept for tuning/monitoring */
28 #ifdef CONFIG_DYNAMIC_DEBUG
29 #define EHCI_STATS
30 #endif
31
32 struct ehci_stats {
33 /* irq usage */
34 unsigned long normal;
35 unsigned long error;
36 unsigned long iaa;
37 unsigned long lost_iaa;
38
39 /* termination of urbs from core */
40 unsigned long complete;
41 unsigned long unlink;
42 };
43
44 /*
45 * Scheduling and budgeting information for periodic transfers, for both
46 * high-speed devices and full/low-speed devices lying behind a TT.
47 */
48 struct ehci_per_sched {
49 struct usb_device *udev; /* access to the TT */
50 struct usb_host_endpoint *ep;
51 struct list_head ps_list; /* node on ehci_tt's ps_list */
52 u16 tt_usecs; /* time on the FS/LS bus */
53 u16 cs_mask; /* C-mask and S-mask bytes */
54 u16 period; /* actual period in frames */
55 u16 phase; /* actual phase, frame part */
56 u8 bw_phase; /* same, for bandwidth
57 reservation */
58 u8 phase_uf; /* uframe part of the phase */
59 u8 usecs, c_usecs; /* times on the HS bus */
60 u8 bw_uperiod; /* period in microframes, for
61 bandwidth reservation */
62 u8 bw_period; /* same, in frames */
63 };
64 #define NO_FRAME 29999 /* frame not assigned yet */
65
66 /* ehci_hcd->lock guards shared data against other CPUs:
67 * ehci_hcd: async, unlink, periodic (and shadow), ...
68 * usb_host_endpoint: hcpriv
69 * ehci_qh: qh_next, qtd_list
70 * ehci_qtd: qtd_list
71 *
72 * Also, hold this lock when talking to HC registers or
73 * when updating hw_* fields in shared qh/qtd/... structures.
74 */
75
76 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
77
78 /*
79 * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the
80 * controller may be doing DMA. Lower values mean there's no DMA.
81 */
82 enum ehci_rh_state {
83 EHCI_RH_HALTED,
84 EHCI_RH_SUSPENDED,
85 EHCI_RH_RUNNING,
86 EHCI_RH_STOPPING
87 };
88
89 /*
90 * Timer events, ordered by increasing delay length.
91 * Always update event_delays_ns[] and event_handlers[] (defined in
92 * ehci-timer.c) in parallel with this list.
93 */
94 enum ehci_hrtimer_event {
95 EHCI_HRTIMER_POLL_ASS, /* Poll for async schedule off */
96 EHCI_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */
97 EHCI_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */
98 EHCI_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */
99 EHCI_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */
100 EHCI_HRTIMER_ACTIVE_UNLINK, /* Wait while unlinking an active QH */
101 EHCI_HRTIMER_START_UNLINK_INTR, /* Unlink empty interrupt QHs */
102 EHCI_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */
103 EHCI_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */
104 EHCI_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */
105 EHCI_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */
106 EHCI_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */
107 EHCI_HRTIMER_NUM_EVENTS /* Must come last */
108 };
109 #define EHCI_HRTIMER_NO_EVENT 99
110
111 struct ehci_hcd { /* one per controller */
112 /* timing support */
113 enum ehci_hrtimer_event next_hrtimer_event;
114 unsigned enabled_hrtimer_events;
115 ktime_t hr_timeouts[EHCI_HRTIMER_NUM_EVENTS];
116 struct hrtimer hrtimer;
117
118 int PSS_poll_count;
119 int ASS_poll_count;
120 int died_poll_count;
121
122 /* glue to PCI and HCD framework */
123 struct ehci_caps __iomem *caps;
124 struct ehci_regs __iomem *regs;
125 struct ehci_dbg_port __iomem *debug;
126
127 __u32 hcs_params; /* cached register copy */
128 spinlock_t lock;
129 enum ehci_rh_state rh_state;
130
131 /* general schedule support */
132 bool scanning:1;
133 bool need_rescan:1;
134 bool intr_unlinking:1;
135 bool iaa_in_progress:1;
136 bool async_unlinking:1;
137 bool shutdown:1;
138 struct ehci_qh *qh_scan_next;
139
140 /* async schedule support */
141 struct ehci_qh *async;
142 struct ehci_qh *dummy; /* For AMD quirk use */
143 struct list_head async_unlink;
144 struct list_head async_idle;
145 unsigned async_unlink_cycle;
146 unsigned async_count; /* async activity count */
147 __hc32 old_current; /* Test for QH becoming */
148 __hc32 old_token; /* inactive during unlink */
149
150 /* periodic schedule support */
151 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */
152 unsigned periodic_size;
153 __hc32 *periodic; /* hw periodic table */
154 dma_addr_t periodic_dma;
155 struct list_head intr_qh_list;
156 unsigned i_thresh; /* uframes HC might cache */
157
158 union ehci_shadow *pshadow; /* mirror hw periodic table */
159 struct list_head intr_unlink_wait;
160 struct list_head intr_unlink;
161 unsigned intr_unlink_wait_cycle;
162 unsigned intr_unlink_cycle;
163 unsigned now_frame; /* frame from HC hardware */
164 unsigned last_iso_frame; /* last frame scanned for iso */
165 unsigned intr_count; /* intr activity count */
166 unsigned isoc_count; /* isoc activity count */
167 unsigned periodic_count; /* periodic activity count */
168 unsigned uframe_periodic_max; /* max periodic time per uframe */
169
170
171 /* list of itds & sitds completed while now_frame was still active */
172 struct list_head cached_itd_list;
173 struct ehci_itd *last_itd_to_free;
174 struct list_head cached_sitd_list;
175 struct ehci_sitd *last_sitd_to_free;
176
177 /* per root hub port */
178 unsigned long reset_done[EHCI_MAX_ROOT_PORTS];
179
180 /* bit vectors (one bit per port) */
181 unsigned long bus_suspended; /* which ports were
182 already suspended at the start of a bus suspend */
183 unsigned long companion_ports; /* which ports are
184 dedicated to the companion controller */
185 unsigned long owned_ports; /* which ports are
186 owned by the companion during a bus suspend */
187 unsigned long port_c_suspend; /* which ports have
188 the change-suspend feature turned on */
189 unsigned long suspended_ports; /* which ports are
190 suspended */
191 unsigned long resuming_ports; /* which ports have
192 started to resume */
193
194 /* per-HC memory pools (could be per-bus, but ...) */
195 struct dma_pool *qh_pool; /* qh per active urb */
196 struct dma_pool *qtd_pool; /* one or more per qh */
197 struct dma_pool *itd_pool; /* itd per iso urb */
198 struct dma_pool *sitd_pool; /* sitd per split iso urb */
199
200 unsigned random_frame;
201 unsigned long next_statechange;
202 ktime_t last_periodic_enable;
203 u32 command;
204
205 /* SILICON QUIRKS */
206 unsigned no_selective_suspend:1;
207 unsigned has_fsl_port_bug:1; /* FreeScale */
208 unsigned has_fsl_hs_errata:1; /* Freescale HS quirk */
209 unsigned has_fsl_susp_errata:1; /* NXP SUSP quirk */
210 unsigned big_endian_mmio:1;
211 unsigned big_endian_desc:1;
212 unsigned big_endian_capbase:1;
213 unsigned has_amcc_usb23:1;
214 unsigned need_io_watchdog:1;
215 unsigned amd_pll_fix:1;
216 unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/
217 unsigned has_synopsys_hc_bug:1; /* Synopsys HC */
218 unsigned frame_index_bug:1; /* MosChip (AKA NetMos) */
219 unsigned need_oc_pp_cycle:1; /* MPC834X port power */
220 unsigned imx28_write_fix:1; /* For Freescale i.MX28 */
221 unsigned spurious_oc:1;
222
223 /* required for usb32 quirk */
224 #define OHCI_CTRL_HCFS (3 << 6)
225 #define OHCI_USB_OPER (2 << 6)
226 #define OHCI_USB_SUSPEND (3 << 6)
227
228 #define OHCI_HCCTRL_OFFSET 0x4
229 #define OHCI_HCCTRL_LEN 0x4
230 __hc32 *ohci_hcctrl_reg;
231 unsigned has_hostpc:1;
232 unsigned has_tdi_phy_lpm:1;
233 unsigned has_ppcd:1; /* support per-port change bits */
234 u8 sbrn; /* packed release number */
235
236 /* irq statistics */
237 #ifdef EHCI_STATS
238 struct ehci_stats stats;
239 # define INCR(x) ((x)++)
240 #else
241 # define INCR(x) do {} while (0)
242 #endif
243
244 /* debug files */
245 #ifdef CONFIG_DYNAMIC_DEBUG
246 struct dentry *debug_dir;
247 #endif
248
249 /* bandwidth usage */
250 #define EHCI_BANDWIDTH_SIZE 64
251 #define EHCI_BANDWIDTH_FRAMES (EHCI_BANDWIDTH_SIZE >> 3)
252 u8 bandwidth[EHCI_BANDWIDTH_SIZE];
253 /* us allocated per uframe */
254 u8 tt_budget[EHCI_BANDWIDTH_SIZE];
255 /* us budgeted per uframe */
256 struct list_head tt_list;
257
258 /* platform-specific data -- must come last */
259 unsigned long priv[] __aligned(sizeof(s64));
260 };
261
262 /* convert between an HCD pointer and the corresponding EHCI_HCD */
hcd_to_ehci(struct usb_hcd * hcd)263 static inline struct ehci_hcd *hcd_to_ehci(struct usb_hcd *hcd)
264 {
265 return (struct ehci_hcd *) (hcd->hcd_priv);
266 }
ehci_to_hcd(struct ehci_hcd * ehci)267 static inline struct usb_hcd *ehci_to_hcd(struct ehci_hcd *ehci)
268 {
269 return container_of((void *) ehci, struct usb_hcd, hcd_priv);
270 }
271
272 /*-------------------------------------------------------------------------*/
273
274 #include <linux/usb/ehci_def.h>
275
276 /*-------------------------------------------------------------------------*/
277
278 #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma)
279
280 /*
281 * EHCI Specification 0.95 Section 3.5
282 * QTD: describe data transfer components (buffer, direction, ...)
283 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
284 *
285 * These are associated only with "QH" (Queue Head) structures,
286 * used with control, bulk, and interrupt transfers.
287 */
288 struct ehci_qtd {
289 /* first part defined by EHCI spec */
290 __hc32 hw_next; /* see EHCI 3.5.1 */
291 __hc32 hw_alt_next; /* see EHCI 3.5.2 */
292 __hc32 hw_token; /* see EHCI 3.5.3 */
293 #define QTD_TOGGLE (1 << 31) /* data toggle */
294 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
295 #define QTD_IOC (1 << 15) /* interrupt on complete */
296 #define QTD_CERR(tok) (((tok)>>10) & 0x3)
297 #define QTD_PID(tok) (((tok)>>8) & 0x3)
298 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
299 #define QTD_STS_HALT (1 << 6) /* halted on error */
300 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
301 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
302 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */
303 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
304 #define QTD_STS_STS (1 << 1) /* split transaction state */
305 #define QTD_STS_PING (1 << 0) /* issue PING? */
306
307 #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE)
308 #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT)
309 #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS)
310
311 __hc32 hw_buf[5]; /* see EHCI 3.5.4 */
312 __hc32 hw_buf_hi[5]; /* Appendix B */
313
314 /* the rest is HCD-private */
315 dma_addr_t qtd_dma; /* qtd address */
316 struct list_head qtd_list; /* sw qtd list */
317 struct urb *urb; /* qtd's urb */
318 size_t length; /* length of buffer */
319 } __aligned(32);
320
321 /* mask NakCnt+T in qh->hw_alt_next */
322 #define QTD_MASK(ehci) cpu_to_hc32(ehci, ~0x1f)
323
324 #define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1)
325
326 /*-------------------------------------------------------------------------*/
327
328 /* type tag from {qh,itd,sitd,fstn}->hw_next */
329 #define Q_NEXT_TYPE(ehci, dma) ((dma) & cpu_to_hc32(ehci, 3 << 1))
330
331 /*
332 * Now the following defines are not converted using the
333 * cpu_to_le32() macro anymore, since we have to support
334 * "dynamic" switching between be and le support, so that the driver
335 * can be used on one system with SoC EHCI controller using big-endian
336 * descriptors as well as a normal little-endian PCI EHCI controller.
337 */
338 /* values for that type tag */
339 #define Q_TYPE_ITD (0 << 1)
340 #define Q_TYPE_QH (1 << 1)
341 #define Q_TYPE_SITD (2 << 1)
342 #define Q_TYPE_FSTN (3 << 1)
343
344 /* next async queue entry, or pointer to interrupt/periodic QH */
345 #define QH_NEXT(ehci, dma) \
346 (cpu_to_hc32(ehci, (((u32) dma) & ~0x01f) | Q_TYPE_QH))
347
348 /* for periodic/async schedules and qtd lists, mark end of list */
349 #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
350
351 /*
352 * Entries in periodic shadow table are pointers to one of four kinds
353 * of data structure. That's dictated by the hardware; a type tag is
354 * encoded in the low bits of the hardware's periodic schedule. Use
355 * Q_NEXT_TYPE to get the tag.
356 *
357 * For entries in the async schedule, the type tag always says "qh".
358 */
359 union ehci_shadow {
360 struct ehci_qh *qh; /* Q_TYPE_QH */
361 struct ehci_itd *itd; /* Q_TYPE_ITD */
362 struct ehci_sitd *sitd; /* Q_TYPE_SITD */
363 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */
364 __hc32 *hw_next; /* (all types) */
365 void *ptr;
366 };
367
368 /*-------------------------------------------------------------------------*/
369
370 /*
371 * EHCI Specification 0.95 Section 3.6
372 * QH: describes control/bulk/interrupt endpoints
373 * See Fig 3-7 "Queue Head Structure Layout".
374 *
375 * These appear in both the async and (for interrupt) periodic schedules.
376 */
377
378 /* first part defined by EHCI spec */
379 struct ehci_qh_hw {
380 __hc32 hw_next; /* see EHCI 3.6.1 */
381 __hc32 hw_info1; /* see EHCI 3.6.2 */
382 #define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */
383 #define QH_HEAD (1 << 15) /* Head of async reclamation list */
384 #define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */
385 #define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */
386 #define QH_LOW_SPEED (1 << 12)
387 #define QH_FULL_SPEED (0 << 12)
388 #define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */
389 __hc32 hw_info2; /* see EHCI 3.6.2 */
390 #define QH_SMASK 0x000000ff
391 #define QH_CMASK 0x0000ff00
392 #define QH_HUBADDR 0x007f0000
393 #define QH_HUBPORT 0x3f800000
394 #define QH_MULT 0xc0000000
395 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
396
397 /* qtd overlay (hardware parts of a struct ehci_qtd) */
398 __hc32 hw_qtd_next;
399 __hc32 hw_alt_next;
400 __hc32 hw_token;
401 __hc32 hw_buf[5];
402 __hc32 hw_buf_hi[5];
403 } __aligned(32);
404
405 struct ehci_qh {
406 struct ehci_qh_hw *hw; /* Must come first */
407 /* the rest is HCD-private */
408 dma_addr_t qh_dma; /* address of qh */
409 union ehci_shadow qh_next; /* ptr to qh; or periodic */
410 struct list_head qtd_list; /* sw qtd list */
411 struct list_head intr_node; /* list of intr QHs */
412 struct ehci_qtd *dummy;
413 struct list_head unlink_node;
414 struct ehci_per_sched ps; /* scheduling info */
415
416 unsigned unlink_cycle;
417
418 u8 qh_state;
419 #define QH_STATE_LINKED 1 /* HC sees this */
420 #define QH_STATE_UNLINK 2 /* HC may still see this */
421 #define QH_STATE_IDLE 3 /* HC doesn't see this */
422 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */
423 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
424
425 u8 xacterrs; /* XactErr retry counter */
426 #define QH_XACTERR_MAX 32 /* XactErr retry limit */
427
428 u8 unlink_reason;
429 #define QH_UNLINK_HALTED 0x01 /* Halt flag is set */
430 #define QH_UNLINK_SHORT_READ 0x02 /* Recover from a short read */
431 #define QH_UNLINK_DUMMY_OVERLAY 0x04 /* QH overlayed the dummy TD */
432 #define QH_UNLINK_SHUTDOWN 0x08 /* The HC isn't running */
433 #define QH_UNLINK_QUEUE_EMPTY 0x10 /* Reached end of the queue */
434 #define QH_UNLINK_REQUESTED 0x20 /* Disable, reset, or dequeue */
435
436 u8 gap_uf; /* uframes split/csplit gap */
437
438 unsigned is_out:1; /* bulk or intr OUT */
439 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */
440 unsigned dequeue_during_giveback:1;
441 unsigned should_be_inactive:1;
442 };
443
444 /*-------------------------------------------------------------------------*/
445
446 /* description of one iso transaction (up to 3 KB data if highspeed) */
447 struct ehci_iso_packet {
448 /* These will be copied to iTD when scheduling */
449 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
450 __hc32 transaction; /* itd->hw_transaction[i] |= */
451 u8 cross; /* buf crosses pages */
452 /* for full speed OUT splits */
453 u32 buf1;
454 };
455
456 /* temporary schedule data for packets from iso urbs (both speeds)
457 * each packet is one logical usb transaction to the device (not TT),
458 * beginning at stream->next_uframe
459 */
460 struct ehci_iso_sched {
461 struct list_head td_list;
462 unsigned span;
463 unsigned first_packet;
464 struct ehci_iso_packet packet[];
465 };
466
467 /*
468 * ehci_iso_stream - groups all (s)itds for this endpoint.
469 * acts like a qh would, if EHCI had them for ISO.
470 */
471 struct ehci_iso_stream {
472 /* first field matches ehci_hq, but is NULL */
473 struct ehci_qh_hw *hw;
474
475 u8 bEndpointAddress;
476 u8 highspeed;
477 struct list_head td_list; /* queued itds/sitds */
478 struct list_head free_list; /* list of unused itds/sitds */
479
480 /* output of (re)scheduling */
481 struct ehci_per_sched ps; /* scheduling info */
482 unsigned next_uframe;
483 __hc32 splits;
484
485 /* the rest is derived from the endpoint descriptor,
486 * including the extra info for hw_bufp[0..2]
487 */
488 u16 uperiod; /* period in uframes */
489 u16 maxp;
490 unsigned bandwidth;
491
492 /* This is used to initialize iTD's hw_bufp fields */
493 __hc32 buf0;
494 __hc32 buf1;
495 __hc32 buf2;
496
497 /* this is used to initialize sITD's tt info */
498 __hc32 address;
499 };
500
501 /*-------------------------------------------------------------------------*/
502
503 /*
504 * EHCI Specification 0.95 Section 3.3
505 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
506 *
507 * Schedule records for high speed iso xfers
508 */
509 struct ehci_itd {
510 /* first part defined by EHCI spec */
511 __hc32 hw_next; /* see EHCI 3.3.1 */
512 __hc32 hw_transaction[8]; /* see EHCI 3.3.2 */
513 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
514 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */
515 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */
516 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
517 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
518 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */
519
520 #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
521
522 __hc32 hw_bufp[7]; /* see EHCI 3.3.3 */
523 __hc32 hw_bufp_hi[7]; /* Appendix B */
524
525 /* the rest is HCD-private */
526 dma_addr_t itd_dma; /* for this itd */
527 union ehci_shadow itd_next; /* ptr to periodic q entry */
528
529 struct urb *urb;
530 struct ehci_iso_stream *stream; /* endpoint's queue */
531 struct list_head itd_list; /* list of stream's itds */
532
533 /* any/all hw_transactions here may be used by that urb */
534 unsigned frame; /* where scheduled */
535 unsigned pg;
536 unsigned index[8]; /* in urb->iso_frame_desc */
537 } __aligned(32);
538
539 /*-------------------------------------------------------------------------*/
540
541 /*
542 * EHCI Specification 0.95 Section 3.4
543 * siTD, aka split-transaction isochronous Transfer Descriptor
544 * ... describe full speed iso xfers through TT in hubs
545 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
546 */
547 struct ehci_sitd {
548 /* first part defined by EHCI spec */
549 __hc32 hw_next;
550 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
551 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */
552 __hc32 hw_uframe; /* EHCI table 3-10 */
553 __hc32 hw_results; /* EHCI table 3-11 */
554 #define SITD_IOC (1 << 31) /* interrupt on completion */
555 #define SITD_PAGE (1 << 30) /* buffer 0/1 */
556 #define SITD_LENGTH(x) (((x) >> 16) & 0x3ff)
557 #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */
558 #define SITD_STS_ERR (1 << 6) /* error from TT */
559 #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */
560 #define SITD_STS_BABBLE (1 << 4) /* device was babbling */
561 #define SITD_STS_XACT (1 << 3) /* illegal IN response */
562 #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */
563 #define SITD_STS_STS (1 << 1) /* split transaction state */
564
565 #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE)
566
567 __hc32 hw_buf[2]; /* EHCI table 3-12 */
568 __hc32 hw_backpointer; /* EHCI table 3-13 */
569 __hc32 hw_buf_hi[2]; /* Appendix B */
570
571 /* the rest is HCD-private */
572 dma_addr_t sitd_dma;
573 union ehci_shadow sitd_next; /* ptr to periodic q entry */
574
575 struct urb *urb;
576 struct ehci_iso_stream *stream; /* endpoint's queue */
577 struct list_head sitd_list; /* list of stream's sitds */
578 unsigned frame;
579 unsigned index;
580 } __aligned(32);
581
582 /*-------------------------------------------------------------------------*/
583
584 /*
585 * EHCI Specification 0.96 Section 3.7
586 * Periodic Frame Span Traversal Node (FSTN)
587 *
588 * Manages split interrupt transactions (using TT) that span frame boundaries
589 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
590 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
591 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
592 */
593 struct ehci_fstn {
594 __hc32 hw_next; /* any periodic q entry */
595 __hc32 hw_prev; /* qh or EHCI_LIST_END */
596
597 /* the rest is HCD-private */
598 dma_addr_t fstn_dma;
599 union ehci_shadow fstn_next; /* ptr to periodic q entry */
600 } __aligned(32);
601
602 /*-------------------------------------------------------------------------*/
603
604 /*
605 * USB-2.0 Specification Sections 11.14 and 11.18
606 * Scheduling and budgeting split transactions using TTs
607 *
608 * A hub can have a single TT for all its ports, or multiple TTs (one for each
609 * port). The bandwidth and budgeting information for the full/low-speed bus
610 * below each TT is self-contained and independent of the other TTs or the
611 * high-speed bus.
612 *
613 * "Bandwidth" refers to the number of microseconds on the FS/LS bus allocated
614 * to an interrupt or isochronous endpoint for each frame. "Budget" refers to
615 * the best-case estimate of the number of full-speed bytes allocated to an
616 * endpoint for each microframe within an allocated frame.
617 *
618 * Removal of an endpoint invalidates a TT's budget. Instead of trying to
619 * keep an up-to-date record, we recompute the budget when it is needed.
620 */
621
622 struct ehci_tt {
623 u16 bandwidth[EHCI_BANDWIDTH_FRAMES];
624
625 struct list_head tt_list; /* List of all ehci_tt's */
626 struct list_head ps_list; /* Items using this TT */
627 struct usb_tt *usb_tt;
628 int tt_port; /* TT port number */
629 };
630
631 /*-------------------------------------------------------------------------*/
632
633 /* Prepare the PORTSC wakeup flags during controller suspend/resume */
634
635 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \
636 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup)
637
638 #define ehci_prepare_ports_for_controller_resume(ehci) \
639 ehci_adjust_port_wakeup_flags(ehci, false, false)
640
641 /*-------------------------------------------------------------------------*/
642
643 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
644
645 /*
646 * Some EHCI controllers have a Transaction Translator built into the
647 * root hub. This is a non-standard feature. Each controller will need
648 * to add code to the following inline functions, and call them as
649 * needed (mostly in root hub code).
650 */
651
652 #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt)
653
654 /* Returns the speed of a device attached to a port on the root hub. */
655 static inline unsigned int
ehci_port_speed(struct ehci_hcd * ehci,unsigned int portsc)656 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
657 {
658 if (ehci_is_TDI(ehci)) {
659 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
660 case 0:
661 return 0;
662 case 1:
663 return USB_PORT_STAT_LOW_SPEED;
664 case 2:
665 default:
666 return USB_PORT_STAT_HIGH_SPEED;
667 }
668 }
669 return USB_PORT_STAT_HIGH_SPEED;
670 }
671
672 #else
673
674 #define ehci_is_TDI(e) (0)
675
676 #define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED
677 #endif
678
679 /*-------------------------------------------------------------------------*/
680
681 #ifdef CONFIG_PPC_83xx
682 /* Some Freescale processors have an erratum in which the TT
683 * port number in the queue head was 0..N-1 instead of 1..N.
684 */
685 #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
686 #else
687 #define ehci_has_fsl_portno_bug(e) (0)
688 #endif
689
690 #define PORTSC_FSL_PFSC 24 /* Port Force Full-Speed Connect */
691
692 #if defined(CONFIG_PPC_85xx)
693 /* Some Freescale processors have an erratum (USB A-005275) in which
694 * incoming packets get corrupted in HS mode
695 */
696 #define ehci_has_fsl_hs_errata(e) ((e)->has_fsl_hs_errata)
697 #else
698 #define ehci_has_fsl_hs_errata(e) (0)
699 #endif
700
701 /*
702 * Some Freescale/NXP processors have an erratum (USB A-005697)
703 * in which we need to wait for 10ms for bus to enter suspend mode
704 * after setting SUSP bit.
705 */
706 #define ehci_has_fsl_susp_errata(e) ((e)->has_fsl_susp_errata)
707
708 /*
709 * While most USB host controllers implement their registers in
710 * little-endian format, a minority (celleb companion chip) implement
711 * them in big endian format.
712 *
713 * This attempts to support either format at compile time without a
714 * runtime penalty, or both formats with the additional overhead
715 * of checking a flag bit.
716 *
717 * ehci_big_endian_capbase is a special quirk for controllers that
718 * implement the HC capability registers as separate registers and not
719 * as fields of a 32-bit register.
720 */
721
722 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
723 #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
724 #define ehci_big_endian_capbase(e) ((e)->big_endian_capbase)
725 #else
726 #define ehci_big_endian_mmio(e) 0
727 #define ehci_big_endian_capbase(e) 0
728 #endif
729
730 /*
731 * Big-endian read/write functions are arch-specific.
732 * Other arches can be added if/when they're needed.
733 */
734 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
735 #define readl_be(addr) __raw_readl((__force unsigned *)addr)
736 #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr)
737 #endif
738
ehci_readl(const struct ehci_hcd * ehci,__u32 __iomem * regs)739 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
740 __u32 __iomem *regs)
741 {
742 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
743 return ehci_big_endian_mmio(ehci) ?
744 readl_be(regs) :
745 readl(regs);
746 #else
747 return readl(regs);
748 #endif
749 }
750
751 #ifdef CONFIG_SOC_IMX28
imx28_ehci_writel(const unsigned int val,volatile __u32 __iomem * addr)752 static inline void imx28_ehci_writel(const unsigned int val,
753 volatile __u32 __iomem *addr)
754 {
755 __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
756 }
757 #else
imx28_ehci_writel(const unsigned int val,volatile __u32 __iomem * addr)758 static inline void imx28_ehci_writel(const unsigned int val,
759 volatile __u32 __iomem *addr)
760 {
761 }
762 #endif
ehci_writel(const struct ehci_hcd * ehci,const unsigned int val,__u32 __iomem * regs)763 static inline void ehci_writel(const struct ehci_hcd *ehci,
764 const unsigned int val, __u32 __iomem *regs)
765 {
766 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
767 ehci_big_endian_mmio(ehci) ?
768 writel_be(val, regs) :
769 writel(val, regs);
770 #else
771 if (ehci->imx28_write_fix)
772 imx28_ehci_writel(val, regs);
773 else
774 writel(val, regs);
775 #endif
776 }
777
778 /*
779 * On certain ppc-44x SoC there is a HW issue, that could only worked around with
780 * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
781 * Other common bits are dependent on has_amcc_usb23 quirk flag.
782 */
783 #ifdef CONFIG_44x
set_ohci_hcfs(struct ehci_hcd * ehci,int operational)784 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
785 {
786 u32 hc_control;
787
788 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
789 if (operational)
790 hc_control |= OHCI_USB_OPER;
791 else
792 hc_control |= OHCI_USB_SUSPEND;
793
794 writel_be(hc_control, ehci->ohci_hcctrl_reg);
795 (void) readl_be(ehci->ohci_hcctrl_reg);
796 }
797 #else
set_ohci_hcfs(struct ehci_hcd * ehci,int operational)798 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
799 { }
800 #endif
801
802 /*-------------------------------------------------------------------------*/
803
804 /*
805 * The AMCC 440EPx not only implements its EHCI registers in big-endian
806 * format, but also its DMA data structures (descriptors).
807 *
808 * EHCI controllers accessed through PCI work normally (little-endian
809 * everywhere), so we won't bother supporting a BE-only mode for now.
810 */
811 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
812 #define ehci_big_endian_desc(e) ((e)->big_endian_desc)
813
814 /* cpu to ehci */
cpu_to_hc32(const struct ehci_hcd * ehci,const u32 x)815 static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)
816 {
817 return ehci_big_endian_desc(ehci)
818 ? (__force __hc32)cpu_to_be32(x)
819 : (__force __hc32)cpu_to_le32(x);
820 }
821
822 /* ehci to cpu */
hc32_to_cpu(const struct ehci_hcd * ehci,const __hc32 x)823 static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)
824 {
825 return ehci_big_endian_desc(ehci)
826 ? be32_to_cpu((__force __be32)x)
827 : le32_to_cpu((__force __le32)x);
828 }
829
hc32_to_cpup(const struct ehci_hcd * ehci,const __hc32 * x)830 static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)
831 {
832 return ehci_big_endian_desc(ehci)
833 ? be32_to_cpup((__force __be32 *)x)
834 : le32_to_cpup((__force __le32 *)x);
835 }
836
837 #else
838
839 /* cpu to ehci */
cpu_to_hc32(const struct ehci_hcd * ehci,const u32 x)840 static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)
841 {
842 return cpu_to_le32(x);
843 }
844
845 /* ehci to cpu */
hc32_to_cpu(const struct ehci_hcd * ehci,const __hc32 x)846 static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)
847 {
848 return le32_to_cpu(x);
849 }
850
hc32_to_cpup(const struct ehci_hcd * ehci,const __hc32 * x)851 static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)
852 {
853 return le32_to_cpup(x);
854 }
855
856 #endif
857
858 /*-------------------------------------------------------------------------*/
859
860 #define ehci_dbg(ehci, fmt, args...) \
861 dev_dbg(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
862 #define ehci_err(ehci, fmt, args...) \
863 dev_err(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
864 #define ehci_info(ehci, fmt, args...) \
865 dev_info(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
866 #define ehci_warn(ehci, fmt, args...) \
867 dev_warn(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
868
869 /*-------------------------------------------------------------------------*/
870
871 /* Declarations of things exported for use by ehci platform drivers */
872
873 struct ehci_driver_overrides {
874 size_t extra_priv_size;
875 int (*reset)(struct usb_hcd *hcd);
876 int (*port_power)(struct usb_hcd *hcd,
877 int portnum, bool enable);
878 };
879
880 extern void ehci_init_driver(struct hc_driver *drv,
881 const struct ehci_driver_overrides *over);
882 extern int ehci_setup(struct usb_hcd *hcd);
883 extern int ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr,
884 u32 mask, u32 done, int usec);
885 extern int ehci_reset(struct ehci_hcd *ehci);
886
887 extern int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup);
888 extern int ehci_resume(struct usb_hcd *hcd, bool force_reset);
889 extern void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci,
890 bool suspending, bool do_wakeup);
891
892 extern int ehci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
893 u16 wIndex, char *buf, u16 wLength);
894
895 #endif /* __LINUX_EHCI_HCD_H */
896