1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
5 //
6 // Copyright(c) 2018 Intel Corporation. All rights reserved.
7 //
8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
10 // Rander Wang <rander.wang@intel.com>
11 // Keyon Jie <yang.jie@linux.intel.com>
12 //
13
14 /*
15 * Hardware interface for audio DSP on Cannonlake.
16 */
17
18 #include "../ops.h"
19 #include "hda.h"
20 #include "hda-ipc.h"
21 #include "../sof-audio.h"
22
23 static const struct snd_sof_debugfs_map cnl_dsp_debugfs[] = {
24 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
25 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
26 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
27 };
28
29 static void cnl_ipc_host_done(struct snd_sof_dev *sdev);
30 static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev);
31
cnl_ipc_irq_thread(int irq,void * context)32 irqreturn_t cnl_ipc_irq_thread(int irq, void *context)
33 {
34 struct snd_sof_dev *sdev = context;
35 u32 hipci;
36 u32 hipcida;
37 u32 hipctdr;
38 u32 hipctdd;
39 u32 msg;
40 u32 msg_ext;
41 bool ipc_irq = false;
42
43 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
44 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);
45 hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDD);
46 hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR);
47
48 /* reply message from DSP */
49 if (hipcida & CNL_DSP_REG_HIPCIDA_DONE) {
50 msg_ext = hipci & CNL_DSP_REG_HIPCIDR_MSG_MASK;
51 msg = hipcida & CNL_DSP_REG_HIPCIDA_MSG_MASK;
52
53 dev_vdbg(sdev->dev,
54 "ipc: firmware response, msg:0x%x, msg_ext:0x%x\n",
55 msg, msg_ext);
56
57 /* mask Done interrupt */
58 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
59 CNL_DSP_REG_HIPCCTL,
60 CNL_DSP_REG_HIPCCTL_DONE, 0);
61
62 spin_lock_irq(&sdev->ipc_lock);
63
64 /* handle immediate reply from DSP core */
65 hda_dsp_ipc_get_reply(sdev);
66 snd_sof_ipc_reply(sdev, msg);
67
68 cnl_ipc_dsp_done(sdev);
69
70 spin_unlock_irq(&sdev->ipc_lock);
71
72 ipc_irq = true;
73 }
74
75 /* new message from DSP */
76 if (hipctdr & CNL_DSP_REG_HIPCTDR_BUSY) {
77 msg = hipctdr & CNL_DSP_REG_HIPCTDR_MSG_MASK;
78 msg_ext = hipctdd & CNL_DSP_REG_HIPCTDD_MSG_MASK;
79
80 dev_vdbg(sdev->dev,
81 "ipc: firmware initiated, msg:0x%x, msg_ext:0x%x\n",
82 msg, msg_ext);
83
84 /* handle messages from DSP */
85 if ((hipctdr & SOF_IPC_PANIC_MAGIC_MASK) ==
86 SOF_IPC_PANIC_MAGIC) {
87 snd_sof_dsp_panic(sdev, HDA_DSP_PANIC_OFFSET(msg_ext));
88 } else {
89 snd_sof_ipc_msgs_rx(sdev);
90 }
91
92 cnl_ipc_host_done(sdev);
93
94 ipc_irq = true;
95 }
96
97 if (!ipc_irq) {
98 /*
99 * This interrupt is not shared so no need to return IRQ_NONE.
100 */
101 dev_dbg_ratelimited(sdev->dev,
102 "nothing to do in IPC IRQ thread\n");
103 }
104
105 return IRQ_HANDLED;
106 }
107
cnl_ipc_host_done(struct snd_sof_dev * sdev)108 static void cnl_ipc_host_done(struct snd_sof_dev *sdev)
109 {
110 /*
111 * clear busy interrupt to tell dsp controller this
112 * interrupt has been accepted, not trigger it again
113 */
114 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
115 CNL_DSP_REG_HIPCTDR,
116 CNL_DSP_REG_HIPCTDR_BUSY,
117 CNL_DSP_REG_HIPCTDR_BUSY);
118 /*
119 * set done bit to ack dsp the msg has been
120 * processed and send reply msg to dsp
121 */
122 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
123 CNL_DSP_REG_HIPCTDA,
124 CNL_DSP_REG_HIPCTDA_DONE,
125 CNL_DSP_REG_HIPCTDA_DONE);
126 }
127
cnl_ipc_dsp_done(struct snd_sof_dev * sdev)128 static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev)
129 {
130 /*
131 * set DONE bit - tell DSP we have received the reply msg
132 * from DSP, and processed it, don't send more reply to host
133 */
134 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
135 CNL_DSP_REG_HIPCIDA,
136 CNL_DSP_REG_HIPCIDA_DONE,
137 CNL_DSP_REG_HIPCIDA_DONE);
138
139 /* unmask Done interrupt */
140 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
141 CNL_DSP_REG_HIPCCTL,
142 CNL_DSP_REG_HIPCCTL_DONE,
143 CNL_DSP_REG_HIPCCTL_DONE);
144 }
145
cnl_compact_ipc_compress(struct snd_sof_ipc_msg * msg,u32 * dr,u32 * dd)146 static bool cnl_compact_ipc_compress(struct snd_sof_ipc_msg *msg,
147 u32 *dr, u32 *dd)
148 {
149 struct sof_ipc_pm_gate *pm_gate;
150
151 if (msg->header == (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE)) {
152 pm_gate = msg->msg_data;
153
154 /* send the compact message via the primary register */
155 *dr = HDA_IPC_MSG_COMPACT | HDA_IPC_PM_GATE;
156
157 /* send payload via the extended data register */
158 *dd = pm_gate->flags;
159
160 return true;
161 }
162
163 return false;
164 }
165
cnl_ipc_send_msg(struct snd_sof_dev * sdev,struct snd_sof_ipc_msg * msg)166 int cnl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
167 {
168 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
169 struct sof_ipc_cmd_hdr *hdr;
170 u32 dr = 0;
171 u32 dd = 0;
172
173 /*
174 * Currently the only compact IPC supported is the PM_GATE
175 * IPC which is used for transitioning the DSP between the
176 * D0I0 and D0I3 states. And these are sent only during the
177 * set_power_state() op. Therefore, there will never be a case
178 * that a compact IPC results in the DSP exiting D0I3 without
179 * the host and FW being in sync.
180 */
181 if (cnl_compact_ipc_compress(msg, &dr, &dd)) {
182 /* send the message via IPC registers */
183 snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDD,
184 dd);
185 snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR,
186 CNL_DSP_REG_HIPCIDR_BUSY | dr);
187 return 0;
188 }
189
190 /* send the message via mailbox */
191 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
192 msg->msg_size);
193 snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR,
194 CNL_DSP_REG_HIPCIDR_BUSY);
195
196 hdr = msg->msg_data;
197
198 /*
199 * Use mod_delayed_work() to schedule the delayed work
200 * to avoid scheduling multiple workqueue items when
201 * IPCs are sent at a high-rate. mod_delayed_work()
202 * modifies the timer if the work is pending.
203 * Also, a new delayed work should not be queued after the
204 * CTX_SAVE IPC, which is sent before the DSP enters D3.
205 */
206 if (hdr->cmd != (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CTX_SAVE))
207 mod_delayed_work(system_wq, &hdev->d0i3_work,
208 msecs_to_jiffies(SOF_HDA_D0I3_WORK_DELAY_MS));
209
210 return 0;
211 }
212
cnl_ipc_dump(struct snd_sof_dev * sdev)213 void cnl_ipc_dump(struct snd_sof_dev *sdev)
214 {
215 u32 hipcctl;
216 u32 hipcida;
217 u32 hipctdr;
218
219 hda_ipc_irq_dump(sdev);
220
221 /* read IPC status */
222 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
223 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCCTL);
224 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);
225
226 /* dump the IPC regs */
227 /* TODO: parse the raw msg */
228 dev_err(sdev->dev,
229 "error: host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n",
230 hipcida, hipctdr, hipcctl);
231 }
232
233 /* cannonlake ops */
234 const struct snd_sof_dsp_ops sof_cnl_ops = {
235 /* probe/remove/shutdown */
236 .probe = hda_dsp_probe,
237 .remove = hda_dsp_remove,
238 .shutdown = hda_dsp_shutdown,
239
240 /* Register IO */
241 .write = sof_io_write,
242 .read = sof_io_read,
243 .write64 = sof_io_write64,
244 .read64 = sof_io_read64,
245
246 /* Block IO */
247 .block_read = sof_block_read,
248 .block_write = sof_block_write,
249
250 /* doorbell */
251 .irq_thread = cnl_ipc_irq_thread,
252
253 /* ipc */
254 .send_msg = cnl_ipc_send_msg,
255 .fw_ready = sof_fw_ready,
256 .get_mailbox_offset = hda_dsp_ipc_get_mailbox_offset,
257 .get_window_offset = hda_dsp_ipc_get_window_offset,
258
259 .ipc_msg_data = hda_ipc_msg_data,
260 .ipc_pcm_params = hda_ipc_pcm_params,
261
262 /* machine driver */
263 .machine_select = hda_machine_select,
264 .machine_register = sof_machine_register,
265 .machine_unregister = sof_machine_unregister,
266 .set_mach_params = hda_set_mach_params,
267
268 /* debug */
269 .debug_map = cnl_dsp_debugfs,
270 .debug_map_count = ARRAY_SIZE(cnl_dsp_debugfs),
271 .dbg_dump = hda_dsp_dump,
272 .ipc_dump = cnl_ipc_dump,
273
274 /* stream callbacks */
275 .pcm_open = hda_dsp_pcm_open,
276 .pcm_close = hda_dsp_pcm_close,
277 .pcm_hw_params = hda_dsp_pcm_hw_params,
278 .pcm_hw_free = hda_dsp_stream_hw_free,
279 .pcm_trigger = hda_dsp_pcm_trigger,
280 .pcm_pointer = hda_dsp_pcm_pointer,
281
282 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
283 /* probe callbacks */
284 .probe_assign = hda_probe_compr_assign,
285 .probe_free = hda_probe_compr_free,
286 .probe_set_params = hda_probe_compr_set_params,
287 .probe_trigger = hda_probe_compr_trigger,
288 .probe_pointer = hda_probe_compr_pointer,
289 #endif
290
291 /* firmware loading */
292 .load_firmware = snd_sof_load_firmware_raw,
293
294 /* pre/post fw run */
295 .pre_fw_run = hda_dsp_pre_fw_run,
296 .post_fw_run = hda_dsp_post_fw_run,
297
298 /* parse platform specific extended manifest */
299 .parse_platform_ext_manifest = hda_dsp_ext_man_get_cavs_config_data,
300
301 /* dsp core power up/down */
302 .core_power_up = hda_dsp_enable_core,
303 .core_power_down = hda_dsp_core_reset_power_down,
304
305 /* firmware run */
306 .run = hda_dsp_cl_boot_firmware,
307
308 /* trace callback */
309 .trace_init = hda_dsp_trace_init,
310 .trace_release = hda_dsp_trace_release,
311 .trace_trigger = hda_dsp_trace_trigger,
312
313 /* DAI drivers */
314 .drv = skl_dai,
315 .num_drv = SOF_SKL_NUM_DAIS,
316
317 /* PM */
318 .suspend = hda_dsp_suspend,
319 .resume = hda_dsp_resume,
320 .runtime_suspend = hda_dsp_runtime_suspend,
321 .runtime_resume = hda_dsp_runtime_resume,
322 .runtime_idle = hda_dsp_runtime_idle,
323 .set_hw_params_upon_resume = hda_dsp_set_hw_params_upon_resume,
324 .set_power_state = hda_dsp_set_power_state,
325
326 /* ALSA HW info flags */
327 .hw_info = SNDRV_PCM_INFO_MMAP |
328 SNDRV_PCM_INFO_MMAP_VALID |
329 SNDRV_PCM_INFO_INTERLEAVED |
330 SNDRV_PCM_INFO_PAUSE |
331 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
332
333 .arch_ops = &sof_xtensa_arch_ops,
334 };
335 EXPORT_SYMBOL_NS(sof_cnl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
336
337 const struct sof_intel_dsp_desc cnl_chip_info = {
338 /* Cannonlake */
339 .cores_num = 4,
340 .init_core_mask = 1,
341 .host_managed_cores_mask = GENMASK(3, 0),
342 .ipc_req = CNL_DSP_REG_HIPCIDR,
343 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
344 .ipc_ack = CNL_DSP_REG_HIPCIDA,
345 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
346 .ipc_ctl = CNL_DSP_REG_HIPCCTL,
347 .rom_init_timeout = 300,
348 .ssp_count = CNL_SSP_COUNT,
349 .ssp_base_offset = CNL_SSP_BASE_OFFSET,
350 };
351 EXPORT_SYMBOL_NS(cnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
352
353 const struct sof_intel_dsp_desc jsl_chip_info = {
354 /* Jasperlake */
355 .cores_num = 2,
356 .init_core_mask = 1,
357 .host_managed_cores_mask = GENMASK(1, 0),
358 .ipc_req = CNL_DSP_REG_HIPCIDR,
359 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
360 .ipc_ack = CNL_DSP_REG_HIPCIDA,
361 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
362 .ipc_ctl = CNL_DSP_REG_HIPCCTL,
363 .rom_init_timeout = 300,
364 .ssp_count = ICL_SSP_COUNT,
365 .ssp_base_offset = CNL_SSP_BASE_OFFSET,
366 };
367 EXPORT_SYMBOL_NS(jsl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
368