1 //! AES block ciphers implementation using AES-NI instruction set. 2 //! 3 //! Ciphers functionality is accessed using `BlockCipher` trait from the 4 //! [`cipher`](https://docs.rs/cipher) crate. 5 //! 6 //! # CTR mode 7 //! In addition to core block cipher functionality this crate provides optimized 8 //! CTR mode implementation. This functionality requires additional `ssse3` 9 //! target feature and feature-gated behind `ctr` feature flag, which is enabled 10 //! by default. 11 //! 12 //! # Vulnerability 13 //! Lazy FP state restory vulnerability can allow local process to leak content 14 //! of the FPU register, in which round keys are stored. This vulnerability 15 //! can be mitigated at the operating system level by installing relevant 16 //! patches. (i.e. keep your OS updated!) More info: 17 //! - [Intel advisory](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00145.html) 18 //! - [Wikipedia](https://en.wikipedia.org/wiki/Lazy_FP_state_restore) 19 //! 20 //! # Related documents 21 //! - [Intel AES-NI whitepaper](https://software.intel.com/sites/default/files/article/165683/aes-wp-2012-09-22-v01.pdf) 22 //! - [Use of the AES Instruction Set](https://www.cosic.esat.kuleuven.be/ecrypt/AESday/slides/Use_of_the_AES_Instruction_Set.pdf) 23 24 #[macro_use] 25 mod utils; 26 27 mod aes128; 28 mod aes192; 29 mod aes256; 30 31 #[cfg(feature = "ctr")] 32 mod ctr; 33 34 #[cfg(feature = "hazmat")] 35 pub(crate) mod hazmat; 36 37 #[cfg(target_arch = "x86")] 38 use core::arch::x86 as arch; 39 #[cfg(target_arch = "x86_64")] 40 use core::arch::x86_64 as arch; 41 42 pub use self::{aes128::Aes128, aes192::Aes192, aes256::Aes256}; 43 44 #[cfg(feature = "ctr")] 45 pub use self::ctr::{Aes128Ctr, Aes192Ctr, Aes256Ctr}; 46