1 /*
2 * Copyright 2008-2018 Cisco Systems, Inc. All rights reserved.
3 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
4 *
5 * LICENSE_BEGIN
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
29 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
30 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
32 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
33 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
34 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
36 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 *
39 * LICENSE_END
40 *
41 *
42 */
43
44 #include <linux/kernel.h>
45 #include <linux/errno.h>
46 #include <linux/types.h>
47 #include <linux/pci.h>
48
49 #include "kcompat.h"
50 #include "vnic_dev.h"
51 #include "vnic_cq.h"
52
53 #ifndef NOT_FOR_OPEN_ENIC
vnic_cq_mem_size(struct vnic_cq * cq,unsigned int desc_count,unsigned int desc_size)54 int vnic_cq_mem_size(struct vnic_cq *cq, unsigned int desc_count,
55 unsigned int desc_size)
56 {
57 int mem_size;
58
59 mem_size = vnic_dev_desc_ring_size(&cq->ring, desc_count, desc_size);
60
61 return mem_size;
62 }
63
64 #endif
vnic_cq_free(struct vnic_cq * cq)65 void vnic_cq_free(struct vnic_cq *cq)
66 {
67 vnic_dev_free_desc_ring(cq->vdev, &cq->ring);
68
69 cq->ctrl = NULL;
70 }
71
vnic_cq_alloc(struct vnic_dev * vdev,struct vnic_cq * cq,unsigned int index,unsigned int desc_count,unsigned int desc_size)72 int vnic_cq_alloc(struct vnic_dev *vdev, struct vnic_cq *cq, unsigned int index,
73 unsigned int desc_count, unsigned int desc_size)
74 {
75 int err;
76
77 cq->index = index;
78 cq->vdev = vdev;
79
80 cq->ctrl = vnic_dev_get_res(vdev, RES_TYPE_CQ, index);
81 if (!cq->ctrl) {
82 pr_err("Failed to hook CQ[%d] resource\n", index);
83 return -EINVAL;
84 }
85
86 err = vnic_dev_alloc_desc_ring(vdev, &cq->ring, desc_count, desc_size);
87 if (err)
88 return err;
89
90 return 0;
91 }
92
vnic_cq_init(struct vnic_cq * cq,unsigned int flow_control_enable,unsigned int color_enable,unsigned int cq_head,unsigned int cq_tail,unsigned int cq_tail_color,unsigned int interrupt_enable,unsigned int cq_entry_enable,unsigned int cq_message_enable,unsigned int interrupt_offset,u64 cq_message_addr)93 void vnic_cq_init(struct vnic_cq *cq, unsigned int flow_control_enable,
94 unsigned int color_enable, unsigned int cq_head, unsigned int cq_tail,
95 unsigned int cq_tail_color, unsigned int interrupt_enable,
96 unsigned int cq_entry_enable, unsigned int cq_message_enable,
97 unsigned int interrupt_offset, u64 cq_message_addr)
98 {
99 u64 paddr;
100
101 paddr = (u64)cq->ring.base_addr | VNIC_PADDR_TARGET;
102 writeq(paddr, &cq->ctrl->ring_base);
103 iowrite32(cq->ring.desc_count, &cq->ctrl->ring_size);
104 iowrite32(flow_control_enable, &cq->ctrl->flow_control_enable);
105 iowrite32(color_enable, &cq->ctrl->color_enable);
106 iowrite32(cq_head, &cq->ctrl->cq_head);
107 iowrite32(cq_tail, &cq->ctrl->cq_tail);
108 iowrite32(cq_tail_color, &cq->ctrl->cq_tail_color);
109 iowrite32(interrupt_enable, &cq->ctrl->interrupt_enable);
110 iowrite32(cq_entry_enable, &cq->ctrl->cq_entry_enable);
111 iowrite32(cq_message_enable, &cq->ctrl->cq_message_enable);
112 iowrite32(interrupt_offset, &cq->ctrl->interrupt_offset);
113 writeq(cq_message_addr, &cq->ctrl->cq_message_addr);
114
115 cq->interrupt_offset = interrupt_offset;
116 }
117
vnic_cq_clean(struct vnic_cq * cq)118 void vnic_cq_clean(struct vnic_cq *cq)
119 {
120 cq->to_clean = 0;
121 cq->last_color = 0;
122
123 iowrite32(0, &cq->ctrl->cq_head);
124 iowrite32(0, &cq->ctrl->cq_tail);
125 iowrite32(1, &cq->ctrl->cq_tail_color);
126
127 vnic_dev_clear_desc_ring(&cq->ring);
128 }
129