1`timescale 1ns / 1ps 2/* 3 * This software is Copyright (c) 2016 Denis Burykin 4 * [denis_burykin yahoo com], [denis-burykin2014 yandex ru] 5 * and it is hereby released to the general public under the following terms: 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted. 8 * 9 */ 10 11//********************************************************** 12// 13// Provides active 'clk_en' for 1 'clk' cycle per 1 'async' pulse 14// 15//********************************************************** 16 17module async2sync( 18 input async, 19 input clk, 20 output reg clk_en = 0 21 ); 22 23 reg async_r; 24 always @(posedge clk or posedge async) 25 if (async) 26 async_r <= 1'b1; 27 else if (done || !init_done) 28 async_r <= 0; 29 30 reg done = 0; 31 reg init_done = 0; 32 33 always @(posedge clk) begin 34 if (!async && !init_done) 35 init_done <= 1; 36 37 if (async_r && init_done) 38 if (!clk_en && !done) begin 39 clk_en <= 1; 40 done <= 1; 41 end 42 else 43 clk_en <= 0; 44 else 45 done <= 0; 46 end 47 48endmodule 49