1 /**
2 ******************************************************************************
3 * @file stm32l1xx_ll_spi.h
4 * @author MCD Application Team
5 * @version V1.2.0
6 * @date 01-July-2016
7 * @brief Header file of SPI LL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32L1xx_LL_SPI_H
40 #define __STM32L1xx_LL_SPI_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32l1xx.h"
48
49 /** @addtogroup STM32L1xx_LL_Driver
50 * @{
51 */
52
53 #if defined (SPI1) || defined (SPI2) || defined (SPI3)
54
55 /** @defgroup SPI_LL SPI
56 * @{
57 */
58
59 /* Private types -------------------------------------------------------------*/
60 /* Private variables ---------------------------------------------------------*/
61 /* Private macros ------------------------------------------------------------*/
62
63 /* Exported types ------------------------------------------------------------*/
64 #if defined(USE_FULL_LL_DRIVER)
65 /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
66 * @{
67 */
68
69 /**
70 * @brief SPI Init structures definition
71 */
72 typedef struct
73 {
74 uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
75 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
76
77 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
78
79 uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
80 This parameter can be a value of @ref SPI_LL_EC_MODE.
81
82 This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
83
84 uint32_t DataWidth; /*!< Specifies the SPI data width.
85 This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
86
87 This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
88
89 uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
90 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
91
92 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
93
94 uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
95 This parameter can be a value of @ref SPI_LL_EC_PHASE.
96
97 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
98
99 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
100 This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
101
102 This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
103
104 uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
105 This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
106 @note The communication clock is derived from the master clock. The slave clock does not need to be set.
107
108 This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
109
110 uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
111 This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
112
113 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
114
115 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
116 This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
117
118 This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
119
120 uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
121 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
122
123 This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
124
125 } LL_SPI_InitTypeDef;
126
127 /**
128 * @}
129 */
130 #endif /* USE_FULL_LL_DRIVER */
131
132 /* Exported constants --------------------------------------------------------*/
133 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
134 * @{
135 */
136
137 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
138 * @brief Flags defines which can be used with LL_SPI_ReadReg function
139 * @{
140 */
141 #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
142 #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
143 #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
144 #define LL_SPI_SR_UDR SPI_SR_UDR /*!< Underrun flag */
145 #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
146 #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
147 #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
148 #define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
149 /**
150 * @}
151 */
152
153 /** @defgroup SPI_LL_EC_IT IT Defines
154 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
155 * @{
156 */
157 #define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
158 #define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
159 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
160 /**
161 * @}
162 */
163
164 /** @defgroup SPI_LL_EC_MODE Operation Mode
165 * @{
166 */
167 #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
168 #define LL_SPI_MODE_SLAVE ((uint32_t)0x00000000U) /*!< Slave configuration */
169 /**
170 * @}
171 */
172
173 #if defined (SPI_CR2_FRF)
174 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
175 * @{
176 */
177 #define LL_SPI_PROTOCOL_MOTOROLA ((uint32_t)0x00000000U) /*!< Motorola mode. Used as default value */
178 #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */
179 /**
180 * @}
181 */
182 #endif /* SPI_CR2_FRF */
183
184 /** @defgroup SPI_LL_EC_PHASE Clock Phase
185 * @{
186 */
187 #define LL_SPI_PHASE_1EDGE ((uint32_t)0x00000000U) /*!< First clock transition is the first data capture edge */
188 #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
189 /**
190 * @}
191 */
192
193 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
194 * @{
195 */
196 #define LL_SPI_POLARITY_LOW ((uint32_t)0x00000000U) /*!< Clock to 0 when idle */
197 #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
198 /**
199 * @}
200 */
201
202 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
203 * @{
204 */
205 #define LL_SPI_BAUDRATEPRESCALER_DIV2 ((uint32_t)0x00000000U) /*!< BaudRate control equal to fPCLK/2 */
206 #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
207 #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
208 #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
209 #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
210 #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
211 #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
212 #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
213 /**
214 * @}
215 */
216
217 /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
218 * @{
219 */
220 #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
221 #define LL_SPI_MSB_FIRST ((uint32_t)0x00000000U) /*!< Data is transmitted/received with the MSB first */
222 /**
223 * @}
224 */
225
226 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
227 * @{
228 */
229 #define LL_SPI_FULL_DUPLEX ((uint32_t)0x00000000U) /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
230 #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
231 #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
232 #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
233 /**
234 * @}
235 */
236
237 /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
238 * @{
239 */
240 #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
241 #define LL_SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U) /*!< NSS pin used in Input. Only used in Master mode */
242 #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
243 /**
244 * @}
245 */
246
247 /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
248 * @{
249 */
250 #define LL_SPI_DATAWIDTH_8BIT ((uint32_t)0x00000000U) /*!< Data length for SPI transfer: 8 bits */
251 #define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /*!< Data length for SPI transfer: 16 bits */
252 /**
253 * @}
254 */
255 #if defined(USE_FULL_LL_DRIVER)
256
257 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
258 * @{
259 */
260 #define LL_SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U) /*!< CRC calculation disabled */
261 #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
262 /**
263 * @}
264 */
265 #endif /* USE_FULL_LL_DRIVER */
266
267 /**
268 * @}
269 */
270
271 /* Exported macro ------------------------------------------------------------*/
272 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
273 * @{
274 */
275
276 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
277 * @{
278 */
279
280 /**
281 * @brief Write a value in SPI register
282 * @param __INSTANCE__ SPI Instance
283 * @param __REG__ Register to be written
284 * @param __VALUE__ Value to be written in the register
285 * @retval None
286 */
287 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
288
289 /**
290 * @brief Read a value in SPI register
291 * @param __INSTANCE__ SPI Instance
292 * @param __REG__ Register to be read
293 * @retval Register value
294 */
295 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
296 /**
297 * @}
298 */
299
300 /**
301 * @}
302 */
303
304 /* Exported functions --------------------------------------------------------*/
305 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
306 * @{
307 */
308
309 /** @defgroup SPI_LL_EF_Configuration Configuration
310 * @{
311 */
312
313 /**
314 * @brief Enable SPI peripheral
315 * @rmtoll CR1 SPE LL_SPI_Enable
316 * @param SPIx SPI Instance
317 * @retval None
318 */
LL_SPI_Enable(SPI_TypeDef * SPIx)319 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
320 {
321 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
322 }
323
324 /**
325 * @brief Disable SPI peripheral
326 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
327 * @rmtoll CR1 SPE LL_SPI_Disable
328 * @param SPIx SPI Instance
329 * @retval None
330 */
LL_SPI_Disable(SPI_TypeDef * SPIx)331 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
332 {
333 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
334 }
335
336 /**
337 * @brief Check if SPI peripheral is enabled
338 * @rmtoll CR1 SPE LL_SPI_IsEnabled
339 * @param SPIx SPI Instance
340 * @retval State of bit (1 or 0).
341 */
LL_SPI_IsEnabled(SPI_TypeDef * SPIx)342 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
343 {
344 return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
345 }
346
347 /**
348 * @brief Set SPI operation mode to Master or Slave
349 * @note This bit should not be changed when communication is ongoing.
350 * @rmtoll CR1 MSTR LL_SPI_SetMode\n
351 * CR1 SSI LL_SPI_SetMode
352 * @param SPIx SPI Instance
353 * @param Mode This parameter can be one of the following values:
354 * @arg @ref LL_SPI_MODE_MASTER
355 * @arg @ref LL_SPI_MODE_SLAVE
356 * @retval None
357 */
LL_SPI_SetMode(SPI_TypeDef * SPIx,uint32_t Mode)358 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
359 {
360 MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
361 }
362
363 /**
364 * @brief Get SPI operation mode (Master or Slave)
365 * @rmtoll CR1 MSTR LL_SPI_GetMode\n
366 * CR1 SSI LL_SPI_GetMode
367 * @param SPIx SPI Instance
368 * @retval Returned value can be one of the following values:
369 * @arg @ref LL_SPI_MODE_MASTER
370 * @arg @ref LL_SPI_MODE_SLAVE
371 */
LL_SPI_GetMode(SPI_TypeDef * SPIx)372 __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
373 {
374 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
375 }
376
377 #if defined (SPI_CR2_FRF)
378 /**
379 * @brief Set serial protocol used
380 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
381 * @rmtoll CR2 FRF LL_SPI_SetStandard
382 * @param SPIx SPI Instance
383 * @param Standard This parameter can be one of the following values:
384 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
385 * @arg @ref LL_SPI_PROTOCOL_TI
386 * @retval None
387 */
LL_SPI_SetStandard(SPI_TypeDef * SPIx,uint32_t Standard)388 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
389 {
390 MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
391 }
392
393 /**
394 * @brief Get serial protocol used
395 * @rmtoll CR2 FRF LL_SPI_GetStandard
396 * @param SPIx SPI Instance
397 * @retval Returned value can be one of the following values:
398 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
399 * @arg @ref LL_SPI_PROTOCOL_TI
400 */
LL_SPI_GetStandard(SPI_TypeDef * SPIx)401 __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
402 {
403 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
404 }
405 #endif /* SPI_CR2_FRF */
406
407 /**
408 * @brief Set clock phase
409 * @note This bit should not be changed when communication is ongoing.
410 * This bit is not used in SPI TI mode.
411 * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
412 * @param SPIx SPI Instance
413 * @param ClockPhase This parameter can be one of the following values:
414 * @arg @ref LL_SPI_PHASE_1EDGE
415 * @arg @ref LL_SPI_PHASE_2EDGE
416 * @retval None
417 */
LL_SPI_SetClockPhase(SPI_TypeDef * SPIx,uint32_t ClockPhase)418 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
419 {
420 MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
421 }
422
423 /**
424 * @brief Get clock phase
425 * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
426 * @param SPIx SPI Instance
427 * @retval Returned value can be one of the following values:
428 * @arg @ref LL_SPI_PHASE_1EDGE
429 * @arg @ref LL_SPI_PHASE_2EDGE
430 */
LL_SPI_GetClockPhase(SPI_TypeDef * SPIx)431 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
432 {
433 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
434 }
435
436 /**
437 * @brief Set clock polarity
438 * @note This bit should not be changed when communication is ongoing.
439 * This bit is not used in SPI TI mode.
440 * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
441 * @param SPIx SPI Instance
442 * @param ClockPolarity This parameter can be one of the following values:
443 * @arg @ref LL_SPI_POLARITY_LOW
444 * @arg @ref LL_SPI_POLARITY_HIGH
445 * @retval None
446 */
LL_SPI_SetClockPolarity(SPI_TypeDef * SPIx,uint32_t ClockPolarity)447 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
448 {
449 MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
450 }
451
452 /**
453 * @brief Get clock polarity
454 * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
455 * @param SPIx SPI Instance
456 * @retval Returned value can be one of the following values:
457 * @arg @ref LL_SPI_POLARITY_LOW
458 * @arg @ref LL_SPI_POLARITY_HIGH
459 */
LL_SPI_GetClockPolarity(SPI_TypeDef * SPIx)460 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
461 {
462 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
463 }
464
465 /**
466 * @brief Set baud rate prescaler
467 * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
468 * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
469 * @param SPIx SPI Instance
470 * @param BaudRate This parameter can be one of the following values:
471 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
472 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
473 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
474 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
475 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
476 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
477 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
478 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
479 * @retval None
480 */
LL_SPI_SetBaudRatePrescaler(SPI_TypeDef * SPIx,uint32_t BaudRate)481 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
482 {
483 MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
484 }
485
486 /**
487 * @brief Get baud rate prescaler
488 * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
489 * @param SPIx SPI Instance
490 * @retval Returned value can be one of the following values:
491 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
492 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
493 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
494 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
495 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
496 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
497 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
498 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
499 */
LL_SPI_GetBaudRatePrescaler(SPI_TypeDef * SPIx)500 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
501 {
502 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
503 }
504
505 /**
506 * @brief Set transfer bit order
507 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
508 * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
509 * @param SPIx SPI Instance
510 * @param BitOrder This parameter can be one of the following values:
511 * @arg @ref LL_SPI_LSB_FIRST
512 * @arg @ref LL_SPI_MSB_FIRST
513 * @retval None
514 */
LL_SPI_SetTransferBitOrder(SPI_TypeDef * SPIx,uint32_t BitOrder)515 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
516 {
517 MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
518 }
519
520 /**
521 * @brief Get transfer bit order
522 * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
523 * @param SPIx SPI Instance
524 * @retval Returned value can be one of the following values:
525 * @arg @ref LL_SPI_LSB_FIRST
526 * @arg @ref LL_SPI_MSB_FIRST
527 */
LL_SPI_GetTransferBitOrder(SPI_TypeDef * SPIx)528 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
529 {
530 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
531 }
532
533 /**
534 * @brief Set transfer direction mode
535 * @note For Half-Duplex mode, Rx Direction is set by default.
536 * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
537 * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
538 * CR1 BIDIMODE LL_SPI_SetTransferDirection\n
539 * CR1 BIDIOE LL_SPI_SetTransferDirection
540 * @param SPIx SPI Instance
541 * @param TransferDirection This parameter can be one of the following values:
542 * @arg @ref LL_SPI_FULL_DUPLEX
543 * @arg @ref LL_SPI_SIMPLEX_RX
544 * @arg @ref LL_SPI_HALF_DUPLEX_RX
545 * @arg @ref LL_SPI_HALF_DUPLEX_TX
546 * @retval None
547 */
LL_SPI_SetTransferDirection(SPI_TypeDef * SPIx,uint32_t TransferDirection)548 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
549 {
550 MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
551 }
552
553 /**
554 * @brief Get transfer direction mode
555 * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
556 * CR1 BIDIMODE LL_SPI_GetTransferDirection\n
557 * CR1 BIDIOE LL_SPI_GetTransferDirection
558 * @param SPIx SPI Instance
559 * @retval Returned value can be one of the following values:
560 * @arg @ref LL_SPI_FULL_DUPLEX
561 * @arg @ref LL_SPI_SIMPLEX_RX
562 * @arg @ref LL_SPI_HALF_DUPLEX_RX
563 * @arg @ref LL_SPI_HALF_DUPLEX_TX
564 */
LL_SPI_GetTransferDirection(SPI_TypeDef * SPIx)565 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
566 {
567 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
568 }
569
570 /**
571 * @brief Set frame data width
572 * @rmtoll CR1 DFF LL_SPI_SetDataWidth
573 * @param SPIx SPI Instance
574 * @param DataWidth This parameter can be one of the following values:
575 * @arg @ref LL_SPI_DATAWIDTH_8BIT
576 * @arg @ref LL_SPI_DATAWIDTH_16BIT
577 * @retval None
578 */
LL_SPI_SetDataWidth(SPI_TypeDef * SPIx,uint32_t DataWidth)579 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
580 {
581 MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
582 }
583
584 /**
585 * @brief Get frame data width
586 * @rmtoll CR1 DFF LL_SPI_GetDataWidth
587 * @param SPIx SPI Instance
588 * @retval Returned value can be one of the following values:
589 * @arg @ref LL_SPI_DATAWIDTH_8BIT
590 * @arg @ref LL_SPI_DATAWIDTH_16BIT
591 */
LL_SPI_GetDataWidth(SPI_TypeDef * SPIx)592 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
593 {
594 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
595 }
596
597 /**
598 * @}
599 */
600
601 /** @defgroup SPI_LL_EF_CRC_Management CRC Management
602 * @{
603 */
604
605 /**
606 * @brief Enable CRC
607 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
608 * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
609 * @param SPIx SPI Instance
610 * @retval None
611 */
LL_SPI_EnableCRC(SPI_TypeDef * SPIx)612 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
613 {
614 SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
615 }
616
617 /**
618 * @brief Disable CRC
619 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
620 * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
621 * @param SPIx SPI Instance
622 * @retval None
623 */
LL_SPI_DisableCRC(SPI_TypeDef * SPIx)624 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
625 {
626 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
627 }
628
629 /**
630 * @brief Check if CRC is enabled
631 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
632 * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
633 * @param SPIx SPI Instance
634 * @retval State of bit (1 or 0).
635 */
LL_SPI_IsEnabledCRC(SPI_TypeDef * SPIx)636 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
637 {
638 return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
639 }
640
641 /**
642 * @brief Set CRCNext to transfer CRC on the line
643 * @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
644 * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
645 * @param SPIx SPI Instance
646 * @retval None
647 */
LL_SPI_SetCRCNext(SPI_TypeDef * SPIx)648 __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
649 {
650 SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
651 }
652
653 /**
654 * @brief Set polynomial for CRC calculation
655 * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
656 * @param SPIx SPI Instance
657 * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
658 * @retval None
659 */
LL_SPI_SetCRCPolynomial(SPI_TypeDef * SPIx,uint32_t CRCPoly)660 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
661 {
662 WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
663 }
664
665 /**
666 * @brief Get polynomial for CRC calculation
667 * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
668 * @param SPIx SPI Instance
669 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
670 */
LL_SPI_GetCRCPolynomial(SPI_TypeDef * SPIx)671 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
672 {
673 return (uint32_t)(READ_REG(SPIx->CRCPR));
674 }
675
676 /**
677 * @brief Get Rx CRC
678 * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
679 * @param SPIx SPI Instance
680 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
681 */
LL_SPI_GetRxCRC(SPI_TypeDef * SPIx)682 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
683 {
684 return (uint32_t)(READ_REG(SPIx->RXCRCR));
685 }
686
687 /**
688 * @brief Get Tx CRC
689 * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
690 * @param SPIx SPI Instance
691 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
692 */
LL_SPI_GetTxCRC(SPI_TypeDef * SPIx)693 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
694 {
695 return (uint32_t)(READ_REG(SPIx->TXCRCR));
696 }
697
698 /**
699 * @}
700 */
701
702 /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
703 * @{
704 */
705
706 /**
707 * @brief Set NSS mode
708 * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
709 * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
710 * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
711 * @param SPIx SPI Instance
712 * @param NSS This parameter can be one of the following values:
713 * @arg @ref LL_SPI_NSS_SOFT
714 * @arg @ref LL_SPI_NSS_HARD_INPUT
715 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
716 * @retval None
717 */
LL_SPI_SetNSSMode(SPI_TypeDef * SPIx,uint32_t NSS)718 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
719 {
720 MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
721 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
722 }
723
724 /**
725 * @brief Get NSS mode
726 * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
727 * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
728 * @param SPIx SPI Instance
729 * @retval Returned value can be one of the following values:
730 * @arg @ref LL_SPI_NSS_SOFT
731 * @arg @ref LL_SPI_NSS_HARD_INPUT
732 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
733 */
LL_SPI_GetNSSMode(SPI_TypeDef * SPIx)734 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
735 {
736 register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
737 register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
738 return (Ssm | Ssoe);
739 }
740
741 /**
742 * @}
743 */
744
745 /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
746 * @{
747 */
748
749 /**
750 * @brief Check if Rx buffer is not empty
751 * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
752 * @param SPIx SPI Instance
753 * @retval State of bit (1 or 0).
754 */
LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef * SPIx)755 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
756 {
757 return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
758 }
759
760 /**
761 * @brief Check if Tx buffer is empty
762 * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
763 * @param SPIx SPI Instance
764 * @retval State of bit (1 or 0).
765 */
LL_SPI_IsActiveFlag_TXE(SPI_TypeDef * SPIx)766 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
767 {
768 return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
769 }
770
771 /**
772 * @brief Get CRC error flag
773 * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
774 * @param SPIx SPI Instance
775 * @retval State of bit (1 or 0).
776 */
LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef * SPIx)777 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
778 {
779 return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
780 }
781
782 /**
783 * @brief Get mode fault error flag
784 * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
785 * @param SPIx SPI Instance
786 * @retval State of bit (1 or 0).
787 */
LL_SPI_IsActiveFlag_MODF(SPI_TypeDef * SPIx)788 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
789 {
790 return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
791 }
792
793 /**
794 * @brief Get overrun error flag
795 * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
796 * @param SPIx SPI Instance
797 * @retval State of bit (1 or 0).
798 */
LL_SPI_IsActiveFlag_OVR(SPI_TypeDef * SPIx)799 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
800 {
801 return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
802 }
803
804 /**
805 * @brief Get busy flag
806 * @note The BSY flag is cleared under any one of the following conditions:
807 * -When the SPI is correctly disabled
808 * -When a fault is detected in Master mode (MODF bit set to 1)
809 * -In Master mode, when it finishes a data transmission and no new data is ready to be
810 * sent
811 * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
812 * each data transfer.
813 * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
814 * @param SPIx SPI Instance
815 * @retval State of bit (1 or 0).
816 */
LL_SPI_IsActiveFlag_BSY(SPI_TypeDef * SPIx)817 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
818 {
819 return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
820 }
821
822 /**
823 * @brief Get frame format error flag
824 * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
825 * @param SPIx SPI Instance
826 * @retval State of bit (1 or 0).
827 */
LL_SPI_IsActiveFlag_FRE(SPI_TypeDef * SPIx)828 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
829 {
830 return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
831 }
832
833 /**
834 * @brief Clear CRC error flag
835 * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
836 * @param SPIx SPI Instance
837 * @retval None
838 */
LL_SPI_ClearFlag_CRCERR(SPI_TypeDef * SPIx)839 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
840 {
841 CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
842 }
843
844 /**
845 * @brief Clear mode fault error flag
846 * @note Clearing this flag is done by a read access to the SPIx_SR
847 * register followed by a write access to the SPIx_CR1 register
848 * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
849 * @param SPIx SPI Instance
850 * @retval None
851 */
LL_SPI_ClearFlag_MODF(SPI_TypeDef * SPIx)852 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
853 {
854 __IO uint32_t tmpreg;
855 tmpreg = SPIx->SR;
856 (void) tmpreg;
857 tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
858 (void) tmpreg;
859 }
860
861 /**
862 * @brief Clear overrun error flag
863 * @note Clearing this flag is done by a read access to the SPIx_DR
864 * register followed by a read access to the SPIx_SR register
865 * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
866 * @param SPIx SPI Instance
867 * @retval None
868 */
LL_SPI_ClearFlag_OVR(SPI_TypeDef * SPIx)869 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
870 {
871 __IO uint32_t tmpreg;
872 tmpreg = SPIx->DR;
873 (void) tmpreg;
874 tmpreg = SPIx->SR;
875 (void) tmpreg;
876 }
877
878 /**
879 * @brief Clear frame format error flag
880 * @note Clearing this flag is done by reading SPIx_SR register
881 * @rmtoll SR FRE LL_SPI_ClearFlag_FRE
882 * @param SPIx SPI Instance
883 * @retval None
884 */
LL_SPI_ClearFlag_FRE(SPI_TypeDef * SPIx)885 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
886 {
887 __IO uint32_t tmpreg;
888 tmpreg = SPIx->SR;
889 (void) tmpreg;
890 }
891
892 /**
893 * @}
894 */
895
896 /** @defgroup SPI_LL_EF_IT_Management Interrupt Management
897 * @{
898 */
899
900 /**
901 * @brief Enable error interrupt
902 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
903 * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
904 * @param SPIx SPI Instance
905 * @retval None
906 */
LL_SPI_EnableIT_ERR(SPI_TypeDef * SPIx)907 __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
908 {
909 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
910 }
911
912 /**
913 * @brief Enable Rx buffer not empty interrupt
914 * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
915 * @param SPIx SPI Instance
916 * @retval None
917 */
LL_SPI_EnableIT_RXNE(SPI_TypeDef * SPIx)918 __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
919 {
920 SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
921 }
922
923 /**
924 * @brief Enable Tx buffer empty interrupt
925 * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
926 * @param SPIx SPI Instance
927 * @retval None
928 */
LL_SPI_EnableIT_TXE(SPI_TypeDef * SPIx)929 __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
930 {
931 SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
932 }
933
934 /**
935 * @brief Disable error interrupt
936 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
937 * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
938 * @param SPIx SPI Instance
939 * @retval None
940 */
LL_SPI_DisableIT_ERR(SPI_TypeDef * SPIx)941 __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
942 {
943 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
944 }
945
946 /**
947 * @brief Disable Rx buffer not empty interrupt
948 * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
949 * @param SPIx SPI Instance
950 * @retval None
951 */
LL_SPI_DisableIT_RXNE(SPI_TypeDef * SPIx)952 __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
953 {
954 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
955 }
956
957 /**
958 * @brief Disable Tx buffer empty interrupt
959 * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
960 * @param SPIx SPI Instance
961 * @retval None
962 */
LL_SPI_DisableIT_TXE(SPI_TypeDef * SPIx)963 __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
964 {
965 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
966 }
967
968 /**
969 * @brief Check if error interrupt is enabled
970 * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
971 * @param SPIx SPI Instance
972 * @retval State of bit (1 or 0).
973 */
LL_SPI_IsEnabledIT_ERR(SPI_TypeDef * SPIx)974 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
975 {
976 return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
977 }
978
979 /**
980 * @brief Check if Rx buffer not empty interrupt is enabled
981 * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
982 * @param SPIx SPI Instance
983 * @retval State of bit (1 or 0).
984 */
LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef * SPIx)985 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
986 {
987 return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
988 }
989
990 /**
991 * @brief Check if Tx buffer empty interrupt
992 * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
993 * @param SPIx SPI Instance
994 * @retval State of bit (1 or 0).
995 */
LL_SPI_IsEnabledIT_TXE(SPI_TypeDef * SPIx)996 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
997 {
998 return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
999 }
1000
1001 /**
1002 * @}
1003 */
1004
1005 /** @defgroup SPI_LL_EF_DMA_Management DMA Management
1006 * @{
1007 */
1008
1009 /**
1010 * @brief Enable DMA Rx
1011 * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
1012 * @param SPIx SPI Instance
1013 * @retval None
1014 */
LL_SPI_EnableDMAReq_RX(SPI_TypeDef * SPIx)1015 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
1016 {
1017 SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
1018 }
1019
1020 /**
1021 * @brief Disable DMA Rx
1022 * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
1023 * @param SPIx SPI Instance
1024 * @retval None
1025 */
LL_SPI_DisableDMAReq_RX(SPI_TypeDef * SPIx)1026 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
1027 {
1028 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
1029 }
1030
1031 /**
1032 * @brief Check if DMA Rx is enabled
1033 * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
1034 * @param SPIx SPI Instance
1035 * @retval State of bit (1 or 0).
1036 */
LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef * SPIx)1037 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
1038 {
1039 return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
1040 }
1041
1042 /**
1043 * @brief Enable DMA Tx
1044 * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
1045 * @param SPIx SPI Instance
1046 * @retval None
1047 */
LL_SPI_EnableDMAReq_TX(SPI_TypeDef * SPIx)1048 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
1049 {
1050 SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
1051 }
1052
1053 /**
1054 * @brief Disable DMA Tx
1055 * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
1056 * @param SPIx SPI Instance
1057 * @retval None
1058 */
LL_SPI_DisableDMAReq_TX(SPI_TypeDef * SPIx)1059 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
1060 {
1061 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
1062 }
1063
1064 /**
1065 * @brief Check if DMA Tx is enabled
1066 * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
1067 * @param SPIx SPI Instance
1068 * @retval State of bit (1 or 0).
1069 */
LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef * SPIx)1070 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
1071 {
1072 return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
1073 }
1074
1075 /**
1076 * @brief Get the data register address used for DMA transfer
1077 * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
1078 * @param SPIx SPI Instance
1079 * @retval Address of data register
1080 */
LL_SPI_DMA_GetRegAddr(SPI_TypeDef * SPIx)1081 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
1082 {
1083 return (uint32_t) & (SPIx->DR);
1084 }
1085
1086 /**
1087 * @}
1088 */
1089
1090 /** @defgroup SPI_LL_EF_DATA_Management DATA Management
1091 * @{
1092 */
1093
1094 /**
1095 * @brief Read 8-Bits in the data register
1096 * @rmtoll DR DR LL_SPI_ReceiveData8
1097 * @param SPIx SPI Instance
1098 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
1099 */
LL_SPI_ReceiveData8(SPI_TypeDef * SPIx)1100 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
1101 {
1102 return (uint8_t)(READ_REG(SPIx->DR));
1103 }
1104
1105 /**
1106 * @brief Read 16-Bits in the data register
1107 * @rmtoll DR DR LL_SPI_ReceiveData16
1108 * @param SPIx SPI Instance
1109 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
1110 */
LL_SPI_ReceiveData16(SPI_TypeDef * SPIx)1111 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
1112 {
1113 return (uint16_t)(READ_REG(SPIx->DR));
1114 }
1115
1116 /**
1117 * @brief Write 8-Bits in the data register
1118 * @rmtoll DR DR LL_SPI_TransmitData8
1119 * @param SPIx SPI Instance
1120 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
1121 * @retval None
1122 */
LL_SPI_TransmitData8(SPI_TypeDef * SPIx,uint8_t TxData)1123 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
1124 {
1125 *((__IO uint8_t *)&SPIx->DR) = TxData;
1126 }
1127
1128 /**
1129 * @brief Write 16-Bits in the data register
1130 * @rmtoll DR DR LL_SPI_TransmitData16
1131 * @param SPIx SPI Instance
1132 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
1133 * @retval None
1134 */
LL_SPI_TransmitData16(SPI_TypeDef * SPIx,uint16_t TxData)1135 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
1136 {
1137 *((__IO uint16_t *)&SPIx->DR) = TxData;
1138 }
1139
1140 /**
1141 * @}
1142 */
1143 #if defined(USE_FULL_LL_DRIVER)
1144 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
1145 * @{
1146 */
1147
1148 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
1149 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
1150 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
1151
1152 /**
1153 * @}
1154 */
1155 #endif /* USE_FULL_LL_DRIVER */
1156 /**
1157 * @}
1158 */
1159
1160 /**
1161 * @}
1162 */
1163
1164 #if defined(SPI_I2S_SUPPORT)
1165 /** @defgroup I2S_LL I2S
1166 * @{
1167 */
1168
1169 /* Private variables ---------------------------------------------------------*/
1170 /* Private constants ---------------------------------------------------------*/
1171 /* Private macros ------------------------------------------------------------*/
1172
1173 /* Exported types ------------------------------------------------------------*/
1174 #if defined(USE_FULL_LL_DRIVER)
1175 /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
1176 * @{
1177 */
1178
1179 /**
1180 * @brief I2S Init structure definition
1181 */
1182
1183 typedef struct
1184 {
1185 uint32_t Mode; /*!< Specifies the I2S operating mode.
1186 This parameter can be a value of @ref I2S_LL_EC_MODE
1187
1188 This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
1189
1190 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
1191 This parameter can be a value of @ref I2S_LL_EC_STANDARD
1192
1193 This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
1194
1195
1196 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
1197 This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
1198
1199 This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
1200
1201
1202 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
1203 This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
1204
1205 This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
1206
1207
1208 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
1209 This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
1210
1211 Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
1212 and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
1213
1214
1215 uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
1216 This parameter can be a value of @ref I2S_LL_EC_POLARITY
1217
1218 This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
1219
1220 } LL_I2S_InitTypeDef;
1221
1222 /**
1223 * @}
1224 */
1225 #endif /*USE_FULL_LL_DRIVER*/
1226
1227 /* Exported constants --------------------------------------------------------*/
1228 /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
1229 * @{
1230 */
1231
1232 /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
1233 * @brief Flags defines which can be used with LL_I2S_ReadReg function
1234 * @{
1235 */
1236 #define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
1237 #define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
1238 #define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
1239 #define LL_I2S_SR_UDR LL_SPI_SR_UDR /*!< Underrun flag */
1240 #define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
1241 #define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
1242 /**
1243 * @}
1244 */
1245
1246 /** @defgroup SPI_LL_EC_IT IT Defines
1247 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
1248 * @{
1249 */
1250 #define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
1251 #define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
1252 #define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */
1253 /**
1254 * @}
1255 */
1256
1257 /** @defgroup I2S_LL_EC_DATA_FORMAT Data format
1258 * @{
1259 */
1260 #define LL_I2S_DATAFORMAT_16B ((uint32_t)0x00000000U) /*!< Data length 16 bits, Channel lenght 16bit */
1261 #define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */
1262 #define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */
1263 #define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */
1264 /**
1265 * @}
1266 */
1267
1268 /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
1269 * @{
1270 */
1271 #define LL_I2S_POLARITY_LOW ((uint32_t)0x00000000U) /*!< Clock steady state is low level */
1272 #define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
1273 /**
1274 * @}
1275 */
1276
1277 /** @defgroup I2S_LL_EC_STANDARD I2s Standard
1278 * @{
1279 */
1280 #define LL_I2S_STANDARD_PHILIPS ((uint32_t)0x00000000U) /*!< I2S standard philips */
1281 #define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
1282 #define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
1283 #define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
1284 #define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */
1285 /**
1286 * @}
1287 */
1288
1289 /** @defgroup I2S_LL_EC_MODE Operation Mode
1290 * @{
1291 */
1292 #define LL_I2S_MODE_SLAVE_TX ((uint32_t)0x00000000U) /*!< Slave Tx configuration */
1293 #define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
1294 #define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
1295 #define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
1296 /**
1297 * @}
1298 */
1299
1300 /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
1301 * @{
1302 */
1303 #define LL_I2S_PRESCALER_PARITY_EVEN ((uint32_t)0x00000000U) /*!< Odd factor: Real divider value is = I2SDIV * 2 */
1304 #define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
1305 /**
1306 * @}
1307 */
1308
1309 #if defined(USE_FULL_LL_DRIVER)
1310
1311 /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
1312 * @{
1313 */
1314 #define LL_I2S_MCLK_OUTPUT_DISABLE ((uint32_t)0x00000000U) /*!< Master clock output is disabled */
1315 #define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
1316 /**
1317 * @}
1318 */
1319
1320 /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
1321 * @{
1322 */
1323
1324 #define LL_I2S_AUDIOFREQ_192K ((uint32_t)192000) /*!< Audio Frequency configuration 192000 Hz */
1325 #define LL_I2S_AUDIOFREQ_96K ((uint32_t) 96000) /*!< Audio Frequency configuration 96000 Hz */
1326 #define LL_I2S_AUDIOFREQ_48K ((uint32_t) 48000) /*!< Audio Frequency configuration 48000 Hz */
1327 #define LL_I2S_AUDIOFREQ_44K ((uint32_t) 44100) /*!< Audio Frequency configuration 44100 Hz */
1328 #define LL_I2S_AUDIOFREQ_32K ((uint32_t) 32000) /*!< Audio Frequency configuration 32000 Hz */
1329 #define LL_I2S_AUDIOFREQ_22K ((uint32_t) 22050) /*!< Audio Frequency configuration 22050 Hz */
1330 #define LL_I2S_AUDIOFREQ_16K ((uint32_t) 16000) /*!< Audio Frequency configuration 16000 Hz */
1331 #define LL_I2S_AUDIOFREQ_11K ((uint32_t) 11025) /*!< Audio Frequency configuration 11025 Hz */
1332 #define LL_I2S_AUDIOFREQ_8K ((uint32_t) 8000) /*!< Audio Frequency configuration 8000 Hz */
1333 #define LL_I2S_AUDIOFREQ_DEFAULT ((uint32_t) 2) /*!< Audio Freq not specified. Register I2SDIV = 2 */
1334 /**
1335 * @}
1336 */
1337 #endif /* USE_FULL_LL_DRIVER */
1338
1339 /**
1340 * @}
1341 */
1342
1343 /* Exported macro ------------------------------------------------------------*/
1344 /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
1345 * @{
1346 */
1347
1348 /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
1349 * @{
1350 */
1351
1352 /**
1353 * @brief Write a value in I2S register
1354 * @param __INSTANCE__ I2S Instance
1355 * @param __REG__ Register to be written
1356 * @param __VALUE__ Value to be written in the register
1357 * @retval None
1358 */
1359 #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1360
1361 /**
1362 * @brief Read a value in I2S register
1363 * @param __INSTANCE__ I2S Instance
1364 * @param __REG__ Register to be read
1365 * @retval Register value
1366 */
1367 #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1368 /**
1369 * @}
1370 */
1371
1372 /**
1373 * @}
1374 */
1375
1376
1377 /* Exported functions --------------------------------------------------------*/
1378
1379 /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
1380 * @{
1381 */
1382
1383 /** @defgroup I2S_LL_EF_Configuration Configuration
1384 * @{
1385 */
1386
1387 /**
1388 * @brief Select I2S mode and Enable I2S peripheral
1389 * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
1390 * I2SCFGR I2SE LL_I2S_Enable
1391 * @param SPIx SPI Instance
1392 * @retval None
1393 */
LL_I2S_Enable(SPI_TypeDef * SPIx)1394 __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
1395 {
1396 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
1397 }
1398
1399 /**
1400 * @brief Disable I2S peripheral
1401 * @rmtoll I2SCFGR I2SE LL_I2S_Disable
1402 * @param SPIx SPI Instance
1403 * @retval None
1404 */
LL_I2S_Disable(SPI_TypeDef * SPIx)1405 __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
1406 {
1407 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
1408 }
1409
1410 /**
1411 * @brief Check if I2S peripheral is enabled
1412 * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
1413 * @param SPIx SPI Instance
1414 * @retval State of bit (1 or 0).
1415 */
LL_I2S_IsEnabled(SPI_TypeDef * SPIx)1416 __STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
1417 {
1418 return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
1419 }
1420
1421 /**
1422 * @brief Set I2S Data frame length
1423 * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
1424 * I2SCFGR CHLEN LL_I2S_SetDataFormat
1425 * @param SPIx SPI Instance
1426 * @param DataFormat This parameter can be one of the following values:
1427 * @arg @ref LL_I2S_DATAFORMAT_16B
1428 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
1429 * @arg @ref LL_I2S_DATAFORMAT_24B
1430 * @arg @ref LL_I2S_DATAFORMAT_32B
1431 * @retval None
1432 */
LL_I2S_SetDataFormat(SPI_TypeDef * SPIx,uint32_t DataFormat)1433 __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
1434 {
1435 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
1436 }
1437
1438 /**
1439 * @brief Get I2S Data frame length
1440 * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
1441 * I2SCFGR CHLEN LL_I2S_GetDataFormat
1442 * @param SPIx SPI Instance
1443 * @retval Returned value can be one of the following values:
1444 * @arg @ref LL_I2S_DATAFORMAT_16B
1445 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
1446 * @arg @ref LL_I2S_DATAFORMAT_24B
1447 * @arg @ref LL_I2S_DATAFORMAT_32B
1448 */
LL_I2S_GetDataFormat(SPI_TypeDef * SPIx)1449 __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
1450 {
1451 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
1452 }
1453
1454 /**
1455 * @brief Set I2S clock polarity
1456 * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
1457 * @param SPIx SPI Instance
1458 * @param ClockPolarity This parameter can be one of the following values:
1459 * @arg @ref LL_I2S_POLARITY_LOW
1460 * @arg @ref LL_I2S_POLARITY_HIGH
1461 * @retval None
1462 */
LL_I2S_SetClockPolarity(SPI_TypeDef * SPIx,uint32_t ClockPolarity)1463 __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
1464 {
1465 SET_BIT(SPIx->I2SCFGR, ClockPolarity);
1466 }
1467
1468 /**
1469 * @brief Get I2S clock polarity
1470 * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
1471 * @param SPIx SPI Instance
1472 * @retval Returned value can be one of the following values:
1473 * @arg @ref LL_I2S_POLARITY_LOW
1474 * @arg @ref LL_I2S_POLARITY_HIGH
1475 */
LL_I2S_GetClockPolarity(SPI_TypeDef * SPIx)1476 __STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
1477 {
1478 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
1479 }
1480
1481 /**
1482 * @brief Set I2S Standard Protocol
1483 * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
1484 * I2SCFGR PCMSYNC LL_I2S_SetStandard
1485 * @param SPIx SPI Instance
1486 * @param Standard This parameter can be one of the following values:
1487 * @arg @ref LL_I2S_STANDARD_PHILIPS
1488 * @arg @ref LL_I2S_STANDARD_MSB
1489 * @arg @ref LL_I2S_STANDARD_LSB
1490 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
1491 * @arg @ref LL_I2S_STANDARD_PCM_LONG
1492 * @retval None
1493 */
LL_I2S_SetStandard(SPI_TypeDef * SPIx,uint32_t Standard)1494 __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
1495 {
1496 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
1497 }
1498
1499 /**
1500 * @brief Get I2S Standard Protocol
1501 * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
1502 * I2SCFGR PCMSYNC LL_I2S_GetStandard
1503 * @param SPIx SPI Instance
1504 * @retval Returned value can be one of the following values:
1505 * @arg @ref LL_I2S_STANDARD_PHILIPS
1506 * @arg @ref LL_I2S_STANDARD_MSB
1507 * @arg @ref LL_I2S_STANDARD_LSB
1508 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
1509 * @arg @ref LL_I2S_STANDARD_PCM_LONG
1510 */
LL_I2S_GetStandard(SPI_TypeDef * SPIx)1511 __STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
1512 {
1513 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
1514 }
1515
1516 /**
1517 * @brief Set I2S Transfer Mode
1518 * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
1519 * @param SPIx SPI Instance
1520 * @param Mode This parameter can be one of the following values:
1521 * @arg @ref LL_I2S_MODE_SLAVE_TX
1522 * @arg @ref LL_I2S_MODE_SLAVE_RX
1523 * @arg @ref LL_I2S_MODE_MASTER_TX
1524 * @arg @ref LL_I2S_MODE_MASTER_RX
1525 * @retval None
1526 */
LL_I2S_SetTransferMode(SPI_TypeDef * SPIx,uint32_t Mode)1527 __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
1528 {
1529 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
1530 }
1531
1532 /**
1533 * @brief Get I2S Transfer Mode
1534 * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
1535 * @param SPIx SPI Instance
1536 * @retval Returned value can be one of the following values:
1537 * @arg @ref LL_I2S_MODE_SLAVE_TX
1538 * @arg @ref LL_I2S_MODE_SLAVE_RX
1539 * @arg @ref LL_I2S_MODE_MASTER_TX
1540 * @arg @ref LL_I2S_MODE_MASTER_RX
1541 */
LL_I2S_GetTransferMode(SPI_TypeDef * SPIx)1542 __STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
1543 {
1544 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
1545 }
1546
1547 /**
1548 * @brief Set I2S linear prescaler
1549 * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
1550 * @param SPIx SPI Instance
1551 * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
1552 * @retval None
1553 */
LL_I2S_SetPrescalerLinear(SPI_TypeDef * SPIx,uint8_t PrescalerLinear)1554 __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
1555 {
1556 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
1557 }
1558
1559 /**
1560 * @brief Get I2S linear prescaler
1561 * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
1562 * @param SPIx SPI Instance
1563 * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
1564 */
LL_I2S_GetPrescalerLinear(SPI_TypeDef * SPIx)1565 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
1566 {
1567 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
1568 }
1569
1570 /**
1571 * @brief Set I2S parity prescaler
1572 * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
1573 * @param SPIx SPI Instance
1574 * @param PrescalerParity This parameter can be one of the following values:
1575 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
1576 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
1577 * @retval None
1578 */
LL_I2S_SetPrescalerParity(SPI_TypeDef * SPIx,uint32_t PrescalerParity)1579 __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
1580 {
1581 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
1582 }
1583
1584 /**
1585 * @brief Get I2S parity prescaler
1586 * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
1587 * @param SPIx SPI Instance
1588 * @retval Returned value can be one of the following values:
1589 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
1590 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
1591 */
LL_I2S_GetPrescalerParity(SPI_TypeDef * SPIx)1592 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
1593 {
1594 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
1595 }
1596
1597 /**
1598 * @brief Enable the Master Clock Ouput (Pin MCK)
1599 * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
1600 * @param SPIx SPI Instance
1601 * @retval None
1602 */
LL_I2S_EnableMasterClock(SPI_TypeDef * SPIx)1603 __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
1604 {
1605 SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
1606 }
1607
1608 /**
1609 * @brief Disable the Master Clock Ouput (Pin MCK)
1610 * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
1611 * @param SPIx SPI Instance
1612 * @retval None
1613 */
LL_I2S_DisableMasterClock(SPI_TypeDef * SPIx)1614 __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
1615 {
1616 CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
1617 }
1618
1619 /**
1620 * @brief Check if the Master Clock Ouput (Pin MCK) is enabled
1621 * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
1622 * @param SPIx SPI Instance
1623 * @retval State of bit (1 or 0).
1624 */
LL_I2S_IsEnabledMasterClock(SPI_TypeDef * SPIx)1625 __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
1626 {
1627 return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
1628 }
1629
1630 /**
1631 * @}
1632 */
1633
1634 /** @defgroup I2S_LL_EF_FLAG FLAG Management
1635 * @{
1636 */
1637
1638 /**
1639 * @brief Check if Rx buffer is not empty
1640 * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
1641 * @param SPIx SPI Instance
1642 * @retval State of bit (1 or 0).
1643 */
LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef * SPIx)1644 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
1645 {
1646 return LL_SPI_IsActiveFlag_RXNE(SPIx);
1647 }
1648
1649 /**
1650 * @brief Check if Tx buffer is empty
1651 * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
1652 * @param SPIx SPI Instance
1653 * @retval State of bit (1 or 0).
1654 */
LL_I2S_IsActiveFlag_TXE(SPI_TypeDef * SPIx)1655 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
1656 {
1657 return LL_SPI_IsActiveFlag_TXE(SPIx);
1658 }
1659
1660 /**
1661 * @brief Get Busy flag
1662 * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
1663 * @param SPIx SPI Instance
1664 * @retval State of bit (1 or 0).
1665 */
LL_I2S_IsActiveFlag_BSY(SPI_TypeDef * SPIx)1666 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
1667 {
1668 return LL_SPI_IsActiveFlag_BSY(SPIx);
1669 }
1670
1671 /**
1672 * @brief Get Overrun error flag
1673 * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
1674 * @param SPIx SPI Instance
1675 * @retval State of bit (1 or 0).
1676 */
LL_I2S_IsActiveFlag_OVR(SPI_TypeDef * SPIx)1677 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
1678 {
1679 return LL_SPI_IsActiveFlag_OVR(SPIx);
1680 }
1681
1682 /**
1683 * @brief Get Underrun error flag
1684 * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
1685 * @param SPIx SPI Instance
1686 * @retval State of bit (1 or 0).
1687 */
LL_I2S_IsActiveFlag_UDR(SPI_TypeDef * SPIx)1688 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
1689 {
1690 return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
1691 }
1692
1693 /**
1694 * @brief Get Frame format error flag
1695 * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
1696 * @param SPIx SPI Instance
1697 * @retval State of bit (1 or 0).
1698 */
LL_I2S_IsActiveFlag_FRE(SPI_TypeDef * SPIx)1699 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
1700 {
1701 return LL_SPI_IsActiveFlag_FRE(SPIx);
1702 }
1703
1704 /**
1705 * @brief Get Channel side flag.
1706 * @note 0: Channel Left has to be transmitted or has been received\n
1707 * 1: Channel Right has to be transmitted or has been received\n
1708 * It has no significance in PCM mode.
1709 * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
1710 * @param SPIx SPI Instance
1711 * @retval State of bit (1 or 0).
1712 */
LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef * SPIx)1713 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
1714 {
1715 return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
1716 }
1717
1718 /**
1719 * @brief Clear Overrun error flag
1720 * @rmtoll SR OVR LL_I2S_ClearFlag_OVR
1721 * @param SPIx SPI Instance
1722 * @retval None
1723 */
LL_I2S_ClearFlag_OVR(SPI_TypeDef * SPIx)1724 __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
1725 {
1726 LL_SPI_ClearFlag_OVR(SPIx);
1727 }
1728
1729 /**
1730 * @brief Clear Underrun error flag
1731 * @rmtoll SR UDR LL_I2S_ClearFlag_UDR
1732 * @param SPIx SPI Instance
1733 * @retval None
1734 */
LL_I2S_ClearFlag_UDR(SPI_TypeDef * SPIx)1735 __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
1736 {
1737 __IO uint32_t tmpreg;
1738 tmpreg = SPIx->SR;
1739 (void)tmpreg;
1740 }
1741
1742 /**
1743 * @brief Clear Frame format error flag
1744 * @rmtoll SR FRE LL_I2S_ClearFlag_FRE
1745 * @param SPIx SPI Instance
1746 * @retval None
1747 */
LL_I2S_ClearFlag_FRE(SPI_TypeDef * SPIx)1748 __STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
1749 {
1750 LL_SPI_ClearFlag_FRE(SPIx);
1751 }
1752
1753 /**
1754 * @}
1755 */
1756
1757 /** @defgroup I2S_LL_EF_IT Interrupt Management
1758 * @{
1759 */
1760
1761 /**
1762 * @brief Enable error IT
1763 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
1764 * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
1765 * @param SPIx SPI Instance
1766 * @retval None
1767 */
LL_I2S_EnableIT_ERR(SPI_TypeDef * SPIx)1768 __STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
1769 {
1770 LL_SPI_EnableIT_ERR(SPIx);
1771 }
1772
1773 /**
1774 * @brief Enable Rx buffer not empty IT
1775 * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
1776 * @param SPIx SPI Instance
1777 * @retval None
1778 */
LL_I2S_EnableIT_RXNE(SPI_TypeDef * SPIx)1779 __STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
1780 {
1781 LL_SPI_EnableIT_RXNE(SPIx);
1782 }
1783
1784 /**
1785 * @brief Enable Tx buffer empty IT
1786 * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
1787 * @param SPIx SPI Instance
1788 * @retval None
1789 */
LL_I2S_EnableIT_TXE(SPI_TypeDef * SPIx)1790 __STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
1791 {
1792 LL_SPI_EnableIT_TXE(SPIx);
1793 }
1794
1795 /**
1796 * @brief Disable Error IT
1797 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
1798 * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
1799 * @param SPIx SPI Instance
1800 * @retval None
1801 */
LL_I2S_DisableIT_ERR(SPI_TypeDef * SPIx)1802 __STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
1803 {
1804 LL_SPI_DisableIT_ERR(SPIx);
1805 }
1806
1807 /**
1808 * @brief Disable Rx buffer not empty IT
1809 * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
1810 * @param SPIx SPI Instance
1811 * @retval None
1812 */
LL_I2S_DisableIT_RXNE(SPI_TypeDef * SPIx)1813 __STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
1814 {
1815 LL_SPI_DisableIT_RXNE(SPIx);
1816 }
1817
1818 /**
1819 * @brief Disable Tx buffer empty IT
1820 * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
1821 * @param SPIx SPI Instance
1822 * @retval None
1823 */
LL_I2S_DisableIT_TXE(SPI_TypeDef * SPIx)1824 __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
1825 {
1826 LL_SPI_DisableIT_TXE(SPIx);
1827 }
1828
1829 /**
1830 * @brief Check if ERR IT is enabled
1831 * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
1832 * @param SPIx SPI Instance
1833 * @retval State of bit (1 or 0).
1834 */
LL_I2S_IsEnabledIT_ERR(SPI_TypeDef * SPIx)1835 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
1836 {
1837 return LL_SPI_IsEnabledIT_ERR(SPIx);
1838 }
1839
1840 /**
1841 * @brief Check if RXNE IT is enabled
1842 * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
1843 * @param SPIx SPI Instance
1844 * @retval State of bit (1 or 0).
1845 */
LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef * SPIx)1846 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
1847 {
1848 return LL_SPI_IsEnabledIT_RXNE(SPIx);
1849 }
1850
1851 /**
1852 * @brief Check if TXE IT is enabled
1853 * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
1854 * @param SPIx SPI Instance
1855 * @retval State of bit (1 or 0).
1856 */
LL_I2S_IsEnabledIT_TXE(SPI_TypeDef * SPIx)1857 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
1858 {
1859 return LL_SPI_IsEnabledIT_TXE(SPIx);
1860 }
1861
1862 /**
1863 * @}
1864 */
1865
1866 /** @defgroup I2S_LL_EF_DMA DMA Management
1867 * @{
1868 */
1869
1870 /**
1871 * @brief Enable DMA Rx
1872 * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
1873 * @param SPIx SPI Instance
1874 * @retval None
1875 */
LL_I2S_EnableDMAReq_RX(SPI_TypeDef * SPIx)1876 __STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
1877 {
1878 LL_SPI_EnableDMAReq_RX(SPIx);
1879 }
1880
1881 /**
1882 * @brief Disable DMA Rx
1883 * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
1884 * @param SPIx SPI Instance
1885 * @retval None
1886 */
LL_I2S_DisableDMAReq_RX(SPI_TypeDef * SPIx)1887 __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
1888 {
1889 LL_SPI_DisableDMAReq_RX(SPIx);
1890 }
1891
1892 /**
1893 * @brief Check if DMA Rx is enabled
1894 * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
1895 * @param SPIx SPI Instance
1896 * @retval State of bit (1 or 0).
1897 */
LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef * SPIx)1898 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
1899 {
1900 return LL_SPI_IsEnabledDMAReq_RX(SPIx);
1901 }
1902
1903 /**
1904 * @brief Enable DMA Tx
1905 * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
1906 * @param SPIx SPI Instance
1907 * @retval None
1908 */
LL_I2S_EnableDMAReq_TX(SPI_TypeDef * SPIx)1909 __STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
1910 {
1911 LL_SPI_EnableDMAReq_TX(SPIx);
1912 }
1913
1914 /**
1915 * @brief Disable DMA Tx
1916 * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
1917 * @param SPIx SPI Instance
1918 * @retval None
1919 */
LL_I2S_DisableDMAReq_TX(SPI_TypeDef * SPIx)1920 __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
1921 {
1922 LL_SPI_DisableDMAReq_TX(SPIx);
1923 }
1924
1925 /**
1926 * @brief Check if DMA Tx is enabled
1927 * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
1928 * @param SPIx SPI Instance
1929 * @retval State of bit (1 or 0).
1930 */
LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef * SPIx)1931 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
1932 {
1933 return LL_SPI_IsEnabledDMAReq_TX(SPIx);
1934 }
1935
1936 /**
1937 * @}
1938 */
1939
1940 /** @defgroup I2S_LL_EF_DATA DATA Management
1941 * @{
1942 */
1943
1944 /**
1945 * @brief Read 16-Bits in data register
1946 * @rmtoll DR DR LL_I2S_ReceiveData16
1947 * @param SPIx SPI Instance
1948 * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
1949 */
LL_I2S_ReceiveData16(SPI_TypeDef * SPIx)1950 __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
1951 {
1952 return LL_SPI_ReceiveData16(SPIx);
1953 }
1954
1955 /**
1956 * @brief Write 16-Bits in data register
1957 * @rmtoll DR DR LL_I2S_TransmitData16
1958 * @param SPIx SPI Instance
1959 * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
1960 * @retval None
1961 */
LL_I2S_TransmitData16(SPI_TypeDef * SPIx,uint16_t TxData)1962 __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
1963 {
1964 LL_SPI_TransmitData16(SPIx, TxData);
1965 }
1966
1967 /**
1968 * @}
1969 */
1970
1971 #if defined(USE_FULL_LL_DRIVER)
1972 /** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
1973 * @{
1974 */
1975
1976 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
1977 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
1978 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
1979 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
1980
1981 /**
1982 * @}
1983 */
1984 #endif /* USE_FULL_LL_DRIVER */
1985
1986 /**
1987 * @}
1988 */
1989
1990 /**
1991 * @}
1992 */
1993 #endif /* SPI_I2S_SUPPORT */
1994
1995 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
1996
1997 /**
1998 * @}
1999 */
2000
2001 #ifdef __cplusplus
2002 }
2003 #endif
2004
2005 #endif /* __STM32L1xx_LL_SPI_H */
2006
2007 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2008