1 /*
2  * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef ARCH_H
8 #define ARCH_H
9 
10 #include <lib/utils_def.h>
11 
12 /*******************************************************************************
13  * MIDR bit definitions
14  ******************************************************************************/
15 #define MIDR_IMPL_MASK		U(0xff)
16 #define MIDR_IMPL_SHIFT		U(24)
17 #define MIDR_VAR_SHIFT		U(20)
18 #define MIDR_VAR_BITS		U(4)
19 #define MIDR_REV_SHIFT		U(0)
20 #define MIDR_REV_BITS		U(4)
21 #define MIDR_PN_MASK		U(0xfff)
22 #define MIDR_PN_SHIFT		U(4)
23 
24 /*******************************************************************************
25  * MPIDR macros
26  ******************************************************************************/
27 #define MPIDR_MT_MASK		(U(1) << 24)
28 #define MPIDR_CPU_MASK		MPIDR_AFFLVL_MASK
29 #define MPIDR_CLUSTER_MASK	(MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
30 #define MPIDR_AFFINITY_BITS	U(8)
31 #define MPIDR_AFFLVL_MASK	U(0xff)
32 #define MPIDR_AFFLVL_SHIFT	U(3)
33 #define MPIDR_AFF0_SHIFT	U(0)
34 #define MPIDR_AFF1_SHIFT	U(8)
35 #define MPIDR_AFF2_SHIFT	U(16)
36 #define MPIDR_AFF_SHIFT(_n)	MPIDR_AFF##_n##_SHIFT
37 #define MPIDR_AFFINITY_MASK	U(0x00ffffff)
38 #define MPIDR_AFFLVL0		U(0)
39 #define MPIDR_AFFLVL1		U(1)
40 #define MPIDR_AFFLVL2		U(2)
41 #define MPIDR_AFFLVL(_n)	MPIDR_AFFLVL##_n
42 
43 #define MPIDR_AFFLVL0_VAL(mpidr) \
44 		(((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
45 #define MPIDR_AFFLVL1_VAL(mpidr) \
46 		(((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
47 #define MPIDR_AFFLVL2_VAL(mpidr) \
48 		(((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
49 #define MPIDR_AFFLVL3_VAL(mpidr)	U(0)
50 
51 #define MPIDR_AFF_ID(mpid, n)					\
52 	(((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK)
53 
54 #define MPID_MASK		(MPIDR_MT_MASK				|\
55 				 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)|\
56 				 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT)|\
57 				 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT))
58 
59 /*
60  * An invalid MPID. This value can be used by functions that return an MPID to
61  * indicate an error.
62  */
63 #define INVALID_MPID		U(0xFFFFFFFF)
64 
65 /*
66  * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
67  * add one while using this macro to define array sizes.
68  */
69 #define MPIDR_MAX_AFFLVL	U(2)
70 
71 /* Data Cache set/way op type defines */
72 #define DC_OP_ISW			U(0x0)
73 #define DC_OP_CISW			U(0x1)
74 #if ERRATA_A53_827319
75 #define DC_OP_CSW			DC_OP_CISW
76 #else
77 #define DC_OP_CSW			U(0x2)
78 #endif
79 
80 /*******************************************************************************
81  * Generic timer memory mapped registers & offsets
82  ******************************************************************************/
83 #define CNTCR_OFF			U(0x000)
84 /* Counter Count Value Lower register */
85 #define CNTCVL_OFF			U(0x008)
86 /* Counter Count Value Upper register */
87 #define CNTCVU_OFF			U(0x00C)
88 #define CNTFID_OFF			U(0x020)
89 
90 #define CNTCR_EN			(U(1) << 0)
91 #define CNTCR_HDBG			(U(1) << 1)
92 #define CNTCR_FCREQ(x)			((x) << 8)
93 
94 /*******************************************************************************
95  * System register bit definitions
96  ******************************************************************************/
97 /* CLIDR definitions */
98 #define LOUIS_SHIFT		U(21)
99 #define LOC_SHIFT		U(24)
100 #define CLIDR_FIELD_WIDTH	U(3)
101 
102 /* CSSELR definitions */
103 #define LEVEL_SHIFT		U(1)
104 
105 /* ID_DFR1_EL1 definitions */
106 #define ID_DFR1_MTPMU_SHIFT	U(0)
107 #define ID_DFR1_MTPMU_MASK	U(0xf)
108 #define ID_DFR1_MTPMU_SUPPORTED	U(1)
109 
110 /* ID_MMFR4 definitions */
111 #define ID_MMFR4_CNP_SHIFT	U(12)
112 #define ID_MMFR4_CNP_LENGTH	U(4)
113 #define ID_MMFR4_CNP_MASK	U(0xf)
114 
115 /* ID_PFR0 definitions */
116 #define ID_PFR0_AMU_SHIFT	U(20)
117 #define ID_PFR0_AMU_LENGTH	U(4)
118 #define ID_PFR0_AMU_MASK	U(0xf)
119 #define ID_PFR0_AMU_NOT_SUPPORTED	U(0x0)
120 #define ID_PFR0_AMU_V1		U(0x1)
121 #define ID_PFR0_AMU_V1P1	U(0x2)
122 
123 #define ID_PFR0_DIT_SHIFT	U(24)
124 #define ID_PFR0_DIT_LENGTH	U(4)
125 #define ID_PFR0_DIT_MASK	U(0xf)
126 #define ID_PFR0_DIT_SUPPORTED	(U(1) << ID_PFR0_DIT_SHIFT)
127 
128 /* ID_PFR1 definitions */
129 #define ID_PFR1_VIRTEXT_SHIFT	U(12)
130 #define ID_PFR1_VIRTEXT_MASK	U(0xf)
131 #define GET_VIRT_EXT(id)	(((id) >> ID_PFR1_VIRTEXT_SHIFT) \
132 				 & ID_PFR1_VIRTEXT_MASK)
133 #define ID_PFR1_GENTIMER_SHIFT	U(16)
134 #define ID_PFR1_GENTIMER_MASK	U(0xf)
135 #define ID_PFR1_GIC_SHIFT	U(28)
136 #define ID_PFR1_GIC_MASK	U(0xf)
137 #define ID_PFR1_SEC_SHIFT	U(4)
138 #define ID_PFR1_SEC_MASK	U(0xf)
139 #define ID_PFR1_ELx_ENABLED	U(1)
140 
141 /* SCTLR definitions */
142 #define SCTLR_RES1_DEF		((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \
143 				 (U(1) << 3))
144 #if ARM_ARCH_MAJOR == 7
145 #define SCTLR_RES1		SCTLR_RES1_DEF
146 #else
147 #define SCTLR_RES1		(SCTLR_RES1_DEF | (U(1) << 11))
148 #endif
149 #define SCTLR_M_BIT		(U(1) << 0)
150 #define SCTLR_A_BIT		(U(1) << 1)
151 #define SCTLR_C_BIT		(U(1) << 2)
152 #define SCTLR_CP15BEN_BIT	(U(1) << 5)
153 #define SCTLR_ITD_BIT		(U(1) << 7)
154 #define SCTLR_Z_BIT		(U(1) << 11)
155 #define SCTLR_I_BIT		(U(1) << 12)
156 #define SCTLR_V_BIT		(U(1) << 13)
157 #define SCTLR_RR_BIT		(U(1) << 14)
158 #define SCTLR_NTWI_BIT		(U(1) << 16)
159 #define SCTLR_NTWE_BIT		(U(1) << 18)
160 #define SCTLR_WXN_BIT		(U(1) << 19)
161 #define SCTLR_UWXN_BIT		(U(1) << 20)
162 #define SCTLR_EE_BIT		(U(1) << 25)
163 #define SCTLR_TRE_BIT		(U(1) << 28)
164 #define SCTLR_AFE_BIT		(U(1) << 29)
165 #define SCTLR_TE_BIT		(U(1) << 30)
166 #define SCTLR_DSSBS_BIT		(U(1) << 31)
167 #define SCTLR_RESET_VAL         (SCTLR_RES1 | SCTLR_NTWE_BIT |		\
168 				SCTLR_NTWI_BIT | SCTLR_CP15BEN_BIT)
169 
170 /* SDCR definitions */
171 #define SDCR_SPD(x)		((x) << 14)
172 #define SDCR_SPD_LEGACY		U(0x0)
173 #define SDCR_SPD_DISABLE	U(0x2)
174 #define SDCR_SPD_ENABLE		U(0x3)
175 #define SDCR_SCCD_BIT		(U(1) << 23)
176 #define SDCR_SPME_BIT		(U(1) << 17)
177 #define SDCR_RESET_VAL		U(0x0)
178 #define SDCR_MTPME_BIT		(U(1) << 28)
179 
180 /* HSCTLR definitions */
181 #define HSCTLR_RES1	((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
182 			 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
183 			 (U(1) << 11) | (U(1) << 4) | (U(1) << 3))
184 
185 #define HSCTLR_M_BIT		(U(1) << 0)
186 #define HSCTLR_A_BIT		(U(1) << 1)
187 #define HSCTLR_C_BIT		(U(1) << 2)
188 #define HSCTLR_CP15BEN_BIT	(U(1) << 5)
189 #define HSCTLR_ITD_BIT		(U(1) << 7)
190 #define HSCTLR_SED_BIT		(U(1) << 8)
191 #define HSCTLR_I_BIT		(U(1) << 12)
192 #define HSCTLR_WXN_BIT		(U(1) << 19)
193 #define HSCTLR_EE_BIT		(U(1) << 25)
194 #define HSCTLR_TE_BIT		(U(1) << 30)
195 
196 /* CPACR definitions */
197 #define CPACR_FPEN(x)		((x) << 20)
198 #define CPACR_FP_TRAP_PL0	UL(0x1)
199 #define CPACR_FP_TRAP_ALL	UL(0x2)
200 #define CPACR_FP_TRAP_NONE	UL(0x3)
201 
202 /* SCR definitions */
203 #define SCR_TWE_BIT		(UL(1) << 13)
204 #define SCR_TWI_BIT		(UL(1) << 12)
205 #define SCR_SIF_BIT		(UL(1) << 9)
206 #define SCR_HCE_BIT		(UL(1) << 8)
207 #define SCR_SCD_BIT		(UL(1) << 7)
208 #define SCR_NET_BIT		(UL(1) << 6)
209 #define SCR_AW_BIT		(UL(1) << 5)
210 #define SCR_FW_BIT		(UL(1) << 4)
211 #define SCR_EA_BIT		(UL(1) << 3)
212 #define SCR_FIQ_BIT		(UL(1) << 2)
213 #define SCR_IRQ_BIT		(UL(1) << 1)
214 #define SCR_NS_BIT		(UL(1) << 0)
215 #define SCR_VALID_BIT_MASK	U(0x33ff)
216 #define SCR_RESET_VAL		U(0x0)
217 
218 #define GET_NS_BIT(scr)		((scr) & SCR_NS_BIT)
219 
220 /* HCR definitions */
221 #define HCR_TGE_BIT		(U(1) << 27)
222 #define HCR_AMO_BIT		(U(1) << 5)
223 #define HCR_IMO_BIT		(U(1) << 4)
224 #define HCR_FMO_BIT		(U(1) << 3)
225 #define HCR_RESET_VAL		U(0x0)
226 
227 /* CNTHCTL definitions */
228 #define CNTHCTL_RESET_VAL	U(0x0)
229 #define PL1PCEN_BIT		(U(1) << 1)
230 #define PL1PCTEN_BIT		(U(1) << 0)
231 
232 /* CNTKCTL definitions */
233 #define PL0PTEN_BIT		(U(1) << 9)
234 #define PL0VTEN_BIT		(U(1) << 8)
235 #define PL0PCTEN_BIT		(U(1) << 0)
236 #define PL0VCTEN_BIT		(U(1) << 1)
237 #define EVNTEN_BIT		(U(1) << 2)
238 #define EVNTDIR_BIT		(U(1) << 3)
239 #define EVNTI_SHIFT		U(4)
240 #define EVNTI_MASK		U(0xf)
241 
242 /* HCPTR definitions */
243 #define HCPTR_RES1		((U(1) << 13) | (U(1) << 12) | U(0x3ff))
244 #define TCPAC_BIT		(U(1) << 31)
245 #define TAM_BIT			(U(1) << 30)
246 #define TTA_BIT			(U(1) << 20)
247 #define TCP11_BIT		(U(1) << 11)
248 #define TCP10_BIT		(U(1) << 10)
249 #define HCPTR_RESET_VAL		HCPTR_RES1
250 
251 /* VTTBR defintions */
252 #define VTTBR_RESET_VAL		ULL(0x0)
253 #define VTTBR_VMID_MASK		ULL(0xff)
254 #define VTTBR_VMID_SHIFT	U(48)
255 #define VTTBR_BADDR_MASK	ULL(0xffffffffffff)
256 #define VTTBR_BADDR_SHIFT	U(0)
257 
258 /* HDCR definitions */
259 #define HDCR_MTPME_BIT		(U(1) << 28)
260 #define HDCR_HLP_BIT		(U(1) << 26)
261 #define HDCR_HPME_BIT		(U(1) << 7)
262 #define HDCR_RESET_VAL		U(0x0)
263 
264 /* HSTR definitions */
265 #define HSTR_RESET_VAL		U(0x0)
266 
267 /* CNTHP_CTL definitions */
268 #define CNTHP_CTL_RESET_VAL	U(0x0)
269 
270 /* NSACR definitions */
271 #define NSASEDIS_BIT		(U(1) << 15)
272 #define NSTRCDIS_BIT		(U(1) << 20)
273 #define NSACR_CP11_BIT		(U(1) << 11)
274 #define NSACR_CP10_BIT		(U(1) << 10)
275 #define NSACR_IMP_DEF_MASK	(U(0x7) << 16)
276 #define NSACR_ENABLE_FP_ACCESS	(NSACR_CP11_BIT | NSACR_CP10_BIT)
277 #define NSACR_RESET_VAL		U(0x0)
278 
279 /* CPACR definitions */
280 #define ASEDIS_BIT		(U(1) << 31)
281 #define TRCDIS_BIT		(U(1) << 28)
282 #define CPACR_CP11_SHIFT	U(22)
283 #define CPACR_CP10_SHIFT	U(20)
284 #define CPACR_ENABLE_FP_ACCESS	((U(0x3) << CPACR_CP11_SHIFT) |\
285 				 (U(0x3) << CPACR_CP10_SHIFT))
286 #define CPACR_RESET_VAL         U(0x0)
287 
288 /* FPEXC definitions */
289 #define FPEXC_RES1		((U(1) << 10) | (U(1) << 9) | (U(1) << 8))
290 #define FPEXC_EN_BIT		(U(1) << 30)
291 #define FPEXC_RESET_VAL		FPEXC_RES1
292 
293 /* SPSR/CPSR definitions */
294 #define SPSR_FIQ_BIT		(U(1) << 0)
295 #define SPSR_IRQ_BIT		(U(1) << 1)
296 #define SPSR_ABT_BIT		(U(1) << 2)
297 #define SPSR_AIF_SHIFT		U(6)
298 #define SPSR_AIF_MASK		U(0x7)
299 
300 #define SPSR_E_SHIFT		U(9)
301 #define SPSR_E_MASK		U(0x1)
302 #define SPSR_E_LITTLE		U(0)
303 #define SPSR_E_BIG		U(1)
304 
305 #define SPSR_T_SHIFT		U(5)
306 #define SPSR_T_MASK		U(0x1)
307 #define SPSR_T_ARM		U(0)
308 #define SPSR_T_THUMB		U(1)
309 
310 #define SPSR_MODE_SHIFT		U(0)
311 #define SPSR_MODE_MASK		U(0x7)
312 
313 #define SPSR_SSBS_BIT		BIT_32(23)
314 
315 #define DISABLE_ALL_EXCEPTIONS \
316 		(SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT)
317 
318 #define CPSR_DIT_BIT		(U(1) << 21)
319 /*
320  * TTBCR definitions
321  */
322 #define TTBCR_EAE_BIT		(U(1) << 31)
323 
324 #define TTBCR_SH1_NON_SHAREABLE		(U(0x0) << 28)
325 #define TTBCR_SH1_OUTER_SHAREABLE	(U(0x2) << 28)
326 #define TTBCR_SH1_INNER_SHAREABLE	(U(0x3) << 28)
327 
328 #define TTBCR_RGN1_OUTER_NC	(U(0x0) << 26)
329 #define TTBCR_RGN1_OUTER_WBA	(U(0x1) << 26)
330 #define TTBCR_RGN1_OUTER_WT	(U(0x2) << 26)
331 #define TTBCR_RGN1_OUTER_WBNA	(U(0x3) << 26)
332 
333 #define TTBCR_RGN1_INNER_NC	(U(0x0) << 24)
334 #define TTBCR_RGN1_INNER_WBA	(U(0x1) << 24)
335 #define TTBCR_RGN1_INNER_WT	(U(0x2) << 24)
336 #define TTBCR_RGN1_INNER_WBNA	(U(0x3) << 24)
337 
338 #define TTBCR_EPD1_BIT		(U(1) << 23)
339 #define TTBCR_A1_BIT		(U(1) << 22)
340 
341 #define TTBCR_T1SZ_SHIFT	U(16)
342 #define TTBCR_T1SZ_MASK		U(0x7)
343 #define TTBCR_TxSZ_MIN		U(0)
344 #define TTBCR_TxSZ_MAX		U(7)
345 
346 #define TTBCR_SH0_NON_SHAREABLE		(U(0x0) << 12)
347 #define TTBCR_SH0_OUTER_SHAREABLE	(U(0x2) << 12)
348 #define TTBCR_SH0_INNER_SHAREABLE	(U(0x3) << 12)
349 
350 #define TTBCR_RGN0_OUTER_NC	(U(0x0) << 10)
351 #define TTBCR_RGN0_OUTER_WBA	(U(0x1) << 10)
352 #define TTBCR_RGN0_OUTER_WT	(U(0x2) << 10)
353 #define TTBCR_RGN0_OUTER_WBNA	(U(0x3) << 10)
354 
355 #define TTBCR_RGN0_INNER_NC	(U(0x0) << 8)
356 #define TTBCR_RGN0_INNER_WBA	(U(0x1) << 8)
357 #define TTBCR_RGN0_INNER_WT	(U(0x2) << 8)
358 #define TTBCR_RGN0_INNER_WBNA	(U(0x3) << 8)
359 
360 #define TTBCR_EPD0_BIT		(U(1) << 7)
361 #define TTBCR_T0SZ_SHIFT	U(0)
362 #define TTBCR_T0SZ_MASK		U(0x7)
363 
364 /*
365  * HTCR definitions
366  */
367 #define HTCR_RES1			((U(1) << 31) | (U(1) << 23))
368 
369 #define HTCR_SH0_NON_SHAREABLE		(U(0x0) << 12)
370 #define HTCR_SH0_OUTER_SHAREABLE	(U(0x2) << 12)
371 #define HTCR_SH0_INNER_SHAREABLE	(U(0x3) << 12)
372 
373 #define HTCR_RGN0_OUTER_NC	(U(0x0) << 10)
374 #define HTCR_RGN0_OUTER_WBA	(U(0x1) << 10)
375 #define HTCR_RGN0_OUTER_WT	(U(0x2) << 10)
376 #define HTCR_RGN0_OUTER_WBNA	(U(0x3) << 10)
377 
378 #define HTCR_RGN0_INNER_NC	(U(0x0) << 8)
379 #define HTCR_RGN0_INNER_WBA	(U(0x1) << 8)
380 #define HTCR_RGN0_INNER_WT	(U(0x2) << 8)
381 #define HTCR_RGN0_INNER_WBNA	(U(0x3) << 8)
382 
383 #define HTCR_T0SZ_SHIFT		U(0)
384 #define HTCR_T0SZ_MASK		U(0x7)
385 
386 #define MODE_RW_SHIFT		U(0x4)
387 #define MODE_RW_MASK		U(0x1)
388 #define MODE_RW_32		U(0x1)
389 
390 #define MODE32_SHIFT		U(0)
391 #define MODE32_MASK		U(0x1f)
392 #define MODE32_usr		U(0x10)
393 #define MODE32_fiq		U(0x11)
394 #define MODE32_irq		U(0x12)
395 #define MODE32_svc		U(0x13)
396 #define MODE32_mon		U(0x16)
397 #define MODE32_abt		U(0x17)
398 #define MODE32_hyp		U(0x1a)
399 #define MODE32_und		U(0x1b)
400 #define MODE32_sys		U(0x1f)
401 
402 #define GET_M32(mode)		(((mode) >> MODE32_SHIFT) & MODE32_MASK)
403 
404 #define SPSR_MODE32(mode, isa, endian, aif) \
405 ( \
406 	( \
407 		(MODE_RW_32 << MODE_RW_SHIFT) | \
408 		(((mode) & MODE32_MASK) << MODE32_SHIFT) | \
409 		(((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \
410 		(((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \
411 		(((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) \
412 	) & \
413 	(~(SPSR_SSBS_BIT)) \
414 )
415 
416 /*
417  * TTBR definitions
418  */
419 #define TTBR_CNP_BIT		ULL(0x1)
420 
421 /*
422  * CTR definitions
423  */
424 #define CTR_CWG_SHIFT		U(24)
425 #define CTR_CWG_MASK		U(0xf)
426 #define CTR_ERG_SHIFT		U(20)
427 #define CTR_ERG_MASK		U(0xf)
428 #define CTR_DMINLINE_SHIFT	U(16)
429 #define CTR_DMINLINE_WIDTH	U(4)
430 #define CTR_DMINLINE_MASK	((U(1) << 4) - U(1))
431 #define CTR_L1IP_SHIFT		U(14)
432 #define CTR_L1IP_MASK		U(0x3)
433 #define CTR_IMINLINE_SHIFT	U(0)
434 #define CTR_IMINLINE_MASK	U(0xf)
435 
436 #define MAX_CACHE_LINE_SIZE	U(0x800) /* 2KB */
437 
438 /* PMCR definitions */
439 #define PMCR_N_SHIFT		U(11)
440 #define PMCR_N_MASK		U(0x1f)
441 #define PMCR_N_BITS		(PMCR_N_MASK << PMCR_N_SHIFT)
442 #define PMCR_LP_BIT		(U(1) << 7)
443 #define PMCR_LC_BIT		(U(1) << 6)
444 #define PMCR_DP_BIT		(U(1) << 5)
445 #define	PMCR_RESET_VAL		U(0x0)
446 
447 /*******************************************************************************
448  * Definitions of register offsets, fields and macros for CPU system
449  * instructions.
450  ******************************************************************************/
451 
452 #define TLBI_ADDR_SHIFT		U(0)
453 #define TLBI_ADDR_MASK		U(0xFFFFF000)
454 #define TLBI_ADDR(x)		(((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
455 
456 /*******************************************************************************
457  * Definitions of register offsets and fields in the CNTCTLBase Frame of the
458  * system level implementation of the Generic Timer.
459  ******************************************************************************/
460 #define CNTCTLBASE_CNTFRQ	U(0x0)
461 #define CNTNSAR			U(0x4)
462 #define CNTNSAR_NS_SHIFT(x)	(x)
463 
464 #define CNTACR_BASE(x)		(U(0x40) + ((x) << 2))
465 #define CNTACR_RPCT_SHIFT	U(0x0)
466 #define CNTACR_RVCT_SHIFT	U(0x1)
467 #define CNTACR_RFRQ_SHIFT	U(0x2)
468 #define CNTACR_RVOFF_SHIFT	U(0x3)
469 #define CNTACR_RWVT_SHIFT	U(0x4)
470 #define CNTACR_RWPT_SHIFT	U(0x5)
471 
472 /*******************************************************************************
473  * Definitions of register offsets and fields in the CNTBaseN Frame of the
474  * system level implementation of the Generic Timer.
475  ******************************************************************************/
476 /* Physical Count register. */
477 #define CNTPCT_LO		U(0x0)
478 /* Counter Frequency register. */
479 #define CNTBASEN_CNTFRQ		U(0x10)
480 /* Physical Timer CompareValue register. */
481 #define CNTP_CVAL_LO		U(0x20)
482 /* Physical Timer Control register. */
483 #define CNTP_CTL		U(0x2c)
484 
485 /* Physical timer control register bit fields shifts and masks */
486 #define CNTP_CTL_ENABLE_SHIFT   0
487 #define CNTP_CTL_IMASK_SHIFT    1
488 #define CNTP_CTL_ISTATUS_SHIFT  2
489 
490 #define CNTP_CTL_ENABLE_MASK    U(1)
491 #define CNTP_CTL_IMASK_MASK     U(1)
492 #define CNTP_CTL_ISTATUS_MASK   U(1)
493 
494 /* MAIR macros */
495 #define MAIR0_ATTR_SET(attr, index)	((attr) << ((index) << U(3)))
496 #define MAIR1_ATTR_SET(attr, index)	((attr) << (((index) - U(3)) << U(3)))
497 
498 /* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */
499 #define SCR		p15, 0, c1, c1, 0
500 #define SCTLR		p15, 0, c1, c0, 0
501 #define ACTLR		p15, 0, c1, c0, 1
502 #define SDCR		p15, 0, c1, c3, 1
503 #define MPIDR		p15, 0, c0, c0, 5
504 #define MIDR		p15, 0, c0, c0, 0
505 #define HVBAR		p15, 4, c12, c0, 0
506 #define VBAR		p15, 0, c12, c0, 0
507 #define MVBAR		p15, 0, c12, c0, 1
508 #define NSACR		p15, 0, c1, c1, 2
509 #define CPACR		p15, 0, c1, c0, 2
510 #define DCCIMVAC	p15, 0, c7, c14, 1
511 #define DCCMVAC		p15, 0, c7, c10, 1
512 #define DCIMVAC		p15, 0, c7, c6, 1
513 #define DCCISW		p15, 0, c7, c14, 2
514 #define DCCSW		p15, 0, c7, c10, 2
515 #define DCISW		p15, 0, c7, c6, 2
516 #define CTR		p15, 0, c0, c0, 1
517 #define CNTFRQ		p15, 0, c14, c0, 0
518 #define ID_MMFR4	p15, 0, c0, c2, 6
519 #define ID_DFR1		p15, 0, c0, c3, 5
520 #define ID_PFR0		p15, 0, c0, c1, 0
521 #define ID_PFR1		p15, 0, c0, c1, 1
522 #define MAIR0		p15, 0, c10, c2, 0
523 #define MAIR1		p15, 0, c10, c2, 1
524 #define TTBCR		p15, 0, c2, c0, 2
525 #define TTBR0		p15, 0, c2, c0, 0
526 #define TTBR1		p15, 0, c2, c0, 1
527 #define TLBIALL		p15, 0, c8, c7, 0
528 #define TLBIALLH	p15, 4, c8, c7, 0
529 #define TLBIALLIS	p15, 0, c8, c3, 0
530 #define TLBIMVA		p15, 0, c8, c7, 1
531 #define TLBIMVAA	p15, 0, c8, c7, 3
532 #define TLBIMVAAIS	p15, 0, c8, c3, 3
533 #define TLBIMVAHIS	p15, 4, c8, c3, 1
534 #define BPIALLIS	p15, 0, c7, c1, 6
535 #define BPIALL		p15, 0, c7, c5, 6
536 #define ICIALLU		p15, 0, c7, c5, 0
537 #define HSCTLR		p15, 4, c1, c0, 0
538 #define HCR		p15, 4, c1, c1, 0
539 #define HCPTR		p15, 4, c1, c1, 2
540 #define HSTR		p15, 4, c1, c1, 3
541 #define CNTHCTL		p15, 4, c14, c1, 0
542 #define CNTKCTL		p15, 0, c14, c1, 0
543 #define VPIDR		p15, 4, c0, c0, 0
544 #define VMPIDR		p15, 4, c0, c0, 5
545 #define ISR		p15, 0, c12, c1, 0
546 #define CLIDR		p15, 1, c0, c0, 1
547 #define CSSELR		p15, 2, c0, c0, 0
548 #define CCSIDR		p15, 1, c0, c0, 0
549 #define HTCR		p15, 4, c2, c0, 2
550 #define HMAIR0		p15, 4, c10, c2, 0
551 #define ATS1CPR		p15, 0, c7, c8, 0
552 #define ATS1HR		p15, 4, c7, c8, 0
553 #define DBGOSDLR	p14, 0, c1, c3, 4
554 
555 /* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
556 #define HDCR		p15, 4, c1, c1, 1
557 #define PMCR		p15, 0, c9, c12, 0
558 #define CNTHP_TVAL	p15, 4, c14, c2, 0
559 #define CNTHP_CTL	p15, 4, c14, c2, 1
560 
561 /* AArch32 coproc registers for 32bit MMU descriptor support */
562 #define PRRR		p15, 0, c10, c2, 0
563 #define NMRR		p15, 0, c10, c2, 1
564 #define DACR		p15, 0, c3, c0, 0
565 
566 /* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
567 #define ICC_IAR1	p15, 0, c12, c12, 0
568 #define ICC_IAR0	p15, 0, c12, c8, 0
569 #define ICC_EOIR1	p15, 0, c12, c12, 1
570 #define ICC_EOIR0	p15, 0, c12, c8, 1
571 #define ICC_HPPIR1	p15, 0, c12, c12, 2
572 #define ICC_HPPIR0	p15, 0, c12, c8, 2
573 #define ICC_BPR1	p15, 0, c12, c12, 3
574 #define ICC_BPR0	p15, 0, c12, c8, 3
575 #define ICC_DIR		p15, 0, c12, c11, 1
576 #define ICC_PMR		p15, 0, c4, c6, 0
577 #define ICC_RPR		p15, 0, c12, c11, 3
578 #define ICC_CTLR	p15, 0, c12, c12, 4
579 #define ICC_MCTLR	p15, 6, c12, c12, 4
580 #define ICC_SRE		p15, 0, c12, c12, 5
581 #define ICC_HSRE	p15, 4, c12, c9, 5
582 #define ICC_MSRE	p15, 6, c12, c12, 5
583 #define ICC_IGRPEN0	p15, 0, c12, c12, 6
584 #define ICC_IGRPEN1	p15, 0, c12, c12, 7
585 #define ICC_MGRPEN1	p15, 6, c12, c12, 7
586 
587 /* 64 bit system register defines The format is: coproc, opt1, CRm */
588 #define TTBR0_64	p15, 0, c2
589 #define TTBR1_64	p15, 1, c2
590 #define CNTVOFF_64	p15, 4, c14
591 #define VTTBR_64	p15, 6, c2
592 #define CNTPCT_64	p15, 0, c14
593 #define HTTBR_64	p15, 4, c2
594 #define CNTHP_CVAL_64	p15, 6, c14
595 #define PAR_64		p15, 0, c7
596 
597 /* 64 bit GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRm */
598 #define ICC_SGI1R_EL1_64	p15, 0, c12
599 #define ICC_ASGI1R_EL1_64	p15, 1, c12
600 #define ICC_SGI0R_EL1_64	p15, 2, c12
601 
602 /*******************************************************************************
603  * Definitions of MAIR encodings for device and normal memory
604  ******************************************************************************/
605 /*
606  * MAIR encodings for device memory attributes.
607  */
608 #define MAIR_DEV_nGnRnE		U(0x0)
609 #define MAIR_DEV_nGnRE		U(0x4)
610 #define MAIR_DEV_nGRE		U(0x8)
611 #define MAIR_DEV_GRE		U(0xc)
612 
613 /*
614  * MAIR encodings for normal memory attributes.
615  *
616  * Cache Policy
617  *  WT:	 Write Through
618  *  WB:	 Write Back
619  *  NC:	 Non-Cacheable
620  *
621  * Transient Hint
622  *  NTR: Non-Transient
623  *  TR:	 Transient
624  *
625  * Allocation Policy
626  *  RA:	 Read Allocate
627  *  WA:	 Write Allocate
628  *  RWA: Read and Write Allocate
629  *  NA:	 No Allocation
630  */
631 #define MAIR_NORM_WT_TR_WA	U(0x1)
632 #define MAIR_NORM_WT_TR_RA	U(0x2)
633 #define MAIR_NORM_WT_TR_RWA	U(0x3)
634 #define MAIR_NORM_NC		U(0x4)
635 #define MAIR_NORM_WB_TR_WA	U(0x5)
636 #define MAIR_NORM_WB_TR_RA	U(0x6)
637 #define MAIR_NORM_WB_TR_RWA	U(0x7)
638 #define MAIR_NORM_WT_NTR_NA	U(0x8)
639 #define MAIR_NORM_WT_NTR_WA	U(0x9)
640 #define MAIR_NORM_WT_NTR_RA	U(0xa)
641 #define MAIR_NORM_WT_NTR_RWA	U(0xb)
642 #define MAIR_NORM_WB_NTR_NA	U(0xc)
643 #define MAIR_NORM_WB_NTR_WA	U(0xd)
644 #define MAIR_NORM_WB_NTR_RA	U(0xe)
645 #define MAIR_NORM_WB_NTR_RWA	U(0xf)
646 
647 #define MAIR_NORM_OUTER_SHIFT	U(4)
648 
649 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer)	\
650 		((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
651 
652 /* PAR fields */
653 #define PAR_F_SHIFT	U(0)
654 #define PAR_F_MASK	ULL(0x1)
655 #define PAR_ADDR_SHIFT	U(12)
656 #define PAR_ADDR_MASK	(BIT_64(40) - ULL(1)) /* 40-bits-wide page address */
657 
658 /*******************************************************************************
659  * Definitions for system register interface to AMU for FEAT_AMUv1
660  ******************************************************************************/
661 #define AMCR		p15, 0, c13, c2, 0
662 #define AMCFGR		p15, 0, c13, c2, 1
663 #define AMCGCR		p15, 0, c13, c2, 2
664 #define AMUSERENR	p15, 0, c13, c2, 3
665 #define AMCNTENCLR0	p15, 0, c13, c2, 4
666 #define AMCNTENSET0	p15, 0, c13, c2, 5
667 #define AMCNTENCLR1	p15, 0, c13, c3, 0
668 #define AMCNTENSET1	p15, 0, c13, c3, 1
669 
670 /* Activity Monitor Group 0 Event Counter Registers */
671 #define AMEVCNTR00	p15, 0, c0
672 #define AMEVCNTR01	p15, 1, c0
673 #define AMEVCNTR02	p15, 2, c0
674 #define AMEVCNTR03	p15, 3, c0
675 
676 /* Activity Monitor Group 0 Event Type Registers */
677 #define AMEVTYPER00	p15, 0, c13, c6, 0
678 #define AMEVTYPER01	p15, 0, c13, c6, 1
679 #define AMEVTYPER02	p15, 0, c13, c6, 2
680 #define AMEVTYPER03	p15, 0, c13, c6, 3
681 
682 /* Activity Monitor Group 1 Event Counter Registers */
683 #define AMEVCNTR10	p15, 0, c4
684 #define AMEVCNTR11	p15, 1, c4
685 #define AMEVCNTR12	p15, 2, c4
686 #define AMEVCNTR13	p15, 3, c4
687 #define AMEVCNTR14	p15, 4, c4
688 #define AMEVCNTR15	p15, 5, c4
689 #define AMEVCNTR16	p15, 6, c4
690 #define AMEVCNTR17	p15, 7, c4
691 #define AMEVCNTR18	p15, 0, c5
692 #define AMEVCNTR19	p15, 1, c5
693 #define AMEVCNTR1A	p15, 2, c5
694 #define AMEVCNTR1B	p15, 3, c5
695 #define AMEVCNTR1C	p15, 4, c5
696 #define AMEVCNTR1D	p15, 5, c5
697 #define AMEVCNTR1E	p15, 6, c5
698 #define AMEVCNTR1F	p15, 7, c5
699 
700 /* Activity Monitor Group 1 Event Type Registers */
701 #define AMEVTYPER10	p15, 0, c13, c14, 0
702 #define AMEVTYPER11	p15, 0, c13, c14, 1
703 #define AMEVTYPER12	p15, 0, c13, c14, 2
704 #define AMEVTYPER13	p15, 0, c13, c14, 3
705 #define AMEVTYPER14	p15, 0, c13, c14, 4
706 #define AMEVTYPER15	p15, 0, c13, c14, 5
707 #define AMEVTYPER16	p15, 0, c13, c14, 6
708 #define AMEVTYPER17	p15, 0, c13, c14, 7
709 #define AMEVTYPER18	p15, 0, c13, c15, 0
710 #define AMEVTYPER19	p15, 0, c13, c15, 1
711 #define AMEVTYPER1A	p15, 0, c13, c15, 2
712 #define AMEVTYPER1B	p15, 0, c13, c15, 3
713 #define AMEVTYPER1C	p15, 0, c13, c15, 4
714 #define AMEVTYPER1D	p15, 0, c13, c15, 5
715 #define AMEVTYPER1E	p15, 0, c13, c15, 6
716 #define AMEVTYPER1F	p15, 0, c13, c15, 7
717 
718 /* AMCR definitions */
719 #define AMCR_CG1RZ_BIT		(ULL(1) << 17)
720 
721 /* AMCFGR definitions */
722 #define AMCFGR_NCG_SHIFT	U(28)
723 #define AMCFGR_NCG_MASK		U(0xf)
724 #define AMCFGR_N_SHIFT		U(0)
725 #define AMCFGR_N_MASK		U(0xff)
726 
727 /* AMCGCR definitions */
728 #define AMCGCR_CG1NC_SHIFT	U(8)
729 #define AMCGCR_CG1NC_MASK	U(0xff)
730 
731 /*******************************************************************************
732  * Definitions for DynamicIQ Shared Unit registers
733  ******************************************************************************/
734 #define CLUSTERPWRDN	p15, 0, c15, c3, 6
735 
736 /* CLUSTERPWRDN register definitions */
737 #define DSU_CLUSTER_PWR_OFF	0
738 #define DSU_CLUSTER_PWR_ON	1
739 #define DSU_CLUSTER_PWR_MASK	U(1)
740 
741 #endif /* ARCH_H */
742