1 /*
2  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
3  * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef TEGRA_DEF_H
9 #define TEGRA_DEF_H
10 
11 #include <lib/utils_def.h>
12 
13 /*******************************************************************************
14  * Platform BL31 specific defines.
15  ******************************************************************************/
16 #define BL31_SIZE			U(0x40000)
17 
18 /*******************************************************************************
19  * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
20  * call as the `state-id` field in the 'power state' parameter.
21  ******************************************************************************/
22 #define PSTATE_ID_SOC_POWERDN	U(0xD)
23 
24 /*******************************************************************************
25  * Platform power states (used by PSCI framework)
26  *
27  * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
28  * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
29  ******************************************************************************/
30 #define PLAT_MAX_RET_STATE		U(1)
31 #define PLAT_MAX_OFF_STATE		(PSTATE_ID_SOC_POWERDN + U(1))
32 
33 /*******************************************************************************
34  * Chip specific page table and MMU setup constants
35  ******************************************************************************/
36 #define PLAT_PHY_ADDR_SPACE_SIZE	(ULL(1) << 35)
37 #define PLAT_VIRT_ADDR_SPACE_SIZE	(ULL(1) << 35)
38 
39 /*******************************************************************************
40  * GIC memory map
41  ******************************************************************************/
42 #define TEGRA_GICD_BASE			U(0x50041000)
43 #define TEGRA_GICC_BASE			U(0x50042000)
44 
45 /*******************************************************************************
46  * Tegra micro-seconds timer constants
47  ******************************************************************************/
48 #define TEGRA_TMRUS_BASE		U(0x60005010)
49 #define TEGRA_TMRUS_SIZE		U(0x1000)
50 
51 /*******************************************************************************
52  * Tegra Clock and Reset Controller constants
53  ******************************************************************************/
54 #define TEGRA_CAR_RESET_BASE		U(0x60006000)
55 #define TEGRA_GPU_RESET_REG_OFFSET	U(0x28C)
56 #define TEGRA_GPU_RESET_GPU_SET_OFFSET	U(0x290)
57 #define  GPU_RESET_BIT			(U(1) << 24)
58 #define  GPU_SET_BIT			(U(1) << 24)
59 
60 /*******************************************************************************
61  * Tegra Flow Controller constants
62  ******************************************************************************/
63 #define TEGRA_FLOWCTRL_BASE		U(0x60007000)
64 
65 /*******************************************************************************
66  * Tegra Secure Boot Controller constants
67  ******************************************************************************/
68 #define TEGRA_SB_BASE			U(0x6000C200)
69 
70 /*******************************************************************************
71  * Tegra Exception Vectors constants
72  ******************************************************************************/
73 #define TEGRA_EVP_BASE			U(0x6000F000)
74 
75 /*******************************************************************************
76  * Tegra Miscellaneous register constants
77  ******************************************************************************/
78 #define TEGRA_MISC_BASE			U(0x70000000)
79 #define  HARDWARE_REVISION_OFFSET	U(0x804)
80 
81 /*******************************************************************************
82  * Tegra UART controller base addresses
83  ******************************************************************************/
84 #define TEGRA_UARTA_BASE		U(0x70006000)
85 #define TEGRA_UARTB_BASE		U(0x70006040)
86 #define TEGRA_UARTC_BASE		U(0x70006200)
87 #define TEGRA_UARTD_BASE		U(0x70006300)
88 #define TEGRA_UARTE_BASE		U(0x70006400)
89 
90 /*******************************************************************************
91  * Tegra Power Mgmt Controller constants
92  ******************************************************************************/
93 #define TEGRA_PMC_BASE			U(0x7000E400)
94 
95 /*******************************************************************************
96  * Tegra Memory Controller constants
97  ******************************************************************************/
98 #define TEGRA_MC_BASE			U(0x70019000)
99 
100 /* Memory Controller Interrupt Status */
101 #define MC_INTSTATUS			0x00U
102 
103 /* TZDRAM carveout configuration registers */
104 #define MC_SECURITY_CFG0_0		U(0x70)
105 #define MC_SECURITY_CFG1_0		U(0x74)
106 #define MC_SECURITY_CFG3_0		U(0x9BC)
107 
108 /* Video Memory carveout configuration registers */
109 #define MC_VIDEO_PROTECT_BASE_HI	U(0x978)
110 #define MC_VIDEO_PROTECT_BASE_LO	U(0x648)
111 #define MC_VIDEO_PROTECT_SIZE_MB	U(0x64c)
112 #define MC_VIDEO_PROTECT_REG_CTRL	U(0x650)
113 #define MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED	U(3)
114 
115 /*******************************************************************************
116  * Tegra TZRAM constants
117  ******************************************************************************/
118 #define TEGRA_TZRAM_BASE		U(0x7C010000)
119 #define TEGRA_TZRAM_SIZE		U(0x10000)
120 
121 /*******************************************************************************
122  * Tegra DRAM memory base address
123  ******************************************************************************/
124 #define TEGRA_DRAM_BASE			ULL(0x80000000)
125 #define TEGRA_DRAM_END			ULL(0x27FFFFFFF)
126 
127 #endif /* TEGRA_DEF_H */
128