1 /* 2 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CONTEXT_H 8 #define CONTEXT_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * Constants that allow assembler code to access members of and the 'gp_regs' 14 * structure at their correct offsets. 15 ******************************************************************************/ 16 #define CTX_GPREGS_OFFSET U(0x0) 17 #define CTX_GPREG_X0 U(0x0) 18 #define CTX_GPREG_X1 U(0x8) 19 #define CTX_GPREG_X2 U(0x10) 20 #define CTX_GPREG_X3 U(0x18) 21 #define CTX_GPREG_X4 U(0x20) 22 #define CTX_GPREG_X5 U(0x28) 23 #define CTX_GPREG_X6 U(0x30) 24 #define CTX_GPREG_X7 U(0x38) 25 #define CTX_GPREG_X8 U(0x40) 26 #define CTX_GPREG_X9 U(0x48) 27 #define CTX_GPREG_X10 U(0x50) 28 #define CTX_GPREG_X11 U(0x58) 29 #define CTX_GPREG_X12 U(0x60) 30 #define CTX_GPREG_X13 U(0x68) 31 #define CTX_GPREG_X14 U(0x70) 32 #define CTX_GPREG_X15 U(0x78) 33 #define CTX_GPREG_X16 U(0x80) 34 #define CTX_GPREG_X17 U(0x88) 35 #define CTX_GPREG_X18 U(0x90) 36 #define CTX_GPREG_X19 U(0x98) 37 #define CTX_GPREG_X20 U(0xa0) 38 #define CTX_GPREG_X21 U(0xa8) 39 #define CTX_GPREG_X22 U(0xb0) 40 #define CTX_GPREG_X23 U(0xb8) 41 #define CTX_GPREG_X24 U(0xc0) 42 #define CTX_GPREG_X25 U(0xc8) 43 #define CTX_GPREG_X26 U(0xd0) 44 #define CTX_GPREG_X27 U(0xd8) 45 #define CTX_GPREG_X28 U(0xe0) 46 #define CTX_GPREG_X29 U(0xe8) 47 #define CTX_GPREG_LR U(0xf0) 48 #define CTX_GPREG_SP_EL0 U(0xf8) 49 #define CTX_GPREGS_END U(0x100) 50 51 /******************************************************************************* 52 * Constants that allow assembler code to access members of and the 'el3_state' 53 * structure at their correct offsets. Note that some of the registers are only 54 * 32-bits wide but are stored as 64-bit values for convenience 55 ******************************************************************************/ 56 #define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END) 57 #define CTX_SCR_EL3 U(0x0) 58 #define CTX_ESR_EL3 U(0x8) 59 #define CTX_RUNTIME_SP U(0x10) 60 #define CTX_SPSR_EL3 U(0x18) 61 #define CTX_ELR_EL3 U(0x20) 62 #define CTX_PMCR_EL0 U(0x28) 63 #define CTX_IS_IN_EL3 U(0x30) 64 #define CTX_EL3STATE_END U(0x40) /* Align to the next 16 byte boundary */ 65 66 /******************************************************************************* 67 * Constants that allow assembler code to access members of and the 68 * 'el1_sys_regs' structure at their correct offsets. Note that some of the 69 * registers are only 32-bits wide but are stored as 64-bit values for 70 * convenience 71 ******************************************************************************/ 72 #define CTX_EL1_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END) 73 #define CTX_SPSR_EL1 U(0x0) 74 #define CTX_ELR_EL1 U(0x8) 75 #define CTX_SCTLR_EL1 U(0x10) 76 #define CTX_TCR_EL1 U(0x18) 77 #define CTX_CPACR_EL1 U(0x20) 78 #define CTX_CSSELR_EL1 U(0x28) 79 #define CTX_SP_EL1 U(0x30) 80 #define CTX_ESR_EL1 U(0x38) 81 #define CTX_TTBR0_EL1 U(0x40) 82 #define CTX_TTBR1_EL1 U(0x48) 83 #define CTX_MAIR_EL1 U(0x50) 84 #define CTX_AMAIR_EL1 U(0x58) 85 #define CTX_ACTLR_EL1 U(0x60) 86 #define CTX_TPIDR_EL1 U(0x68) 87 #define CTX_TPIDR_EL0 U(0x70) 88 #define CTX_TPIDRRO_EL0 U(0x78) 89 #define CTX_PAR_EL1 U(0x80) 90 #define CTX_FAR_EL1 U(0x88) 91 #define CTX_AFSR0_EL1 U(0x90) 92 #define CTX_AFSR1_EL1 U(0x98) 93 #define CTX_CONTEXTIDR_EL1 U(0xa0) 94 #define CTX_VBAR_EL1 U(0xa8) 95 96 /* 97 * If the platform is AArch64-only, there is no need to save and restore these 98 * AArch32 registers. 99 */ 100 #if CTX_INCLUDE_AARCH32_REGS 101 #define CTX_SPSR_ABT U(0xb0) /* Align to the next 16 byte boundary */ 102 #define CTX_SPSR_UND U(0xb8) 103 #define CTX_SPSR_IRQ U(0xc0) 104 #define CTX_SPSR_FIQ U(0xc8) 105 #define CTX_DACR32_EL2 U(0xd0) 106 #define CTX_IFSR32_EL2 U(0xd8) 107 #define CTX_AARCH32_END U(0xe0) /* Align to the next 16 byte boundary */ 108 #else 109 #define CTX_AARCH32_END U(0xb0) /* Align to the next 16 byte boundary */ 110 #endif /* CTX_INCLUDE_AARCH32_REGS */ 111 112 /* 113 * If the timer registers aren't saved and restored, we don't have to reserve 114 * space for them in the context 115 */ 116 #if NS_TIMER_SWITCH 117 #define CTX_CNTP_CTL_EL0 (CTX_AARCH32_END + U(0x0)) 118 #define CTX_CNTP_CVAL_EL0 (CTX_AARCH32_END + U(0x8)) 119 #define CTX_CNTV_CTL_EL0 (CTX_AARCH32_END + U(0x10)) 120 #define CTX_CNTV_CVAL_EL0 (CTX_AARCH32_END + U(0x18)) 121 #define CTX_CNTKCTL_EL1 (CTX_AARCH32_END + U(0x20)) 122 #define CTX_TIMER_SYSREGS_END (CTX_AARCH32_END + U(0x30)) /* Align to the next 16 byte boundary */ 123 #else 124 #define CTX_TIMER_SYSREGS_END CTX_AARCH32_END 125 #endif /* NS_TIMER_SWITCH */ 126 127 #if CTX_INCLUDE_MTE_REGS 128 #define CTX_TFSRE0_EL1 (CTX_TIMER_SYSREGS_END + U(0x0)) 129 #define CTX_TFSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x8)) 130 #define CTX_RGSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x10)) 131 #define CTX_GCR_EL1 (CTX_TIMER_SYSREGS_END + U(0x18)) 132 133 /* Align to the next 16 byte boundary */ 134 #define CTX_MTE_REGS_END (CTX_TIMER_SYSREGS_END + U(0x20)) 135 #else 136 #define CTX_MTE_REGS_END CTX_TIMER_SYSREGS_END 137 #endif /* CTX_INCLUDE_MTE_REGS */ 138 139 /* 140 * End of system registers. 141 */ 142 #define CTX_EL1_SYSREGS_END CTX_MTE_REGS_END 143 144 /* 145 * EL2 register set 146 */ 147 148 #if CTX_INCLUDE_EL2_REGS 149 /* For later discussion 150 * ICH_AP0R<n>_EL2 151 * ICH_AP1R<n>_EL2 152 * AMEVCNTVOFF0<n>_EL2 153 * AMEVCNTVOFF1<n>_EL2 154 * ICH_LR<n>_EL2 155 */ 156 #define CTX_EL2_SYSREGS_OFFSET (CTX_EL1_SYSREGS_OFFSET + CTX_EL1_SYSREGS_END) 157 158 #define CTX_ACTLR_EL2 U(0x0) 159 #define CTX_AFSR0_EL2 U(0x8) 160 #define CTX_AFSR1_EL2 U(0x10) 161 #define CTX_AMAIR_EL2 U(0x18) 162 #define CTX_CNTHCTL_EL2 U(0x20) 163 #define CTX_CNTVOFF_EL2 U(0x28) 164 #define CTX_CPTR_EL2 U(0x30) 165 #define CTX_DBGVCR32_EL2 U(0x38) 166 #define CTX_ELR_EL2 U(0x40) 167 #define CTX_ESR_EL2 U(0x48) 168 #define CTX_FAR_EL2 U(0x50) 169 #define CTX_HACR_EL2 U(0x58) 170 #define CTX_HCR_EL2 U(0x60) 171 #define CTX_HPFAR_EL2 U(0x68) 172 #define CTX_HSTR_EL2 U(0x70) 173 #define CTX_ICC_SRE_EL2 U(0x78) 174 #define CTX_ICH_HCR_EL2 U(0x80) 175 #define CTX_ICH_VMCR_EL2 U(0x88) 176 #define CTX_MAIR_EL2 U(0x90) 177 #define CTX_MDCR_EL2 U(0x98) 178 #define CTX_PMSCR_EL2 U(0xa0) 179 #define CTX_SCTLR_EL2 U(0xa8) 180 #define CTX_SPSR_EL2 U(0xb0) 181 #define CTX_SP_EL2 U(0xb8) 182 #define CTX_TCR_EL2 U(0xc0) 183 #define CTX_TPIDR_EL2 U(0xc8) 184 #define CTX_TTBR0_EL2 U(0xd0) 185 #define CTX_VBAR_EL2 U(0xd8) 186 #define CTX_VMPIDR_EL2 U(0xe0) 187 #define CTX_VPIDR_EL2 U(0xe8) 188 #define CTX_VTCR_EL2 U(0xf0) 189 #define CTX_VTTBR_EL2 U(0xf8) 190 191 // Only if MTE registers in use 192 #define CTX_TFSR_EL2 U(0x100) 193 194 // Only if ENABLE_MPAM_FOR_LOWER_ELS==1 195 #define CTX_MPAM2_EL2 U(0x108) 196 #define CTX_MPAMHCR_EL2 U(0x110) 197 #define CTX_MPAMVPM0_EL2 U(0x118) 198 #define CTX_MPAMVPM1_EL2 U(0x120) 199 #define CTX_MPAMVPM2_EL2 U(0x128) 200 #define CTX_MPAMVPM3_EL2 U(0x130) 201 #define CTX_MPAMVPM4_EL2 U(0x138) 202 #define CTX_MPAMVPM5_EL2 U(0x140) 203 #define CTX_MPAMVPM6_EL2 U(0x148) 204 #define CTX_MPAMVPM7_EL2 U(0x150) 205 #define CTX_MPAMVPMV_EL2 U(0x158) 206 207 // Starting with Armv8.6 208 #define CTX_HAFGRTR_EL2 U(0x160) 209 #define CTX_HDFGRTR_EL2 U(0x168) 210 #define CTX_HDFGWTR_EL2 U(0x170) 211 #define CTX_HFGITR_EL2 U(0x178) 212 #define CTX_HFGRTR_EL2 U(0x180) 213 #define CTX_HFGWTR_EL2 U(0x188) 214 #define CTX_CNTPOFF_EL2 U(0x190) 215 216 // Starting with Armv8.4 217 #define CTX_CONTEXTIDR_EL2 U(0x198) 218 #define CTX_SDER32_EL2 U(0x1a0) 219 #define CTX_TTBR1_EL2 U(0x1a8) 220 #define CTX_VDISR_EL2 U(0x1b0) 221 #define CTX_VNCR_EL2 U(0x1b8) 222 #define CTX_VSESR_EL2 U(0x1c0) 223 #define CTX_VSTCR_EL2 U(0x1c8) 224 #define CTX_VSTTBR_EL2 U(0x1d0) 225 #define CTX_TRFCR_EL2 U(0x1d8) 226 227 // Starting with Armv8.5 228 #define CTX_SCXTNUM_EL2 U(0x1e0) 229 /* Align to the next 16 byte boundary */ 230 #define CTX_EL2_SYSREGS_END U(0x1f0) 231 232 #endif /* CTX_INCLUDE_EL2_REGS */ 233 234 /******************************************************************************* 235 * Constants that allow assembler code to access members of and the 'fp_regs' 236 * structure at their correct offsets. 237 ******************************************************************************/ 238 #if CTX_INCLUDE_EL2_REGS 239 # define CTX_FPREGS_OFFSET (CTX_EL2_SYSREGS_OFFSET + CTX_EL2_SYSREGS_END) 240 #else 241 # define CTX_FPREGS_OFFSET (CTX_EL1_SYSREGS_OFFSET + CTX_EL1_SYSREGS_END) 242 #endif 243 #if CTX_INCLUDE_FPREGS 244 #define CTX_FP_Q0 U(0x0) 245 #define CTX_FP_Q1 U(0x10) 246 #define CTX_FP_Q2 U(0x20) 247 #define CTX_FP_Q3 U(0x30) 248 #define CTX_FP_Q4 U(0x40) 249 #define CTX_FP_Q5 U(0x50) 250 #define CTX_FP_Q6 U(0x60) 251 #define CTX_FP_Q7 U(0x70) 252 #define CTX_FP_Q8 U(0x80) 253 #define CTX_FP_Q9 U(0x90) 254 #define CTX_FP_Q10 U(0xa0) 255 #define CTX_FP_Q11 U(0xb0) 256 #define CTX_FP_Q12 U(0xc0) 257 #define CTX_FP_Q13 U(0xd0) 258 #define CTX_FP_Q14 U(0xe0) 259 #define CTX_FP_Q15 U(0xf0) 260 #define CTX_FP_Q16 U(0x100) 261 #define CTX_FP_Q17 U(0x110) 262 #define CTX_FP_Q18 U(0x120) 263 #define CTX_FP_Q19 U(0x130) 264 #define CTX_FP_Q20 U(0x140) 265 #define CTX_FP_Q21 U(0x150) 266 #define CTX_FP_Q22 U(0x160) 267 #define CTX_FP_Q23 U(0x170) 268 #define CTX_FP_Q24 U(0x180) 269 #define CTX_FP_Q25 U(0x190) 270 #define CTX_FP_Q26 U(0x1a0) 271 #define CTX_FP_Q27 U(0x1b0) 272 #define CTX_FP_Q28 U(0x1c0) 273 #define CTX_FP_Q29 U(0x1d0) 274 #define CTX_FP_Q30 U(0x1e0) 275 #define CTX_FP_Q31 U(0x1f0) 276 #define CTX_FP_FPSR U(0x200) 277 #define CTX_FP_FPCR U(0x208) 278 #if CTX_INCLUDE_AARCH32_REGS 279 #define CTX_FP_FPEXC32_EL2 U(0x210) 280 #define CTX_FPREGS_END U(0x220) /* Align to the next 16 byte boundary */ 281 #else 282 #define CTX_FPREGS_END U(0x210) /* Align to the next 16 byte boundary */ 283 #endif 284 #else 285 #define CTX_FPREGS_END U(0) 286 #endif 287 288 /******************************************************************************* 289 * Registers related to CVE-2018-3639 290 ******************************************************************************/ 291 #define CTX_CVE_2018_3639_OFFSET (CTX_FPREGS_OFFSET + CTX_FPREGS_END) 292 #define CTX_CVE_2018_3639_DISABLE U(0) 293 #define CTX_CVE_2018_3639_END U(0x10) /* Align to the next 16 byte boundary */ 294 295 /******************************************************************************* 296 * Registers related to ARMv8.3-PAuth. 297 ******************************************************************************/ 298 #define CTX_PAUTH_REGS_OFFSET (CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_END) 299 #if CTX_INCLUDE_PAUTH_REGS 300 #define CTX_PACIAKEY_LO U(0x0) 301 #define CTX_PACIAKEY_HI U(0x8) 302 #define CTX_PACIBKEY_LO U(0x10) 303 #define CTX_PACIBKEY_HI U(0x18) 304 #define CTX_PACDAKEY_LO U(0x20) 305 #define CTX_PACDAKEY_HI U(0x28) 306 #define CTX_PACDBKEY_LO U(0x30) 307 #define CTX_PACDBKEY_HI U(0x38) 308 #define CTX_PACGAKEY_LO U(0x40) 309 #define CTX_PACGAKEY_HI U(0x48) 310 #define CTX_PAUTH_REGS_END U(0x50) /* Align to the next 16 byte boundary */ 311 #else 312 #define CTX_PAUTH_REGS_END U(0) 313 #endif /* CTX_INCLUDE_PAUTH_REGS */ 314 315 #ifndef __ASSEMBLER__ 316 317 #include <stdint.h> 318 319 #include <lib/cassert.h> 320 321 /* 322 * Common constants to help define the 'cpu_context' structure and its 323 * members below. 324 */ 325 #define DWORD_SHIFT U(3) 326 #define DEFINE_REG_STRUCT(name, num_regs) \ 327 typedef struct name { \ 328 uint64_t ctx_regs[num_regs]; \ 329 } __aligned(16) name##_t 330 331 /* Constants to determine the size of individual context structures */ 332 #define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT) 333 #define CTX_EL1_SYSREGS_ALL (CTX_EL1_SYSREGS_END >> DWORD_SHIFT) 334 #if CTX_INCLUDE_EL2_REGS 335 # define CTX_EL2_SYSREGS_ALL (CTX_EL2_SYSREGS_END >> DWORD_SHIFT) 336 #endif 337 #if CTX_INCLUDE_FPREGS 338 # define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT) 339 #endif 340 #define CTX_EL3STATE_ALL (CTX_EL3STATE_END >> DWORD_SHIFT) 341 #define CTX_CVE_2018_3639_ALL (CTX_CVE_2018_3639_END >> DWORD_SHIFT) 342 #if CTX_INCLUDE_PAUTH_REGS 343 # define CTX_PAUTH_REGS_ALL (CTX_PAUTH_REGS_END >> DWORD_SHIFT) 344 #endif 345 346 /* 347 * AArch64 general purpose register context structure. Usually x0-x18, 348 * lr are saved as the compiler is expected to preserve the remaining 349 * callee saved registers if used by the C runtime and the assembler 350 * does not touch the remaining. But in case of world switch during 351 * exception handling, we need to save the callee registers too. 352 */ 353 DEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL); 354 355 /* 356 * AArch64 EL1 system register context structure for preserving the 357 * architectural state during world switches. 358 */ 359 DEFINE_REG_STRUCT(el1_sysregs, CTX_EL1_SYSREGS_ALL); 360 361 362 /* 363 * AArch64 EL2 system register context structure for preserving the 364 * architectural state during world switches. 365 */ 366 #if CTX_INCLUDE_EL2_REGS 367 DEFINE_REG_STRUCT(el2_sysregs, CTX_EL2_SYSREGS_ALL); 368 #endif 369 370 /* 371 * AArch64 floating point register context structure for preserving 372 * the floating point state during switches from one security state to 373 * another. 374 */ 375 #if CTX_INCLUDE_FPREGS 376 DEFINE_REG_STRUCT(fp_regs, CTX_FPREG_ALL); 377 #endif 378 379 /* 380 * Miscellaneous registers used by EL3 firmware to maintain its state 381 * across exception entries and exits 382 */ 383 DEFINE_REG_STRUCT(el3_state, CTX_EL3STATE_ALL); 384 385 /* Function pointer used by CVE-2018-3639 dynamic mitigation */ 386 DEFINE_REG_STRUCT(cve_2018_3639, CTX_CVE_2018_3639_ALL); 387 388 /* Registers associated to ARMv8.3-PAuth */ 389 #if CTX_INCLUDE_PAUTH_REGS 390 DEFINE_REG_STRUCT(pauth, CTX_PAUTH_REGS_ALL); 391 #endif 392 393 /* 394 * Macros to access members of any of the above structures using their 395 * offsets 396 */ 397 #define read_ctx_reg(ctx, offset) ((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) 398 #define write_ctx_reg(ctx, offset, val) (((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) \ 399 = (uint64_t) (val)) 400 401 /* 402 * Top-level context structure which is used by EL3 firmware to 403 * preserve the state of a core at EL1 in one of the two security 404 * states and save enough EL3 meta data to be able to return to that 405 * EL and security state. The context management library will be used 406 * to ensure that SP_EL3 always points to an instance of this 407 * structure at exception entry and exit. Each instance will 408 * correspond to either the secure or the non-secure state. 409 */ 410 typedef struct cpu_context { 411 gp_regs_t gpregs_ctx; 412 el3_state_t el3state_ctx; 413 el1_sysregs_t el1_sysregs_ctx; 414 #if CTX_INCLUDE_EL2_REGS 415 el2_sysregs_t el2_sysregs_ctx; 416 #endif 417 #if CTX_INCLUDE_FPREGS 418 fp_regs_t fpregs_ctx; 419 #endif 420 cve_2018_3639_t cve_2018_3639_ctx; 421 #if CTX_INCLUDE_PAUTH_REGS 422 pauth_t pauth_ctx; 423 #endif 424 } cpu_context_t; 425 426 /* Macros to access members of the 'cpu_context_t' structure */ 427 #define get_el3state_ctx(h) (&((cpu_context_t *) h)->el3state_ctx) 428 #if CTX_INCLUDE_FPREGS 429 # define get_fpregs_ctx(h) (&((cpu_context_t *) h)->fpregs_ctx) 430 #endif 431 #define get_el1_sysregs_ctx(h) (&((cpu_context_t *) h)->el1_sysregs_ctx) 432 #if CTX_INCLUDE_EL2_REGS 433 # define get_el2_sysregs_ctx(h) (&((cpu_context_t *) h)->el2_sysregs_ctx) 434 #endif 435 #define get_gpregs_ctx(h) (&((cpu_context_t *) h)->gpregs_ctx) 436 #define get_cve_2018_3639_ctx(h) (&((cpu_context_t *) h)->cve_2018_3639_ctx) 437 #if CTX_INCLUDE_PAUTH_REGS 438 # define get_pauth_ctx(h) (&((cpu_context_t *) h)->pauth_ctx) 439 #endif 440 441 /* 442 * Compile time assertions related to the 'cpu_context' structure to 443 * ensure that the assembler and the compiler view of the offsets of 444 * the structure members is the same. 445 */ 446 CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), \ 447 assert_core_context_gp_offset_mismatch); 448 CASSERT(CTX_EL1_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, el1_sysregs_ctx), \ 449 assert_core_context_el1_sys_offset_mismatch); 450 #if CTX_INCLUDE_EL2_REGS 451 CASSERT(CTX_EL2_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, el2_sysregs_ctx), \ 452 assert_core_context_el2_sys_offset_mismatch); 453 #endif 454 #if CTX_INCLUDE_FPREGS 455 CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx), \ 456 assert_core_context_fp_offset_mismatch); 457 #endif 458 CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx), \ 459 assert_core_context_el3state_offset_mismatch); 460 CASSERT(CTX_CVE_2018_3639_OFFSET == __builtin_offsetof(cpu_context_t, cve_2018_3639_ctx), \ 461 assert_core_context_cve_2018_3639_offset_mismatch); 462 #if CTX_INCLUDE_PAUTH_REGS 463 CASSERT(CTX_PAUTH_REGS_OFFSET == __builtin_offsetof(cpu_context_t, pauth_ctx), \ 464 assert_core_context_pauth_offset_mismatch); 465 #endif 466 467 /* 468 * Helper macro to set the general purpose registers that correspond to 469 * parameters in an aapcs_64 call i.e. x0-x7 470 */ 471 #define set_aapcs_args0(ctx, x0) do { \ 472 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \ 473 } while (0) 474 #define set_aapcs_args1(ctx, x0, x1) do { \ 475 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, x1); \ 476 set_aapcs_args0(ctx, x0); \ 477 } while (0) 478 #define set_aapcs_args2(ctx, x0, x1, x2) do { \ 479 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \ 480 set_aapcs_args1(ctx, x0, x1); \ 481 } while (0) 482 #define set_aapcs_args3(ctx, x0, x1, x2, x3) do { \ 483 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, x3); \ 484 set_aapcs_args2(ctx, x0, x1, x2); \ 485 } while (0) 486 #define set_aapcs_args4(ctx, x0, x1, x2, x3, x4) do { \ 487 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X4, x4); \ 488 set_aapcs_args3(ctx, x0, x1, x2, x3); \ 489 } while (0) 490 #define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \ 491 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \ 492 set_aapcs_args4(ctx, x0, x1, x2, x3, x4); \ 493 } while (0) 494 #define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \ 495 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X6, x6); \ 496 set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \ 497 } while (0) 498 #define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \ 499 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X7, x7); \ 500 set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \ 501 } while (0) 502 503 /******************************************************************************* 504 * Function prototypes 505 ******************************************************************************/ 506 void el1_sysregs_context_save(el1_sysregs_t *regs); 507 void el1_sysregs_context_restore(el1_sysregs_t *regs); 508 509 #if CTX_INCLUDE_EL2_REGS 510 void el2_sysregs_context_save(el2_sysregs_t *regs); 511 void el2_sysregs_context_restore(el2_sysregs_t *regs); 512 #endif 513 514 #if CTX_INCLUDE_FPREGS 515 void fpregs_context_save(fp_regs_t *regs); 516 void fpregs_context_restore(fp_regs_t *regs); 517 #endif 518 519 #endif /* __ASSEMBLER__ */ 520 521 #endif /* CONTEXT_H */ 522