1 /*
2 * Copyright 2021 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8 #include <errno.h>
9 #include <stdbool.h>
10 #include <stdint.h>
11 #include <stdio.h>
12 #include <stdlib.h>
13
14 #include <common/debug.h>
15 #include <ddr.h>
16 #include <lib/utils.h>
17
cal_cwl(const unsigned long clk)18 static inline unsigned int cal_cwl(const unsigned long clk)
19 {
20 const unsigned int mclk_ps = get_memory_clk_ps(clk);
21
22 return mclk_ps >= 1250U ? 9U :
23 (mclk_ps >= 1070U ? 10U :
24 (mclk_ps >= 935U ? 11U :
25 (mclk_ps >= 833U ? 12U :
26 (mclk_ps >= 750U ? 14U :
27 (mclk_ps >= 625U ? 16U : 18U)))));
28 }
29
cal_csn_config(int i,struct ddr_cfg_regs * regs,const struct memctl_opt * popts,const struct dimm_params * pdimm)30 static void cal_csn_config(int i,
31 struct ddr_cfg_regs *regs,
32 const struct memctl_opt *popts,
33 const struct dimm_params *pdimm)
34 {
35 unsigned int intlv_en = 0U;
36 unsigned int intlv_ctl = 0U;
37 const unsigned int cs_n_en = 1U;
38 const unsigned int ap_n_en = popts->cs_odt[i].auto_precharge;
39 const unsigned int odt_rd_cfg = popts->cs_odt[i].odt_rd_cfg;
40 const unsigned int odt_wr_cfg = popts->cs_odt[i].odt_wr_cfg;
41 const unsigned int ba_bits_cs_n = pdimm->bank_addr_bits;
42 const unsigned int row_bits_cs_n = pdimm->n_row_addr - 12U;
43 const unsigned int col_bits_cs_n = pdimm->n_col_addr - 8U;
44 const unsigned int bg_bits_cs_n = pdimm->bank_group_bits;
45
46 if (i == 0) {
47 /* These fields only available in CS0_CONFIG */
48 if (popts->ctlr_intlv != 0) {
49 switch (popts->ctlr_intlv_mode) {
50 case DDR_256B_INTLV:
51 intlv_en = popts->ctlr_intlv;
52 intlv_ctl = popts->ctlr_intlv_mode;
53 break;
54 default:
55 break;
56 }
57 }
58 }
59 regs->cs[i].config = ((cs_n_en & 0x1) << 31) |
60 ((intlv_en & 0x3) << 29) |
61 ((intlv_ctl & 0xf) << 24) |
62 ((ap_n_en & 0x1) << 23) |
63 ((odt_rd_cfg & 0x7) << 20) |
64 ((odt_wr_cfg & 0x7) << 16) |
65 ((ba_bits_cs_n & 0x3) << 14) |
66 ((row_bits_cs_n & 0x7) << 8) |
67 ((bg_bits_cs_n & 0x3) << 4) |
68 ((col_bits_cs_n & 0x7) << 0);
69 debug("cs%d\n", i);
70 debug(" _config = 0x%x\n", regs->cs[i].config);
71 }
72
avoid_odt_overlap(const struct ddr_conf * conf,const struct dimm_params * pdimm)73 static inline int avoid_odt_overlap(const struct ddr_conf *conf,
74 const struct dimm_params *pdimm)
75 {
76 if ((conf->cs_in_use == 0xf) != 0) {
77 return 2;
78 }
79
80 #if DDRC_NUM_DIMM >= 2
81 if (conf->dimm_in_use[0] != 0 && conf->dimm_in_use[1] != 0) {
82 return 1;
83 }
84 #endif
85 return 0;
86 }
87
88 /* Requires rcw2 set first */
cal_timing_cfg(const unsigned long clk,struct ddr_cfg_regs * regs,const struct memctl_opt * popts,const struct dimm_params * pdimm,const struct ddr_conf * conf,unsigned int cas_latency,unsigned int additive_latency)89 static void cal_timing_cfg(const unsigned long clk,
90 struct ddr_cfg_regs *regs,
91 const struct memctl_opt *popts,
92 const struct dimm_params *pdimm,
93 const struct ddr_conf *conf,
94 unsigned int cas_latency,
95 unsigned int additive_latency)
96 {
97 const unsigned int mclk_ps = get_memory_clk_ps(clk);
98 /* tXP=max(4nCK, 6ns) */
99 const int txp = max((int)mclk_ps * 4, 6000);
100 /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */
101 static const int wrrec_table[] = {
102 10, 10, 10, 10, 10,
103 10, 10, 10, 10, 10,
104 12, 12, 14, 14, 16,
105 16, 18, 18, 20, 20,
106 24, 24, 24, 24,
107 };
108 int trwt_mclk = (clk / 1000000 > 1900) ? 3 : 2;
109 int twrt_mclk;
110 int trrt_mclk;
111 int twwt_mclk;
112 const int act_pd_exit_mclk = picos_to_mclk(clk, txp);
113 const int pre_pd_exit_mclk = act_pd_exit_mclk;
114 const int taxpd_mclk = 0;
115 /*
116 * MRS_CYC = max(tMRD, tMOD)
117 * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
118 */
119 const int tmrd_mclk = max(24U, picos_to_mclk(clk, 15000));
120 const int pretoact_mclk = picos_to_mclk(clk, pdimm->trp_ps);
121 const int acttopre_mclk = picos_to_mclk(clk, pdimm->tras_ps);
122 const int acttorw_mclk = picos_to_mclk(clk, pdimm->trcd_ps);
123 const int caslat_ctrl = (cas_latency - 1) << 1;
124 const int trfc1_min = pdimm->die_density >= 0x3 ? 16000 :
125 (pdimm->die_density == 0x4 ? 26000 :
126 (pdimm->die_density == 0x5 ? 35000 :
127 55000));
128 const int refrec_ctrl = picos_to_mclk(clk,
129 pdimm->trfc1_ps) - 8;
130 int wrrec_mclk = picos_to_mclk(clk, pdimm->twr_ps);
131 const int acttoact_mclk = max(picos_to_mclk(clk,
132 pdimm->trrds_ps),
133 4U);
134 int wrtord_mclk = max(2U, picos_to_mclk(clk, 2500));
135 const unsigned int cpo = 0U;
136 const int wr_lat = cal_cwl(clk);
137 int rd_to_pre = picos_to_mclk(clk, 7500);
138 const int wr_data_delay = popts->wr_data_delay;
139 const int cke_pls = max(3U, picos_to_mclk(clk, 5000));
140 #ifdef ERRATA_DDR_A050450
141 const unsigned short four_act = ((popts->twot_en == 0) &&
142 (popts->threet_en == 0) &&
143 (popts->tfaw_ps % 2 == 0)) ?
144 (picos_to_mclk(clk, popts->tfaw_ps) + 1) :
145 picos_to_mclk(clk, popts->tfaw_ps);
146 #else
147 const unsigned short four_act = picos_to_mclk(clk,
148 popts->tfaw_ps);
149 #endif
150 const unsigned int cntl_adj = 0U;
151 const unsigned int ext_pretoact = picos_to_mclk(clk,
152 pdimm->trp_ps) >> 4U;
153 const unsigned int ext_acttopre = picos_to_mclk(clk,
154 pdimm->tras_ps) >> 4U;
155 const unsigned int ext_acttorw = picos_to_mclk(clk,
156 pdimm->trcd_ps) >> 4U;
157 const unsigned int ext_caslat = (2U * cas_latency - 1U) >> 4U;
158 const unsigned int ext_add_lat = additive_latency >> 4U;
159 const unsigned int ext_refrec = (picos_to_mclk(clk,
160 pdimm->trfc1_ps) - 8U) >> 4U;
161 const unsigned int ext_wrrec = (picos_to_mclk(clk, pdimm->twr_ps) +
162 (popts->otf_burst_chop_en ? 2U : 0U)) >> 4U;
163 const unsigned int rwt_same_cs = 0U;
164 const unsigned int wrt_same_cs = 0U;
165 const unsigned int rrt_same_cs = popts->burst_length == DDR_BL8 ? 0U : 2U;
166 const unsigned int wwt_same_cs = popts->burst_length == DDR_BL8 ? 0U : 2U;
167 const unsigned int dll_lock = 2U;
168 unsigned int rodt_on = 0U;
169 const unsigned int rodt_off = 4U;
170 const unsigned int wodt_on = 1U;
171 const unsigned int wodt_off = 4U;
172 const unsigned int hs_caslat = 0U;
173 const unsigned int hs_wrlat = 0U;
174 const unsigned int hs_wrrec = 0U;
175 const unsigned int hs_clkadj = 0U;
176 const unsigned int hs_wrlvl_start = 0U;
177 const unsigned int txpr = max(5U,
178 picos_to_mclk(clk,
179 pdimm->trfc1_ps + 10000U));
180 const unsigned int tcksre = max(5U, picos_to_mclk(clk, 10000U));
181 const unsigned int tcksrx = max(5U, picos_to_mclk(clk, 10000U));
182 const unsigned int cs_to_cmd = 0U;
183 const unsigned int cke_rst = txpr <= 200U ? 0U :
184 (txpr <= 256U ? 1U :
185 (txpr <= 512U ? 2U : 3U));
186 const unsigned int cksre = tcksre <= 19U ? tcksre - 5U : 15U;
187 const unsigned int cksrx = tcksrx <= 19U ? tcksrx - 5U : 15U;
188 unsigned int par_lat = 0U;
189 const int tccdl = max(5U, picos_to_mclk(clk, pdimm->tccdl_ps));
190 int rwt_bg = cas_latency + 2 + 4 - wr_lat;
191 int wrt_bg = wr_lat + 4 + 1 - cas_latency;
192 const int rrt_bg = popts->burst_length == DDR_BL8 ?
193 tccdl - 4 : tccdl - 2;
194 const int wwt_bg = popts->burst_length == DDR_BL8 ?
195 tccdl - 4 : tccdl - 2;
196 const unsigned int acttoact_bg = picos_to_mclk(clk, pdimm->trrdl_ps);
197 const unsigned int wrtord_bg = max(4U, picos_to_mclk(clk, 7500)) +
198 (popts->otf_burst_chop_en ? 2 : 0);
199 const unsigned int pre_all_rec = 0;
200 const unsigned int refrec_cid_mclk = pdimm->package_3ds ?
201 picos_to_mclk(clk, pdimm->trfc_slr_ps) : 0;
202 const unsigned int acttoact_cid_mclk = pdimm->package_3ds ? 4U : 0;
203
204
205 /* for two dual-rank DIMMs to avoid ODT overlap */
206 if (avoid_odt_overlap(conf, pdimm) == 2) {
207 twrt_mclk = 2;
208 twwt_mclk = 2;
209 trrt_mclk = 2;
210 } else {
211 twrt_mclk = 1;
212 twwt_mclk = 1;
213 trrt_mclk = 0;
214 }
215
216 if (popts->trwt_override != 0) {
217 trwt_mclk = popts->trwt;
218 if (popts->twrt != 0) {
219 twrt_mclk = popts->twrt;
220 }
221 if (popts->trrt != 0) {
222 trrt_mclk = popts->trrt;
223 }
224 if (popts->twwt != 0) {
225 twwt_mclk = popts->twwt;
226 }
227 }
228 regs->timing_cfg[0] = (((trwt_mclk & 0x3) << 30) |
229 ((twrt_mclk & 0x3) << 28) |
230 ((trrt_mclk & 0x3) << 26) |
231 ((twwt_mclk & 0x3) << 24) |
232 ((act_pd_exit_mclk & 0xf) << 20) |
233 ((pre_pd_exit_mclk & 0xF) << 16) |
234 ((taxpd_mclk & 0xf) << 8) |
235 ((tmrd_mclk & 0x1f) << 0));
236 debug("timing_cfg[0] = 0x%x\n", regs->timing_cfg[0]);
237
238 if ((wrrec_mclk < 1) || (wrrec_mclk > 24)) {
239 ERROR("WRREC doesn't support clock %d\n", wrrec_mclk);
240 } else {
241 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
242 }
243
244 if (popts->otf_burst_chop_en != 0) {
245 wrrec_mclk += 2;
246 wrtord_mclk += 2;
247 }
248
249 if (pdimm->trfc1_ps < trfc1_min) {
250 ERROR("trfc1_ps (%d) < %d\n", pdimm->trfc1_ps, trfc1_min);
251 }
252
253 regs->timing_cfg[1] = (((pretoact_mclk & 0x0F) << 28) |
254 ((acttopre_mclk & 0x0F) << 24) |
255 ((acttorw_mclk & 0xF) << 20) |
256 ((caslat_ctrl & 0xF) << 16) |
257 ((refrec_ctrl & 0xF) << 12) |
258 ((wrrec_mclk & 0x0F) << 8) |
259 ((acttoact_mclk & 0x0F) << 4) |
260 ((wrtord_mclk & 0x0F) << 0));
261 debug("timing_cfg[1] = 0x%x\n", regs->timing_cfg[1]);
262
263 if (rd_to_pre < 4) {
264 rd_to_pre = 4;
265 }
266 if (popts->otf_burst_chop_en) {
267 rd_to_pre += 2;
268 }
269
270 regs->timing_cfg[2] = (((additive_latency & 0xf) << 28) |
271 ((cpo & 0x1f) << 23) |
272 ((wr_lat & 0xf) << 19) |
273 (((wr_lat & 0x10) >> 4) << 18) |
274 ((rd_to_pre & 0xf) << 13) |
275 ((wr_data_delay & 0xf) << 9) |
276 ((cke_pls & 0x7) << 6) |
277 ((four_act & 0x3f) << 0));
278 debug("timing_cfg[2] = 0x%x\n", regs->timing_cfg[2]);
279
280 regs->timing_cfg[3] = (((ext_pretoact & 0x1) << 28) |
281 ((ext_acttopre & 0x3) << 24) |
282 ((ext_acttorw & 0x1) << 22) |
283 ((ext_refrec & 0x3F) << 16) |
284 ((ext_caslat & 0x3) << 12) |
285 ((ext_add_lat & 0x1) << 10) |
286 ((ext_wrrec & 0x1) << 8) |
287 ((cntl_adj & 0x7) << 0));
288 debug("timing_cfg[3] = 0x%x\n", regs->timing_cfg[3]);
289
290 regs->timing_cfg[4] = (((rwt_same_cs & 0xf) << 28) |
291 ((wrt_same_cs & 0xf) << 24) |
292 ((rrt_same_cs & 0xf) << 20) |
293 ((wwt_same_cs & 0xf) << 16) |
294 ((trwt_mclk & 0xc) << 12) |
295 ((twrt_mclk & 0x4) << 10) |
296 ((trrt_mclk & 0x4) << 8) |
297 ((twwt_mclk & 0x4) << 6) |
298 (dll_lock & 0x3));
299 debug("timing_cfg[4] = 0x%x\n", regs->timing_cfg[4]);
300
301 /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
302 if (cas_latency >= wr_lat) {
303 rodt_on = cas_latency - wr_lat + 1;
304 }
305
306 regs->timing_cfg[5] = (((rodt_on & 0x1f) << 24) |
307 ((rodt_off & 0x7) << 20) |
308 ((wodt_on & 0x1f) << 12) |
309 (wodt_off & 0x7) << 8);
310 debug("timing_cfg[5] = 0x%x\n", regs->timing_cfg[5]);
311
312 regs->timing_cfg[6] = (((hs_caslat & 0x1f) << 24) |
313 ((hs_wrlat & 0x1f) << 19) |
314 ((hs_wrrec & 0x1f) << 12) |
315 ((hs_clkadj & 0x1f) << 6) |
316 ((hs_wrlvl_start & 0x1f) << 0));
317 debug("timing_cfg[6] = 0x%x\n", regs->timing_cfg[6]);
318
319 if (popts->ap_en != 0) {
320 par_lat = (regs->sdram_rcw[1] & 0xf) + 1;
321 debug("PAR_LAT = 0x%x\n", par_lat);
322 }
323
324 regs->timing_cfg[7] = (((cke_rst & 0x3) << 28) |
325 ((cksre & 0xf) << 24) |
326 ((cksrx & 0xf) << 20) |
327 ((par_lat & 0xf) << 16) |
328 ((cs_to_cmd & 0xf) << 4));
329 debug("timing_cfg[7] = 0x%x\n", regs->timing_cfg[7]);
330
331 if (rwt_bg < tccdl) {
332 rwt_bg = tccdl - rwt_bg;
333 } else {
334 rwt_bg = 0;
335 }
336 if (wrt_bg < tccdl) {
337 wrt_bg = tccdl - wrt_bg;
338 } else {
339 wrt_bg = 0;
340 }
341 regs->timing_cfg[8] = (((rwt_bg & 0xf) << 28) |
342 ((wrt_bg & 0xf) << 24) |
343 ((rrt_bg & 0xf) << 20) |
344 ((wwt_bg & 0xf) << 16) |
345 ((acttoact_bg & 0xf) << 12) |
346 ((wrtord_bg & 0xf) << 8) |
347 ((pre_all_rec & 0x1f) << 0));
348 debug("timing_cfg[8] = 0x%x\n", regs->timing_cfg[8]);
349
350 regs->timing_cfg[9] = (refrec_cid_mclk & 0x3ff) << 16 |
351 (acttoact_cid_mclk & 0xf) << 8;
352 debug("timing_cfg[9] = 0x%x\n", regs->timing_cfg[9]);
353 }
354
cal_ddr_sdram_rcw(const unsigned long clk,struct ddr_cfg_regs * regs,const struct memctl_opt * popts,const struct dimm_params * pdimm)355 static void cal_ddr_sdram_rcw(const unsigned long clk,
356 struct ddr_cfg_regs *regs,
357 const struct memctl_opt *popts,
358 const struct dimm_params *pdimm)
359 {
360 const unsigned int freq = clk / 1000000U;
361 unsigned int rc0a, rc0f;
362
363 if (pdimm->rdimm == 0) {
364 return;
365 }
366
367 rc0a = freq > 3200U ? 7U :
368 (freq > 2933U ? 6U :
369 (freq > 2666U ? 5U :
370 (freq > 2400U ? 4U :
371 (freq > 2133U ? 3U :
372 (freq > 1866U ? 2U :
373 (freq > 1600U ? 1U : 0U))))));
374 rc0f = freq > 3200U ? 3U :
375 (freq > 2400U ? 2U :
376 (freq > 2133U ? 1U : 0U));
377 rc0f = (regs->sdram_cfg[1] & SDRAM_CFG2_AP_EN) ? rc0f : 4;
378 regs->sdram_rcw[0] =
379 pdimm->rcw[0] << 28 |
380 pdimm->rcw[1] << 24 |
381 pdimm->rcw[2] << 20 |
382 pdimm->rcw[3] << 16 |
383 pdimm->rcw[4] << 12 |
384 pdimm->rcw[5] << 8 |
385 pdimm->rcw[6] << 4 |
386 pdimm->rcw[7];
387 regs->sdram_rcw[1] =
388 pdimm->rcw[8] << 28 |
389 pdimm->rcw[9] << 24 |
390 rc0a << 20 |
391 pdimm->rcw[11] << 16 |
392 pdimm->rcw[12] << 12 |
393 pdimm->rcw[13] << 8 |
394 pdimm->rcw[14] << 4 |
395 rc0f;
396 regs->sdram_rcw[2] =
397 ((freq - 1260 + 19) / 20) << 8;
398
399 debug("sdram_rcw[0] = 0x%x\n", regs->sdram_rcw[0]);
400 debug("sdram_rcw[1] = 0x%x\n", regs->sdram_rcw[1]);
401 debug("sdram_rcw[2] = 0x%x\n", regs->sdram_rcw[2]);
402 }
403
cal_ddr_sdram_cfg(const unsigned long clk,struct ddr_cfg_regs * regs,const struct memctl_opt * popts,const struct dimm_params * pdimm,const unsigned int ip_rev)404 static void cal_ddr_sdram_cfg(const unsigned long clk,
405 struct ddr_cfg_regs *regs,
406 const struct memctl_opt *popts,
407 const struct dimm_params *pdimm,
408 const unsigned int ip_rev)
409 {
410 const unsigned int mem_en = 1U;
411 const unsigned int sren = popts->self_refresh_in_sleep;
412 const unsigned int ecc_en = popts->ecc_mode;
413 const unsigned int rd_en = (pdimm->rdimm != 0U) ? 1U : 0U;
414 const unsigned int dyn_pwr = popts->dynamic_power;
415 const unsigned int dbw = popts->data_bus_used;
416 const unsigned int eight_be = (dbw == 1U ||
417 popts->burst_length == DDR_BL8) ? 1U : 0U;
418 const unsigned int ncap = 0U;
419 const unsigned int threet_en = popts->threet_en;
420 const unsigned int twot_en = pdimm->rdimm ?
421 0U : popts->twot_en;
422 const unsigned int ba_intlv = popts->ba_intlv;
423 const unsigned int x32_en = 0U;
424 const unsigned int pchb8 = 0U;
425 const unsigned int hse = popts->half_strength_drive_en;
426 const unsigned int acc_ecc_en = (dbw != 0U && ecc_en == 1U) ? 1U : 0U;
427 const unsigned int mem_halt = 0U;
428 #ifdef PHY_GEN2
429 const unsigned int bi = 1U;
430 #else
431 const unsigned int bi = 0U;
432 #endif
433 const unsigned int sdram_type = SDRAM_TYPE_DDR4;
434 unsigned int odt_cfg = 0U;
435 const unsigned int frc_sr = 0U;
436 const unsigned int sr_ie = popts->self_refresh_irq_en;
437 const unsigned int num_pr = pdimm->package_3ds + 1U;
438 const unsigned int slow = (clk < 1249000000U) ? 1U : 0U;
439 const unsigned int x4_en = popts->x4_en;
440 const unsigned int obc_cfg = popts->otf_burst_chop_en;
441 const unsigned int ap_en = ip_rev == 0x50500U ? 0U : popts->ap_en;
442 const unsigned int d_init = popts->ctlr_init_ecc;
443 const unsigned int rcw_en = popts->rdimm;
444 const unsigned int md_en = popts->mirrored_dimm;
445 const unsigned int qd_en = popts->quad_rank_present;
446 const unsigned int unq_mrs_en = ip_rev < 0x50500U ? 1U : 0U;
447 const unsigned int rd_pre = popts->quad_rank_present;
448 int i;
449
450 regs->sdram_cfg[0] = ((mem_en & 0x1) << 31) |
451 ((sren & 0x1) << 30) |
452 ((ecc_en & 0x1) << 29) |
453 ((rd_en & 0x1) << 28) |
454 ((sdram_type & 0x7) << 24) |
455 ((dyn_pwr & 0x1) << 21) |
456 ((dbw & 0x3) << 19) |
457 ((eight_be & 0x1) << 18) |
458 ((ncap & 0x1) << 17) |
459 ((threet_en & 0x1) << 16) |
460 ((twot_en & 0x1) << 15) |
461 ((ba_intlv & 0x7F) << 8) |
462 ((x32_en & 0x1) << 5) |
463 ((pchb8 & 0x1) << 4) |
464 ((hse & 0x1) << 3) |
465 ((acc_ecc_en & 0x1) << 2) |
466 ((mem_halt & 0x1) << 1) |
467 ((bi & 0x1) << 0);
468 debug("sdram_cfg[0] = 0x%x\n", regs->sdram_cfg[0]);
469
470 for (i = 0; i < DDRC_NUM_CS; i++) {
471 if (popts->cs_odt[i].odt_rd_cfg != 0 ||
472 popts->cs_odt[i].odt_wr_cfg != 0) {
473 odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
474 break;
475 }
476 }
477
478 regs->sdram_cfg[1] = (0
479 | ((frc_sr & 0x1) << 31)
480 | ((sr_ie & 0x1) << 30)
481 | ((odt_cfg & 0x3) << 21)
482 | ((num_pr & 0xf) << 12)
483 | ((slow & 1) << 11)
484 | (x4_en << 10)
485 | (qd_en << 9)
486 | (unq_mrs_en << 8)
487 | ((obc_cfg & 0x1) << 6)
488 | ((ap_en & 0x1) << 5)
489 | ((d_init & 0x1) << 4)
490 | ((rcw_en & 0x1) << 2)
491 | ((md_en & 0x1) << 0)
492 );
493 debug("sdram_cfg[1] = 0x%x\n", regs->sdram_cfg[1]);
494
495 regs->sdram_cfg[2] = (rd_pre & 0x1) << 16 |
496 (popts->rdimm ? 1 : 0);
497 if (pdimm->package_3ds != 0) {
498 if (((pdimm->package_3ds + 1) & 0x1) != 0) {
499 WARN("Unsupported 3DS DIMM\n");
500 } else {
501 regs->sdram_cfg[2] |= ((pdimm->package_3ds + 1) >> 1)
502 << 4;
503 }
504 }
505 debug("sdram_cfg[2] = 0x%x\n", regs->sdram_cfg[2]);
506 }
507
508
cal_ddr_sdram_interval(const unsigned long clk,struct ddr_cfg_regs * regs,const struct memctl_opt * popts,const struct dimm_params * pdimm)509 static void cal_ddr_sdram_interval(const unsigned long clk,
510 struct ddr_cfg_regs *regs,
511 const struct memctl_opt *popts,
512 const struct dimm_params *pdimm)
513 {
514 const unsigned int refint = picos_to_mclk(clk, pdimm->refresh_rate_ps);
515 const unsigned int bstopre = popts->bstopre;
516
517 regs->interval = ((refint & 0xFFFF) << 16) |
518 ((bstopre & 0x3FFF) << 0);
519 debug("interval = 0x%x\n", regs->interval);
520 }
521
522 /* Require cs and cfg first */
cal_ddr_sdram_mode(const unsigned long clk,struct ddr_cfg_regs * regs,const struct memctl_opt * popts,const struct ddr_conf * conf,const struct dimm_params * pdimm,unsigned int cas_latency,unsigned int additive_latency,const unsigned int ip_rev)523 static void cal_ddr_sdram_mode(const unsigned long clk,
524 struct ddr_cfg_regs *regs,
525 const struct memctl_opt *popts,
526 const struct ddr_conf *conf,
527 const struct dimm_params *pdimm,
528 unsigned int cas_latency,
529 unsigned int additive_latency,
530 const unsigned int ip_rev)
531 {
532 int i;
533 unsigned short esdmode; /* Extended SDRAM mode */
534 unsigned short sdmode; /* SDRAM mode */
535
536 /* Mode Register - MR1 */
537 const unsigned int qoff = 0;
538 const unsigned int tdqs_en = 0;
539 unsigned int rtt;
540 const unsigned int wrlvl_en = 0;
541 unsigned int al = 0;
542 unsigned int dic = 0;
543 const unsigned int dll_en = 1;
544
545 /* Mode Register - MR0 */
546 unsigned int wr = 0;
547 const unsigned int dll_rst = 0;
548 const unsigned int mode = 0;
549 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
550 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
551 const unsigned int bt = 0;
552 const unsigned int bl = popts->burst_length == DDR_BL8 ? 0 :
553 (popts->burst_length == DDR_BC4 ? 2 : 1);
554
555 const unsigned int wr_mclk = picos_to_mclk(clk, pdimm->twr_ps);
556 /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */
557 static const int wr_table[] = {
558 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6
559 };
560 /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */
561 static const int cas_latency_table[] = {
562 0, 1, 2, 3, 4, 5, 6, 7, 13, 8,
563 14, 9, 15, 10, 12, 11, 16, 17,
564 18, 19, 20, 21, 22, 23
565 };
566 const unsigned int unq_mrs_en = ip_rev < U(0x50500) ? 1U : 0U;
567 unsigned short esdmode2 = 0U;
568 unsigned short esdmode3 = 0U;
569 const unsigned int wr_crc = 0U;
570 unsigned int rtt_wr = 0U;
571 const unsigned int srt = 0U;
572 unsigned int cwl = cal_cwl(clk);
573 const unsigned int mpr = 0U;
574 const unsigned int mclk_ps = get_memory_clk_ps(clk);
575 const unsigned int wc_lat = 0U;
576 unsigned short esdmode4 = 0U;
577 unsigned short esdmode5;
578 int rtt_park_all = 0;
579 unsigned int rtt_park;
580 const bool four_cs = conf->cs_in_use == 0xf ? true : false;
581 unsigned short esdmode6 = 0U; /* Extended SDRAM mode 6 */
582 unsigned short esdmode7 = 0U; /* Extended SDRAM mode 7 */
583 const unsigned int tccdl_min = max(5U,
584 picos_to_mclk(clk, pdimm->tccdl_ps));
585
586 if (popts->rtt_override != 0U) {
587 rtt = popts->rtt_override_value;
588 } else {
589 rtt = popts->cs_odt[0].odt_rtt_norm;
590 }
591
592 if (additive_latency == (cas_latency - 1)) {
593 al = 1;
594 }
595 if (additive_latency == (cas_latency - 2)) {
596 al = 2;
597 }
598
599 if (popts->quad_rank_present != 0 || popts->output_driver_impedance != 0) {
600 dic = 1; /* output driver impedance 240/7 ohm */
601 }
602
603 esdmode = (((qoff & 0x1) << 12) |
604 ((tdqs_en & 0x1) << 11) |
605 ((rtt & 0x7) << 8) |
606 ((wrlvl_en & 0x1) << 7) |
607 ((al & 0x3) << 3) |
608 ((dic & 0x3) << 1) |
609 ((dll_en & 0x1) << 0));
610
611 if (wr_mclk >= 10 && wr_mclk <= 24) {
612 wr = wr_table[wr_mclk - 10];
613 } else {
614 ERROR("unsupported wc_mclk = %d for mode register\n", wr_mclk);
615 }
616
617 /* look up table to get the cas latency bits */
618 if (cas_latency >= 9 && cas_latency <= 32) {
619 caslat = cas_latency_table[cas_latency - 9];
620 } else {
621 WARN("Error: unsupported cas latency for mode register\n");
622 }
623
624 sdmode = (((caslat & 0x10) << 8) |
625 ((wr & 0x7) << 9) |
626 ((dll_rst & 0x1) << 8) |
627 ((mode & 0x1) << 7) |
628 (((caslat >> 1) & 0x7) << 4) |
629 ((bt & 0x1) << 3) |
630 ((caslat & 1) << 2) |
631 ((bl & 0x3) << 0));
632
633 regs->sdram_mode[0] = (((esdmode & 0xFFFF) << 16) |
634 ((sdmode & 0xFFFF) << 0));
635 debug("sdram_mode[0] = 0x%x\n", regs->sdram_mode[0]);
636
637 switch (cwl) {
638 case 9:
639 case 10:
640 case 11:
641 case 12:
642 cwl -= 9;
643 break;
644 case 14:
645 cwl -= 10;
646 break;
647 case 16:
648 cwl -= 11;
649 break;
650 case 18:
651 cwl -= 12;
652 break;
653 case 20:
654 cwl -= 13;
655 break;
656 default:
657 printf("Error CWL\n");
658 break;
659 }
660
661 if (popts->rtt_override != 0) {
662 rtt_wr = popts->rtt_wr_override_value;
663 } else {
664 rtt_wr = popts->cs_odt[0].odt_rtt_wr;
665 }
666
667 esdmode2 = ((wr_crc & 0x1) << 12) |
668 ((rtt_wr & 0x7) << 9) |
669 ((srt & 0x3) << 6) |
670 ((cwl & 0x7) << 3);
671 esdmode3 = ((mpr & 0x3) << 11) | ((wc_lat & 0x3) << 9);
672
673 regs->sdram_mode[1] = ((esdmode2 & 0xFFFF) << 16) |
674 ((esdmode3 & 0xFFFF) << 0);
675 debug("sdram_mode[1] = 0x%x\n", regs->sdram_mode[1]);
676
677 esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
678 if (popts->vref_dimm != 0) {
679 esdmode6 |= popts->vref_dimm & 0x7f;
680 } else if ((popts->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2) != 0) {
681 esdmode6 |= 1 << 6; /* Range 2 */
682 }
683
684 regs->sdram_mode[9] = ((esdmode6 & 0xffff) << 16) |
685 ((esdmode7 & 0xffff) << 0);
686 debug("sdram_mode[9] = 0x%x\n", regs->sdram_mode[9]);
687
688 rtt_park = (popts->rtt_park != 0) ? popts->rtt_park : 240;
689 switch (rtt_park) {
690 case 240:
691 rtt_park = 0x4;
692 break;
693 case 120:
694 rtt_park = 0x2;
695 break;
696 case 80:
697 rtt_park = 0x6;
698 break;
699 case 60:
700 rtt_park = 0x1;
701 break;
702 case 48:
703 rtt_park = 0x5;
704 break;
705 case 40:
706 rtt_park = 0x3;
707 break;
708 case 34:
709 rtt_park = 0x7;
710 break;
711 default:
712 rtt_park = 0;
713 break;
714 }
715
716 for (i = 0; i < DDRC_NUM_CS; i++) {
717 if (i != 0 && unq_mrs_en == 0) {
718 break;
719 }
720
721 if (popts->rtt_override != 0) {
722 rtt = popts->rtt_override_value;
723 rtt_wr = popts->rtt_wr_override_value;
724 } else {
725 rtt = popts->cs_odt[i].odt_rtt_norm;
726 rtt_wr = popts->cs_odt[i].odt_rtt_wr;
727 }
728
729 esdmode &= 0xF8FF; /* clear bit 10,9,8 for rtt */
730 esdmode |= (rtt & 0x7) << 8;
731 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
732 esdmode2 |= (rtt_wr & 0x3) << 9;
733 esdmode5 = (popts->x4_en) ? 0 : 0x400; /* data mask */
734
735 if (rtt_park_all == 0 &&
736 ((regs->cs[i].config & SDRAM_CS_CONFIG_EN) != 0)) {
737 esdmode5 |= rtt_park << 6;
738 rtt_park_all = four_cs ? 0 : 1;
739 }
740
741 if (((regs->sdram_cfg[1] & SDRAM_CFG2_AP_EN) != 0) &&
742 (popts->rdimm == 0)) {
743 if (mclk_ps >= 935) {
744 esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK;
745 } else if (mclk_ps >= 833) {
746 esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
747 } else {
748 esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
749 WARN("mclk_ps not supported %d", mclk_ps);
750
751 }
752 }
753
754 switch (i) {
755 case 0:
756 regs->sdram_mode[8] = ((esdmode4 & 0xffff) << 16) |
757 ((esdmode5 & 0xffff) << 0);
758 debug("sdram_mode[8] = 0x%x\n", regs->sdram_mode[8]);
759 break;
760 case 1:
761 regs->sdram_mode[2] = (((esdmode & 0xFFFF) << 16) |
762 ((sdmode & 0xFFFF) << 0));
763 regs->sdram_mode[3] = ((esdmode2 & 0xFFFF) << 16) |
764 ((esdmode3 & 0xFFFF) << 0);
765 regs->sdram_mode[10] = ((esdmode4 & 0xFFFF) << 16) |
766 ((esdmode5 & 0xFFFF) << 0);
767 regs->sdram_mode[11] = ((esdmode6 & 0xFFFF) << 16) |
768 ((esdmode7 & 0xFFFF) << 0);
769 debug("sdram_mode[2] = 0x%x\n", regs->sdram_mode[2]);
770 debug("sdram_mode[3] = 0x%x\n", regs->sdram_mode[3]);
771 debug("sdram_mode[10] = 0x%x\n", regs->sdram_mode[10]);
772 debug("sdram_mode[11] = 0x%x\n", regs->sdram_mode[11]);
773 break;
774 case 2:
775 regs->sdram_mode[4] = (((esdmode & 0xFFFF) << 16) |
776 ((sdmode & 0xFFFF) << 0));
777 regs->sdram_mode[5] = ((esdmode2 & 0xFFFF) << 16) |
778 ((esdmode3 & 0xFFFF) << 0);
779 regs->sdram_mode[12] = ((esdmode4 & 0xFFFF) << 16) |
780 ((esdmode5 & 0xFFFF) << 0);
781 regs->sdram_mode[13] = ((esdmode6 & 0xFFFF) << 16) |
782 ((esdmode7 & 0xFFFF) << 0);
783 debug("sdram_mode[4] = 0x%x\n", regs->sdram_mode[4]);
784 debug("sdram_mode[5] = 0x%x\n", regs->sdram_mode[5]);
785 debug("sdram_mode[12] = 0x%x\n", regs->sdram_mode[12]);
786 debug("sdram_mode[13] = 0x%x\n", regs->sdram_mode[13]);
787 break;
788 case 3:
789 regs->sdram_mode[6] = (((esdmode & 0xFFFF) << 16) |
790 ((sdmode & 0xFFFF) << 0));
791 regs->sdram_mode[7] = ((esdmode2 & 0xFFFF) << 16) |
792 ((esdmode3 & 0xFFFF) << 0);
793 regs->sdram_mode[14] = ((esdmode4 & 0xFFFF) << 16) |
794 ((esdmode5 & 0xFFFF) << 0);
795 regs->sdram_mode[15] = ((esdmode6 & 0xFFFF) << 16) |
796 ((esdmode7 & 0xFFFF) << 0);
797 debug("sdram_mode[6] = 0x%x\n", regs->sdram_mode[6]);
798 debug("sdram_mode[7] = 0x%x\n", regs->sdram_mode[7]);
799 debug("sdram_mode[14] = 0x%x\n", regs->sdram_mode[14]);
800 debug("sdram_mode[15] = 0x%x\n", regs->sdram_mode[15]);
801 break;
802 default:
803 break;
804 }
805 }
806 }
807
808 #ifndef CONFIG_MEM_INIT_VALUE
809 #define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
810 #endif
cal_ddr_data_init(struct ddr_cfg_regs * regs)811 static void cal_ddr_data_init(struct ddr_cfg_regs *regs)
812 {
813 regs->data_init = CONFIG_MEM_INIT_VALUE;
814 }
815
cal_ddr_dq_mapping(struct ddr_cfg_regs * regs,const struct dimm_params * pdimm)816 static void cal_ddr_dq_mapping(struct ddr_cfg_regs *regs,
817 const struct dimm_params *pdimm)
818 {
819 const unsigned int acc_ecc_en = (regs->sdram_cfg[0] >> 2) & 0x1;
820 /* FIXME: revert the dq mapping from DIMM */
821 regs->dq_map[0] = ((pdimm->dq_mapping[0] & 0x3F) << 26) |
822 ((pdimm->dq_mapping[1] & 0x3F) << 20) |
823 ((pdimm->dq_mapping[2] & 0x3F) << 14) |
824 ((pdimm->dq_mapping[3] & 0x3F) << 8) |
825 ((pdimm->dq_mapping[4] & 0x3F) << 2);
826
827 regs->dq_map[1] = ((pdimm->dq_mapping[5] & 0x3F) << 26) |
828 ((pdimm->dq_mapping[6] & 0x3F) << 20) |
829 ((pdimm->dq_mapping[7] & 0x3F) << 14) |
830 ((pdimm->dq_mapping[10] & 0x3F) << 8) |
831 ((pdimm->dq_mapping[11] & 0x3F) << 2);
832
833 regs->dq_map[2] = ((pdimm->dq_mapping[12] & 0x3F) << 26) |
834 ((pdimm->dq_mapping[13] & 0x3F) << 20) |
835 ((pdimm->dq_mapping[14] & 0x3F) << 14) |
836 ((pdimm->dq_mapping[15] & 0x3F) << 8) |
837 ((pdimm->dq_mapping[16] & 0x3F) << 2);
838
839 /* dq_map for ECC[4:7] is set to 0 if accumulated ECC is enabled */
840 regs->dq_map[3] = ((pdimm->dq_mapping[17] & 0x3F) << 26) |
841 ((pdimm->dq_mapping[8] & 0x3F) << 20) |
842 ((acc_ecc_en != 0) ? 0 :
843 (pdimm->dq_mapping[9] & 0x3F) << 14) |
844 pdimm->dq_mapping_ors;
845 debug("dq_map[0] = 0x%x\n", regs->dq_map[0]);
846 debug("dq_map[1] = 0x%x\n", regs->dq_map[1]);
847 debug("dq_map[2] = 0x%x\n", regs->dq_map[2]);
848 debug("dq_map[3] = 0x%x\n", regs->dq_map[3]);
849 }
cal_ddr_zq_cntl(struct ddr_cfg_regs * regs)850 static void cal_ddr_zq_cntl(struct ddr_cfg_regs *regs)
851 {
852 const unsigned int zqinit = 10U; /* 1024 clocks */
853 const unsigned int zqoper = 9U; /* 512 clocks */
854 const unsigned int zqcs = 7U; /* 128 clocks */
855 const unsigned int zqcs_init = 5U; /* 1024 refresh seqences */
856 const unsigned int zq_en = 1U; /* enabled */
857
858 regs->zq_cntl = ((zq_en & 0x1) << 31) |
859 ((zqinit & 0xF) << 24) |
860 ((zqoper & 0xF) << 16) |
861 ((zqcs & 0xF) << 8) |
862 ((zqcs_init & 0xF) << 0);
863 debug("zq_cntl = 0x%x\n", regs->zq_cntl);
864 }
865
cal_ddr_sr_cntr(struct ddr_cfg_regs * regs,const struct memctl_opt * popts)866 static void cal_ddr_sr_cntr(struct ddr_cfg_regs *regs,
867 const struct memctl_opt *popts)
868 {
869 const unsigned int sr_it = (popts->auto_self_refresh_en) ?
870 popts->sr_it : 0;
871
872 regs->ddr_sr_cntr = (sr_it & 0xF) << 16;
873 debug("ddr_sr_cntr = 0x%x\n", regs->ddr_sr_cntr);
874 }
875
cal_ddr_eor(struct ddr_cfg_regs * regs,const struct memctl_opt * popts)876 static void cal_ddr_eor(struct ddr_cfg_regs *regs,
877 const struct memctl_opt *popts)
878 {
879 if (popts->addr_hash != 0) {
880 regs->eor = 0x40000000; /* address hash enable */
881 debug("eor = 0x%x\n", regs->eor);
882 }
883 }
884
cal_ddr_csn_bnds(struct ddr_cfg_regs * regs,const struct memctl_opt * popts,const struct ddr_conf * conf,const struct dimm_params * pdimm)885 static void cal_ddr_csn_bnds(struct ddr_cfg_regs *regs,
886 const struct memctl_opt *popts,
887 const struct ddr_conf *conf,
888 const struct dimm_params *pdimm)
889 {
890 int i;
891 unsigned long long ea, sa;
892
893 /* Chip Select Memory Bounds (CSn_BNDS) */
894 for (i = 0;
895 i < DDRC_NUM_CS && conf->cs_size[i];
896 i++) {
897 debug("cs_in_use = 0x%x\n", conf->cs_in_use);
898 if (conf->cs_in_use != 0) {
899 sa = conf->cs_base_addr[i];
900 ea = sa + conf->cs_size[i] - 1;
901 sa >>= 24;
902 ea >>= 24;
903 regs->cs[i].bnds = ((sa & 0xffff) << 16) |
904 ((ea & 0xffff) << 0);
905 cal_csn_config(i, regs, popts, pdimm);
906 } else {
907 /* setting bnds to 0xffffffff for inactive CS */
908 regs->cs[i].bnds = 0xffffffff;
909 }
910
911 debug("cs[%d].bnds = 0x%x\n", i, regs->cs[i].bnds);
912 }
913 }
914
cal_ddr_addr_dec(struct ddr_cfg_regs * regs)915 static void cal_ddr_addr_dec(struct ddr_cfg_regs *regs)
916 {
917 #ifdef CONFIG_DDR_ADDR_DEC
918 unsigned int ba_bits __unused;
919 char p __unused;
920 const unsigned int cs0_config = regs->cs[0].config;
921 const int cacheline = PLATFORM_CACHE_LINE_SHIFT;
922 unsigned int bg_bits;
923 unsigned int row_bits;
924 unsigned int col_bits;
925 unsigned int cs;
926 unsigned int map_row[18];
927 unsigned int map_col[11];
928 unsigned int map_ba[2];
929 unsigned int map_cid[2] = {0x3F, 0x3F};
930 unsigned int map_bg[2] = {0x3F, 0x3F};
931 unsigned int map_cs[2] = {0x3F, 0x3F};
932 unsigned int dbw;
933 unsigned int ba_intlv;
934 int placement;
935 int intlv;
936 int abort = 0;
937 int i;
938 int j;
939
940 col_bits = (cs0_config >> 0) & 0x7;
941 if (col_bits < 4) {
942 col_bits += 8;
943 } else if (col_bits < 7 || col_bits > 10) {
944 ERROR("Error %s col_bits = %d\n", __func__, col_bits);
945 }
946 row_bits = ((cs0_config >> 8) & 0x7) + 12;
947 ba_bits = ((cs0_config >> 14) & 0x3) + 2;
948 bg_bits = ((cs0_config >> 4) & 0x3) + 0;
949 intlv = (cs0_config >> 24) & 0xf;
950 ba_intlv = (regs->sdram_cfg[0] >> 8) & 0x7f;
951 switch (ba_intlv) {
952 case DDR_BA_INTLV_CS01:
953 cs = 1;
954 break;
955 case DDR_BA_INTLV_CS0123:
956 cs = 2;
957 break;
958 case DDR_BA_NONE:
959 cs = 0;
960 break;
961 default:
962 ERROR("%s ba_intlv 0x%x\n", __func__, ba_intlv);
963 return;
964 }
965 debug("col %d, row %d, ba %d, bg %d, intlv %d\n",
966 col_bits, row_bits, ba_bits, bg_bits, intlv);
967 /*
968 * Example mapping of 15x2x2x10
969 * ---- --rr rrrr rrrr rrrr rCBB Gccc cccI cGcc cbbb
970 */
971 dbw = (regs->sdram_cfg[0] >> 19) & 0x3;
972 switch (dbw) {
973 case 0: /* 64-bit */
974 placement = 3;
975 break;
976 case 1: /* 32-bit */
977 placement = 2;
978 break;
979 default:
980 ERROR("%s dbw = %d\n", __func__, dbw);
981 return;
982 }
983 debug("cacheline size %d\n", cacheline);
984 for (i = 0; placement < cacheline; i++) {
985 map_col[i] = placement++;
986 }
987 map_bg[0] = placement++;
988 for ( ; i < col_bits; i++) {
989 map_col[i] = placement++;
990 if (placement == intlv) {
991 placement++;
992 }
993 }
994 for ( ; i < 11; i++) {
995 map_col[i] = 0x3F; /* unused col bits */
996 }
997
998 if (bg_bits >= 2) {
999 map_bg[1] = placement++;
1000 }
1001 map_ba[0] = placement++;
1002 map_ba[1] = placement++;
1003 if (cs != 0U) {
1004 map_cs[0] = placement++;
1005 if (cs == 2U) {
1006 map_cs[1] = placement++;
1007 }
1008 } else {
1009 map_cs[0] = U(0x3F);
1010 }
1011
1012 for (i = 0; i < row_bits; i++) {
1013 map_row[i] = placement++;
1014 }
1015
1016 for ( ; i < 18; i++) {
1017 map_row[i] = 0x3F; /* unused row bits */
1018 }
1019
1020 for (i = 39; i >= 0 ; i--) {
1021 if (i == intlv) {
1022 placement = 8;
1023 p = 'I';
1024 } else if (i < 3) {
1025 p = 'b';
1026 placement = 0;
1027 } else {
1028 placement = 0;
1029 p = '-';
1030 }
1031 for (j = 0; j < 18; j++) {
1032 if (map_row[j] != i) {
1033 continue;
1034 }
1035 if (placement != 0) {
1036 abort = 1;
1037 ERROR("%s wrong address bit %d\n", __func__, i);
1038 }
1039 placement = i;
1040 p = 'r';
1041 }
1042 for (j = 0; j < 11; j++) {
1043 if (map_col[j] != i) {
1044 continue;
1045 }
1046 if (placement != 0) {
1047 abort = 1;
1048 ERROR("%s wrong address bit %d\n", __func__, i);
1049 }
1050 placement = i;
1051 p = 'c';
1052 }
1053 for (j = 0; j < 2; j++) {
1054 if (map_ba[j] != i) {
1055 continue;
1056 }
1057 if (placement != 0) {
1058 abort = 1;
1059 ERROR("%s wrong address bit %d\n", __func__, i);
1060 }
1061 placement = i;
1062 p = 'B';
1063 }
1064 for (j = 0; j < 2; j++) {
1065 if (map_bg[j] != i) {
1066 continue;
1067 }
1068 if (placement != 0) {
1069 abort = 1;
1070 ERROR("%s wrong address bit %d\n", __func__, i);
1071 }
1072 placement = i;
1073 p = 'G';
1074 }
1075 for (j = 0; j < 2; j++) {
1076 if (map_cs[j] != i) {
1077 continue;
1078 }
1079 if (placement != 0) {
1080 abort = 1;
1081 ERROR("%s wrong address bit %d\n", __func__, i);
1082 }
1083 placement = i;
1084 p = 'C';
1085 }
1086 #ifdef DDR_DEBUG
1087 printf("%c", p);
1088 if ((i % 4) == 0) {
1089 printf(" ");
1090 }
1091 #endif
1092 }
1093 #ifdef DDR_DEBUG
1094 puts("\n");
1095 #endif
1096
1097 if (abort != 0) {
1098 return;
1099 }
1100
1101 regs->dec[0] = map_row[17] << 26 |
1102 map_row[16] << 18 |
1103 map_row[15] << 10 |
1104 map_row[14] << 2;
1105 regs->dec[1] = map_row[13] << 26 |
1106 map_row[12] << 18 |
1107 map_row[11] << 10 |
1108 map_row[10] << 2;
1109 regs->dec[2] = map_row[9] << 26 |
1110 map_row[8] << 18 |
1111 map_row[7] << 10 |
1112 map_row[6] << 2;
1113 regs->dec[3] = map_row[5] << 26 |
1114 map_row[4] << 18 |
1115 map_row[3] << 10 |
1116 map_row[2] << 2;
1117 regs->dec[4] = map_row[1] << 26 |
1118 map_row[0] << 18 |
1119 map_col[10] << 10 |
1120 map_col[9] << 2;
1121 regs->dec[5] = map_col[8] << 26 |
1122 map_col[7] << 18 |
1123 map_col[6] << 10 |
1124 map_col[5] << 2;
1125 regs->dec[6] = map_col[4] << 26 |
1126 map_col[3] << 18 |
1127 map_col[2] << 10 |
1128 map_col[1] << 2;
1129 regs->dec[7] = map_col[0] << 26 |
1130 map_ba[1] << 18 |
1131 map_ba[0] << 10 |
1132 map_cid[1] << 2;
1133 regs->dec[8] = map_cid[1] << 26 |
1134 map_cs[1] << 18 |
1135 map_cs[0] << 10 |
1136 map_bg[1] << 2;
1137 regs->dec[9] = map_bg[0] << 26 |
1138 1;
1139 for (i = 0; i < 10; i++) {
1140 debug("dec[%d] = 0x%x\n", i, regs->dec[i]);
1141 }
1142 #endif
1143 }
skip_caslat(unsigned int tckmin_ps,unsigned int taamin_ps,unsigned int mclk_ps,unsigned int package_3ds)1144 static unsigned int skip_caslat(unsigned int tckmin_ps,
1145 unsigned int taamin_ps,
1146 unsigned int mclk_ps,
1147 unsigned int package_3ds)
1148 {
1149 int i, j, k;
1150 struct cas {
1151 const unsigned int tckmin_ps;
1152 const unsigned int caslat[4];
1153 };
1154 struct speed {
1155 const struct cas *cl;
1156 const unsigned int taamin_ps[4];
1157 };
1158 const struct cas cl_3200[] = {
1159 {625, {0xa00000, 0xb00000, 0xf000000,} },
1160 {750, { 0x20000, 0x60000, 0xe00000,} },
1161 {833, { 0x8000, 0x18000, 0x38000,} },
1162 {937, { 0x4000, 0x4000, 0xc000,} },
1163 {1071, { 0x1000, 0x1000, 0x3000,} },
1164 {1250, { 0x400, 0x400, 0xc00,} },
1165 {1500, { 0, 0x600, 0x200,} },
1166 };
1167 const struct cas cl_2933[] = {
1168 {682, { 0, 0x80000, 0x180000, 0x380000} },
1169 {750, { 0x20000, 0x60000, 0x60000, 0xe0000} },
1170 {833, { 0x8000, 0x18000, 0x18000, 0x38000} },
1171 {937, { 0x4000, 0x4000, 0x4000, 0xc000} },
1172 {1071, { 0x1000, 0x1000, 0x1000, 0x3000} },
1173 {1250, { 0x400, 0x400, 0x400, 0xc00} },
1174 {1500, { 0, 0x200, 0x200, 0x200} },
1175 };
1176 const struct cas cl_2666[] = {
1177 {750, { 0, 0x20000, 0x60000, 0xe0000} },
1178 {833, { 0x8000, 0x18000, 0x18000, 0x38000} },
1179 {937, { 0x4000, 0x4000, 0x4000, 0xc000} },
1180 {1071, { 0x1000, 0x1000, 0x1000, 0x3000} },
1181 {1250, { 0x400, 0x400, 0x400, 0xc00} },
1182 {1500, { 0, 0, 0x200, 0x200} },
1183 };
1184 const struct cas cl_2400[] = {
1185 {833, { 0, 0x8000, 0x18000, 0x38000} },
1186 {937, { 0xc000, 0x4000, 0x4000, 0xc000} },
1187 {1071, { 0x3000, 0x1000, 0x1000, 0x3000} },
1188 {1250, { 0xc00, 0x400, 0x400, 0xc00} },
1189 {1500, { 0, 0x400, 0x200, 0x200} },
1190 };
1191 const struct cas cl_2133[] = {
1192 {937, { 0, 0x4000, 0xc000,} },
1193 {1071, { 0x2000, 0, 0x2000,} },
1194 {1250, { 0x800, 0, 0x800,} },
1195 {1500, { 0, 0x400, 0x200,} },
1196 };
1197 const struct cas cl_1866[] = {
1198 {1071, { 0, 0x1000, 0x3000,} },
1199 {1250, { 0xc00, 0x400, 0xc00,} },
1200 {1500, { 0, 0x400, 0x200,} },
1201 };
1202 const struct cas cl_1600[] = {
1203 {1250, { 0, 0x400, 0xc00,} },
1204 {1500, { 0, 0x400, 0x200,} },
1205 };
1206 const struct speed bin_0[] = {
1207 {cl_3200, {12500, 13750, 15000,} },
1208 {cl_2933, {12960, 13640, 13750, 15000,} },
1209 {cl_2666, {12750, 13500, 13750, 15000,} },
1210 {cl_2400, {12500, 13320, 13750, 15000,} },
1211 {cl_2133, {13130, 13500, 15000,} },
1212 {cl_1866, {12850, 13500, 15000,} },
1213 {cl_1600, {12500, 13500, 15000,} }
1214 };
1215 const struct cas cl_3200_3ds[] = {
1216 {625, { 0xa000000, 0xb000000, 0xf000000,} },
1217 {750, { 0xaa00000, 0xab00000, 0xef00000,} },
1218 {833, { 0xaac0000, 0xaac0000, 0xebc0000,} },
1219 {937, { 0xaab0000, 0xaab0000, 0xeaf0000,} },
1220 {1071, { 0xaaa4000, 0xaaac000, 0xeaec000,} },
1221 {1250, { 0xaaa0000, 0xaaa2000, 0xeaeb000,} },
1222 };
1223 const struct cas cl_2666_3ds[] = {
1224 {750, { 0xa00000, 0xb00000, 0xf00000,} },
1225 {833, { 0xac0000, 0xac0000, 0xbc0000,} },
1226 {937, { 0xab0000, 0xab0000, 0xaf0000,} },
1227 {1071, { 0xaa4000, 0xaac000, 0xaac000,} },
1228 {1250, { 0xaa0000, 0xaaa000, 0xaaa000,} },
1229 };
1230 const struct cas cl_2400_3ds[] = {
1231 {833, { 0xe00000, 0xe40000, 0xec0000, 0xb00000} },
1232 {937, { 0xe00000, 0xe00000, 0xea0000, 0xae0000} },
1233 {1071, { 0xe00000, 0xe04000, 0xeac000, 0xaec000} },
1234 {1250, { 0xe00000, 0xe00000, 0xeaa000, 0xae2000} },
1235 };
1236 const struct cas cl_2133_3ds[] = {
1237 {937, { 0x90000, 0xb0000, 0xf0000,} },
1238 {1071, { 0x84000, 0xac000, 0xec000,} },
1239 {1250, { 0x80000, 0xa2000, 0xe2000,} },
1240 };
1241 const struct cas cl_1866_3ds[] = {
1242 {1071, { 0, 0x4000, 0xc000,} },
1243 {1250, { 0, 0x1000, 0x3000,} },
1244 };
1245 const struct cas cl_1600_3ds[] = {
1246 {1250, { 0, 0x1000, 0x3000,} },
1247 };
1248 const struct speed bin_3ds[] = {
1249 {cl_3200_3ds, {15000, 16250, 17140,} },
1250 {cl_2666_3ds, {15000, 16500, 17140,} },
1251 {cl_2400_3ds, {15000, 15830, 16670, 17140} },
1252 {cl_2133_3ds, {15950, 16880, 17140,} },
1253 {cl_1866_3ds, {15000, 16070, 17140,} },
1254 {cl_1600_3ds, {15000, 16250, 17500,} },
1255 };
1256 const struct speed *bin;
1257 int size;
1258 unsigned int taamin_max, tck_max;
1259
1260 if (taamin_ps > ((package_3ds != 0) ? 21500 : 18000)) {
1261 ERROR("taamin_ps %u invalid\n", taamin_ps);
1262 return 0;
1263 }
1264 if (package_3ds != 0) {
1265 bin = bin_3ds;
1266 size = ARRAY_SIZE(bin_3ds);
1267 taamin_max = 1250;
1268 tck_max = 1500;
1269 } else {
1270 bin = bin_0;
1271 size = ARRAY_SIZE(bin_0);
1272 taamin_max = 1500;
1273 tck_max = 1600;
1274 }
1275 if (mclk_ps < 625 || mclk_ps > tck_max) {
1276 ERROR("mclk %u invalid\n", mclk_ps);
1277 return 0;
1278 }
1279
1280 for (i = 0; i < size; i++) {
1281 if (bin[i].cl[0].tckmin_ps >= tckmin_ps) {
1282 break;
1283 }
1284 }
1285 if (i >= size) {
1286 ERROR("speed bin not found\n");
1287 return 0;
1288 }
1289 if (bin[i].cl[0].tckmin_ps > tckmin_ps && i > 0) {
1290 i--;
1291 }
1292
1293 for (j = 0; j < 4; j++) {
1294 if ((bin[i].taamin_ps[j] == 0) ||
1295 bin[i].taamin_ps[j] >= taamin_ps) {
1296 break;
1297 }
1298 }
1299
1300 if (j >= 4) {
1301 ERROR("taamin_ps out of range.\n");
1302 return 0;
1303 }
1304
1305 if ((bin[i].taamin_ps[j] == 0) ||
1306 (bin[i].taamin_ps[j] > taamin_ps && j > 0)) {
1307 j--;
1308 }
1309
1310 for (k = 0; bin[i].cl[k].tckmin_ps < mclk_ps &&
1311 bin[i].cl[k].tckmin_ps < taamin_max; k++)
1312 ;
1313 if (bin[i].cl[k].tckmin_ps > mclk_ps && k > 0) {
1314 k--;
1315 }
1316
1317 debug("Skip CL mask for this speed 0x%x\n", bin[i].cl[k].caslat[j]);
1318
1319 return bin[i].cl[k].caslat[j];
1320 }
1321
compute_ddrc(const unsigned long clk,const struct memctl_opt * popts,const struct ddr_conf * conf,struct ddr_cfg_regs * regs,const struct dimm_params * pdimm,unsigned int ip_rev)1322 int compute_ddrc(const unsigned long clk,
1323 const struct memctl_opt *popts,
1324 const struct ddr_conf *conf,
1325 struct ddr_cfg_regs *regs,
1326 const struct dimm_params *pdimm,
1327 unsigned int ip_rev)
1328 {
1329 unsigned int cas_latency;
1330 unsigned int caslat_skip;
1331 unsigned int additive_latency;
1332 const unsigned int mclk_ps = get_memory_clk_ps(clk);
1333 int i;
1334
1335 zeromem(regs, sizeof(struct ddr_cfg_regs));
1336
1337 if (mclk_ps < pdimm->tckmin_x_ps) {
1338 ERROR("DDR Clk: MCLK cycle is %u ps.\n", mclk_ps);
1339 ERROR("DDR Clk is faster than DIMM can support.\n");
1340 }
1341
1342 /* calculate cas latency, override first */
1343 cas_latency = (popts->caslat_override != 0) ?
1344 popts->caslat_override_value :
1345 (pdimm->taa_ps + mclk_ps - 1) / mclk_ps;
1346
1347 /* skip unsupported caslat based on speed bin */
1348 caslat_skip = skip_caslat(pdimm->tckmin_x_ps,
1349 pdimm->taa_ps,
1350 mclk_ps,
1351 pdimm->package_3ds);
1352 debug("Skip caslat 0x%x\n", caslat_skip);
1353
1354 /* Check if DIMM supports the cas latency */
1355 i = 24;
1356 while (((pdimm->caslat_x & ~caslat_skip & (1 << cas_latency)) == 0) &&
1357 (i-- > 0)) {
1358 cas_latency++;
1359 }
1360
1361 if (i <= 0) {
1362 ERROR("Failed to find a proper cas latency\n");
1363 return -EINVAL;
1364 }
1365 /* Verify cas latency does not exceed 18ns for DDR4 */
1366 if (cas_latency * mclk_ps > 18000) {
1367 ERROR("cas latency is too large %d\n", cas_latency);
1368 return -EINVAL;
1369 }
1370
1371 additive_latency = (popts->addt_lat_override != 0) ?
1372 popts->addt_lat_override_value : 0;
1373
1374 cal_ddr_csn_bnds(regs, popts, conf, pdimm);
1375 cal_ddr_sdram_cfg(clk, regs, popts, pdimm, ip_rev);
1376 cal_ddr_sdram_rcw(clk, regs, popts, pdimm);
1377 cal_timing_cfg(clk, regs, popts, pdimm, conf, cas_latency,
1378 additive_latency);
1379 cal_ddr_dq_mapping(regs, pdimm);
1380
1381 if (ip_rev >= 0x50500) {
1382 cal_ddr_addr_dec(regs);
1383 }
1384
1385 cal_ddr_sdram_mode(clk, regs, popts, conf, pdimm, cas_latency,
1386 additive_latency, ip_rev);
1387 cal_ddr_eor(regs, popts);
1388 cal_ddr_data_init(regs);
1389 cal_ddr_sdram_interval(clk, regs, popts, pdimm);
1390 cal_ddr_zq_cntl(regs);
1391 cal_ddr_sr_cntr(regs, popts);
1392
1393 return 0;
1394 }
1395