1 /*
2 * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9 #include <stdbool.h>
10 #include <stdint.h>
11 #include <stdio.h>
12
13 #include <platform_def.h>
14
15 #include <arch_helpers.h>
16 #include <common/debug.h>
17 #include <lib/utils_def.h>
18 #include <lib/xlat_tables/xlat_tables_defs.h>
19 #include <lib/xlat_tables/xlat_tables_v2.h>
20
21 #include "xlat_tables_private.h"
22
23 #if LOG_LEVEL < LOG_LEVEL_VERBOSE
24
xlat_mmap_print(__unused const mmap_region_t * mmap)25 void xlat_mmap_print(__unused const mmap_region_t *mmap)
26 {
27 /* Empty */
28 }
29
xlat_tables_print(__unused xlat_ctx_t * ctx)30 void xlat_tables_print(__unused xlat_ctx_t *ctx)
31 {
32 /* Empty */
33 }
34
35 #else /* if LOG_LEVEL >= LOG_LEVEL_VERBOSE */
36
xlat_mmap_print(const mmap_region_t * mmap)37 void xlat_mmap_print(const mmap_region_t *mmap)
38 {
39 printf("mmap:\n");
40 const mmap_region_t *mm = mmap;
41
42 while (mm->size != 0U) {
43 printf(" VA:0x%lx PA:0x%llx size:0x%zx attr:0x%x granularity:0x%zx\n",
44 mm->base_va, mm->base_pa, mm->size, mm->attr,
45 mm->granularity);
46 ++mm;
47 };
48 printf("\n");
49 }
50
51 /* Print the attributes of the specified block descriptor. */
xlat_desc_print(const xlat_ctx_t * ctx,uint64_t desc)52 static void xlat_desc_print(const xlat_ctx_t *ctx, uint64_t desc)
53 {
54 uint64_t mem_type_index = ATTR_INDEX_GET(desc);
55 int xlat_regime = ctx->xlat_regime;
56
57 if (mem_type_index == ATTR_IWBWA_OWBWA_NTR_INDEX) {
58 printf("MEM");
59 } else if (mem_type_index == ATTR_NON_CACHEABLE_INDEX) {
60 printf("NC");
61 } else {
62 assert(mem_type_index == ATTR_DEVICE_INDEX);
63 printf("DEV");
64 }
65
66 if ((xlat_regime == EL3_REGIME) || (xlat_regime == EL2_REGIME)) {
67 /* For EL3 and EL2 only check the AP[2] and XN bits. */
68 printf(((desc & LOWER_ATTRS(AP_RO)) != 0ULL) ? "-RO" : "-RW");
69 printf(((desc & UPPER_ATTRS(XN)) != 0ULL) ? "-XN" : "-EXEC");
70 } else {
71 assert(xlat_regime == EL1_EL0_REGIME);
72 /*
73 * For EL0 and EL1:
74 * - In AArch64 PXN and UXN can be set independently but in
75 * AArch32 there is no UXN (XN affects both privilege levels).
76 * For consistency, we set them simultaneously in both cases.
77 * - RO and RW permissions must be the same in EL1 and EL0. If
78 * EL0 can access that memory region, so can EL1, with the
79 * same permissions.
80 */
81 #if ENABLE_ASSERTIONS
82 uint64_t xn_mask = xlat_arch_regime_get_xn_desc(EL1_EL0_REGIME);
83 uint64_t xn_perm = desc & xn_mask;
84
85 assert((xn_perm == xn_mask) || (xn_perm == 0ULL));
86 #endif
87 printf(((desc & LOWER_ATTRS(AP_RO)) != 0ULL) ? "-RO" : "-RW");
88 /* Only check one of PXN and UXN, the other one is the same. */
89 printf(((desc & UPPER_ATTRS(PXN)) != 0ULL) ? "-XN" : "-EXEC");
90 /*
91 * Privileged regions can only be accessed from EL1, user
92 * regions can be accessed from EL1 and EL0.
93 */
94 printf(((desc & LOWER_ATTRS(AP_ACCESS_UNPRIVILEGED)) != 0ULL)
95 ? "-USER" : "-PRIV");
96 }
97
98 printf(((LOWER_ATTRS(NS) & desc) != 0ULL) ? "-NS" : "-S");
99
100 #ifdef __aarch64__
101 /* Check Guarded Page bit */
102 if ((desc & GP) != 0ULL) {
103 printf("-GP");
104 }
105 #endif
106 }
107
108 static const char * const level_spacers[] = {
109 "[LV0] ",
110 " [LV1] ",
111 " [LV2] ",
112 " [LV3] "
113 };
114
115 static const char *invalid_descriptors_ommited =
116 "%s(%d invalid descriptors omitted)\n";
117
118 /*
119 * Recursive function that reads the translation tables passed as an argument
120 * and prints their status.
121 */
xlat_tables_print_internal(xlat_ctx_t * ctx,uintptr_t table_base_va,const uint64_t * table_base,unsigned int table_entries,unsigned int level)122 static void xlat_tables_print_internal(xlat_ctx_t *ctx, uintptr_t table_base_va,
123 const uint64_t *table_base, unsigned int table_entries,
124 unsigned int level)
125 {
126 assert(level <= XLAT_TABLE_LEVEL_MAX);
127
128 uint64_t desc;
129 uintptr_t table_idx_va = table_base_va;
130 unsigned int table_idx = 0U;
131 size_t level_size = XLAT_BLOCK_SIZE(level);
132
133 /*
134 * Keep track of how many invalid descriptors are counted in a row.
135 * Whenever multiple invalid descriptors are found, only the first one
136 * is printed, and a line is added to inform about how many descriptors
137 * have been omitted.
138 */
139 int invalid_row_count = 0;
140
141 while (table_idx < table_entries) {
142
143 desc = table_base[table_idx];
144
145 if ((desc & DESC_MASK) == INVALID_DESC) {
146
147 if (invalid_row_count == 0) {
148 printf("%sVA:0x%lx size:0x%zx\n",
149 level_spacers[level],
150 table_idx_va, level_size);
151 }
152 invalid_row_count++;
153
154 } else {
155
156 if (invalid_row_count > 1) {
157 printf(invalid_descriptors_ommited,
158 level_spacers[level],
159 invalid_row_count - 1);
160 }
161 invalid_row_count = 0;
162
163 /*
164 * Check if this is a table or a block. Tables are only
165 * allowed in levels other than 3, but DESC_PAGE has the
166 * same value as DESC_TABLE, so we need to check.
167 */
168 if (((desc & DESC_MASK) == TABLE_DESC) &&
169 (level < XLAT_TABLE_LEVEL_MAX)) {
170 /*
171 * Do not print any PA for a table descriptor,
172 * as it doesn't directly map physical memory
173 * but instead points to the next translation
174 * table in the translation table walk.
175 */
176 printf("%sVA:0x%lx size:0x%zx\n",
177 level_spacers[level],
178 table_idx_va, level_size);
179
180 uintptr_t addr_inner = desc & TABLE_ADDR_MASK;
181
182 xlat_tables_print_internal(ctx, table_idx_va,
183 (uint64_t *)addr_inner,
184 XLAT_TABLE_ENTRIES, level + 1U);
185 } else {
186 printf("%sVA:0x%lx PA:0x%llx size:0x%zx ",
187 level_spacers[level], table_idx_va,
188 (uint64_t)(desc & TABLE_ADDR_MASK),
189 level_size);
190 xlat_desc_print(ctx, desc);
191 printf("\n");
192 }
193 }
194
195 table_idx++;
196 table_idx_va += level_size;
197 }
198
199 if (invalid_row_count > 1) {
200 printf(invalid_descriptors_ommited,
201 level_spacers[level], invalid_row_count - 1);
202 }
203 }
204
xlat_tables_print(xlat_ctx_t * ctx)205 void xlat_tables_print(xlat_ctx_t *ctx)
206 {
207 const char *xlat_regime_str;
208 int used_page_tables;
209
210 if (ctx->xlat_regime == EL1_EL0_REGIME) {
211 xlat_regime_str = "1&0";
212 } else if (ctx->xlat_regime == EL2_REGIME) {
213 xlat_regime_str = "2";
214 } else {
215 assert(ctx->xlat_regime == EL3_REGIME);
216 xlat_regime_str = "3";
217 }
218 VERBOSE("Translation tables state:\n");
219 VERBOSE(" Xlat regime: EL%s\n", xlat_regime_str);
220 VERBOSE(" Max allowed PA: 0x%llx\n", ctx->pa_max_address);
221 VERBOSE(" Max allowed VA: 0x%lx\n", ctx->va_max_address);
222 VERBOSE(" Max mapped PA: 0x%llx\n", ctx->max_pa);
223 VERBOSE(" Max mapped VA: 0x%lx\n", ctx->max_va);
224
225 VERBOSE(" Initial lookup level: %u\n", ctx->base_level);
226 VERBOSE(" Entries @initial lookup level: %u\n",
227 ctx->base_table_entries);
228
229 #if PLAT_XLAT_TABLES_DYNAMIC
230 used_page_tables = 0;
231 for (int i = 0; i < ctx->tables_num; ++i) {
232 if (ctx->tables_mapped_regions[i] != 0)
233 ++used_page_tables;
234 }
235 #else
236 used_page_tables = ctx->next_table;
237 #endif
238 VERBOSE(" Used %d sub-tables out of %d (spare: %d)\n",
239 used_page_tables, ctx->tables_num,
240 ctx->tables_num - used_page_tables);
241
242 xlat_tables_print_internal(ctx, 0U, ctx->base_table,
243 ctx->base_table_entries, ctx->base_level);
244 }
245
246 #endif /* LOG_LEVEL >= LOG_LEVEL_VERBOSE */
247
248 /*
249 * Do a translation table walk to find the block or page descriptor that maps
250 * virtual_addr.
251 *
252 * On success, return the address of the descriptor within the translation
253 * table. Its lookup level is stored in '*out_level'.
254 * On error, return NULL.
255 *
256 * xlat_table_base
257 * Base address for the initial lookup level.
258 * xlat_table_base_entries
259 * Number of entries in the translation table for the initial lookup level.
260 * virt_addr_space_size
261 * Size in bytes of the virtual address space.
262 */
find_xlat_table_entry(uintptr_t virtual_addr,void * xlat_table_base,unsigned int xlat_table_base_entries,unsigned long long virt_addr_space_size,unsigned int * out_level)263 static uint64_t *find_xlat_table_entry(uintptr_t virtual_addr,
264 void *xlat_table_base,
265 unsigned int xlat_table_base_entries,
266 unsigned long long virt_addr_space_size,
267 unsigned int *out_level)
268 {
269 unsigned int start_level;
270 uint64_t *table;
271 unsigned int entries;
272
273 start_level = GET_XLAT_TABLE_LEVEL_BASE(virt_addr_space_size);
274
275 table = xlat_table_base;
276 entries = xlat_table_base_entries;
277
278 for (unsigned int level = start_level;
279 level <= XLAT_TABLE_LEVEL_MAX;
280 ++level) {
281 uint64_t idx, desc, desc_type;
282
283 idx = XLAT_TABLE_IDX(virtual_addr, level);
284 if (idx >= entries) {
285 WARN("Missing xlat table entry at address 0x%lx\n",
286 virtual_addr);
287 return NULL;
288 }
289
290 desc = table[idx];
291 desc_type = desc & DESC_MASK;
292
293 if (desc_type == INVALID_DESC) {
294 VERBOSE("Invalid entry (memory not mapped)\n");
295 return NULL;
296 }
297
298 if (level == XLAT_TABLE_LEVEL_MAX) {
299 /*
300 * Only page descriptors allowed at the final lookup
301 * level.
302 */
303 assert(desc_type == PAGE_DESC);
304 *out_level = level;
305 return &table[idx];
306 }
307
308 if (desc_type == BLOCK_DESC) {
309 *out_level = level;
310 return &table[idx];
311 }
312
313 assert(desc_type == TABLE_DESC);
314 table = (uint64_t *)(uintptr_t)(desc & TABLE_ADDR_MASK);
315 entries = XLAT_TABLE_ENTRIES;
316 }
317
318 /*
319 * This shouldn't be reached, the translation table walk should end at
320 * most at level XLAT_TABLE_LEVEL_MAX and return from inside the loop.
321 */
322 assert(false);
323
324 return NULL;
325 }
326
327
xlat_get_mem_attributes_internal(const xlat_ctx_t * ctx,uintptr_t base_va,uint32_t * attributes,uint64_t ** table_entry,unsigned long long * addr_pa,unsigned int * table_level)328 static int xlat_get_mem_attributes_internal(const xlat_ctx_t *ctx,
329 uintptr_t base_va, uint32_t *attributes, uint64_t **table_entry,
330 unsigned long long *addr_pa, unsigned int *table_level)
331 {
332 uint64_t *entry;
333 uint64_t desc;
334 unsigned int level;
335 unsigned long long virt_addr_space_size;
336
337 /*
338 * Sanity-check arguments.
339 */
340 assert(ctx != NULL);
341 assert(ctx->initialized);
342 assert((ctx->xlat_regime == EL1_EL0_REGIME) ||
343 (ctx->xlat_regime == EL2_REGIME) ||
344 (ctx->xlat_regime == EL3_REGIME));
345
346 virt_addr_space_size = (unsigned long long)ctx->va_max_address + 1ULL;
347 assert(virt_addr_space_size > 0U);
348
349 entry = find_xlat_table_entry(base_va,
350 ctx->base_table,
351 ctx->base_table_entries,
352 virt_addr_space_size,
353 &level);
354 if (entry == NULL) {
355 WARN("Address 0x%lx is not mapped.\n", base_va);
356 return -EINVAL;
357 }
358
359 if (addr_pa != NULL) {
360 *addr_pa = *entry & TABLE_ADDR_MASK;
361 }
362
363 if (table_entry != NULL) {
364 *table_entry = entry;
365 }
366
367 if (table_level != NULL) {
368 *table_level = level;
369 }
370
371 desc = *entry;
372
373 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE
374 VERBOSE("Attributes: ");
375 xlat_desc_print(ctx, desc);
376 printf("\n");
377 #endif /* LOG_LEVEL >= LOG_LEVEL_VERBOSE */
378
379 assert(attributes != NULL);
380 *attributes = 0U;
381
382 uint64_t attr_index = (desc >> ATTR_INDEX_SHIFT) & ATTR_INDEX_MASK;
383
384 if (attr_index == ATTR_IWBWA_OWBWA_NTR_INDEX) {
385 *attributes |= MT_MEMORY;
386 } else if (attr_index == ATTR_NON_CACHEABLE_INDEX) {
387 *attributes |= MT_NON_CACHEABLE;
388 } else {
389 assert(attr_index == ATTR_DEVICE_INDEX);
390 *attributes |= MT_DEVICE;
391 }
392
393 uint64_t ap2_bit = (desc >> AP2_SHIFT) & 1U;
394
395 if (ap2_bit == AP2_RW)
396 *attributes |= MT_RW;
397
398 if (ctx->xlat_regime == EL1_EL0_REGIME) {
399 uint64_t ap1_bit = (desc >> AP1_SHIFT) & 1U;
400
401 if (ap1_bit == AP1_ACCESS_UNPRIVILEGED)
402 *attributes |= MT_USER;
403 }
404
405 uint64_t ns_bit = (desc >> NS_SHIFT) & 1U;
406
407 if (ns_bit == 1U)
408 *attributes |= MT_NS;
409
410 uint64_t xn_mask = xlat_arch_regime_get_xn_desc(ctx->xlat_regime);
411
412 if ((desc & xn_mask) == xn_mask) {
413 *attributes |= MT_EXECUTE_NEVER;
414 } else {
415 assert((desc & xn_mask) == 0U);
416 }
417
418 return 0;
419 }
420
421
xlat_get_mem_attributes_ctx(const xlat_ctx_t * ctx,uintptr_t base_va,uint32_t * attr)422 int xlat_get_mem_attributes_ctx(const xlat_ctx_t *ctx, uintptr_t base_va,
423 uint32_t *attr)
424 {
425 return xlat_get_mem_attributes_internal(ctx, base_va, attr,
426 NULL, NULL, NULL);
427 }
428
429
xlat_change_mem_attributes_ctx(const xlat_ctx_t * ctx,uintptr_t base_va,size_t size,uint32_t attr)430 int xlat_change_mem_attributes_ctx(const xlat_ctx_t *ctx, uintptr_t base_va,
431 size_t size, uint32_t attr)
432 {
433 /* Note: This implementation isn't optimized. */
434
435 assert(ctx != NULL);
436 assert(ctx->initialized);
437
438 unsigned long long virt_addr_space_size =
439 (unsigned long long)ctx->va_max_address + 1U;
440 assert(virt_addr_space_size > 0U);
441
442 if (!IS_PAGE_ALIGNED(base_va)) {
443 WARN("%s: Address 0x%lx is not aligned on a page boundary.\n",
444 __func__, base_va);
445 return -EINVAL;
446 }
447
448 if (size == 0U) {
449 WARN("%s: Size is 0.\n", __func__);
450 return -EINVAL;
451 }
452
453 if ((size % PAGE_SIZE) != 0U) {
454 WARN("%s: Size 0x%zx is not a multiple of a page size.\n",
455 __func__, size);
456 return -EINVAL;
457 }
458
459 if (((attr & MT_EXECUTE_NEVER) == 0U) && ((attr & MT_RW) != 0U)) {
460 WARN("%s: Mapping memory as read-write and executable not allowed.\n",
461 __func__);
462 return -EINVAL;
463 }
464
465 size_t pages_count = size / PAGE_SIZE;
466
467 VERBOSE("Changing memory attributes of %zu pages starting from address 0x%lx...\n",
468 pages_count, base_va);
469
470 uintptr_t base_va_original = base_va;
471
472 /*
473 * Sanity checks.
474 */
475 for (unsigned int i = 0U; i < pages_count; ++i) {
476 const uint64_t *entry;
477 uint64_t desc, attr_index;
478 unsigned int level;
479
480 entry = find_xlat_table_entry(base_va,
481 ctx->base_table,
482 ctx->base_table_entries,
483 virt_addr_space_size,
484 &level);
485 if (entry == NULL) {
486 WARN("Address 0x%lx is not mapped.\n", base_va);
487 return -EINVAL;
488 }
489
490 desc = *entry;
491
492 /*
493 * Check that all the required pages are mapped at page
494 * granularity.
495 */
496 if (((desc & DESC_MASK) != PAGE_DESC) ||
497 (level != XLAT_TABLE_LEVEL_MAX)) {
498 WARN("Address 0x%lx is not mapped at the right granularity.\n",
499 base_va);
500 WARN("Granularity is 0x%lx, should be 0x%lx.\n",
501 XLAT_BLOCK_SIZE(level), PAGE_SIZE);
502 return -EINVAL;
503 }
504
505 /*
506 * If the region type is device, it shouldn't be executable.
507 */
508 attr_index = (desc >> ATTR_INDEX_SHIFT) & ATTR_INDEX_MASK;
509 if (attr_index == ATTR_DEVICE_INDEX) {
510 if ((attr & MT_EXECUTE_NEVER) == 0U) {
511 WARN("Setting device memory as executable at address 0x%lx.",
512 base_va);
513 return -EINVAL;
514 }
515 }
516
517 base_va += PAGE_SIZE;
518 }
519
520 /* Restore original value. */
521 base_va = base_va_original;
522
523 for (unsigned int i = 0U; i < pages_count; ++i) {
524
525 uint32_t old_attr = 0U, new_attr;
526 uint64_t *entry = NULL;
527 unsigned int level = 0U;
528 unsigned long long addr_pa = 0ULL;
529
530 (void) xlat_get_mem_attributes_internal(ctx, base_va, &old_attr,
531 &entry, &addr_pa, &level);
532
533 /*
534 * From attr, only MT_RO/MT_RW, MT_EXECUTE/MT_EXECUTE_NEVER and
535 * MT_USER/MT_PRIVILEGED are taken into account. Any other
536 * information is ignored.
537 */
538
539 /* Clean the old attributes so that they can be rebuilt. */
540 new_attr = old_attr & ~(MT_RW | MT_EXECUTE_NEVER | MT_USER);
541
542 /*
543 * Update attributes, but filter out the ones this function
544 * isn't allowed to change.
545 */
546 new_attr |= attr & (MT_RW | MT_EXECUTE_NEVER | MT_USER);
547
548 /*
549 * The break-before-make sequence requires writing an invalid
550 * descriptor and making sure that the system sees the change
551 * before writing the new descriptor.
552 */
553 *entry = INVALID_DESC;
554 #if !HW_ASSISTED_COHERENCY
555 dccvac((uintptr_t)entry);
556 #endif
557 /* Invalidate any cached copy of this mapping in the TLBs. */
558 xlat_arch_tlbi_va(base_va, ctx->xlat_regime);
559
560 /* Ensure completion of the invalidation. */
561 xlat_arch_tlbi_va_sync();
562
563 /* Write new descriptor */
564 *entry = xlat_desc(ctx, new_attr, addr_pa, level);
565 #if !HW_ASSISTED_COHERENCY
566 dccvac((uintptr_t)entry);
567 #endif
568 base_va += PAGE_SIZE;
569 }
570
571 /* Ensure that the last descriptor writen is seen by the system. */
572 dsbish();
573
574 return 0;
575 }
576