1 /*
2 * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef SE_PRIVATE_H
9 #define SE_PRIVATE_H
10
11 #include <stdbool.h>
12 #include <security_engine.h>
13
14 /*
15 * PMC registers
16 */
17
18 /* SC7 context save scratch register for T210 */
19 #define PMC_SCRATCH43_REG_OFFSET U(0x22C)
20
21 /* Secure scratch registers */
22 #define PMC_SECURE_SCRATCH4_OFFSET 0xC0U
23 #define PMC_SECURE_SCRATCH5_OFFSET 0xC4U
24 #define PMC_SECURE_SCRATCH6_OFFSET 0x224U
25 #define PMC_SECURE_SCRATCH7_OFFSET 0x228U
26 #define PMC_SECURE_SCRATCH116_OFFSET 0xB28U
27 #define PMC_SECURE_SCRATCH117_OFFSET 0xB2CU
28 #define PMC_SECURE_SCRATCH120_OFFSET 0xB38U
29 #define PMC_SECURE_SCRATCH121_OFFSET 0xB3CU
30 #define PMC_SECURE_SCRATCH122_OFFSET 0xB40U
31 #define PMC_SECURE_SCRATCH123_OFFSET 0xB44U
32
33 /*
34 * AHB arbitration memory write queue
35 */
36 #define ARAHB_MEM_WRQUE_MST_ID_OFFSET 0xFCU
37 #define ARAHB_MST_ID_SE2_MASK (0x1U << 13)
38 #define ARAHB_MST_ID_SE_MASK (0x1U << 14)
39
40 /**
41 * SE registers
42 */
43 #define TEGRA_SE_AES_KEYSLOT_COUNT 16
44 #define SE_MAX_LAST_BLOCK_SIZE 0xFFFFF
45
46 /* SE Status register */
47 #define SE_STATUS_OFFSET 0x800U
48 #define SE_STATUS_SHIFT 0
49 #define SE_STATUS_IDLE \
50 ((0U) << SE_STATUS_SHIFT)
51 #define SE_STATUS_BUSY \
52 ((1U) << SE_STATUS_SHIFT)
53 #define SE_STATUS(x) \
54 ((x) & ((0x3U) << SE_STATUS_SHIFT))
55
56 #define SE_MEM_INTERFACE_SHIFT 2
57 #define SE_MEM_INTERFACE_IDLE 0
58 #define SE_MEM_INTERFACE_BUSY 1
59 #define SE_MEM_INTERFACE(x) ((x) << SE_STATUS_SHIFT)
60
61 /* SE register definitions */
62 #define SE_SECURITY_REG_OFFSET 0x0
63 #define SE_SECURITY_TZ_LOCK_SOFT_SHIFT 5
64 #define SE_SECURE 0x0
65 #define SE_SECURITY_TZ_LOCK_SOFT(x) ((x) << SE_SECURITY_TZ_LOCK_SOFT_SHIFT)
66
67 #define SE_SEC_ENG_DIS_SHIFT 1
68 #define SE_DISABLE_FALSE 0
69 #define SE_DISABLE_TRUE 1
70 #define SE_SEC_ENG_DISABLE(x)((x) << SE_SEC_ENG_DIS_SHIFT)
71
72 /* SE config register */
73 #define SE_CONFIG_REG_OFFSET 0x14U
74 #define SE_CONFIG_ENC_ALG_SHIFT 12
75 #define SE_CONFIG_ENC_ALG_AES_ENC \
76 ((1U) << SE_CONFIG_ENC_ALG_SHIFT)
77 #define SE_CONFIG_ENC_ALG_RNG \
78 ((2U) << SE_CONFIG_ENC_ALG_SHIFT)
79 #define SE_CONFIG_ENC_ALG_SHA \
80 ((3U) << SE_CONFIG_ENC_ALG_SHIFT)
81 #define SE_CONFIG_ENC_ALG_RSA \
82 ((4U) << SE_CONFIG_ENC_ALG_SHIFT)
83 #define SE_CONFIG_ENC_ALG_NOP \
84 ((0U) << SE_CONFIG_ENC_ALG_SHIFT)
85 #define SE_CONFIG_ENC_ALG(x) \
86 ((x) & ((0xFU) << SE_CONFIG_ENC_ALG_SHIFT))
87
88 #define SE_CONFIG_DEC_ALG_SHIFT 8
89 #define SE_CONFIG_DEC_ALG_AES \
90 ((1U) << SE_CONFIG_DEC_ALG_SHIFT)
91 #define SE_CONFIG_DEC_ALG_NOP \
92 ((0U) << SE_CONFIG_DEC_ALG_SHIFT)
93 #define SE_CONFIG_DEC_ALG(x) \
94 ((x) & ((0xFU) << SE_CONFIG_DEC_ALG_SHIFT))
95
96 #define SE_CONFIG_DST_SHIFT 2
97 #define SE_CONFIG_DST_MEMORY \
98 ((0U) << SE_CONFIG_DST_SHIFT)
99 #define SE_CONFIG_DST_HASHREG \
100 ((1U) << SE_CONFIG_DST_SHIFT)
101 #define SE_CONFIG_DST_KEYTAB \
102 ((2U) << SE_CONFIG_DST_SHIFT)
103 #define SE_CONFIG_DST_SRK \
104 ((3U) << SE_CONFIG_DST_SHIFT)
105 #define SE_CONFIG_DST_RSAREG \
106 ((4U) << SE_CONFIG_DST_SHIFT)
107 #define SE_CONFIG_DST(x) \
108 ((x) & ((0x7U) << SE_CONFIG_DST_SHIFT))
109
110 #define SE_CONFIG_ENC_MODE_SHIFT 24
111 #define SE_CONFIG_ENC_MODE_KEY128 \
112 ((0UL) << SE_CONFIG_ENC_MODE_SHIFT)
113 #define SE_CONFIG_ENC_MODE_KEY192 \
114 ((1UL) << SE_CONFIG_ENC_MODE_SHIFT)
115 #define SE_CONFIG_ENC_MODE_KEY256 \
116 ((2UL) << SE_CONFIG_ENC_MODE_SHIFT)
117 #define SE_CONFIG_ENC_MODE_SHA1 \
118 ((0UL) << SE_CONFIG_ENC_MODE_SHIFT)
119 #define SE_CONFIG_ENC_MODE_SHA224 \
120 ((4UL) << SE_CONFIG_ENC_MODE_SHIFT)
121 #define SE_CONFIG_ENC_MODE_SHA256 \
122 ((5UL) << SE_CONFIG_ENC_MODE_SHIFT)
123 #define SE_CONFIG_ENC_MODE_SHA384 \
124 ((6UL) << SE_CONFIG_ENC_MODE_SHIFT)
125 #define SE_CONFIG_ENC_MODE_SHA512 \
126 ((7UL) << SE_CONFIG_ENC_MODE_SHIFT)
127 #define SE_CONFIG_ENC_MODE(x)\
128 ((x) & ((0xFFUL) << SE_CONFIG_ENC_MODE_SHIFT))
129
130 #define SE_CONFIG_DEC_MODE_SHIFT 16
131 #define SE_CONFIG_DEC_MODE_KEY128 \
132 ((0UL) << SE_CONFIG_DEC_MODE_SHIFT)
133 #define SE_CONFIG_DEC_MODE_KEY192 \
134 ((1UL) << SE_CONFIG_DEC_MODE_SHIFT)
135 #define SE_CONFIG_DEC_MODE_KEY256 \
136 ((2UL) << SE_CONFIG_DEC_MODE_SHIFT)
137 #define SE_CONFIG_DEC_MODE_SHA1 \
138 ((0UL) << SE_CONFIG_DEC_MODE_SHIFT)
139 #define SE_CONFIG_DEC_MODE_SHA224 \
140 ((4UL) << SE_CONFIG_DEC_MODE_SHIFT)
141 #define SE_CONFIG_DEC_MODE_SHA256 \
142 ((5UL) << SE_CONFIG_DEC_MODE_SHIFT)
143 #define SE_CONFIG_DEC_MODE_SHA384 \
144 ((6UL) << SE_CONFIG_DEC_MODE_SHIFT)
145 #define SE_CONFIG_DEC_MODE_SHA512 \
146 ((7UL) << SE_CONFIG_DEC_MODE_SHIFT)
147 #define SE_CONFIG_DEC_MODE(x)\
148 ((x) & ((0xFFUL) << SE_CONFIG_DEC_MODE_SHIFT))
149
150
151 /* DRBG random number generator config */
152 #define SE_RNG_CONFIG_REG_OFFSET 0x340
153
154 #define DRBG_MODE_SHIFT 0
155 #define DRBG_MODE_NORMAL \
156 ((0U) << DRBG_MODE_SHIFT)
157 #define DRBG_MODE_FORCE_INSTANTION \
158 ((1U) << DRBG_MODE_SHIFT)
159 #define DRBG_MODE_FORCE_RESEED \
160 ((2U) << DRBG_MODE_SHIFT)
161 #define SE_RNG_CONFIG_MODE(x) \
162 ((x) & ((0x3U) << DRBG_MODE_SHIFT))
163
164 #define DRBG_SRC_SHIFT 2
165 #define DRBG_SRC_NONE \
166 ((0U) << DRBG_SRC_SHIFT)
167 #define DRBG_SRC_ENTROPY \
168 ((1U) << DRBG_SRC_SHIFT)
169 #define DRBG_SRC_LFSR \
170 ((2U) << DRBG_SRC_SHIFT)
171 #define SE_RNG_SRC_CONFIG_MODE(x) \
172 ((x) & ((0x3U) << DRBG_SRC_SHIFT))
173
174 /* DRBG random number generator entropy config */
175
176 #define SE_RNG_SRC_CONFIG_REG_OFFSET 0x344U
177
178 #define DRBG_RO_ENT_SRC_SHIFT 1
179 #define DRBG_RO_ENT_SRC_ENABLE \
180 ((1U) << DRBG_RO_ENT_SRC_SHIFT)
181 #define DRBG_RO_ENT_SRC_DISABLE \
182 ((0U) << DRBG_RO_ENT_SRC_SHIFT)
183 #define SE_RNG_SRC_CONFIG_RO_ENT_SRC(x) \
184 ((x) & ((0x1U) << DRBG_RO_ENT_SRC_SHIFT))
185
186 #define DRBG_RO_ENT_SRC_LOCK_SHIFT 0
187 #define DRBG_RO_ENT_SRC_LOCK_ENABLE \
188 ((1U) << DRBG_RO_ENT_SRC_LOCK_SHIFT)
189 #define DRBG_RO_ENT_SRC_LOCK_DISABLE \
190 ((0U) << DRBG_RO_ENT_SRC_LOCK_SHIFT)
191 #define SE_RNG_SRC_CONFIG_RO_ENT_SRC_LOCK(x) \
192 ((x) & ((0x1U) << DRBG_RO_ENT_SRC_LOCK_SHIFT))
193
194 #define DRBG_RO_ENT_IGNORE_MEM_SHIFT 12
195 #define DRBG_RO_ENT_IGNORE_MEM_ENABLE \
196 ((1U) << DRBG_RO_ENT_IGNORE_MEM_SHIFT)
197 #define DRBG_RO_ENT_IGNORE_MEM_DISABLE \
198 ((0U) << DRBG_RO_ENT_IGNORE_MEM_SHIFT)
199 #define SE_RNG_SRC_CONFIG_RO_ENT_IGNORE_MEM(x) \
200 ((x) & ((0x1U) << DRBG_RO_ENT_IGNORE_MEM_SHIFT))
201
202 #define SE_RNG_RESEED_INTERVAL_REG_OFFSET 0x348
203
204 /* SE CRYPTO */
205 #define SE_CRYPTO_REG_OFFSET 0x304
206 #define SE_CRYPTO_HASH_SHIFT 0
207 #define SE_CRYPTO_HASH_DISABLE \
208 ((0U) << SE_CRYPTO_HASH_SHIFT)
209 #define SE_CRYPTO_HASH_ENABLE \
210 ((1U) << SE_CRYPTO_HASH_SHIFT)
211
212 #define SE_CRYPTO_XOR_POS_SHIFT 1
213 #define SE_CRYPTO_XOR_BYPASS \
214 ((0U) << SE_CRYPTO_XOR_POS_SHIFT)
215 #define SE_CRYPTO_XOR_TOP \
216 ((2U) << SE_CRYPTO_XOR_POS_SHIFT)
217 #define SE_CRYPTO_XOR_BOTTOM \
218 ((3U) << SE_CRYPTO_XOR_POS_SHIFT)
219
220 #define SE_CRYPTO_INPUT_SEL_SHIFT 3
221 #define SE_CRYPTO_INPUT_AHB \
222 ((0U) << SE_CRYPTO_INPUT_SEL_SHIFT)
223 #define SE_CRYPTO_INPUT_RANDOM \
224 ((1U) << SE_CRYPTO_INPUT_SEL_SHIFT)
225 #define SE_CRYPTO_INPUT_AESOUT \
226 ((2U) << SE_CRYPTO_INPUT_SEL_SHIFT)
227 #define SE_CRYPTO_INPUT_LNR_CTR \
228 ((3U) << SE_CRYPTO_INPUT_SEL_SHIFT)
229
230 #define SE_CRYPTO_VCTRAM_SEL_SHIFT 5
231 #define SE_CRYPTO_VCTRAM_AHB \
232 ((0U) << SE_CRYPTO_VCTRAM_SEL_SHIFT)
233 #define SE_CRYPTO_VCTRAM_AESOUT \
234 ((2U) << SE_CRYPTO_VCTRAM_SEL_SHIFT)
235 #define SE_CRYPTO_VCTRAM_PREVAHB \
236 ((3U) << SE_CRYPTO_VCTRAM_SEL_SHIFT)
237
238 #define SE_CRYPTO_IV_SEL_SHIFT 7
239 #define SE_CRYPTO_IV_ORIGINAL \
240 ((0U) << SE_CRYPTO_IV_SEL_SHIFT)
241 #define SE_CRYPTO_IV_UPDATED \
242 ((1U) << SE_CRYPTO_IV_SEL_SHIFT)
243
244 #define SE_CRYPTO_CORE_SEL_SHIFT 8
245 #define SE_CRYPTO_CORE_DECRYPT \
246 ((0U) << SE_CRYPTO_CORE_SEL_SHIFT)
247 #define SE_CRYPTO_CORE_ENCRYPT \
248 ((1U) << SE_CRYPTO_CORE_SEL_SHIFT)
249
250 #define SE_CRYPTO_KEY_INDEX_SHIFT 24
251 #define SE_CRYPTO_KEY_INDEX(x) (x << SE_CRYPTO_KEY_INDEX_SHIFT)
252
253 #define SE_CRYPTO_MEMIF_AHB \
254 ((0U) << SE_CRYPTO_MEMIF_SHIFT)
255 #define SE_CRYPTO_MEMIF_MCCIF \
256 ((1U) << SE_CRYPTO_MEMIF_SHIFT)
257 #define SE_CRYPTO_MEMIF_SHIFT 31
258
259 /* KEY TABLE */
260 #define SE_KEYTABLE_REG_OFFSET 0x31C
261
262 /* KEYIV PKT - key slot */
263 #define SE_KEYTABLE_SLOT_SHIFT 4
264 #define SE_KEYTABLE_SLOT(x) (x << SE_KEYTABLE_SLOT_SHIFT)
265
266 /* KEYIV PKT - KEYIV select */
267 #define SE_KEYIV_PKT_KEYIV_SEL_SHIFT 3
268 #define SE_CRYPTO_KEYIV_KEY \
269 ((0U) << SE_KEYIV_PKT_KEYIV_SEL_SHIFT)
270 #define SE_CRYPTO_KEYIV_IVS \
271 ((1U) << SE_KEYIV_PKT_KEYIV_SEL_SHIFT)
272
273 /* KEYIV PKT - IV select */
274 #define SE_KEYIV_PKT_IV_SEL_SHIFT 2
275 #define SE_CRYPTO_KEYIV_IVS_OIV \
276 ((0U) << SE_KEYIV_PKT_IV_SEL_SHIFT)
277 #define SE_CRYPTO_KEYIV_IVS_UIV \
278 ((1U) << SE_KEYIV_PKT_IV_SEL_SHIFT)
279
280 /* KEYIV PKT - key word */
281 #define SE_KEYIV_PKT_KEY_WORD_SHIFT 0
282 #define SE_KEYIV_PKT_KEY_WORD(x) \
283 ((x) << SE_KEYIV_PKT_KEY_WORD_SHIFT)
284
285 /* KEYIV PKT - iv word */
286 #define SE_KEYIV_PKT_IV_WORD_SHIFT 0
287 #define SE_KEYIV_PKT_IV_WORD(x) \
288 ((x) << SE_KEYIV_PKT_IV_WORD_SHIFT)
289
290 /* SE OPERATION */
291 #define SE_OPERATION_REG_OFFSET 0x8U
292 #define SE_OPERATION_SHIFT 0
293 #define SE_OP_ABORT \
294 ((0x0U) << SE_OPERATION_SHIFT)
295 #define SE_OP_START \
296 ((0x1U) << SE_OPERATION_SHIFT)
297 #define SE_OP_RESTART \
298 ((0x2U) << SE_OPERATION_SHIFT)
299 #define SE_OP_CTX_SAVE \
300 ((0x3U) << SE_OPERATION_SHIFT)
301 #define SE_OP_RESTART_IN \
302 ((0x4U) << SE_OPERATION_SHIFT)
303 #define SE_OPERATION(x) \
304 ((x) & ((0x7U) << SE_OPERATION_SHIFT))
305
306 /* SE CONTEXT */
307 #define SE_CTX_SAVE_CONFIG_REG_OFFSET 0x70
308 #define SE_CTX_SAVE_WORD_QUAD_SHIFT 0
309 #define SE_CTX_SAVE_WORD_QUAD(x) \
310 (x << SE_CTX_SAVE_WORD_QUAD_SHIFT)
311 #define SE_CTX_SAVE_WORD_QUAD_KEYS_0_3 \
312 ((0U) << SE_CTX_SAVE_WORD_QUAD_SHIFT)
313 #define SE_CTX_SAVE_WORD_QUAD_KEYS_4_7 \
314 ((1U) << SE_CTX_SAVE_WORD_QUAD_SHIFT)
315 #define SE_CTX_SAVE_WORD_QUAD_ORIG_IV \
316 ((2U) << SE_CTX_SAVE_WORD_QUAD_SHIFT)
317 #define SE_CTX_SAVE_WORD_QUAD_UPD_IV \
318 ((3U) << SE_CTX_SAVE_WORD_QUAD_SHIFT)
319
320 #define SE_CTX_SAVE_KEY_INDEX_SHIFT 8
321 #define SE_CTX_SAVE_KEY_INDEX(x) (x << SE_CTX_SAVE_KEY_INDEX_SHIFT)
322
323 #define SE_CTX_SAVE_STICKY_WORD_QUAD_SHIFT 24
324 #define SE_CTX_SAVE_STICKY_WORD_QUAD_STICKY_0_3 \
325 ((0U) << SE_CTX_SAVE_STICKY_WORD_QUAD_SHIFT)
326 #define SE_CTX_SAVE_STICKY_WORD_QUAD_STICKY_4_7 \
327 ((1U) << SE_CTX_SAVE_STICKY_WORD_QUAD_SHIFT)
328 #define SE_CTX_SAVE_STICKY_WORD_QUAD(x) \
329 (x << SE_CTX_SAVE_STICKY_WORD_QUAD_SHIFT)
330
331 #define SE_CTX_SAVE_SRC_SHIFT 29
332 #define SE_CTX_SAVE_SRC_STICKY_BITS \
333 ((0U) << SE_CTX_SAVE_SRC_SHIFT)
334 #define SE_CTX_SAVE_SRC_RSA_KEYTABLE \
335 ((1U) << SE_CTX_SAVE_SRC_SHIFT)
336 #define SE_CTX_SAVE_SRC_AES_KEYTABLE \
337 ((2U) << SE_CTX_SAVE_SRC_SHIFT)
338 #define SE_CTX_SAVE_SRC_PKA1_STICKY_BITS \
339 ((3U) << SE_CTX_SAVE_SRC_SHIFT)
340 #define SE_CTX_SAVE_SRC_MEM \
341 ((4U) << SE_CTX_SAVE_SRC_SHIFT)
342 #define SE_CTX_SAVE_SRC_SRK \
343 ((6U) << SE_CTX_SAVE_SRC_SHIFT)
344 #define SE_CTX_SAVE_SRC_PKA1_KEYTABLE \
345 ((7U) << SE_CTX_SAVE_SRC_SHIFT)
346
347 #define SE_CTX_STICKY_WORD_QUAD_SHIFT 24
348 #define SE_CTX_STICKY_WORD_QUAD_WORDS_0_3 \
349 ((0U) << SE_CTX_STICKY_WORD_QUAD_SHIFT)
350 #define SE_CTX_STICKY_WORD_QUAD_WORDS_4_7 \
351 ((1U) << SE_CTX_STICKY_WORD_QUAD_SHIFT)
352 #define SE_CTX_STICKY_WORD_QUAD(x) (x << SE_CTX_STICKY_WORD_QUAD_SHIFT)
353
354 #define SE_CTX_SAVE_RSA_KEY_INDEX_SHIFT 16
355 #define SE_CTX_SAVE_RSA_KEY_INDEX(x) \
356 (x << SE_CTX_SAVE_RSA_KEY_INDEX_SHIFT)
357
358 #define SE_CTX_RSA_WORD_QUAD_SHIFT 12
359 #define SE_CTX_RSA_WORD_QUAD(x) \
360 (x << SE_CTX_RSA_WORD_QUAD_SHIFT)
361
362 #define SE_CTX_PKA1_WORD_QUAD_L_SHIFT 0
363 #define SE_CTX_PKA1_WORD_QUAD_L_SIZE \
364 ((true ? 4:0) - \
365 (false ? 4:0) + 1)
366 #define SE_CTX_PKA1_WORD_QUAD_L(x)\
367 (((x) << SE_CTX_PKA1_WORD_QUAD_L_SHIFT) & 0x1f)
368
369 #define SE_CTX_PKA1_WORD_QUAD_H_SHIFT 12
370 #define SE_CTX_PKA1_WORD_QUAD_H(x)\
371 ((((x) >> SE_CTX_PKA1_WORD_QUAD_L_SIZE) & 0xf) \
372 << SE_CTX_PKA1_WORD_QUAD_H_SHIFT)
373
374 #define SE_RSA_KEY_INDEX_SLOT0_EXP 0
375 #define SE_RSA_KEY_INDEX_SLOT0_MOD 1
376 #define SE_RSA_KEY_INDEX_SLOT1_EXP 2
377 #define SE_RSA_KEY_INDEX_SLOT1_MOD 3
378
379
380 /* SE_CTX_SAVE_AUTO */
381 #define SE_CTX_SAVE_AUTO_REG_OFFSET 0x74U
382
383 /* Enable */
384 #define SE_CTX_SAVE_AUTO_ENABLE_SHIFT 0
385 #define SE_CTX_SAVE_AUTO_DIS \
386 ((0U) << SE_CTX_SAVE_AUTO_ENABLE_SHIFT)
387 #define SE_CTX_SAVE_AUTO_EN \
388 ((1U) << SE_CTX_SAVE_AUTO_ENABLE_SHIFT)
389 #define SE_CTX_SAVE_AUTO_ENABLE(x) \
390 ((x) & ((0x1U) << SE_CTX_SAVE_AUTO_ENABLE_SHIFT))
391
392 /* Lock */
393 #define SE_CTX_SAVE_AUTO_LOCK_SHIFT 8
394 #define SE_CTX_SAVE_AUTO_LOCK_EN \
395 ((1U) << SE_CTX_SAVE_AUTO_LOCK_SHIFT)
396 #define SE_CTX_SAVE_AUTO_LOCK_DIS \
397 ((0U) << SE_CTX_SAVE_AUTO_LOCK_SHIFT)
398 #define SE_CTX_SAVE_AUTO_LOCK(x) \
399 ((x) & ((0x1U) << SE_CTX_SAVE_AUTO_LOCK_SHIFT))
400
401 /* Current context save number of blocks*/
402 #define SE_CTX_SAVE_AUTO_CURR_CNT_SHIFT 16
403 #define SE_CTX_SAVE_AUTO_CURR_CNT_MASK 0x3FFU
404 #define SE_CTX_SAVE_GET_BLK_COUNT(x) \
405 (((x) >> SE_CTX_SAVE_AUTO_CURR_CNT_SHIFT) & \
406 SE_CTX_SAVE_AUTO_CURR_CNT_MASK)
407
408 #define SE_CTX_SAVE_SIZE_BLOCKS_SE1 133
409 #define SE_CTX_SAVE_SIZE_BLOCKS_SE2 646
410
411 /* SE TZRAM OPERATION - only for SE1 */
412 #define SE_TZRAM_OPERATION 0x540U
413
414 #define SE_TZRAM_OP_MODE_SHIFT 1
415 #define SE_TZRAM_OP_COMMAND_INIT 1
416 #define SE_TZRAM_OP_COMMAND_SHIFT 0
417 #define SE_TZRAM_OP_MODE_SAVE \
418 ((0U) << SE_TZRAM_OP_MODE_SHIFT)
419 #define SE_TZRAM_OP_MODE_RESTORE \
420 ((1U) << SE_TZRAM_OP_MODE_SHIFT)
421 #define SE_TZRAM_OP_MODE(x) \
422 ((x) & ((0x1U) << SE_TZRAM_OP_MODE_SHIFT))
423
424 #define SE_TZRAM_OP_BUSY_SHIFT 2
425 #define SE_TZRAM_OP_BUSY_OFF \
426 ((0U) << SE_TZRAM_OP_BUSY_SHIFT)
427 #define SE_TZRAM_OP_BUSY_ON \
428 ((1U) << SE_TZRAM_OP_BUSY_SHIFT)
429 #define SE_TZRAM_OP_BUSY(x) \
430 ((x) & ((0x1U) << SE_TZRAM_OP_BUSY_SHIFT))
431
432 #define SE_TZRAM_OP_REQ_SHIFT 0
433 #define SE_TZRAM_OP_REQ_IDLE \
434 ((0U) << SE_TZRAM_OP_REQ_SHIFT)
435 #define SE_TZRAM_OP_REQ_INIT \
436 ((1U) << SE_TZRAM_OP_REQ_SHIFT)
437 #define SE_TZRAM_OP_REQ(x) \
438 ((x) & ((0x1U) << SE_TZRAM_OP_REQ_SHIFT))
439
440 /* SE Interrupt */
441 #define SE_INT_ENABLE_REG_OFFSET U(0xC)
442 #define SE_INT_STATUS_REG_OFFSET 0x10U
443 #define SE_INT_OP_DONE_SHIFT 4
444 #define SE_INT_OP_DONE_CLEAR \
445 ((0U) << SE_INT_OP_DONE_SHIFT)
446 #define SE_INT_OP_DONE_ACTIVE \
447 ((1U) << SE_INT_OP_DONE_SHIFT)
448 #define SE_INT_OP_DONE(x) \
449 ((x) & ((0x1U) << SE_INT_OP_DONE_SHIFT))
450
451 /* SE TZRAM SECURITY */
452 #define SE_TZRAM_SEC_REG_OFFSET 0x4
453
454 #define SE_TZRAM_SEC_SETTING_SHIFT 0
455 #define SE_TZRAM_SECURE \
456 ((0UL) << SE_TZRAM_SEC_SETTING_SHIFT)
457 #define SE_TZRAM_NONSECURE \
458 ((1UL) << SE_TZRAM_SEC_SETTING_SHIFT)
459 #define SE_TZRAM_SEC_SETTING(x) \
460 ((x) & ((0x1UL) << SE_TZRAM_SEC_SETTING_SHIFT))
461
462 /* PKA1 KEY SLOTS */
463 #define TEGRA_SE_PKA1_KEYSLOT_COUNT 4
464
465
466 /* SE error status */
467 #define SE_ERR_STATUS_REG_OFFSET 0x804U
468 #define SE_CRYPTO_KEYTABLE_DST_REG_OFFSET 0x330
469 #define SE_CRYPTO_KEYTABLE_DST_WORD_QUAD_SHIFT 0
470 #define SE_CRYPTO_KEYTABLE_DST_WORD_QUAD(x) \
471 (x << SE_CRYPTO_KEYTABLE_DST_WORD_QUAD_SHIFT)
472
473 #define SE_KEY_INDEX_SHIFT 8
474 #define SE_CRYPTO_KEYTABLE_DST_KEY_INDEX(x) (x << SE_KEY_INDEX_SHIFT)
475
476
477 /* SE linked list (LL) register */
478 #define SE_IN_LL_ADDR_REG_OFFSET 0x18U
479 #define SE_OUT_LL_ADDR_REG_OFFSET 0x24U
480 #define SE_BLOCK_COUNT_REG_OFFSET 0x318U
481
482 /* AES data sizes */
483 #define TEGRA_SE_KEY_256_SIZE 32
484 #define TEGRA_SE_KEY_192_SIZE 24
485 #define TEGRA_SE_KEY_128_SIZE 16
486 #define TEGRA_SE_AES_BLOCK_SIZE 16
487 #define TEGRA_SE_AES_MIN_KEY_SIZE 16
488 #define TEGRA_SE_AES_MAX_KEY_SIZE 32
489 #define TEGRA_SE_AES_IV_SIZE 16
490
491 #define TEGRA_SE_RNG_IV_SIZE 16
492 #define TEGRA_SE_RNG_DT_SIZE 16
493 #define TEGRA_SE_RNG_KEY_SIZE 16
494 #define TEGRA_SE_RNG_SEED_SIZE (TEGRA_SE_RNG_IV_SIZE + \
495 TEGRA_SE_RNG_KEY_SIZE + \
496 TEGRA_SE_RNG_DT_SIZE)
497 #define TEGRA_SE_RSA512_DIGEST_SIZE 64
498 #define TEGRA_SE_RSA1024_DIGEST_SIZE 128
499 #define TEGRA_SE_RSA1536_DIGEST_SIZE 192
500 #define TEGRA_SE_RSA2048_DIGEST_SIZE 256
501
502 #define SE_KEY_TABLE_ACCESS_REG_OFFSET 0x284
503 #define SE_KEY_READ_DISABLE_SHIFT 0
504
505 #define SE_CTX_BUFER_SIZE 1072
506 #define SE_CTX_DRBG_BUFER_SIZE 2112
507
508 /* SE blobs size in bytes */
509 #define SE_CTX_SAVE_RSA_KEY_LENGTH 1024
510 #define SE_CTX_SAVE_RANDOM_DATA_SIZE 16
511 #define SE_CTX_SAVE_STICKY_BITS_SIZE 16
512 #define SE2_CONTEXT_SAVE_PKA1_STICKY_BITS_LENGTH 16
513 #define SE2_CONTEXT_SAVE_PKA1_KEYS_LENGTH 8192
514 #define SE_CTX_KNOWN_PATTERN_SIZE 16
515 #define SE_CTX_KNOWN_PATTERN_SIZE_WORDS (SE_CTX_KNOWN_PATTERN_SIZE/4)
516
517 /* SE RSA */
518 #define TEGRA_SE_RSA_KEYSLOT_COUNT 2
519 #define SE_RSA_KEY_SIZE_REG_OFFSET 0x404
520 #define SE_RSA_EXP_SIZE_REG_OFFSET 0x408
521 #define SE_RSA_MAX_EXP_BIT_SIZE 2048
522 #define SE_RSA_MAX_EXP_SIZE32 \
523 (SE_RSA_MAX_EXP_BIT_SIZE >> 5)
524 #define SE_RSA_MAX_MOD_BIT_SIZE 2048
525 #define SE_RSA_MAX_MOD_SIZE32 \
526 (SE_RSA_MAX_MOD_BIT_SIZE >> 5)
527
528 /* SE_RSA_KEYTABLE_ADDR */
529 #define SE_RSA_KEYTABLE_ADDR 0x420
530 #define RSA_KEY_PKT_WORD_ADDR_SHIFT 0
531 #define RSA_KEY_PKT_EXPMOD_SEL_SHIFT \
532 ((6U) << RSA_KEY_PKT_WORD_ADDR_SHIFT)
533 #define RSA_KEY_MOD \
534 ((1U) << RSA_KEY_PKT_EXPMOD_SEL_SHIFT)
535 #define RSA_KEY_EXP \
536 ((0U) << RSA_KEY_PKT_EXPMOD_SEL_SHIFT)
537 #define RSA_KEY_PKT_SLOT_SHIFT 7
538 #define RSA_KEY_SLOT_1 \
539 ((0U) << RSA_KEY_PKT_SLOT_SHIFT)
540 #define RSA_KEY_SLOT_2 \
541 ((1U) << RSA_KEY_PKT_SLOT_SHIFT)
542 #define RSA_KEY_PKT_INPUT_MODE_SHIFT 8
543 #define RSA_KEY_REG_INPUT \
544 ((0U) << RSA_KEY_PKT_INPUT_MODE_SHIFT)
545 #define RSA_KEY_DMA_INPUT \
546 ((1U) << RSA_KEY_PKT_INPUT_MODE_SHIFT)
547
548 /* SE_RSA_KEYTABLE_DATA */
549 #define SE_RSA_KEYTABLE_DATA 0x424
550
551 /* SE_RSA_CONFIG register */
552 #define SE_RSA_CONFIG 0x400
553 #define RSA_KEY_SLOT_SHIFT 24
554 #define RSA_KEY_SLOT(x) \
555 ((x) << RSA_KEY_SLOT_SHIFT)
556
557 /*******************************************************************************
558 * Structure definition
559 ******************************************************************************/
560
561 /* SE context blob */
562 #pragma pack(push, 1)
563 typedef struct tegra_aes_key_slot {
564 /* 0 - 7 AES key */
565 uint32_t key[8];
566 /* 8 - 11 Original IV */
567 uint32_t oiv[4];
568 /* 12 - 15 Updated IV */
569 uint32_t uiv[4];
570 } tegra_se_aes_key_slot_t;
571 #pragma pack(pop)
572
573 #pragma pack(push, 1)
574 typedef struct tegra_se_context {
575 /* random number */
576 unsigned char rand_data[SE_CTX_SAVE_RANDOM_DATA_SIZE];
577 /* Sticky bits */
578 unsigned char sticky_bits[SE_CTX_SAVE_STICKY_BITS_SIZE * 2];
579 /* AES key slots */
580 tegra_se_aes_key_slot_t key_slots[TEGRA_SE_AES_KEYSLOT_COUNT];
581 /* RSA key slots */
582 unsigned char rsa_keys[SE_CTX_SAVE_RSA_KEY_LENGTH];
583 } tegra_se_context_t;
584 #pragma pack(pop)
585
586 /* PKA context blob */
587 #pragma pack(push, 1)
588 typedef struct tegra_pka_context {
589 unsigned char sticky_bits[SE2_CONTEXT_SAVE_PKA1_STICKY_BITS_LENGTH];
590 unsigned char pka_keys[SE2_CONTEXT_SAVE_PKA1_KEYS_LENGTH];
591 } tegra_pka_context_t;
592 #pragma pack(pop)
593
594 /* SE context blob */
595 #pragma pack(push, 1)
596 typedef struct tegra_se_context_blob {
597 /* SE context */
598 tegra_se_context_t se_ctx;
599 /* Known Pattern */
600 unsigned char known_pattern[SE_CTX_KNOWN_PATTERN_SIZE];
601 } tegra_se_context_blob_t;
602 #pragma pack(pop)
603
604 /* SE2 and PKA1 context blob */
605 #pragma pack(push, 1)
606 typedef struct tegra_se2_context_blob {
607 /* SE2 context */
608 tegra_se_context_t se_ctx;
609 /* PKA1 context */
610 tegra_pka_context_t pka_ctx;
611 /* Known Pattern */
612 unsigned char known_pattern[SE_CTX_KNOWN_PATTERN_SIZE];
613 } tegra_se2_context_blob_t;
614 #pragma pack(pop)
615
616 /* SE AES key type 128bit, 192bit, 256bit */
617 typedef enum {
618 SE_AES_KEY128,
619 SE_AES_KEY192,
620 SE_AES_KEY256,
621 } tegra_se_aes_key_type_t;
622
623 /* SE RSA key slot */
624 typedef struct tegra_se_rsa_key_slot {
625 /* 0 - 63 exponent key */
626 uint32_t exponent[SE_RSA_MAX_EXP_SIZE32];
627 /* 64 - 127 modulus key */
628 uint32_t modulus[SE_RSA_MAX_MOD_SIZE32];
629 } tegra_se_rsa_key_slot_t;
630
631
632 /*******************************************************************************
633 * Inline functions definition
634 ******************************************************************************/
635
tegra_se_read_32(const tegra_se_dev_t * dev,uint32_t offset)636 static inline uint32_t tegra_se_read_32(const tegra_se_dev_t *dev, uint32_t offset)
637 {
638 return mmio_read_32(dev->se_base + offset);
639 }
640
tegra_se_write_32(const tegra_se_dev_t * dev,uint32_t offset,uint32_t val)641 static inline void tegra_se_write_32(const tegra_se_dev_t *dev, uint32_t offset, uint32_t val)
642 {
643 mmio_write_32(dev->se_base + offset, val);
644 }
645
tegra_pka_read_32(tegra_pka_dev_t * dev,uint32_t offset)646 static inline uint32_t tegra_pka_read_32(tegra_pka_dev_t *dev, uint32_t offset)
647 {
648 return mmio_read_32(dev->pka_base + offset);
649 }
650
tegra_pka_write_32(tegra_pka_dev_t * dev,uint32_t offset,uint32_t val)651 static inline void tegra_pka_write_32(tegra_pka_dev_t *dev, uint32_t offset,
652 uint32_t val)
653 {
654 mmio_write_32(dev->pka_base + offset, val);
655 }
656
657 /*******************************************************************************
658 * Prototypes
659 ******************************************************************************/
660 int tegra_se_start_normal_operation(const tegra_se_dev_t *, uint32_t);
661 int tegra_se_start_ctx_save_operation(const tegra_se_dev_t *, uint32_t);
662
663 #endif /* SE_PRIVATE_H */
664