1 /*
2  * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef RK3288_DEF_H
8 #define RK3288_DEF_H
9 
10 /* Special value used to verify platform parameters from BL2 to BL31 */
11 #define RK_BL31_PLAT_PARAM_VAL	0x0f1e2d3c4b5a6978ULL
12 
13 #define SIZE_K(n)		((n) * 1024)
14 #define SIZE_M(n)		((n) * 1024 * 1024)
15 
16 #define SRAM_TEXT_LIMIT		(4 * 1024)
17 #define SRAM_DATA_LIMIT		(4 * 1024)
18 
19 #define DDR_PCTL0_BASE		0xff610000
20 #define DDR_PCTL0_SIZE		SIZE_K(64)
21 
22 #define DDR_PHY0_BASE		0xff620000
23 #define DDR_PHY0_SIZE		SIZE_K(64)
24 
25 #define DDR_PCTL1_BASE		0xff630000
26 #define DDR_PCTL1_SIZE		SIZE_K(64)
27 
28 #define DDR_PHY1_BASE		0xff640000
29 #define DDR_PHY1_SIZE		SIZE_K(64)
30 
31 #define UART0_BASE		0xff180000
32 #define UART0_SIZE		SIZE_K(64)
33 
34 #define UART1_BASE		0xff190000
35 #define UART1_SIZE		SIZE_K(64)
36 
37 #define UART2_BASE		0xff690000
38 #define UART2_SIZE		SIZE_K(64)
39 
40 #define UART3_BASE		0xff1b0000
41 #define UART3_SIZE		SIZE_K(64)
42 
43 #define UART4_BASE		0xff1c0000
44 #define UART4_SIZE		SIZE_K(64)
45 
46 /* 96k instead of 64k? */
47 #define SRAM_BASE		0xff700000
48 #define SRAM_SIZE		SIZE_K(64)
49 
50 #define PMUSRAM_BASE		0xff720000
51 #define PMUSRAM_SIZE		SIZE_K(4)
52 #define PMUSRAM_RSIZE		SIZE_K(4)
53 
54 #define PMU_BASE		0xff730000
55 #define PMU_SIZE		SIZE_K(64)
56 
57 #define SGRF_BASE		0xff740000
58 #define SGRF_SIZE		SIZE_K(64)
59 
60 #define CRU_BASE		0xff760000
61 #define CRU_SIZE		SIZE_K(64)
62 
63 #define GRF_BASE		0xff770000
64 #define GRF_SIZE		SIZE_K(64)
65 
66 /* timer 6+7 can be set as secure in SGRF */
67 #define STIME_BASE		0xff810000
68 #define STIME_SIZE		SIZE_K(64)
69 
70 #define SERVICE_BUS_BASE	0xffac0000
71 #define SERVICE_BUS_SIZE	SIZE_K(64)
72 
73 #define TZPC_BASE		0xffb00000
74 #define TZPC_SIZE		SIZE_K(64)
75 
76 #define GIC400_BASE		0xffc00000
77 #define GIC400_SIZE		SIZE_K(64)
78 
79 #define CORE_AXI_BUS_BASE	0xffd00000
80 #define CORE_AXI_BUS_SIZE	SIZE_M(1)
81 
82 #define COLD_BOOT_BASE		0xffff0000
83 /**************************************************************************
84  * UART related constants
85  **************************************************************************/
86 #define RK3288_BAUDRATE		115200
87 #define RK3288_UART_CLOCK	24000000
88 
89 /******************************************************************************
90  * System counter frequency related constants
91  ******************************************************************************/
92 #define SYS_COUNTER_FREQ_IN_TICKS	24000000
93 
94 /******************************************************************************
95  * GIC-400 & interrupt handling related constants
96  ******************************************************************************/
97 
98 /* Base rk_platform compatible GIC memory map */
99 #define RK3288_GICD_BASE		(GIC400_BASE + 0x1000)
100 #define RK3288_GICC_BASE		(GIC400_BASE + 0x2000)
101 #define RK3288_GICR_BASE		0	/* no GICR in GIC-400 */
102 
103 /******************************************************************************
104  * sgi, ppi
105  ******************************************************************************/
106 #define RK_IRQ_SEC_PHY_TIMER	29
107 
108 /* what are these, and are they present on rk3288? */
109 #define RK_IRQ_SEC_SGI_0	8
110 #define RK_IRQ_SEC_SGI_1	9
111 #define RK_IRQ_SEC_SGI_2	10
112 #define RK_IRQ_SEC_SGI_3	11
113 #define RK_IRQ_SEC_SGI_4	12
114 #define RK_IRQ_SEC_SGI_5	13
115 #define RK_IRQ_SEC_SGI_6	14
116 #define RK_IRQ_SEC_SGI_7	15
117 
118 /*
119  * Define a list of Group 0 interrupts.
120  */
121 #define PLAT_RK_GICV2_G0_IRQS						\
122 	INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,	\
123 		       GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),		\
124 	INTR_PROP_DESC(RK_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY,	\
125 		       GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
126 
127 #endif /* RK3288_DEF_H */
128