1Performance Monitoring Unit
2===========================
3
4The Performance Monitoring Unit (PMU) allows recording of architectural and
5microarchitectural events for profiling purposes.
6
7This document gives an overview of the PMU counter configuration to assist with
8implementation and to complement the PMU security guidelines given in the
9:ref:`Secure Development Guidelines` document.
10
11.. note::
12   This section applies to Armv8-A implementations which have version 3
13   of the Performance Monitors Extension (PMUv3).
14
15PMU Counters
16------------
17
18The PMU makes 32 counters available at all privilege levels:
19
20-  31 programmable event counters: ``PMEVCNTR<n>``, where ``n`` is ``0`` to
21   ``30``.
22-  A dedicated cycle counter: ``PMCCNTR``.
23
24Architectural mappings
25~~~~~~~~~~~~~~~~~~~~~~
26
27+--------------+---------+----------------------------+
28| Counters     | State   | System Register Name       |
29+==============+=========+============================+
30|              | AArch64 | ``PMEVCNTR<n>_EL0[63*:0]`` |
31| Programmable +---------+----------------------------+
32|              | AArch32 | ``PMEVCNTR<n>[31:0]``      |
33+--------------+---------+----------------------------+
34|              | AArch64 | ``PMCCNTR_EL0[63:0]``      |
35| Cycle        +---------+----------------------------+
36|              | AArch32 | ``PMCCNTR[63:0]``          |
37+--------------+---------+----------------------------+
38
39.. note::
40   Bits [63:32] are only available if ARMv8.5-PMU is implemented. Refer to the
41   `Arm ARM`_ for a detailed description of ARMv8.5-PMU features.
42
43Configuring the PMU for counting events
44---------------------------------------
45
46Each programmable counter has an associated register, ``PMEVTYPER<n>`` which
47configures it. The cycle counter has the ``PMCCFILTR_EL0`` register, which has
48an identical function and bit field layout as ``PMEVTYPER<n>``. In addition,
49the counters are enabled (permitted to increment) via the ``PMCNTENSET`` and
50``PMCR`` registers. These can be accessed at all privilege levels.
51
52Architectural mappings
53~~~~~~~~~~~~~~~~~~~~~~
54
55+-----------------------------+------------------------+
56| AArch64                     | AArch32                |
57+=============================+========================+
58| ``PMEVTYPER<n>_EL0[63*:0]`` | ``PMEVTYPER<n>[31:0]`` |
59+-----------------------------+------------------------+
60| ``PMCCFILTR_EL0[63*:0]``    | ``PMCCFILTR[31:0]``    |
61+-----------------------------+------------------------+
62| ``PMCNTENSET_EL0[63*:0]``   | ``PMCNTENSET[31:0]``   |
63+-----------------------------+------------------------+
64| ``PMCR_EL0[63*:0]``         | ``PMCR[31:0]``         |
65+-----------------------------+------------------------+
66
67.. note::
68   Bits [63:32] are reserved.
69
70Relevant register fields
71~~~~~~~~~~~~~~~~~~~~~~~~
72
73For ``PMEVTYPER<n>_EL0``/``PMEVTYPER<n>`` and ``PMCCFILTR_EL0/PMCCFILTR``, the
74most important fields are:
75
76-  ``P``:
77
78   -  Bit 31.
79   -  If set to ``0``, will increment the associated ``PMEVCNTR<n>`` at EL1.
80
81-  ``NSK``:
82
83   -  Bit 29.
84   -  If equal to the ``P`` bit it enables the associated ``PMEVCNTR<n>`` at
85      Non-secure EL1.
86   -  Reserved if EL3 not implemented.
87
88-  ``NSH``:
89
90   -  Bit 27.
91   -  If set to ``1``, will increment the associated ``PMEVCNTR<n>`` at EL2.
92   -  Reserved if EL2 not implemented.
93
94-  ``SH``:
95
96   -  Bit 24.
97   -  If different to the ``NSH`` bit it enables the associated ``PMEVCNTR<n>``
98      at Secure EL2.
99   -  Reserved if Secure EL2 not implemented.
100
101-  ``M``:
102
103   -  Bit 26.
104   -  If equal to the ``P`` bit it enables the associated ``PMEVCNTR<n>`` at
105      EL3.
106
107-  ``evtCount[15:10]``:
108
109   -  Extension to ``evtCount[9:0]``. Reserved unless ARMv8.1-PMU implemented.
110
111-  ``evtCount[9:0]``:
112
113   -  The event number that the associated ``PMEVCNTR<n>`` will count.
114
115For ``PMCNTENSET_EL0``/``PMCNTENSET``, the most important fields are:
116
117-  ``P[30:0]``:
118
119   -  Setting bit ``P[n]`` to ``1`` enables counter ``PMEVCNTR<n>``.
120   -  The effects of ``PMEVTYPER<n>`` are applied on top of this.
121      In other words, the counter will not increment at any privilege level or
122      security state unless it is enabled here.
123
124-  ``C``:
125
126   -  Bit 31.
127   -  If set to ``1`` enables the cycle counter ``PMCCNTR``.
128
129For ``PMCR``/``PMCR_EL0``, the most important fields are:
130
131-  ``DP``:
132
133   -  Bit 5.
134   -  If set to ``1`` it disables the cycle counter ``PMCCNTR`` where event
135      counting (by ``PMEVCNTR<n>``) is prohibited (e.g. EL2 and the Secure
136      world).
137   -  If set to ``0``, ``PMCCNTR`` will not be affected by this bit and
138      therefore will be able to count where the programmable counters are
139      prohibited.
140
141-  ``E``:
142
143   -  Bit 0.
144   -  Enables/disables counting altogether.
145   -  The effects of ``PMCNTENSET`` and ``PMCR.DP`` are applied on top of this.
146      In other words, if this bit is ``0`` then no counters will increment
147      regardless of how the other PMU system registers or bit fields are
148      configured.
149
150.. rubric:: References
151
152-  `Arm ARM`_
153
154--------------
155
156*Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved.*
157
158.. _Arm ARM: https://developer.arm.com/docs/ddi0487/latest
159