1 /** @file
2 Do platform initialization for PCI bridge.
3
4 Copyright (c) 2013-2015 Intel Corporation.
5
6 SPDX-License-Identifier: BSD-2-Clause-Patent
7
8
9 **/
10
11 #include "PciHostBridge.h"
12
13 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo;
14
15 EFI_STATUS
ChipsetPreprocessController(IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL * This,IN EFI_HANDLE RootBridgeHandle,IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase)16 ChipsetPreprocessController (
17 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
18 IN EFI_HANDLE RootBridgeHandle,
19 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
20 IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
21 )
22 /*++
23
24 Routine Description:
25 This function is called for all the PCI controllers that the PCI
26 bus driver finds. Can be used to Preprogram the controller.
27
28 Arguments:
29 This -- The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance
30 RootBridgeHandle -- The PCI Root Bridge handle
31 PciBusAddress -- Address of the controller on the PCI bus
32 Phase -- The Phase during resource allocation
33
34 Returns:
35 EFI_SUCCESS
36
37 --*/
38
39 // GC_TODO: PciAddress - add argument and description to function comment
40 //
41 // GC_TODO: PciAddress - add argument and description to function comment
42 //
43 // GC_TODO: PciAddress - add argument and description to function comment
44 //
45 // GC_TODO: PciAddress - add argument and description to function comment
46 //
47 {
48
49 EFI_STATUS Status;
50 UINT8 Latency;
51 UINT8 CacheLineSize;
52
53 if (mPciRootBridgeIo == NULL) {
54 //
55 // Get root bridge in the system.
56 //
57 Status = gBS->HandleProtocol (RootBridgeHandle, &gEfiPciRootBridgeIoProtocolGuid, (VOID **) &mPciRootBridgeIo);
58 ASSERT_EFI_ERROR (Status);
59 }
60
61 if (Phase == EfiPciBeforeResourceCollection) {
62 //
63 // Program the latency register, CLS register
64 //
65 PciAddress.Register = PCI_LATENCY_TIMER_OFFSET;
66 mPciRootBridgeIo->Pci.Read (
67 mPciRootBridgeIo,
68 EfiPciWidthUint8,
69 *((UINT64 *) &PciAddress),
70 1,
71 &Latency
72 );
73
74 //
75 // PCI-x cards come up with a default latency of 0x40. Don't touch them.
76 //
77 if (Latency == 0) {
78 Latency = DEFAULT_PCI_LATENCY;
79 mPciRootBridgeIo->Pci.Write (
80 mPciRootBridgeIo,
81 EfiPciWidthUint8,
82 *((UINT64 *) &PciAddress),
83 1,
84 &Latency
85 );
86 }
87 //
88 // Program Cache Line Size as 64bytes
89 // 16 of DWORDs = 64bytes (0x10)
90 //
91 PciAddress.Register = PCI_CACHELINE_SIZE_OFFSET;
92 CacheLineSize = 0x10;
93 mPciRootBridgeIo->Pci.Write (
94 mPciRootBridgeIo,
95 EfiPciWidthUint8,
96 *((UINT64 *) &PciAddress),
97 1,
98 &CacheLineSize
99 );
100
101 }
102
103 return EFI_SUCCESS;
104 }
105
106 UINT64
GetAllocAttributes(IN UINTN RootBridgeIndex)107 GetAllocAttributes (
108 IN UINTN RootBridgeIndex
109 )
110 /*++
111
112 Routine Description:
113
114 Returns the Allocation attributes for the BNB Root Bridge.
115
116 Arguments:
117
118 RootBridgeIndex - The root bridge number. 0 based.
119
120 Returns:
121
122 EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | EFI_PCI_HOST_BRIDGE_MEM64_DECODE
123
124 --*/
125 {
126 //
127 // Cannot have more than one Root bridge
128 //
129 //ASSERT (RootBridgeIndex == 0);
130
131 //
132 // PCI Root Bridge does not support separate windows for Non-prefetchable
133 // and Prefetchable memory. A PCI bus driver needs to include requests for
134 // Prefetchable memory in the Non-prefetchable memory pool.
135 // Further TNB does not support 64 bit memory apertures for PCI. BNB
136 // can only have system memory above 4 GB,
137 //
138
139 return EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | EFI_PCI_HOST_BRIDGE_MEM64_DECODE;
140 }
141