1/** @file 2 Thunderbolt ACPI methods 3 4 5 Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> 6 SPDX-License-Identifier: BSD-2-Clause-Patent 7**/ 8 9#define DTBT_CONTROLLER 0x00 10#define DTBT_TYPE_PCH 0x01 11#define DTBT_TYPE_PEG 0x02 12#define DTBT_SMI_HANDLER_NUMBER 0xF7 13#define TBT_SMI_ENUMERATION_FUNCTION 21 14#define TBT_SMI_RESET_SWITCH_FUNCTION 22 15#define TBT_SMI_DISABLE_MSI_FUNCTION 23 16#ifndef BIT29 17#define BIT29 0x20000000 18#endif 19 20Name(LDLY, 300) //300 ms 21Name (TNVB, 0xFFFF0000) // TBT NVS Base address 22Name (TNVL, 0xAA55) // TBT NVS Length 23Include ("Acpi/TbtNvs.asl") 24 25External(\_SB.PCI0.RP02.L23D, MethodObj) 26External(\_SB.PCI0.RP03.L23D, MethodObj) 27External(\_SB.PCI0.RP04.L23D, MethodObj) 28External(\_SB.PCI0.RP05.L23D, MethodObj) 29External(\_SB.PCI0.RP06.L23D, MethodObj) 30External(\_SB.PCI0.RP07.L23D, MethodObj) 31External(\_SB.PCI0.RP08.L23D, MethodObj) 32External(\_SB.PCI0.RP09.L23D, MethodObj) 33External(\_SB.PCI0.RP10.L23D, MethodObj) 34External(\_SB.PCI0.RP11.L23D, MethodObj) 35External(\_SB.PCI0.RP12.L23D, MethodObj) 36External(\_SB.PCI0.RP13.L23D, MethodObj) 37External(\_SB.PCI0.RP14.L23D, MethodObj) 38External(\_SB.PCI0.RP15.L23D, MethodObj) 39External(\_SB.PCI0.RP16.L23D, MethodObj) 40External(\_SB.PCI0.RP17.L23D, MethodObj) 41External(\_SB.PCI0.RP18.L23D, MethodObj) 42External(\_SB.PCI0.RP19.L23D, MethodObj) 43External(\_SB.PCI0.RP20.L23D, MethodObj) 44External(\_SB.PCI0.RP21.L23D, MethodObj) 45External(\_SB.PCI0.RP22.L23D, MethodObj) 46External(\_SB.PCI0.RP23.L23D, MethodObj) 47External(\_SB.PCI0.RP24.L23D, MethodObj) 48 49External(\_SB.PCI0.RP01.DL23, MethodObj) 50External(\_SB.PCI0.RP02.DL23, MethodObj) 51External(\_SB.PCI0.RP03.DL23, MethodObj) 52External(\_SB.PCI0.RP04.DL23, MethodObj) 53External(\_SB.PCI0.RP05.DL23, MethodObj) 54External(\_SB.PCI0.RP06.DL23, MethodObj) 55External(\_SB.PCI0.RP07.DL23, MethodObj) 56External(\_SB.PCI0.RP08.DL23, MethodObj) 57External(\_SB.PCI0.RP09.DL23, MethodObj) 58External(\_SB.PCI0.RP10.DL23, MethodObj) 59External(\_SB.PCI0.RP11.DL23, MethodObj) 60External(\_SB.PCI0.RP12.DL23, MethodObj) 61External(\_SB.PCI0.RP13.DL23, MethodObj) 62External(\_SB.PCI0.RP14.DL23, MethodObj) 63External(\_SB.PCI0.RP15.DL23, MethodObj) 64External(\_SB.PCI0.RP16.DL23, MethodObj) 65External(\_SB.PCI0.RP17.DL23, MethodObj) 66External(\_SB.PCI0.RP18.DL23, MethodObj) 67External(\_SB.PCI0.RP19.DL23, MethodObj) 68External(\_SB.PCI0.RP20.DL23, MethodObj) 69External(\_SB.PCI0.RP21.DL23, MethodObj) 70External(\_SB.PCI0.RP22.DL23, MethodObj) 71External(\_SB.PCI0.RP23.DL23, MethodObj) 72External(\_SB.PCI0.RP24.DL23, MethodObj) 73 74External(\_SB.PCI0.RTEN, MethodObj) 75External(\_SB.PCI0.RTDS, MethodObj) 76External(\_SB.PCI0.RP01.PON, MethodObj) 77External(\_SB.PCI0.RP02.PON, MethodObj) 78External(\_SB.PCI0.RP03.PON, MethodObj) 79External(\_SB.PCI0.RP04.PON, MethodObj) 80External(\_SB.PCI0.RP05.PON, MethodObj) 81External(\_SB.PCI0.RP06.PON, MethodObj) 82External(\_SB.PCI0.RP07.PON, MethodObj) 83External(\_SB.PCI0.RP08.PON, MethodObj) 84External(\_SB.PCI0.RP09.PON, MethodObj) 85External(\_SB.PCI0.RP10.PON, MethodObj) 86External(\_SB.PCI0.RP11.PON, MethodObj) 87External(\_SB.PCI0.RP12.PON, MethodObj) 88External(\_SB.PCI0.RP13.PON, MethodObj) 89External(\_SB.PCI0.RP14.PON, MethodObj) 90External(\_SB.PCI0.RP15.PON, MethodObj) 91External(\_SB.PCI0.RP16.PON, MethodObj) 92External(\_SB.PCI0.RP17.PON, MethodObj) 93External(\_SB.PCI0.RP18.PON, MethodObj) 94External(\_SB.PCI0.RP19.PON, MethodObj) 95External(\_SB.PCI0.RP20.PON, MethodObj) 96External(\_SB.PCI0.RP21.PON, MethodObj) 97External(\_SB.PCI0.RP22.PON, MethodObj) 98External(\_SB.PCI0.RP23.PON, MethodObj) 99External(\_SB.PCI0.RP24.PON, MethodObj) 100External(\_SB.PCI0.PEG0.PG00._ON, MethodObj) 101External(\_SB.PCI0.PEG1.PG01._ON, MethodObj) 102External(\_SB.PCI0.PEG2.PG02._ON, MethodObj) 103 104Name(TRDO, 0) // 1 during TBT RTD3 _ON 105Name(TRD3, 0) // 1 during TBT RTD3 _OFF 106Name(TBPE, 0) // Reflects RTD3_PWR_EN value 107Name(TOFF, 0) // param to TBT _OFF method 108 109 Method (TBON, 0, Serialized) { 110 // TBT On process before entering Sx state. 111 Store(1, TRDO) 112 Switch (ToInteger(\RPS0)) { // TBT Root port Selector 113 Case (1) { 114 If (CondRefOf(\_SB.PCI0.RP01.PON)) { 115 \_SB.PCI0.RP01.PON() 116 } 117 } 118 Case (2) { 119 If (CondRefOf(\_SB.PCI0.RP02.PON)) { 120 \_SB.PCI0.RP02.PON() 121 } 122 } 123 Case (3) { 124 If (CondRefOf(\_SB.PCI0.RP03.PON)) { 125 \_SB.PCI0.RP03.PON() 126 } 127 } 128 Case (4) { 129 If (CondRefOf(\_SB.PCI0.RP04.PON)) { 130 \_SB.PCI0.RP04.PON() 131 } 132 } 133 Case (5) { 134 If (CondRefOf(\_SB.PCI0.RP05.PON)) { 135 \_SB.PCI0.RP05.PON() 136 } 137 } 138 Case (6) { 139 If (CondRefOf(\_SB.PCI0.RP06.PON)) { 140 \_SB.PCI0.RP06.PON() 141 } 142 } 143 Case (7) { 144 If (CondRefOf(\_SB.PCI0.RP07.PON)) { 145 \_SB.PCI0.RP07.PON() 146 } 147 } 148 Case (8) { 149 If (CondRefOf(\_SB.PCI0.RP08.PON)) { 150 \_SB.PCI0.RP08.PON() 151 } 152 } 153 Case (9) { 154 If (CondRefOf(\_SB.PCI0.RP09.PON)) { 155 \_SB.PCI0.RP09.PON() 156 } 157 } 158 Case (10) { 159 If (CondRefOf(\_SB.PCI0.RP10.PON)) { 160 \_SB.PCI0.RP10.PON() 161 } 162 } 163 Case (11) { 164 If (CondRefOf(\_SB.PCI0.RP11.PON)) { 165 \_SB.PCI0.RP11.PON() 166 } 167 } 168 Case (12) { 169 If (CondRefOf(\_SB.PCI0.RP12.PON)) { 170 \_SB.PCI0.RP12.PON() 171 } 172 } 173 Case (13) { 174 If (CondRefOf(\_SB.PCI0.RP13.PON)) { 175 \_SB.PCI0.RP13.PON() 176 } 177 } 178 Case (14) { 179 If (CondRefOf(\_SB.PCI0.RP14.PON)) { 180 \_SB.PCI0.RP14.PON() 181 } 182 } 183 Case (15) { 184 If (CondRefOf(\_SB.PCI0.RP15.PON)) { 185 \_SB.PCI0.RP15.PON() 186 } 187 } 188 Case (16) { 189 If (CondRefOf(\_SB.PCI0.RP16.PON)) { 190 \_SB.PCI0.RP16.PON() 191 } 192 } 193 Case (17) { 194 If (CondRefOf(\_SB.PCI0.RP17.PON)) { 195 \_SB.PCI0.RP17.PON() 196 } 197 } 198 Case (18) { 199 If (CondRefOf(\_SB.PCI0.RP18.PON)) { 200 \_SB.PCI0.RP18.PON() 201 } 202 } 203 Case (19) { 204 If (CondRefOf(\_SB.PCI0.RP19.PON)) { 205 \_SB.PCI0.RP19.PON() 206 } 207 } 208 Case (20) { 209 If (CondRefOf(\_SB.PCI0.RP20.PON)) { 210 \_SB.PCI0.RP20.PON() 211 } 212 } 213 Case (21) { 214 If (CondRefOf(\_SB.PCI0.RP21.PON)) { 215 \_SB.PCI0.RP21.PON() 216 } 217 } 218 Case (22) { 219 If (CondRefOf(\_SB.PCI0.RP22.PON)) { 220 \_SB.PCI0.RP22.PON() 221 } 222 } 223 Case (23) { 224 If (CondRefOf(\_SB.PCI0.RP23.PON)) { 225 \_SB.PCI0.RP23.PON() 226 } 227 } 228 Case (24) { 229 If (CondRefOf(\_SB.PCI0.RP24.PON)) { 230 \_SB.PCI0.RP24.PON() 231 } 232 } 233 }//Switch(ToInteger(RPS0)) // TBT Selector 234 Store(0, TRDO) 235 } // End of TBON 236 // 237 // Name: TBTD 238 // Description: Function to return the TBT RP# device no 239 // Input: Arg0 -> Tbt Root Port value from Tbt NVS 240 // Input: Arg1 -> Tbt port type value from Tbt NVS 241 // Return: TBT RP# device no 242 // 243 Method(TBTD,2) 244 { 245 ADBG("TBTD") 246 If (LEqual(Arg1, DTBT_TYPE_PCH)) { 247 Switch(ToInteger(Arg0)) 248 { 249 Case (Package () {1, 2, 3, 4, 5, 6, 7, 8}) 250 { 251 Store(0x1C, Local0) //Device28-Function0...Function7 = 11100.000...111 252 } 253 Case (Package () {9, 10, 11, 12, 13, 14, 15, 16}) 254 { 255 Store(0x1D, Local0) //Device29-Function0...Function7 = 11101.000...111 256 } 257 Case (Package () {17, 18, 19, 20, 21, 22, 23, 24}) 258 { 259 Store(0x1B, Local0) //Device27-Function0...Function3 = 11011.000...011 260 } 261 } 262 } ElseIf (LEqual(Arg1, DTBT_TYPE_PEG)) { 263 Switch(ToInteger(Arg0)) 264 { 265 Case (Package () {1, 2, 3}) 266 { 267 Store(0x1, Local0) //Device1-Function0...Function2 = 00001.000...010 268 } 269 } 270 } Else { 271 Store(0xFF, Local0) 272 } 273 274 ADBG("Device no") 275 ADBG(Local0) 276 277 Return(Local0) 278 } // End of Method(TBTD,1) 279 280 // 281 // Name: TBTF 282 // Description: Function to return the TBT RP# function no 283 // Input: Arg0 -> Tbt Root Port value from Tbt NVS 284 // Input: Arg1 -> Tbt port type value from Tbt NVS 285 // Return: TBT RP# function no 286 // 287 Method(TBTF,2) 288 { 289 ADBG("TBTF") 290 If (LEqual(Arg1, DTBT_TYPE_PCH)) { 291 Switch(ToInteger(Arg0)) 292 { 293 Case (1) 294 { 295 Store(And(\RPA1,0xF), Local0) //Device28-Function0 = 11100.000 296 } 297 Case (2) 298 { 299 Store(And(\RPA2,0xF), Local0) //Device28-Function1 = 11100.001 300 } 301 Case (3) 302 { 303 Store(And(\RPA3,0xF), Local0) //Device28-Function2 = 11100.010 304 } 305 Case (4) 306 { 307 Store(And(\RPA4,0xF), Local0) //Device28-Function3 = 11100.011 308 } 309 Case (5) 310 { 311 Store(And(\RPA5,0xF), Local0) //Device28-Function4 = 11100.100 312 } 313 Case (6) 314 { 315 Store(And(\RPA6,0xF), Local0) //Device28-Function5 = 11100.101 316 } 317 Case (7) 318 { 319 Store(And(\RPA7,0xF), Local0) //Device28-Function6 = 11100.110 320 } 321 Case (8) 322 { 323 Store(And(\RPA8,0xF), Local0) //Device28-Function7 = 11100.111 324 } 325 Case (9) 326 { 327 Store(And(\RPA9,0xF), Local0) //Device29-Function0 = 11101.000 328 } 329 Case (10) 330 { 331 Store(And(\RPAA,0xF), Local0) //Device29-Function1 = 11101.001 332 } 333 Case (11) 334 { 335 Store(And(\RPAB,0xF), Local0) //Device29-Function2 = 11101.010 336 } 337 Case (12) 338 { 339 Store(And(\RPAC,0xF), Local0) //Device29-Function3 = 11101.011 340 } 341 Case (13) 342 { 343 Store(And(\RPAD,0xF), Local0) //Device29-Function4 = 11101.100 344 } 345 Case (14) 346 { 347 Store(And(\RPAE,0xF), Local0) //Device29-Function5 = 11101.101 348 } 349 Case (15) 350 { 351 Store(And(\RPAF,0xF), Local0) //Device29-Function6 = 11101.110 352 } 353 Case (16) 354 { 355 Store(And(\RPAG,0xF), Local0) //Device29-Function7 = 11101.111 356 } 357 Case (17) 358 { 359 Store(And(\RPAH,0xF), Local0) //Device27-Function0 = 11011.000 360 } 361 Case (18) 362 { 363 Store(And(\RPAI,0xF), Local0) //Device27-Function1 = 11011.001 364 } 365 Case (19) 366 { 367 Store(And(\RPAJ,0xF), Local0) //Device27-Function2 = 11011.010 368 } 369 Case (20) 370 { 371 Store(And(\RPAK,0xF), Local0) //Device27-Function3 = 11011.011 372 } 373 Case (21) 374 { 375 Store(And(\RPAL,0xF), Local0) //Device27-Function4 = 11011.100 376 } 377 Case (22) 378 { 379 Store(And(\RPAM,0xF), Local0) //Device27-Function5 = 11011.101 380 } 381 Case (23) 382 { 383 Store(And(\RPAN,0xF), Local0) //Device27-Function6 = 11011.110 384 } 385 Case (24) 386 { 387 Store(And(\RPAO,0xF), Local0) //Device27-Function7 = 11011.111 388 } 389 } 390 } ElseIf (LEqual(Arg1, DTBT_TYPE_PEG)) { 391 Switch(ToInteger(Arg0)) 392 { 393 Case (1) 394 { 395 Store(0x0, Local0) //Device1-Function0 = 00001.000 396 } 397 Case (2) 398 { 399 Store(0x1, Local0) //Device1-Function1 = 00001.001 400 } 401 Case (3) 402 { 403 Store(0x2, Local0) //Device1-Function2 = 00001.010 404 } 405 } 406 } Else { 407 Store(0xFF, Local0) 408 } 409 410 ADBG("Function no") 411 ADBG(Local0) 412 413 Return(Local0) 414 } // End of Method(TBTF,1) 415 416 // 417 // Name: MMRP 418 // Description: Function to return the Pci base address of TBT rootport 419 // Input: Arg0 -> Tbt Root Port value from Tbt NVS 420 // Input: Arg1 -> Tbt port type value from Tbt NVS 421 // 422 423 Method(MMRP, 2, Serialized) 424 { 425 Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address 426 Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no 427 Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no 428 429 Return(Local0) 430 } // End of Method(MMRP) 431 432 // 433 // Name: MMRP 434 // Description: Function to return the Pci base address of TBT Up stream port 435 // Input: Arg0 -> Tbt Root Port value from Tbt NVS 436 // Input: Arg1 -> Tbt port type value from Tbt NVS 437 // 438 Method(MMTB, 2, Serialized) 439 { 440 ADBG("MMTB") 441 442 Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address 443 444 Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no 445 Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no 446 447 OperationRegion (MMMM, SystemMemory, Local0, 0x1A) 448 Field (MMMM, AnyAcc, NoLock, Preserve) 449 { 450 Offset(0x19), 451 SBUS, 8 452 } 453 Store(SBUS, Local2) 454 Store(\_SB.PCI0.GPCB(), Local0) 455 Multiply(Local2, 0x100000, Local2) 456 Add(Local2, Local0, Local0) // TBT HR US port 457 458 ADBG("TBT-US-ADR") 459 ADBG(Local0) 460 461 Return(Local0) 462 } // End of Method(MMTB, 1, Serialized) 463 // 464 // Name: FFTB 465 // Description: Function to Check for FFFF in TBT PCIe 466 // Input: Arg0 -> Tbt Root Port value from Tbt NVS 467 // Input: Arg1 -> Tbt port type value from Tbt NVS 468 // Return: 1 if TBT PCIe space has value FFFF, 0 if not 469 // 470 Method(FFTB, 2, Serialized) 471 { 472 ADBG("FFTB") 473 474 Add(MMTB(Arg0, Arg1), 0x548, Local0) 475 OperationRegion(PXVD,SystemMemory,Local0,0x08) 476 Field(PXVD,DWordAcc, NoLock, Preserve) 477 { 478 TB2P, 32, 479 P2TB, 32 480 } 481 482 Store(TB2P, Local1) 483 484 If(LEqual(Local1, 0xFFFFFFFF)) 485 { 486 ADBG("FFTb 1") 487 Return (1) 488 } 489 Else 490 { 491 ADBG("FFTb 0") 492 Return (0) 493 } 494 } // End of Method(FFTB) 495 496Name(TDMA, 0x80000000) // Address of Thunderbolt(TM) debug memory buffer, fixed up during POST 497 498Scope(\_GPE) 499{ 500 // 501 // 502 //OS up Mail Box command execution to host router upstream port each time 503 //exiting from Sx State .Avoids intermediate 504 //PCIe Scan by OS during resorce allocation 505 // Arg0 : PCIe Base address 506 // Arg1 : Controller Type 0x00 : DTBT 507 //Developer notes: Called twice 508 // 1. During OS INIT (booting to OS from S3-S5/Reboot) 509 // 2. Up on Hot plug 510 // 511 Method(OSUP, 2, Serialized) 512 { 513 ADBG("OSUP") 514 515 Add(Arg0, 0x540, Local0) 516 OperationRegion(PXVD,SystemMemory,Local0,0x10) 517 Field(PXVD,DWordAcc, NoLock, Preserve) 518 { 519 IT2P, 32, 520 IP2T, 32, 521 DT2P, 32, 522 DP2T, 32 523 } 524 525 Store(100, Local1) 526 Store(0x0D, DP2T) // Write OS_Up to PCIe2TBT 527 528 While(LGreater(Local1, 0)) 529 { 530 Store(Subtract(Local1, 1), Local1) 531 Store(DT2P, Local2) 532 533 If(LAnd(LEqual(Local2, 0xFFFFFFFF),LEqual(Arg1, DTBT_CONTROLLER)))// Device gone 534 { 535 ADBG("Dev gone") 536 Return(2) 537 } 538 If(And(Local2, 1)) // Done 539 { 540 ADBG("Cmd acknowledged") 541 break 542 } 543 Sleep(50) 544 } 545 If(LEqual(TRWA,1)) 546 { 547 Store(0xC, DP2T) // Write OSUP to PCIe2TBT 548 } 549 Else 550 { 551 Store(0x0, DP2T) // Write 0 to PCIe2TBT 552 } 553 554 //Store(0x00, P2TB) // Write 0 to PCIe2TBT 555 556 ADBG("End-of-OSUP") 557 558 Return(1) 559 } // End of Method(OSUP, 1, Serialized) 560 561 // 562 // Check for FFFF in TBT 563 // Input: Arg0 -> Tbt Root Port value from Tbt NVS 564 // Input: Arg1 -> Tbt port type value from Tbt NVS 565 // 566 567 Method(TBFF, 2, Serialized) 568 { 569 ADBG("TBFF") 570 571 Store(MMTB(Arg0, Arg1), Local0) 572 OperationRegion (PXVD, SystemMemory, Local0, 0x8) 573 Field (PXVD, DWordAcc, NoLock, Preserve) { 574 VEDI, 32, // Vendor/Device ID 575 CMDR, 32 // CMD register 576 } 577 578 Store(VEDI, Local1) 579 580 If (LEqual(Local1, 0xFFFFFFFF)) { 581 If (LNotEqual(\TWIN, 0)) { // TBT Enumeration is Native mode? 582 If (LEqual(CMDR, 0xFFFFFFFF)) { // Device Gone 583 Return (2)// Notify only 584 } 585 Return (1)// Exit w/o notify 586 } Else { 587 Return (OSUP(Local0, DTBT_CONTROLLER)) 588 } 589 } Else 590 { 591 ADBG("Dev Present") 592 Return (0) 593 } 594 } // End of Method(TBFF, 1, Serialized) 595 596 // 597 // Secondary bus of TBT RP 598 // Input: Arg0 -> Tbt Root Port value from Tbt NVS 599 // Input: Arg1 -> Tbt port type value from Tbt NVS 600 // 601 602 Method(TSUB, 2, Serialized) 603 { 604 ADBG("TSUB") 605 606 Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address 607 608 Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no 609 Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no 610 611 ADBG("ADR") 612 ADBG(Local0) 613 614 OperationRegion (MMMM, SystemMemory, Local0, 0x1A) 615 Field (MMMM, AnyAcc, NoLock, Preserve) 616 { 617 Offset(0x19), 618 SBUS, 8 619 } 620 621 ADBG("Sec Bus") 622 ADBG(SBUS) 623 624 Return(SBUS) 625 } // End of Method(TSUB, 0, Serialized) 626 627 // 628 // Pmem of TBT RP 629 // Input: Arg0 -> Tbt Root Port value from Tbt NVS 630 // Input: Arg1 -> Tbt port type value from Tbt NVS 631 // 632 633 Method(TSUP, 2, Serialized) 634 { 635 ADBG("TSUB") 636 637 Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address 638 639 Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no 640 Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no 641 642 ADBG("ADR:") 643 ADBG(Local0) 644 645 OperationRegion (MMMM, SystemMemory, Local0, 0x30) 646 Field (MMMM, AnyAcc, NoLock, Preserve) 647 { 648 CMDS, 32, 649 Offset(0x19), 650 SBUS, 8, 651 SBU5, 8, 652 Offset(0x1C), 653 SEIO, 32, 654 MMBL, 32, 655 PMBL, 32, 656 657 } 658 659 ADBG("Pmem of TBT RP:") 660 ADBG(PMBL) 661 662 Return(PMBL) 663 } // End of Method(TSUP, 0, Serialized) 664 665 // 666 // Wait for secondary bus in TBT RP 667 // Input: Arg0 -> Tbt Root Port value from Tbt NVS 668 // Input: Arg1 -> Tbt port type value from Tbt NVS 669 // 670 671 Method(WSUB, 2, Serialized) 672 { 673 ADBG(Concatenate("WSUB=", ToHexString(Arg0))) 674 ADBG(ToHexString(Timer)) 675 676 Store(0, Local0) 677 Store(0, Local1) 678 While(1) 679 { 680 Store(TSUP(Arg0, Arg1), Local1) 681 If(LGreater(Local1, 0x1FFF1)) 682 { 683 ADBG("WSUB-Finished") 684 Break 685 } 686 Else 687 { 688 Add(Local0, 1, Local0) 689 If(LGreater(Local0, 1000)) 690 { 691 Sleep(1000) 692 ADBG("WSUB-Deadlock") 693 } 694 Else 695 { 696 Sleep(16) 697 } 698 } 699 } 700 ADBG(Concatenate("WSUb=", ToHexString(Local1))) 701 } // End of Method(WSUB) 702 703 // Wait for _WAK finished 704 Method(WWAK) 705 { 706 ADBG("WWAK") 707 708 Wait(WFEV, 0xFFFF) 709 Signal(WFEV) // Set it, to enter on next HP 710 } // End of Method(WWAK) 711 712 Method(NTFY, 2, Serialized) 713 { 714 ADBG("NTFY") 715 716 If(LEqual(NOHP,1)) 717 { 718 If (LEqual(Arg1, DTBT_TYPE_PCH)) { 719 Switch(ToInteger(Arg0)) // TBT Selector 720 { 721 Case (1) 722 { 723 ADBG("Notify RP01") 724 Notify(\_SB.PCI0.RP01,0) 725 } 726 Case (2) 727 { 728 ADBG("Notify RP02") 729 Notify(\_SB.PCI0.RP02,0) 730 } 731 Case (3) 732 { 733 ADBG("Notify RP03") 734 Notify(\_SB.PCI0.RP03,0) 735 } 736 Case (4) 737 { 738 ADBG("Notify RP04") 739 Notify(\_SB.PCI0.RP04,0) 740 } 741 Case (5) 742 { 743 ADBG("Notify RP05") 744 Notify(\_SB.PCI0.RP05,0) 745 } 746 Case (6) 747 { 748 ADBG("Notify RP06") 749 Notify(\_SB.PCI0.RP06,0) 750 } 751 Case (7) 752 { 753 ADBG("Notify RP07") 754 Notify(\_SB.PCI0.RP07,0) 755 } 756 Case (8) 757 { 758 ADBG("Notify RP08") 759 Notify(\_SB.PCI0.RP08,0) 760 } 761 Case (9) 762 { 763 ADBG("Notify RP09") 764 Notify(\_SB.PCI0.RP09,0) 765 } 766 Case (10) 767 { 768 ADBG("Notify RP10") 769 Notify(\_SB.PCI0.RP10,0) 770 } 771 Case (11) 772 { 773 ADBG("Notify RP11") 774 Notify(\_SB.PCI0.RP11,0) 775 } 776 Case (12) 777 { 778 ADBG("Notify RP12") 779 Notify(\_SB.PCI0.RP12,0) 780 } 781 Case (13) 782 { 783 ADBG("Notify RP13") 784 Notify(\_SB.PCI0.RP13,0) 785 } 786 Case (14) 787 { 788 ADBG("Notify RP14") 789 Notify(\_SB.PCI0.RP14,0) 790 } 791 Case (15) 792 { 793 ADBG("Notify RP15") 794 Notify(\_SB.PCI0.RP15,0) 795 } 796 Case (16) 797 { 798 ADBG("Notify RP16") 799 Notify(\_SB.PCI0.RP16,0) 800 } 801 Case (17) 802 { 803 ADBG("Notify RP17") 804 Notify(\_SB.PCI0.RP17,0) 805 } 806 Case (18) 807 { 808 ADBG("Notify RP18") 809 Notify(\_SB.PCI0.RP18,0) 810 } 811 Case (19) 812 { 813 ADBG("Notify RP19") 814 Notify(\_SB.PCI0.RP19,0) 815 } 816 Case (20) 817 { 818 ADBG("Notify RP20") 819 Notify(\_SB.PCI0.RP20,0) 820 } 821 Case (21) 822 { 823 ADBG("Notify RP21") 824 Notify(\_SB.PCI0.RP21,0) 825 } 826 Case (22) 827 { 828 ADBG("Notify RP22") 829 Notify(\_SB.PCI0.RP22,0) 830 } 831 Case (23) 832 { 833 ADBG("Notify RP23") 834 Notify(\_SB.PCI0.RP23,0) 835 } 836 Case (24) 837 { 838 ADBG("Notify RP24") 839 Notify(\_SB.PCI0.RP24,0) 840 } 841 }//Switch(ToInteger(TBSS)) // TBT Selector 842 } ElseIf (LEqual(Arg1, DTBT_TYPE_PEG)) { 843 Switch(ToInteger(Arg0)) 844 { 845 Case (1) 846 { 847 ADBG("Notify PEG0") 848 Notify(\_SB.PCI0.PEG0,0) 849 } 850 Case (2) 851 { 852 ADBG("Notify PEG1") 853 Notify(\_SB.PCI0.PEG1,0) 854 } 855 Case (3) 856 { 857 ADBG("Notify PEG2") 858 Notify(\_SB.PCI0.PEG2,0) 859 } 860 } 861 }//Switch(ToInteger(TBSS)) // TBT Selector 862 }//If(NOHP()) 863 P8XH(0,0xC2) 864 P8XH(1,0xC2) 865 }// End of Method(NTFY) 866 867// 868// TBT BIOS, GPIO 5 filtering, 869// Hot plug of 12V USB devices, into TBT host router, cause electrical noise on PCH GPIOs, 870// This noise cause false hot-plug events, and negatively influence BIOS assisted hot-plug. 871// WHL-PCH GPIO does not implement Glitch Filter logic (refer to GPIO HAS) on any GPIO pad. Native functions have to implement their own digital glitch-filter logic 872// if needed. As HW filter was not implemented on WHL PCH, because of that SW workaround should be implemented in BIOS. 873// Register 0x544(Bios mailbox) bit 0 definition: 874// if BIOS reads bit as 1, BIOS will clear the bit and continue normal flow, if bit is 0 BIOS will exit from method 875// 876 877 Method(GNIS,2, Serialized) 878 { 879 880 ADBG("GNIS") 881 If(LEqual(GP5F, 0)) 882 { 883 ADBG("GNIS_Dis=0") 884 Return(0) 885 } 886 // 887 // BIOS mailbox command for GPIO filter 888 // 889 Add(MMTB(Arg0, Arg1), 0x544, Local0) 890 OperationRegion(PXVD,SystemMemory,Local0,0x08) 891 892 Field(PXVD,DWordAcc, NoLock, Preserve) 893 { 894 HPFI, 1, 895 Offset(0x4), 896 TB2P, 32 897 } 898 Store(TB2P, Local1) 899 ADBG(Concatenate("TB2P=", ToHexString(Local1))) 900 If(LEqual(Local1, 0xFFFFFFFF)) // Disconnect? 901 { 902 ADBG("GNIS=0") 903 Return(0) 904 } 905 Store(HPFI, Local2) 906 ADBG(Concatenate("HPFI=", ToHexString(Local2))) 907 If(LEqual(Local2, 0x01)) 908 { 909 Store(0x00, HPFI) 910 ADBG("GNIS=0") 911 Return(0) 912 } 913 // Any other values treated as a GPIO noise 914 ADBG("GNIS=1") 915 Return(1) 916 } 917 918 Method(CHKP,2, Serialized) 919 { 920 Add(MMTB(Arg0, Arg1), 0x544, Local0) 921 OperationRegion(PXVE,SystemMemory,Local0,0x08) 922 923 Field(PXVE,DWordAcc, NoLock, Preserve) 924 { 925 HPFI, 1, 926 Offset(0x4), 927 TB2P, 32 928 } 929 Store(TB2P, Local1) 930 And(Local1,BIT29,Local1) 931 ADBG(Concatenate("Local1=", ToHexString(Local1))) 932 //ADBG(Concatenate("BIT29=", ToHexString(LAnd(Local1,BIT29)))) 933 If(LEqual(Local1, BIT29)) 934 { 935 Return(1) 936 } 937 Else 938 { 939 Return(0) 940 } 941 } 942 943 // 944 // Method to Handle enumerate PCIe structure through 945 // SMI for Thunderbolt(TM) devices 946 // 947 Method(XTBT,2, Serialized) 948 { 949 ADBG("XTBT") 950 ADBG("RP :") 951 ADBG(Arg0) 952 Store(Arg0, DTCP) // Root port to enumerate 953 Store(Arg1, DTPT) // Root port Type 954 If(LEqual(Arg0, RPS0)) { 955 Store (1, Local0) 956 } ElseIf (LEqual(Arg0, RPS1)) { 957 Store (2, Local0) 958 } Else { 959 Store (0, Local0) 960 Return () 961 } 962 963 If (TRDO) { 964 ADBG("Durng TBT_ON") 965 Return () 966 } 967 968 If (TRD3) { 969 ADBG("During TBT_OFF") 970 Return () 971 } 972 WWAK() 973 WSUB(Arg0, Arg1) 974 If(GNIS(Arg0, Arg1)) 975 { 976 Return() 977 } 978 979 OperationRegion(SPRT,SystemIO, 0xB2,2) 980 Field (SPRT, ByteAcc, Lock, Preserve) 981 { 982 SSMP, 8 983 } 984 985 ADBG("TBT-HP-Handler") 986 987 Acquire(OSUM, 0xFFFF) 988 Store(TBFF(Arg0, Arg1), Local1) 989 If(LEqual(Local1, 1))// Only HR 990 { 991 Sleep(16) 992 Release(OSUM) 993 ADBG("OS_Up_Received") 994 Return () 995 } 996 If(LEqual(Local1, 2)) // Disconnect 997 { 998 NTFY(Arg0, Arg1) 999 Sleep(16) 1000 Release(OSUM) 1001 ADBG("Disconnect") 1002 Return () 1003 } 1004 1005 // HR and EP 1006 If(LEqual(SOHP, 1)) 1007 { 1008 // Trigger SMI to enumerate PCIe Structure 1009 ADBG("TBT SW SMI") 1010 Store(21, TBSF) 1011 Store(0xF7, SSMP) 1012 } 1013 NTFY(Arg0, Arg1) 1014 Sleep(16) 1015 Release(OSUM) 1016 1017 ADBG("End-of-XTBT") 1018 } // End of Method(XTBT) 1019 1020 // 1021 // Calling Method to Handle enumerate PCIe structure through 1022 // SMI for Thunderbolt(TM) devices for Tier 1 GPIOs 1023 // Used in Two ways , 1024 // If CIO GPIO(1 Tier) is Different for the Controllers, this will be used as 1 Tier GPIO Handler for 1st controller 1025 // If CIO GPIO(1 Tier) is Same for all the controllers, this will be used as 1 Tier GPIO Handler for All the controllers 1026 // 1027 Method(ATBT) 1028 { 1029 ADBG("ATBT") 1030 // 1031 // Calling Method to Handle enumerate PCIe structure through 1032 // 1033 If(LEqual(CGST,0)) { // If GPIO is Different for each controller 1034 If(LEqual(RPN0,1)) 1035 { 1036 XTBT(RPS0, RPT0) 1037 } 1038 } Else { 1039 If(LEqual(RPN0,1)) 1040 { 1041 XTBT(RPS0, RPT0) 1042 } 1043 ElseIf(LEqual(RPN1,1)) 1044 { 1045 XTBT(RPS1, RPT1) 1046 } 1047 } 1048 ADBG("End-of-ATBT") 1049 } // End of Method(ATBT) 1050 1051 Method(BTBT) 1052 { 1053 ADBG("BTBT") 1054 // 1055 // Calling Method to Handle enumerate PCIe structure through 1056 // 1057 If(LEqual(CGST,0)) { // If GPIO is Different for each controller 1058 If(LEqual(RPN1,1)) 1059 { 1060 XTBT(RPS1, RPT1) 1061 } 1062 } 1063 ADBG("End-of-BTBT") 1064 } // End of Method(BTBT) 1065 // 1066 // Method to call OSPU Mail box command 1067 // Arg0 : Controller type 0x00 : Discrete 0x80 : Integrated TBT 1068 // Arg1 : TBT RP Selector / DMA 1069 // Arg2 : TBT Type (PCH or PEG) 1070 // 1071 Method(TINI, 3, Serialized) 1072 { 1073 ADBG("TINI") 1074 If(Lequal (Arg0, DTBT_CONTROLLER)) 1075 { 1076 //ADBG("DTBT") 1077 Store(MMRP(Arg1, Arg2), Local0) 1078 OperationRegion(RP_X,SystemMemory,Local0,0x20) 1079 Field(RP_X,DWordAcc, NoLock, Preserve) 1080 { 1081 REG0, 32, 1082 REG1, 32, 1083 REG2, 32, 1084 REG3, 32, 1085 REG4, 32, 1086 REG5, 32, 1087 REG6, 32, 1088 REG7, 32 1089 } 1090 Store(REG6, Local1) 1091 Store(0x00F0F000, REG6) 1092 Store(MMTB(Arg1, Arg2), Local2) 1093 OSUP(Local2, DTBT_CONTROLLER) 1094 Store(Local1, REG6) 1095 } 1096 ADBG("End-of-TINI") 1097 } 1098 1099} // End of Scope (\_GPE) 1100 1101Scope (\_SB) 1102{ 1103 // 1104 // The code needs to be executed for TBT Hotplug Handler event (2-tier GPI GPE event architecture) is presented here 1105 // 1106 Method(THDR, 3, Serialized) 1107 { 1108 ADBG("THDR") 1109 \_SB.CAGS(Arg0) 1110 \_GPE.XTBT(Arg1, Arg2) 1111 } // End of Method(THDR, 3, Serialized) 1112} // End of Scope(\_SB) 1113 1114Scope (\_SB) 1115{ 1116 // 1117 // Name: CGWR [Combined GPIO Write] 1118 // Description: Function to write into GPIO 1119 // Input: Arg0 -> GpioPad / Expander pin 1120 // Arg1 -> Value 1121 // Return: Nothing 1122 // 1123 Method(CGWR, 2, Serialized) 1124 { 1125 // PCH 1126 If (CondRefOf(\_SB.SGOV)) 1127 { 1128 \_SB.SGOV(Arg0, Arg1) 1129 } 1130 } // End of Method(CGWR, 4, Serialized) 1131 1132 // 1133 // Name: CGRD [Combined GPIO Read] 1134 // Description: Function to read from GPIO 1135 // Input: Arg0 -> GpioPad / Expander pin 1136 // Arg1 -> 0: GPO [GPIO TX State] 1137 // 1: GPI [GPIO RX State] 1138 // Return: Value 1139 // 1140 Method(CGRD, 2, Serialized) 1141 { 1142 Store(1, Local0) 1143 // PCH 1144 If (LEqual(Arg1, 0)) 1145 { 1146 // GPIO TX State 1147 If (CondRefOf(\_SB.GGOV)) 1148 { 1149 Store(\_SB.GGOV(Arg0), Local0) 1150 } 1151 } 1152 ElseIf (LEqual(Arg1, 1)) 1153 { 1154 // GPIO RX State 1155 If (CondRefOf(\_SB.GGIV)) 1156 { 1157 Store(\_SB.GGIV(Arg0), Local0) 1158 } 1159 } 1160 Return(Local0) 1161 } // End of Method(CGRD, 4, Serialized) 1162 // 1163 // Name: WRGP [GPIO Write] 1164 // Description: Function to write into GPIO 1165 // Input: Arg0 -> COMMON_GPIO_CONFIG GpioInfo 1166 // Arg1 -> Value 1167 // Return: Nothing 1168 // 1169 Method(WRGP, 2, Serialized) 1170 { 1171 Store(Arg0, Local0) 1172 Store(Arg0, Local1) 1173 And(Local0, 0xFFFFFFFF, Local0) // Low 32 bits (31:00) 1174 ShiftRight(Local1, 32, Local1) // High 32 bits (63:32) 1175 If (LEqual(And(Local0, 0xFF), 1)) 1176 { 1177 // PCH 1178 \_SB.CGWR(Local1, Arg1) 1179 } 1180 } // End of Method(WRGP, 2, Serialized) 1181 1182 // 1183 // Name: RDGP [GPIO Read] 1184 // Description: Function to write into GPIO 1185 // Input: Arg0 -> COMMON_GPIO_CONFIG GpioInfo 1186 // Arg1 -> In case of PCH Gpio Read {GPIO TX(0)/RX(1) State indicator} 1187 // Return: Value 1188 // 1189 Method(RDGP, 2, Serialized) 1190 { 1191 Store(1, Local7) 1192 Store(Arg0, Local0) 1193 Store(Arg0, Local1) 1194 And(Local0, 0xFFFFFFFF, Local0) // Low 32 bits (31:00) 1195 ShiftRight(Local1, 32, Local1) // High 32 bits (63:32) 1196 If (LEqual(And(Local0, 0xFF), 1)) 1197 { 1198 // PCH 1199 Store(\_SB.CGRD(Local1, Arg1), Local7) 1200 } 1201 Return(Local7) 1202 } // End of Method(RDGP, 2, Serialized) 1203 1204} // End of Scope(\_SB) 1205 1206Scope(\_SB) 1207{ 1208 // Asserts/De-asserts TBT force power 1209 Method(TBFP, 2) 1210 { 1211 If(Arg0) 1212 { 1213 // Implementation dependent way to assert TBT force power 1214 If(LEqual(Arg1, 1)) { 1215 CGWR(FPG0, FP0L) 1216 } 1217 Else { 1218 CGWR(FPG1, FP1L) 1219 } 1220 } 1221 Else 1222 { 1223 // Implementation dependent way to de-assert TBT force power 1224 If(LEqual(Arg1, 1)) { 1225 CGWR(FPG0, LNot(FP0L)) 1226 } 1227 Else { 1228 CGWR(FPG1, LNot(FP1L)) 1229 } 1230 } 1231 } 1232 1233 // WMI ACPI device to control TBT force power 1234 Device(WMTF) 1235 { 1236 // pnp0c14 is pnp id assigned to WMI mapper 1237 Name(_HID, "PNP0C14") 1238 Name(_UID, "TBFP") 1239 1240 Name(_WDG, Buffer() { 1241 // {86CCFD48-205E-4A77-9C48-2021CBEDE341} 1242 0x48, 0xFD, 0xCC, 0x86, 1243 0x5E, 0x20, 1244 0x77, 0x4A, 1245 0x9C, 0x48, 1246 0x20, 0x21, 0xCB, 0xED, 0xE3, 0x41, 1247 84, 70, // Object Id (TF) 1248 1, // Instance Count 1249 0x02 // Flags (WMIACPI_REGFLAG_METHOD) 1250 }) 1251 1252 // Set TBT force power 1253 // Arg2 is force power value 1254 Method(WMTF, 3) 1255 { 1256 CreateByteField(Arg2,0,FP) 1257 1258 If(FP) 1259 { 1260 TBFP(1, 1) 1261 } 1262 Else 1263 { 1264 TBFP(0, 1) 1265 } 1266 } 1267 } 1268} // End of Scope(\_SB) 1269 1270 1271If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 1),LEqual(RPS1, 1)))) 1272{ 1273 Scope(\_SB.PCI0.RP01) 1274 { 1275 Device(HRUS)// Host router Upstream port 1276 { 1277 Name(_ADR, 0x00000000) 1278 1279 Method(_RMV) 1280 { 1281 Return(TARS) 1282 } // end _RMV 1283 } 1284 }//End of Scope(\_SB.PCI0.RP01) 1285} 1286 1287If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 2),LEqual(RPS1, 2)))) 1288{ 1289 Scope(\_SB.PCI0.RP02) 1290 { 1291 Device(HRUS)// Host router Upstream port 1292 { 1293 Name(_ADR, 0x00000000) 1294 1295 Method(_RMV) 1296 { 1297 Return(TARS) 1298 } // end _RMV 1299 } 1300 }//End of Scope(\_SB.PCI0.RP02) 1301} 1302 1303If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 3),LEqual(RPS1, 3)))) 1304{ 1305 Scope(\_SB.PCI0.RP03) 1306 { 1307 Device(HRUS)// Host router Upstream port 1308 { 1309 Name(_ADR, 0x00000000) 1310 1311 Method(_RMV) 1312 { 1313 Return(TARS) 1314 } // end _RMV 1315 } 1316 }//End of Scope(\_SB.PCI0.RP03) 1317} 1318 1319If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 4),LEqual(RPS1, 4)))) 1320{ 1321 Scope(\_SB.PCI0.RP04) 1322 { 1323 Device(HRUS)// Host router Upstream port 1324 { 1325 Name(_ADR, 0x00000000) 1326 1327 Method(_RMV) 1328 { 1329 Return(TARS) 1330 } // end _RMV 1331 } 1332 }//End of Scope(\_SB.PCI0.RP04) 1333} 1334 1335If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 5),LEqual(RPS1, 5)))) 1336{ 1337 Scope(\_SB.PCI0.RP05) 1338 { 1339 Device(HRUS)// Host router Upstream port 1340 { 1341 Name(_ADR, 0x00000000) 1342 1343 Method(_RMV) 1344 { 1345 Return(TARS) 1346 } // end _RMV 1347 } 1348 }//End of Scope(\_SB.PCI0.RP05) 1349} 1350 1351If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 6),LEqual(RPS1, 6)))) 1352{ 1353 Scope(\_SB.PCI0.RP06) 1354 { 1355 Device(HRUS)// Host router Upstream port 1356 { 1357 Name(_ADR, 0x00000000) 1358 1359 Method(_RMV) 1360 { 1361 Return(TARS) 1362 } // end _RMV 1363 } 1364 }//End of Scope(\_SB.PCI0.RP06) 1365} 1366 1367If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 7),LEqual(RPS1, 7)))) 1368{ 1369 Scope(\_SB.PCI0.RP07) 1370 { 1371 Device(HRUS)// Host router Upstream port 1372 { 1373 Name(_ADR, 0x00000000) 1374 1375 Method(_RMV) 1376 { 1377 Return(TARS) 1378 } // end _RMV 1379 } 1380 }//End of Scope(\_SB.PCI0.RP07) 1381} 1382 1383If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 8),LEqual(RPS1, 8)))) 1384{ 1385 Scope(\_SB.PCI0.RP08) 1386 { 1387 Device(HRUS)// Host router Upstream port 1388 { 1389 Name(_ADR, 0x00000000) 1390 1391 Method(_RMV) 1392 { 1393 Return(TARS) 1394 } // end _RMV 1395 } 1396 }//End of Scope(\_SB.PCI0.RP08) 1397} 1398 1399If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 9),LEqual(RPS1, 9)))) 1400{ 1401 Scope(\_SB.PCI0.RP09) 1402 { 1403 Device(HRUS)// Host router Upstream port 1404 { 1405 Name(_ADR, 0x00000000) 1406 1407 Method(_RMV) 1408 { 1409 Return(TARS) 1410 } // end _RMV 1411 } 1412 }//End of Scope(\_SB.PCI0.RP09) 1413} 1414 1415If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 10),LEqual(RPS1, 10)))) 1416{ 1417 Scope(\_SB.PCI0.RP10) 1418 { 1419 Device(HRUS)// Host router Upstream port 1420 { 1421 Name(_ADR, 0x00000000) 1422 1423 Method(_RMV) 1424 { 1425 Return(TARS) 1426 } // end _RMV 1427 } 1428 }//End of Scope(\_SB.PCI0.RP10) 1429} 1430 1431If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 11),LEqual(RPS1, 11)))) 1432{ 1433 Scope(\_SB.PCI0.RP11) 1434 { 1435 Device(HRUS)// Host router Upstream port 1436 { 1437 Name(_ADR, 0x00000000) 1438 1439 Method(_RMV) 1440 { 1441 Return(TARS) 1442 } // end _RMV 1443 } 1444 }//End of Scope(\_SB.PCI0.RP11) 1445} 1446 1447If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 12),LEqual(RPS1, 12)))) 1448{ 1449 Scope(\_SB.PCI0.RP12) 1450 { 1451 Device(HRUS)// Host router Upstream port 1452 { 1453 Name(_ADR, 0x00000000) 1454 1455 Method(_RMV) 1456 { 1457 Return(TARS) 1458 } // end _RMV 1459 } 1460 }//End of Scope(\_SB.PCI0.RP12) 1461} 1462 1463If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 13),LEqual(RPS1, 13)))) 1464{ 1465 Scope(\_SB.PCI0.RP13) 1466 { 1467 Device(HRUS)// Host router Upstream port 1468 { 1469 Name(_ADR, 0x00000000) 1470 1471 Method(_RMV) 1472 { 1473 Return(TARS) 1474 } // end _RMV 1475 } 1476 }//End of Scope(\_SB.PCI0.RP13) 1477} 1478 1479If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 14),LEqual(RPS1, 14)))) 1480{ 1481 Scope(\_SB.PCI0.RP14) 1482 { 1483 Device(HRUS)// Host router Upstream port 1484 { 1485 Name(_ADR, 0x00000000) 1486 1487 Method(_RMV) 1488 { 1489 Return(TARS) 1490 } // end _RMV 1491 } 1492 }//End of Scope(\_SB.PCI0.RP14) 1493} 1494 1495If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 15),LEqual(RPS1, 15)))) 1496{ 1497 Scope(\_SB.PCI0.RP15) 1498 { 1499 Device(HRUS)// Host router Upstream port 1500 { 1501 Name(_ADR, 0x00000000) 1502 1503 Method(_RMV) 1504 { 1505 Return(TARS) 1506 } // end _RMV 1507 } 1508 }//End of Scope(\_SB.PCI0.RP15) 1509} 1510 1511If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 16),LEqual(RPS1, 16)))) 1512{ 1513 Scope(\_SB.PCI0.RP16) 1514 { 1515 Device(HRUS)// Host router Upstream port 1516 { 1517 Name(_ADR, 0x00000000) 1518 1519 Method(_RMV) 1520 { 1521 Return(TARS) 1522 } // end _RMV 1523 } 1524 }//End of Scope(\_SB.PCI0.RP16) 1525} 1526 1527If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 17),LEqual(RPS1, 17)))) 1528{ 1529 Scope(\_SB.PCI0.RP17) 1530 { 1531 Device(HRUS)// Host router Upstream port 1532 { 1533 Name(_ADR, 0x00000000) 1534 1535 Method(_RMV) 1536 { 1537 Return(TARS) 1538 } // end _RMV 1539 } 1540 }//End of Scope(\_SB.PCI0.RP17) 1541} 1542 1543If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 18),LEqual(RPS1, 18)))) 1544{ 1545 Scope(\_SB.PCI0.RP18) 1546 { 1547 Device(HRUS)// Host router Upstream port 1548 { 1549 Name(_ADR, 0x00000000) 1550 1551 Method(_RMV) 1552 { 1553 Return(TARS) 1554 } // end _RMV 1555 } 1556 }//End of Scope(\_SB.PCI0.RP18) 1557} 1558 1559If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 19),LEqual(RPS1, 19)))) 1560{ 1561 Scope(\_SB.PCI0.RP19) 1562 { 1563 Device(HRUS)// Host router Upstream port 1564 { 1565 Name(_ADR, 0x00000000) 1566 1567 Method(_RMV) 1568 { 1569 Return(TARS) 1570 } // end _RMV 1571 } 1572 }//End of Scope(\_SB.PCI0.RP19) 1573} 1574 1575If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 20),LEqual(RPS1, 20)))) 1576{ 1577 Scope(\_SB.PCI0.RP20) 1578 { 1579 Device(HRUS)// Host router Upstream port 1580 { 1581 Name(_ADR, 0x00000000) 1582 1583 Method(_RMV) 1584 { 1585 Return(TARS) 1586 } // end _RMV 1587 } 1588 }//End of Scope(\_SB.PCI0.RP20) 1589} 1590 1591If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 21),LEqual(RPS1, 21)))) 1592{ 1593 Scope(\_SB.PCI0.PEG0) 1594 { 1595 Device(HRUS)// Host router Upstream port 1596 { 1597 Name(_ADR, 0x00000000) 1598 1599 Method(_RMV) 1600 { 1601 Return(TARS) 1602 } // end _RMV 1603 } 1604 }//End of Scope(\_SB.PCI0.PEG0) 1605} 1606 1607If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 22),LEqual(RPS1, 22)))) 1608{ 1609 Scope(\_SB.PCI0.PEG1) 1610 { 1611 Device(HRUS)// Host router Upstream port 1612 { 1613 Name(_ADR, 0x00000000) 1614 1615 Method(_RMV) 1616 { 1617 Return(TARS) 1618 } // end _RMV 1619 } 1620 }//End of Scope(\_SB.PCI0.PEG1) 1621} 1622 1623If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 23),LEqual(RPS1, 23)))) 1624{ 1625 Scope(\_SB.PCI0.PEG2) 1626 { 1627 Device(HRUS)// Host router Upstream port 1628 { 1629 Name(_ADR, 0x00000000) 1630 1631 Method(_RMV) 1632 { 1633 Return(TARS) 1634 } // end _RMV 1635 } 1636 }//End of Scope(\_SB.PCI0.PEG2) 1637} 1638 1639Scope(\_SB) 1640{ 1641 // 1642 // Name: PERB 1643 // Description: Function to read a Byte from PCIE-MMIO 1644 // Input: Arg0 -> PCIE base address 1645 // Arg1 -> Bus 1646 // Arg2 -> Device 1647 // Arg3 -> Function 1648 // Arg4 -> Register offset 1649 // Return: Byte data read from PCIE-MMIO 1650 // 1651 Method(PERB,5,Serialized) 1652 { 1653 ADBG("PERB") 1654 1655 Store(Arg0, Local7) 1656 Or(Local7, ShiftLeft(Arg1, 20), Local7) 1657 Or(Local7, ShiftLeft(Arg2, 15), Local7) 1658 Or(Local7, ShiftLeft(Arg3, 12), Local7) 1659 Or(Local7, Arg4, Local7) 1660 1661 OperationRegion(PCI0, SystemMemory, Local7, 1) 1662 Field(PCI0, ByteAcc,NoLock,Preserve) 1663 { 1664 TEMP, 8 1665 } 1666 1667 Return(TEMP) 1668 } // End of Method(PERB,5,Serialized) 1669 1670 // 1671 // Name: PEWB 1672 // Description: Function to write a Byte into PCIE-MMIO 1673 // Input: Arg0 -> PCIE base address 1674 // Arg1 -> Bus 1675 // Arg2 -> Device 1676 // Arg3 -> Function 1677 // Arg4 -> Register offset 1678 // Arg5 -> Data 1679 // Return: Nothing 1680 // 1681 Method(PEWB,6,Serialized) 1682 { 1683 ADBG("PEWB") 1684 1685 Store(Arg0, Local7) 1686 Or(Local7, ShiftLeft(Arg1, 20), Local7) 1687 Or(Local7, ShiftLeft(Arg2, 15), Local7) 1688 Or(Local7, ShiftLeft(Arg3, 12), Local7) 1689 Or(Local7, Arg4, Local7) 1690 1691 OperationRegion(PCI0, SystemMemory, Local7, 1) 1692 Field(PCI0, ByteAcc,NoLock,Preserve) 1693 { 1694 TEMP, 8 1695 } 1696 1697 Store(Arg5,TEMP) 1698 } // End of Method(PEWB,6,Serialized) 1699 1700 // 1701 // Name: PERW 1702 // Description: Function to read a Word from PCIE-MMIO 1703 // Input: Arg0 -> PCIE base address 1704 // Arg1 -> Bus 1705 // Arg2 -> Device 1706 // Arg3 -> Function 1707 // Arg4 -> Register offset 1708 // Return: Word data read from PCIE-MMIO 1709 // 1710 Method(PERW,5,Serialized) 1711 { 1712 ADBG("PERW") 1713 1714 Store(Arg0, Local7) 1715 Or(Local7, ShiftLeft(Arg1, 20), Local7) 1716 Or(Local7, ShiftLeft(Arg2, 15), Local7) 1717 Or(Local7, ShiftLeft(Arg3, 12), Local7) 1718 Or(Local7, Arg4, Local7) 1719 1720 OperationRegion(PCI0, SystemMemory, Local7, 2) 1721 Field(PCI0, ByteAcc,NoLock,Preserve) 1722 { 1723 TEMP, 16 1724 } 1725 1726 Return(TEMP) 1727 } // End of Method(PERW,5,Serialized) 1728 1729 // 1730 // Name: PEWW 1731 // Description: Function to write a Word into PCIE-MMIO 1732 // Input: Arg0 -> PCIE base address 1733 // Arg1 -> Bus 1734 // Arg2 -> Device 1735 // Arg3 -> Function 1736 // Arg4 -> Register offset 1737 // Arg5 -> Data 1738 // Return: Nothing 1739 // 1740 Method(PEWW,6,Serialized) 1741 { 1742 ADBG("PEWW") 1743 1744 Store(Arg0, Local7) 1745 Or(Local7, ShiftLeft(Arg1, 20), Local7) 1746 Or(Local7, ShiftLeft(Arg2, 15), Local7) 1747 Or(Local7, ShiftLeft(Arg3, 12), Local7) 1748 Or(Local7, Arg4, Local7) 1749 1750 OperationRegion(PCI0, SystemMemory, Local7, 2) 1751 Field(PCI0, ByteAcc,NoLock,Preserve) 1752 { 1753 TEMP, 16 1754 } 1755 1756 Store(Arg5,TEMP) 1757 } // End of Method(PEWW,6,Serialized) 1758 1759 // 1760 // Name: PERD 1761 // Description: Function to read a Dword from PCIE-MMIO 1762 // Input: Arg0 -> PCIE base address 1763 // Arg1 -> Bus 1764 // Arg2 -> Device 1765 // Arg3 -> Function 1766 // Arg4 -> Register offset 1767 // Return: Dword data read from PCIE-MMIO 1768 // 1769 Method(PERD,5,Serialized) 1770 { 1771 ADBG("PERD") 1772 1773 Store(Arg0, Local7) 1774 Or(Local7, ShiftLeft(Arg1, 20), Local7) 1775 Or(Local7, ShiftLeft(Arg2, 15), Local7) 1776 Or(Local7, ShiftLeft(Arg3, 12), Local7) 1777 Or(Local7, Arg4, Local7) 1778 1779 OperationRegion(PCI0, SystemMemory, Local7, 4) 1780 Field(PCI0, ByteAcc,NoLock,Preserve) 1781 { 1782 TEMP, 32 1783 } 1784 1785 Return(TEMP) 1786 } // End of Method(PERD,5,Serialized) 1787 1788 // 1789 // Name: PEWD 1790 // Description: Function to write a Dword into PCIE-MMIO 1791 // Input: Arg0 -> PCIE base address 1792 // Arg1 -> Bus 1793 // Arg2 -> Device 1794 // Arg3 -> Function 1795 // Arg4 -> Register offset 1796 // Arg5 -> Data 1797 // Return: Nothing 1798 // 1799 Method(PEWD,6,Serialized) 1800 { 1801 ADBG("PEWD") 1802 1803 Store(Arg0, Local7) 1804 Or(Local7, ShiftLeft(Arg1, 20), Local7) 1805 Or(Local7, ShiftLeft(Arg2, 15), Local7) 1806 Or(Local7, ShiftLeft(Arg3, 12), Local7) 1807 Or(Local7, Arg4, Local7) 1808 1809 OperationRegion(PCI0, SystemMemory, Local7, 4) 1810 Field(PCI0, ByteAcc,NoLock,Preserve) 1811 { 1812 TEMP, 32 1813 } 1814 1815 Store(Arg5,TEMP) 1816 } // End of Method(PEWD,6,Serialized) 1817 1818 // 1819 // Name: STDC 1820 // Description: Function to get Standard Capability Register Offset 1821 // Input: Arg0 -> PCIE base address 1822 // Arg1 -> Bus 1823 // Arg2 -> Device 1824 // Arg3 -> Function 1825 // Arg4 -> Capability ID 1826 // Return: Capability Register Offset data 1827 // 1828 Method(STDC,5,Serialized) 1829 { 1830 ADBG("STDC") 1831 1832 //Check for Referenced device is present or not 1833 Store(PERW(Arg0, Arg1, Arg2, Arg3, 0x00), Local7) //Vendor ID register 1834 If(LEqual(Local7, 0xFFFF)) 1835 { 1836 ADBG("Referenced device is not present") 1837 Return(0) 1838 } 1839 1840 Store(PERW(Arg0, Arg1, Arg2, Arg3, 0x06), Local0) //Device Status register 1841 If (LEqual(And(Local0, 16), 0)) //Bit4 - Capabilities List 1842 { 1843 //No Capabilities linked list is available 1844 ADBG("No Capabilities linked list is available") 1845 Return(0) 1846 } 1847 1848 //Local1 is for storing CapabilityID 1849 //Local2 is for storing CapabilityPtr 1850 Store(PERB(Arg0, Arg1, Arg2, Arg3, 0x34), Local2) //CapabilityPtr 1851 1852 While(1) 1853 { 1854 And(Local2, 0xFC, Local2) //Each capability must be DWORD aligned 1855 1856 If(LEqual(Local2, 0)) //A pointer value of 00h is used to indicate the last capability in the list 1857 { 1858 ADBG("Capability ID is not found") 1859 Return(0) 1860 } 1861 1862 Store(PERB(Arg0, Arg1, Arg2, Arg3, Local2), Local1) //CapabilityID 1863 1864 If(LEqual(Arg4, Local1)) //CapabilityID match 1865 { 1866 ADBG("Capability ID is found") 1867 ADBG("Capability Offset : ") 1868 ADBG(Local2) 1869 Return(Local2) 1870 } 1871 Store(PERB(Arg0, Arg1, Arg2, Arg3, Add(Local2, 1)), Local2) //CapabilityPtr 1872 Return(0) 1873 } 1874 } // End of Method(STDC,5,Serialized) 1875 1876} // End Scope(\_SB) 1877 1878