1 /** @file 2 * 3 * Copyright (c) Microsoft Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-2-Clause-Patent 6 * 7 **/ 8 9 #include <IndustryStandard/Bcm2836.h> 10 11 #ifndef __BCM2836_SDIO_H__ 12 #define __BCM2836_SDIO_H__ 13 14 // MMC/SD/SDIO1 register definitions. 15 #define MMCHS1_OFFSET 0x00300000 16 #define MMCHS2_OFFSET 0x00340000 17 #define MMCHS1_BASE (BCM2836_SOC_REGISTERS + MMCHS1_OFFSET) 18 #define MMCHS2_BASE (BCM2836_SOC_REGISTERS + MMCHS2_OFFSET) 19 #define MMCHS1_LENGTH 0x00000100 20 #define MMCHS2_LENGTH 0x00000100 21 22 #define MMCHS_BLK (mMmcHsBase + 0x4) 23 #define BLEN_512BYTES (0x200UL << 0) 24 25 #define MMCHS_ARG (mMmcHsBase + 0x8) 26 27 #define MMCHS_CMD (mMmcHsBase + 0xC) 28 #define BCE_ENABLE BIT1 29 #define DDIR_READ BIT4 30 #define DDIR_WRITE (0x0UL << 4) 31 #define MSBS_SGLEBLK (0x0UL << 5) 32 #define MSBS_MULTBLK BIT5 33 #define RSP_TYPE_MASK (0x3UL << 16) 34 #define RSP_TYPE_136BITS BIT16 35 #define RSP_TYPE_48BITS (0x2UL << 16) 36 #define RSP_TYPE_48BUSY (0x3UL << 16) 37 #define CCCE_ENABLE BIT19 38 #define CICE_ENABLE BIT20 39 #define DP_ENABLE BIT21 40 41 #define CMD_TYPE_NORMAL 0 42 #define CMD_TYPE_ABORT 3 43 #define TYPE(CMD_TYPE) (((CMD_TYPE) & 0x3) << 22) 44 #define _INDX(CMD_INDX) ((CMD_INDX & 0x3F) << 24) 45 #define MMC_CMD_NUM(CMD) (((CMD) >> 24) & 0x3F) 46 #define INDX(CMD_INDX) (TYPE(CMD_TYPE_NORMAL) | _INDX(CMD_INDX)) 47 #define INDX_ABORT(CMD_INDX) (TYPE(CMD_TYPE_ABORT) | _INDX(CMD_INDX)) 48 49 #define MMCHS_RSP10 (mMmcHsBase + 0x10) 50 #define MMCHS_RSP32 (mMmcHsBase + 0x14) 51 #define MMCHS_RSP54 (mMmcHsBase + 0x18) 52 #define MMCHS_RSP76 (mMmcHsBase + 0x1C) 53 #define MMCHS_DATA (mMmcHsBase + 0x20) 54 55 #define MMCHS_PRES_STATE (mMmcHsBase + 0x24) 56 #define CMDI_MASK BIT0 57 #define CMDI_ALLOWED (0x0UL << 0) 58 #define CMDI_NOT_ALLOWED BIT0 59 #define DATI_MASK BIT1 60 #define DATI_ALLOWED (0x0UL << 1) 61 #define DATI_NOT_ALLOWED BIT1 62 #define WRITE_PROTECT_OFF BIT19 63 64 #define MMCHS_HCTL (mMmcHsBase + 0x28) 65 #define DTW_1_BIT (0x0UL << 1) 66 #define DTW_4_BIT BIT1 67 #define SDBP_MASK BIT8 68 #define SDBP_OFF (0x0UL << 8) 69 #define SDBP_ON BIT8 70 #define SDVS_MASK (0x7UL << 9) 71 #define SDVS_1_8_V (0x5UL << 9) 72 #define SDVS_3_0_V (0x6UL << 9) 73 #define SDVS_3_3_V (0x7UL << 9) 74 #define IWE BIT24 75 76 #define MMCHS_SYSCTL (mMmcHsBase + 0x2C) 77 #define ICE BIT0 78 #define ICS_MASK BIT1 79 #define ICS BIT1 80 #define CEN BIT2 81 #define CLKD_MASK (0x3FFUL << 6) 82 #define CLKD_80KHZ (0x258UL) //(96*1000/80)/2 83 #define CLKD_400KHZ (0xF0UL) 84 #define CLKD_12500KHZ (0x200UL) 85 #define DTO_MASK (0xFUL << 16) 86 #define DTO_VAL (0xEUL << 16) 87 #define SRA BIT24 88 #define SRC_MASK BIT25 89 #define SRC BIT25 90 #define SRD BIT26 91 92 #define MMCHS_INT_STAT (mMmcHsBase + 0x30) 93 #define CC BIT0 94 #define TC BIT1 95 #define BWR BIT4 96 #define BRR BIT5 97 #define CARD_INS BIT6 98 #define ERRI BIT15 99 #define CTO BIT16 100 #define DTO BIT20 101 #define DCRC BIT21 102 #define DEB BIT22 103 104 #define MMCHS_IE (mMmcHsBase + 0x34) 105 #define CC_EN BIT0 106 #define TC_EN BIT1 107 #define BWR_EN BIT4 108 #define BRR_EN BIT5 109 #define CTO_EN BIT16 110 #define CCRC_EN BIT17 111 #define CEB_EN BIT18 112 #define CIE_EN BIT19 113 #define DTO_EN BIT20 114 #define DCRC_EN BIT21 115 #define DEB_EN BIT22 116 #define CERR_EN BIT28 117 #define BADA_EN BIT29 118 #define ALL_EN 0xFFFFFFFF 119 120 #define MMCHS_ISE (mMmcHsBase + 0x38) 121 #define CC_SIGEN BIT0 122 #define TC_SIGEN BIT1 123 #define BWR_SIGEN BIT4 124 #define BRR_SIGEN BIT5 125 #define CTO_SIGEN BIT16 126 #define CCRC_SIGEN BIT17 127 #define CEB_SIGEN BIT18 128 #define CIE_SIGEN BIT19 129 #define DTO_SIGEN BIT20 130 #define DCRC_SIGEN BIT21 131 #define DEB_SIGEN BIT22 132 #define CERR_SIGEN BIT28 133 #define BADA_SIGEN BIT29 134 135 #define MMCHS_AC12 (mMmcHsBase + 0x3C) 136 #define MMCHS_HC2R (mMmcHsBase + 0x3E) 137 138 #define MMCHS_CAPA (mMmcHsBase + 0x40) 139 #define VS30 BIT25 140 #define VS18 BIT26 141 142 #define MMCHS_CUR_CAPA (mMmcHsBase + 0x48) 143 #define MMCHS_REV (mMmcHsBase + 0xFC) 144 145 #define BLOCK_COUNT_SHIFT 16 146 #define RCA_SHIFT 16 147 148 #define CMD_R1 (RSP_TYPE_48BITS | CCCE_ENABLE | CICE_ENABLE) 149 #define CMD_R1B (RSP_TYPE_48BUSY | CCCE_ENABLE | CICE_ENABLE) 150 #define CMD_R2 (RSP_TYPE_136BITS | CCCE_ENABLE) 151 #define CMD_R3 (RSP_TYPE_48BITS) 152 #define CMD_R6 (RSP_TYPE_48BITS | CCCE_ENABLE | CICE_ENABLE) 153 #define CMD_R7 (RSP_TYPE_48BITS | CCCE_ENABLE | CICE_ENABLE) 154 155 #define CMD_R1_ADTC (CMD_R1 | DP_ENABLE) 156 #define CMD_R1_ADTC_READ (CMD_R1_ADTC | DDIR_READ) 157 #define CMD_R1_ADTC_WRITE (CMD_R1_ADTC | DDIR_WRITE) 158 159 #define CMD0 (INDX(0)) // Go idle 160 #define CMD1 (INDX(1) | CMD_R3) // MMC: Send Op Cond 161 #define CMD2 (INDX(2) | CMD_R2) // Send CID 162 #define CMD3 (INDX(3) | CMD_R6) // Set Relative Addr 163 #define CMD4 (INDX(4)) // Set DSR 164 #define CMD5 (INDX(5) | CMD_R1B) // SDIO: Sleep/Awake 165 #define CMD6 (INDX(6) | CMD_R1_ADTC_READ) // Switch 166 #define CMD7 (INDX(7) | CMD_R1B) // Select/Deselect 167 #define CMD8_SD (INDX(8) | CMD_R7) // Send If Cond 168 #define CMD8_SD_ARG (0x0UL << 12 | BIT8 | 0xCEUL << 0) 169 #define CMD8_MMC (INDX(8) | CMD_R1_ADTC_READ) // Send Ext Csd 170 #define CMD8_MMC_ARG (0) 171 #define CMD9 (INDX(9) | CMD_R2) // Send CSD 172 #define CMD10 (INDX(10) | CMD_R2) // Send CID 173 #define CMD11 (INDX(11) | CMD_R1) // Voltage Switch 174 #define CMD12 (INDX_ABORT(12) | CMD_R1B) // Stop Transmission 175 #define CMD13 (INDX(13) | CMD_R1) // Send Status 176 #define CMD15 (INDX(15)) // Go inactive state 177 #define CMD16 (INDX(16) | CMD_R1) // Set Blocklen 178 #define CMD17 (INDX(17) | CMD_R1_ADTC_READ) // Read Single Block 179 #define CMD18 (INDX(18) | CMD_R1_ADTC_READ | MSBS_MULTBLK) // Read Multiple Blocks 180 #define CMD19 (INDX(19) | CMD_R1_ADTC_READ) // SD: Send Tuning Block (64 bytes) 181 #define CMD20 (INDX(20) | CMD_R1B) // SD: Speed Class Control 182 #define CMD23 (INDX(23) | CMD_R1) // Set Block Count for CMD18 and CMD25 183 #define CMD24 (INDX(24) | CMD_R1_ADTC_WRITE) // Write Block 184 #define CMD25 (INDX(25) | CMD_R1_ADTC_WRITE | MSBS_MULTBLK) // Write Multiple Blocks 185 #define CMD55 (INDX(55) | CMD_R1) // App Cmd 186 187 #define ACMD6 (INDX(6) | CMD_R1) // Set Bus Width 188 #define ACMD22 (INDX(22) | CMD_R1_ADTC_READ) // SEND_NUM_WR_BLOCKS 189 #define ACMD41 (INDX(41) | CMD_R3) // Send Op Cond 190 #define ACMD51 (INDX(51) | CMD_R1_ADTC_READ) // Send SCR 191 192 // User-friendly command names 193 #define CMD_IO_SEND_OP_COND CMD5 194 #define CMD_SEND_CSD CMD9 // CSD: Card-Specific Data 195 #define CMD_STOP_TRANSMISSION CMD12 196 #define CMD_SEND_STATUS CMD13 197 #define CMD_READ_SINGLE_BLOCK CMD17 198 #define CMD_READ_MULTIPLE_BLOCK CMD18 199 #define CMD_SET_BLOCK_COUNT CMD23 200 #define CMD_WRITE_SINGLE_BLOCK CMD24 201 #define CMD_WRITE_MULTIPLE_BLOCK CMD25 202 203 #endif /* __BCM2836_SDIO_H__ */ 204