1/**@file 2 3Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> 4SPDX-License-Identifier: BSD-2-Clause-Patent 5 6**/ 7 8#include <PchAccess.h> 9 10Name (PNVB, 0xFFFF0000) // PCH NVS Base address 11Name (PNVL, 0xAA55) // PCH NVS Length 12Include ("PchNvs.asl") 13 14// 15// Include GPIO macros and access library 16// 17include("GpioAcpiDefines.h") 18include("GpioLib.asl") 19 20// 21// Trace Hub debug library 22// Include it earlier so the debug function can be used as soon as possible 23// 24Include ("TraceHubDebug.asl") 25 26Name(SPTH,1) 27Name(SPTL,2) 28Method(PCHV) { 29 If(LEqual(PCHS, 1)) { Return (SPTH) } // series=H -> SPT-H 30 If(LEqual(PCHS, 2)) { Return (SPTL) } // series=LP -> SPT-LP 31 Return (0) 32} 33 34// 35// This PME event (PCH's GPE 6Dh) is received when any PCH internal device with 36// PCI Power Management capabilities on bus 0 asserts the equivalent of the PME# signal. 37// 38Scope(\_GPE) { 39 Method(_L6D, 0, Serialized) { 40 \_SB.PCI0.XHC.GPEH() 41 \_SB.PCI0.HDAS.GPEH() 42 \_SB.PCI0.GLAN.GPEH() 43 \_SB.PCI0.XDCI.GPEH() 44 } 45} 46 47Scope (\_SB.PCI0) { 48 49 Name(TEMP,0) // scratch variable that does not cause compiler warnings as writes to Localx variables do. 50 51 // 52 // PCH reserved resource 53 // 54 Device(PRRE) { 55 Name(_HID,EISAID("PNP0C02")) // motherboard resource 56 Name(_UID,"PCHRESV") 57 Name(_STA,0x3) // device present and decodes its resources, but not to be displayed in OSPM 58 59 Method(_CRS,0,Serialized) 60 { 61 Name(BUF0,ResourceTemplate(){ 62 // 63 // PCH RESERVED MMIO RANGE 64 // 0xFD000000 to 0xFE7FFFFF 65 // to skip over address range that might be claimed by the GPIO, Intel Serial IO, Thermal, TraceHub and CIO2 devices 66 // need to split this into 5 ranges 67 // The GPIO COMM0,1,3 and SerialIO ranges will be handled by SIRC device. 68 // 69 Memory32Fixed(ReadWrite,0xFD000000,0x00AC0000) // 0xFD000000 - 0xFDABFFFF 70 // Skip 0xFDAC0000 - 0xFDACFFFF for GPIO_COMM3 71 Memory32Fixed(ReadWrite,0xFDAD0000,0x00010000) // 0xFDAD0000 - 0xFDADFFFF, only cover GPIO_COMM2 range 72 // Skip 0xFDAE0000 - 0xFDAFFFFF for GPIO_COMM0 and GPIO_COMM1 73 Memory32Fixed(ReadWrite,0xFDB00000,0x00500000) // 0xFDB00000 - 0xFDFFFFFF 74 Memory32Fixed(ReadWrite,0xFE000000,0x00020000) // 0xFE000000 - 0xFE01FFFF 75 // Skip 0xFE020000 - 0xFE035FFF for Serial IO 76 Memory32Fixed(ReadWrite,0xFE036000,0x00006000) // 0xFE036000 - 0xFE03BFFF 77 // Skip 0xFE03C000 - 0xFE03CFFF for Thermal Device in ACPI mode 78 Memory32Fixed(ReadWrite,0xFE03D000,0x003C3000) // 0xFE03D000 - 0xFE3FFFFF 79 // Skip 0xFE400000 - 0xFE40FFFF for CIO2 in ACPI mode 80 Memory32Fixed(ReadWrite,0xFE410000,0x003F0000) // 0xFE410000 - 0xFE7FFFFF 81 }) 82 Return(BUF0) 83 } 84 } 85 Device(IOTR) { 86 // 87 // This device claims IO range reserved for IO traps 88 // to prevent OS from reusing it for other purposes 89 // 90 Name(_HID,EISAID("PNP0C02")) 91 Name(_UID,"IoTraps") 92 Method(_CRS) { 93 Store(ResourceTemplate() { }, Local0) 94 Name(BUF0,ResourceTemplate(){ Io(Decode16,0x0,0x0,0x1,0xFF,TAG0) }) 95 Name(BUF1,ResourceTemplate(){ Io(Decode16,0x0,0x0,0x1,0xFF,TAG1) }) 96 Name(BUF2,ResourceTemplate(){ Io(Decode16,0x0,0x0,0x1,0xFF,TAG2) }) 97 Name(BUF3,ResourceTemplate(){ Io(Decode16,0x0,0x0,0x1,0xFF,TAG3) }) 98 CreateWordField(BUF0,TAG0._MIN,AMI0);CreateWordField(BUF0,TAG0._MAX,AMA0) 99 CreateWordField(BUF1,TAG1._MIN,AMI1);CreateWordField(BUF1,TAG1._MAX,AMA1) 100 CreateWordField(BUF2,TAG2._MIN,AMI2);CreateWordField(BUF2,TAG2._MAX,AMA2) 101 CreateWordField(BUF3,TAG3._MIN,AMI3);CreateWordField(BUF3,TAG3._MAX,AMA3) 102 Store(ITA0,AMI0);Store(ITA0,AMA0) 103 Store(ITA1,AMI1);Store(ITA1,AMA1) 104 Store(ITA2,AMI2);Store(ITA2,AMA2) 105 Store(ITA3,AMI3);Store(ITA3,AMA3) 106 // Win7 can't store result of ConcatenateResTemplate directly into one of its input parameters 107 if(LEqual(ITS0,1)) { ConcatenateResTemplate(Local0, BUF0, Local1); Store(Local1, Local0) } 108 if(LEqual(ITS1,1)) { ConcatenateResTemplate(Local0, BUF1, Local1); Store(Local1, Local0) } 109 if(LEqual(ITS2,1)) { ConcatenateResTemplate(Local0, BUF2, Local1); Store(Local1, Local0) } 110 if(LEqual(ITS3,1)) { ConcatenateResTemplate(Local0, BUF3, Local1); Store(Local1, Local0) } 111 return (Local0) 112 } 113 } 114 115 116 // 117 // LPC Bridge - Device 31, Function 0, this is only for PCH register Memory Region declare, 118 // it's better to be declared as early as possible since it's widely used in whole ACPI name space. 119 // Please add any code which needs to reference any register of it after this 120 // 121 Device(LPCB) { 122 Name(_ADR, 0x001F0000) 123 Method(_DSM,4,serialized){if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }; Return(Buffer() {0})} 124 125 OperationRegion(LPC, PCI_Config, 0x00, 0x100) 126 Field(LPC, AnyAcc, NoLock, Preserve) 127 { 128 Offset(0x02), 129 CDID, 16, 130 Offset(0x08), 131 CRID, 8, 132 Offset(R_PCH_LPC_IOD), // 0x80 133 IOD0, 8, 134 IOD1, 8, 135 Offset(0xA0), 136 , 9, 137 PRBL, 1, 138 Offset(R_PCH_LPC_BC), // 0xDC 139 , 2, 140 ESPI, 1, 141 } 142 } 143 144 // 145 // PCH Power Management Controller 146 // 147 Device(PPMC) { 148 Name(_ADR, 0x001F0002) 149 Method(_DSM,4,serialized){if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }; Return(Buffer() {0})} 150 } 151 152 // 153 // SMBus Controller - Device 31, Function 4 154 // 155 Device(SBUS) { 156 Name(_ADR,0x001F0004) 157 Method(_DSM,4,serialized){if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }; Return(Buffer() {0})} 158 } 159} 160 161scope(\_SB) { 162 Include ("IrqLink.asl") 163} 164 165Scope(\) 166{ 167 // 168 // PCR Register Access Methods 169 // 170 // PCR Dword Read 171 // arg0: PID 172 // arg1: Offset 173 // 174 Method (PCRR, 2, Serialized) { 175 Add (ShiftLeft (arg0, 16), arg1, Local0) 176 Add (SBRG, Local0, Local0) 177 OperationRegion (PCR0, SystemMemory, Local0, 0x4) 178 Field(PCR0,DWordAcc,Lock,Preserve) { 179 Offset(0x00), 180 DAT0, 32 181 } // End Field PCR0 182 Return (DAT0) 183 } // End Method PCRR 184 185 // 186 // PCR Dword Write 187 // arg0: PID 188 // arg1: Offset 189 // arg2: write data 190 // 191 Method (PCRW, 3, Serialized) { 192 Add (ShiftLeft (arg0, 16), arg1, Local0) 193 Add (SBRG, Local0, Local0) 194 OperationRegion (PCR0, SystemMemory, Local0, 0x4) 195 Field(PCR0,DWordAcc,Lock,Preserve) { 196 Offset(0x00), 197 DAT0, 32 198 } // End Field PCR0 199 Store (arg2, DAT0) 200 // read back for PCR back to back limitation 201 Store (PCRR (PID_LPC, R_PCH_PCR_RTC_RTCDCG), local0) 202 } // End Method PCRW 203 204 // 205 // PCR Dword Or 206 // arg0: PID 207 // arg1: Offset 208 // arg2: Or data 209 // 210 Method (PCRO, 3, Serialized) { 211 Store(PCRR(arg0,arg1),Local0) // Store PCR Read data in Local0 212 Store(Or(Local0,arg2),Local1) // Or data 213 PCRW(arg0,arg1,Local1) // Write data back 214 } 215 216 // 217 // PCR Dword And 218 // arg0: PID 219 // arg1: Offset 220 // arg2: And data 221 // 222 Method (PCRA, 3, Serialized) { 223 Store(PCRR(arg0,arg1),Local0) // Store PCR Read data in Local0 224 Store(And(Local0,arg2),Local1) // And data 225 PCRW(arg0,arg1,Local1) // Write data back 226 } 227 228 // 229 // PCR Dword AndThenOr 230 // arg0: PID 231 // arg1: Offset 232 // arg2: And data 233 // arg3: Or data 234 // 235 Method (PCAO, 4, Serialized) { 236 Store(PCRR(arg0,arg1),Local0) // Store PCR Read data in Local0 237 Store(Or(And(Local0,arg2),arg3),Local1) // AndThenOr 238 PCRW(arg0,arg1,Local1) // Write data back 239 } 240 241 Name (TCBV, 0) // TCO I/O base address value 242 Method (TCBS, 0) { 243 If (LEqual(TCBV, 0)) { 244 // PCR[DMI] + 2778h[15:5] 245 Store(PCRR (PID_DMI, R_PCH_PCR_DMI_TCOBASE),Local0) 246 And(Local0,B_PCH_PCR_DMI_TCOBASE_TCOBA,TCBV) 247 } 248 Return (TCBV) 249 } 250 251 // 252 // Define PCH ACPIBASE I/O as an ACPI operating region. The base address 253 // can be found in Device 31, Function 2, Offset 40h. 254 // 255 OperationRegion(PMIO, SystemIo, PMBS, 0x60) 256 Field(PMIO, ByteAcc, NoLock, Preserve) { 257 , 8, 258 PBSS, 1, // Power Button Status 259 Offset(R_PCH_ACPI_GPE_CNTL), // 0x40, General Purpose Event Control 260 , 17, 261 GPEC, 1 // Software GPE Control 262 } 263 264 // 265 // Define PCH TCOBASE I/O 266 // 267 OperationRegion(TCBA, SystemIo, TCBS, 0x10) 268 Field(TCBA, ByteAcc, NoLock, Preserve) { 269 Offset(R_PCH_TCO1_STS), // 0x04 270 , 9, 271 CPSC, 1, // CPUSCI_STS 272 } 273 274 // 275 // PWRM register definitions 276 // 277 OperationRegion(PWMR, SystemMemory, \PWRM, 0x800) 278 Field(PWMR, AnyAcc, NoLock, Preserve) { 279 Offset(R_PCH_PWRM_CFG3), // 0xE0 280 , 16, 281 DWLE, 1, // Deep-Sx WLAN Phy Power Enable 282 HWLE, 1, // Host Wireless LAN Phy Power Enable 283 Offset(R_PCH_PWRM_31C), // 0x31C 284 , 13, 285 SLS0, 1, // SLP_S0# Low Voltage Mode Enable (SLPS0LVEN) 286 , 8, 287 XSQD, 1, // 24MHz Crystal Shutdown Qualification Disable (XTALSDQDIS) 288 } 289 290 // 291 // 292 OperationRegion(PMST, SystemMemory, PWRM, 0x80) 293 Field(PMST, DWordAcc, NoLock, Preserve) { 294 Offset(R_PCH_PWRM_CFG), // 0x18, Power Management Configuration Reg 1 (PM_CFG) 295 , 25, // 296 USBP, 1, // Allow USB2 PHY Core Power Gating (ALLOW_USB2_CORE_PG) 297 Offset(R_PCH_PWRM_PCH_PM_STS), // 0x1C, PCH Power Management Status (PCH_PM_STS) 298 , 24, // 299 PMFS, 1, // PMC Message Full Status (PMC_MSG_FULL_STS) 300 Offset(R_PCH_PWRM_MTPMC), // 0x20, Message to PMC (MTPMC) 301 MPMC, 32, // Message to PMC (MTPMC) 302 Offset(R_PCH_PWRM_PCH_PM_STS2), // 0x24, PCH Power Management Status (PCH_PM_STS2) 303 , 20, // 304 UWAB, 1, // USB2 Workaround Available Bit 305 } 306 307} //end Scope(\) 308 309Scope (\_SB.PCI0) { 310 Name(LTRZ, 0) 311 Name(OBFZ, 0) 312 313 Name(LMSL, 0) 314 Name(LNSL, 0) 315 316 // 317 // LAN Controller - Device 31, Function 6 318 // 319 Device(GLAN) { // GbE Controller 320 Name(_ADR, 0x001F0006) 321 Method(_DSM,4,serialized){if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }; Return(Buffer() {0})} 322 OperationRegion(GLBA, PCI_Config, 0,0x100) 323 Field(GLBA,AnyAcc,NoLock,Preserve) 324 { 325 DVID, 16 326 } 327 // 328 // Byte access for PMCS field to avoid race condition on device D-state 329 // 330 Field(GLBA,ByteAcc,NoLock,Preserve) 331 { 332 Offset(R_PCH_LAN_PMCS), // 0xCC 333 , 8, 334 PMEE, 1, // PME Enable 335 , 6, 336 PMES, 1 // PME Status 337 } 338 339 Method(_PRW, 0) { Return(GPRW(0x6D, 4)) } // can wakeup from S4 state 340 341 Method(_DSW, 3) 342 { 343 Store(Arg0, PMEE) 344 } 345 346 // 347 // GPE handler for GbE, this is part of _Lxx handler for bus 0 PME 348 // 349 Method(GPEH) 350 { 351 If(LEqual(DVID, 0xFFFF)) { 352 Return() 353 } 354 If(LAnd(PMEE, PMES)) { 355 Store(1, PMES) // clear PME Status 356 Notify(GLAN, 0x02) 357 } 358 } 359 } // end "GbE Controller" 360 361} //scope 362 363// 364// xHCI Controller - Device 20, Function 0 365// 366Include("PchXhci.asl") 367 368// 369// xDCI (OTG) Controller - Device 20, Function 1 370// 371include("PchXdci.asl") 372 373Scope(\_SB_.PCI0) { 374 // 375 // High Definition Audio Controller - Device 31, Function 3 376 // 377 include("PchHda.asl") 378 379 // 380 // PCIE Root Port #01 381 // 382 Device(RP01) { 383 Method (_ADR, 0) { 384 If (LNotEqual(RPA1,0)) { 385 Return (RPA1) 386 } Else { 387 Return (0x001C0000) 388 } 389 } 390 // 391 // Pass LTRx to LTRZ so PchPcie.asl can be reused for PCIes. 392 // 393 Method(_INI) 394 { 395 Store (LTR1, LTRZ) 396 Store (PML1, LMSL) 397 Store (PNL1, LNSL) 398 Store (OBF1, OBFZ) 399 } 400 Include("PchPcie.asl") 401 Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 state 402 Method(_PRT, 0) { 403 If(PICM) { Return(AR04) }// APIC mode 404 Return (PR04) // PIC Mode 405 } // end _PRT 406 } // end "PCIE Root Port #01" 407 408 // 409 // PCIE Root Port #02 410 // 411 Device(RP02) { 412 Method (_ADR, 0) { 413 If (LNotEqual(RPA2,0)) { 414 Return (RPA2) 415 } Else { 416 Return (0x001C0001) 417 } 418 } 419 // 420 // Pass LTRx to LTRZ so PchPcie.asl can be reused for PCIes. 421 // 422 Method(_INI) 423 { 424 Store (LTR2, LTRZ) 425 Store (PML2, LMSL) 426 Store (PNL2, LNSL) 427 Store (OBF2, OBFZ) 428 } 429 Include("PchPcie.asl") 430 Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 state 431 Method(_PRT, 0) { 432 If(PICM) { Return(AR05) }// APIC mode 433 Return (PR05) // PIC Mode 434 } // end _PRT 435 } // end "PCIE Root Port #02" 436 437 // 438 // PCIE Root Port #03 439 // 440 Device(RP03) { 441 Method (_ADR, 0) { 442 If (LNotEqual(RPA3,0)) { 443 Return (RPA3) 444 } Else { 445 Return (0x001C0002) 446 } 447 } 448 // 449 // Pass LTRx to LTRZ so PchPcie.asl can be reused for PCIes. 450 // 451 Method(_INI) 452 { 453 Store (LTR3, LTRZ) 454 Store (PML3, LMSL) 455 Store (PNL3, LNSL) 456 Store (OBF3, OBFZ) 457 } 458 Include("PchPcie.asl") 459 Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 state 460 Method(_PRT, 0) { 461 If(PICM) { Return(AR06) }// APIC mode 462 Return (PR06) // PIC Mode 463 } // end _PRT 464 } // end "PCIE Root Port #03" 465 466 // 467 // PCIE Root Port #04 468 // 469 Device(RP04) { 470 Method (_ADR, 0) { 471 If (LNotEqual(RPA4,0)) { 472 Return (RPA4) 473 } Else { 474 Return (0x001C0003) 475 } 476 } 477 // 478 // Pass LTRx to LTRZ so PchPcie.asl can be reused for PCIes. 479 // 480 Method(_INI) 481 { 482 Store (LTR4, LTRZ) 483 Store (PML4, LMSL) 484 Store (PNL4, LNSL) 485 Store (OBF4, OBFZ) 486 } 487 Include("PchPcie.asl") 488 Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 state 489 Method(_PRT, 0) { 490 If(PICM) { Return(AR07) }// APIC mode 491 Return (PR07) // PIC Mode 492 } // end _PRT 493 } // end "PCIE Root Port #04" 494 495 // 496 // PCIE Root Port #05 497 // 498 Device(RP05) { 499 Method (_ADR, 0) { 500 If (LNotEqual(RPA5,0)) { 501 Return (RPA5) 502 } Else { 503 Return (0x001C0004) 504 } 505 } 506 // 507 // Pass LTRx to LTRZ so PchPcie.asl can be reused for PCIes. 508 // 509 Method(_INI) 510 { 511 Store (LTR5, LTRZ) 512 Store (PML5, LMSL) 513 Store (PNL5, LNSL) 514 Store (OBF5, OBFZ) 515 } 516 Include("PchPcie.asl") 517 Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 state 518 Method(_PRT, 0) { 519 If(PICM) { Return(AR04) }// APIC mode 520 Return (PR04) // PIC Mode 521 } // end _PRT 522 } // end "PCIE Root Port #05" 523 524 // 525 // PCIE Root Port #06 526 // 527 Device(RP06) { 528 Method (_ADR, 0) { 529 If (LNotEqual(RPA6,0)) { 530 Return (RPA6) 531 } Else { 532 Return (0x001C0005) 533 } 534 } 535 // 536 // Pass LTRx to LTRZ so PchPcie.asl can be reused for PCIes. 537 // 538 Method(_INI) 539 { 540 Store (LTR6, LTRZ) 541 Store (PML6, LMSL) 542 Store (PNL6, LNSL) 543 Store (OBF6, OBFZ) 544 } 545 Include("PchPcie.asl") 546 Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 state 547 Method(_PRT, 0) { 548 If(PICM) { Return(AR05) }// APIC mode 549 Return (PR05) // PIC Mode 550 } // end _PRT 551 } // end "PCIE Root Port #06" 552 553 // 554 // PCIE Root Port #07 555 // 556 Device(RP07) { 557 Method (_ADR, 0) { 558 If (LNotEqual(RPA7,0)) { 559 Return (RPA7) 560 } Else { 561 Return (0x001C0006) 562 } 563 } 564 // 565 // Pass LTRx to LTRZ so PchPcie.asl can be reused for PCIes. 566 // 567 Method(_INI) 568 { 569 Store (LTR7, LTRZ) 570 Store (PML7, LMSL) 571 Store (PNL7, LNSL) 572 Store (OBF7, OBFZ) 573 } 574 Include("PchPcie.asl") 575 Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 state 576 Method(_PRT, 0) { 577 If(PICM) { Return(AR06) } // APIC mode 578 Return (PR06) // PIC Mode 579 } // end _PRT 580 } // end "PCIE Root Port #07" 581 582 // 583 // PCIE Root Port #08 584 // 585 Device(RP08) { 586 Method (_ADR, 0) { 587 If (LNotEqual(RPA8,0)) { 588 Return (RPA8) 589 } Else { 590 Return (0x001C0007) 591 } 592 } 593 // 594 // Pass LTRx to LTRZ so PchPcie.asl can be reused for PCIes. 595 // 596 Method(_INI) 597 { 598 Store (LTR8, LTRZ) 599 Store (PML8, LMSL) 600 Store (PNL8, LNSL) 601 Store (OBF8, OBFZ) 602 } 603 Include("PchPcie.asl") 604 Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 state 605 Method(_PRT, 0) { 606 If(PICM) { Return(AR07) }// APIC mode 607 Return (PR07) // PIC Mode 608 } // end _PRT 609 } // end "PCIE Root Port #08" 610 611 // 612 // PCIE Root Port #09 613 // 614 Device(RP09) { 615 Method (_ADR, 0) { 616 If (LNotEqual(RPA9,0)) { 617 Return (RPA9) 618 } Else { 619 Return (0x001D0000) 620 } 621 } 622 // 623 // Pass LTRx to LTRZ so PchPcie.asl can be reused for PCIes. 624 // 625 Method(_INI) 626 { 627 Store (LTR9, LTRZ) 628 Store (PML9, LMSL) 629 Store (PNL9, LNSL) 630 Store (OBF9, OBFZ) 631 } 632 Include("PchPcie.asl") 633 Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 state 634 Method(_PRT, 0) { 635 If(PICM) { Return(AR04) }// APIC mode 636 Return (PR04) // PIC Mode 637 } // end _PRT 638 } // end "PCIE Root Port #09" 639 640 // 641 // PCIE Root Port #10 642 // 643 Device(RP10) { 644 Method (_ADR, 0) { 645 If (LNotEqual(RPAA,0)) { 646 Return (RPAA) 647 } Else { 648 Return (0x001D0001) 649 } 650 } 651 // 652 // Pass LTRx to LTRZ so PchPcie.asl can be reused for PCIes. 653 // 654 Method(_INI) 655 { 656 Store (LTRA, LTRZ) 657 Store (PMLA, LMSL) 658 Store (PNLA, LNSL) 659 Store (OBFA, OBFZ) 660 } 661 Include("PchPcie.asl") 662 Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 state 663 Method(_PRT, 0) { 664 If(PICM) { Return(AR05) }// APIC mode 665 Return (PR05) // PIC Mode 666 } // end _PRT 667 } // end "PCIE Root Port #10" 668 669 // 670 // PCIE Root Port #11 671 // 672 Device(RP11) { 673 Method (_ADR, 0) { 674 If (LNotEqual(RPAB,0)) { 675 Return (RPAB) 676 } Else { 677 Return (0x001D0002) 678 } 679 } 680 // 681 // Pass LTRx to LTRZ so PchPcie.asl can be reused for PCIes. 682 // 683 Method(_INI) 684 { 685 Store (LTRB, LTRZ) 686 Store (PMLB, LMSL) 687 Store (PNLB, LNSL) 688 Store (OBFB, OBFZ) 689 } 690 Include("PchPcie.asl") 691 Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 state 692 Method(_PRT, 0) { 693 If(PICM) { Return(AR06) }// APIC mode 694 Return (PR06) // PIC Mode 695 } // end _PRT 696 } // end "PCIE Root Port #11" 697 698 // 699 // PCIE Root Port #12 700 // 701 Device(RP12) { 702 Method (_ADR, 0) { 703 If (LNotEqual(RPAC,0)) { 704 Return (RPAC) 705 } Else { 706 Return (0x001D0003) 707 } 708 } 709 // 710 // Pass LTRx to LTRZ so PchPcie.asl can be reused for PCIes. 711 // 712 Method(_INI) 713 { 714 Store (LTRC, LTRZ) 715 Store (PMLC, LMSL) 716 Store (PNLC, LNSL) 717 Store (OBFC, OBFZ) 718 } 719 Include("PchPcie.asl") 720 Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 state 721 Method(_PRT, 0) { 722 If(PICM) { Return(AR07) }// APIC mode 723 Return (PR07) // PIC Mode 724 } // end _PRT 725 } // end "PCIE Root Port #12" 726 727 // 728 // PCIE Root Port #13 729 // 730 Device(RP13) { 731 Method (_ADR, 0) { 732 If (LNotEqual(RPAD,0)) { 733 Return (RPAD) 734 } Else { 735 Return (0x001D0004) 736 } 737 } 738 // 739 // Pass LTRx to LTRZ so PchPcie.asl can be reused for PCIes. 740 // 741 Method(_INI) 742 { 743 Store (LTRD, LTRZ) 744 Store (PMLD, LMSL) 745 Store (PNLD, LNSL) 746 Store (OBFD, OBFZ) 747 } 748 Include("PchPcie.asl") 749 Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 state 750 Method(_PRT, 0) { 751 If(PICM) { Return(AR04) }// APIC mode 752 Return (PR04) // PIC Mode 753 } // end _PRT 754 } // end "PCIE Root Port #13" 755 756 // 757 // PCIE Root Port #14 758 // 759 Device(RP14) { 760 Method (_ADR, 0) { 761 If (LNotEqual(RPAE,0)) { 762 Return (RPAE) 763 } Else { 764 Return (0x001D0005) 765 } 766 } 767 // 768 // Pass LTRx to LTRZ so PchPcie.asl can be reused for PCIes. 769 // 770 Method(_INI) 771 { 772 Store (LTRE, LTRZ) 773 Store (PMLE, LMSL) 774 Store (PNLE, LNSL) 775 Store (OBFE, OBFZ) 776 } 777 Include("PchPcie.asl") 778 Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 state 779 Method(_PRT, 0) { 780 If(PICM) { Return(AR05) }// APIC mode 781 Return (PR05) // PIC Mode 782 } // end _PRT 783 } // end "PCIE Root Port #14" 784 785 // 786 // PCIE Root Port #15 787 // 788 Device(RP15) { 789 Method (_ADR, 0) { 790 If (LNotEqual(RPAF,0)) { 791 Return (RPAF) 792 } Else { 793 Return (0x001D0006) 794 } 795 } 796 // 797 // Pass LTRx to LTRZ so PchPcie.asl can be reused for PCIes. 798 // 799 Method(_INI) 800 { 801 Store (LTRF, LTRZ) 802 Store (PMLF, LMSL) 803 Store (PNLF, LNSL) 804 Store (OBFF, OBFZ) 805 } 806 Include("PchPcie.asl") 807 Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 state 808 Method(_PRT, 0) { 809 If(PICM) { Return(AR06) }// APIC mode 810 Return (PR06) // PIC Mode 811 } // end _PRT 812 } // end "PCIE Root Port #15" 813 814 // 815 // PCIE Root Port #16 816 // 817 Device(RP16) { 818 Method (_ADR, 0) { 819 If (LNotEqual(RPAG,0)) { 820 Return (RPAG) 821 } Else { 822 Return (0x001D0007) 823 } 824 } 825 // 826 // Pass LTRx to LTRZ so PchPcie.asl can be reused for PCIes. 827 // 828 Method(_INI) 829 { 830 Store (LTRG, LTRZ) 831 Store (PMLG, LMSL) 832 Store (PNLG, LNSL) 833 Store (OBFG, OBFZ) 834 } 835 Include("PchPcie.asl") 836 Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 state 837 Method(_PRT, 0) { 838 If(PICM) { Return(AR07) }// APIC mode 839 Return (PR07) // PIC Mode 840 } // end _PRT 841 } // end "PCIE Root Port #16" 842 843 // 844 // PCIE Root Port #17 845 // 846 Device(RP17) { 847 Method (_ADR, 0) { 848 If (LNotEqual(RPAH,0)) { 849 Return (RPAH) 850 } Else { 851 Return (0x001B0000) 852 } 853 } 854 // 855 // Pass LTRx to LTRZ so PchPcie.asl can be reused for PCIes. 856 // 857 Method(_INI) 858 { 859 Store (LTRH, LTRZ) 860 Store (PMLH, LMSL) 861 Store (PNLH, LNSL) 862 Store (OBFH, OBFZ) 863 } 864 Include("PchPcie.asl") 865 Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 state 866 Method(_PRT, 0) { 867 If(PICM) { Return(AR04) }// APIC mode 868 Return (PR04) // PIC Mode 869 } // end _PRT 870 } // end "PCIE Root Port #17" 871 872 // 873 // PCIE Root Port #18 874 // 875 Device(RP18) { 876 Method (_ADR, 0) { 877 If (LNotEqual(RPAI,0)) { 878 Return (RPAI) 879 } Else { 880 Return (0x001B0001) 881 } 882 } 883 // 884 // Pass LTRx to LTRZ so PchPcie.asl can be reused for PCIes. 885 // 886 Method(_INI) 887 { 888 Store (LTRI, LTRZ) 889 Store (PMLI, LMSL) 890 Store (PNLI, LNSL) 891 Store (OBFI, OBFZ) 892 } 893 Include("PchPcie.asl") 894 Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 state 895 Method(_PRT, 0) { 896 If(PICM) { Return(AR05) }// APIC mode 897 Return (PR05) // PIC Mode 898 } // end _PRT 899 } // end "PCIE Root Port #18" 900 901 // 902 // PCIE Root Port #19 903 // 904 Device(RP19) { 905 Method (_ADR, 0) { 906 If (LNotEqual(RPAJ,0)) { 907 Return (RPAJ) 908 } Else { 909 Return (0x001B0002) 910 } 911 } 912 // 913 // Pass LTRx to LTRZ so PchPcie.asl can be reused for PCIes. 914 // 915 Method(_INI) 916 { 917 Store (LTRJ, LTRZ) 918 Store (PMLJ, LMSL) 919 Store (PNLJ, LNSL) 920 Store (OBFJ, OBFZ) 921 } 922 Include("PchPcie.asl") 923 Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 state 924 Method(_PRT, 0) { 925 If(PICM) { Return(AR06) }// APIC mode 926 Return (PR06) // PIC Mode 927 } // end _PRT 928 } // end "PCIE Root Port #19" 929 930 // 931 // PCIE Root Port #20 932 // 933 Device(RP20) { 934 Method (_ADR, 0) { 935 If (LNotEqual(RPAK,0)) { 936 Return (RPAK) 937 } Else { 938 Return (0x001B0003) 939 } 940 } 941 // 942 // Pass LTRx to LTRZ so PchPcie.asl can be reused for PCIes. 943 // 944 Method(_INI) 945 { 946 Store (LTRK, LTRZ) 947 Store (PMLK, LMSL) 948 Store (PNLK, LNSL) 949 Store (OBFK, OBFZ) 950 } 951 Include("PchPcie.asl") 952 Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 state 953 Method(_PRT, 0) { 954 If(PICM) { Return(AR07) }// APIC mode 955 Return (PR07) // PIC Mode 956 } // end _PRT 957 } // end "PCIE Root Port #20" 958 959 // 960 // PCIE Root Port #21 961 // 962 Device(RP21) { 963 Method (_ADR, 0) { 964 If (LNotEqual(RPAL,0)) { 965 Return (RPAL) 966 } Else { 967 Return (0x001B0004) 968 } 969 } 970 // 971 // Pass LTRx to LTRZ so PchPcie.asl can be reused for PCIes. 972 // 973 Method(_INI) 974 { 975 Store (LTRL, LTRZ) 976 Store (PMLL, LMSL) 977 Store (PNLL, LNSL) 978 Store (OBFL, OBFZ) 979 } 980 Include("PchPcie.asl") 981 Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 state 982 Method(_PRT, 0) { 983 If(PICM) { Return(AR04) }// APIC mode 984 Return (PR04) // PIC Mode 985 } // end _PRT 986 } // end "PCIE Root Port #21" 987 988 // 989 // PCIE Root Port #21 990 // 991 Device(RP22) { 992 Method (_ADR, 0) { 993 If (LNotEqual(RPAM,0)) { 994 Return (RPAM) 995 } Else { 996 Return (0x001B0005) 997 } 998 } 999 // 1000 // Pass LTRx to LTRZ so PchPcie.asl can be reused for PCIes. 1001 // 1002 Method(_INI) 1003 { 1004 Store (LTRM, LTRZ) 1005 Store (PMLM, LMSL) 1006 Store (PNLM, LNSL) 1007 Store (OBFM, OBFZ) 1008 } 1009 Include("PchPcie.asl") 1010 Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 state 1011 Method(_PRT, 0) { 1012 If(PICM) { Return(AR05) }// APIC mode 1013 Return (PR05) // PIC Mode 1014 } // end _PRT 1015 } // end "PCIE Root Port #22" 1016 1017 // 1018 // PCIE Root Port #22 1019 // 1020 Device(RP23) { 1021 Method (_ADR, 0) { 1022 If (LNotEqual(RPAN,0)) { 1023 Return (RPAN) 1024 } Else { 1025 Return (0x001B0006) 1026 } 1027 } 1028 // 1029 // Pass LTRx to LTRZ so PchPcie.asl can be reused for PCIes. 1030 // 1031 Method(_INI) 1032 { 1033 Store (LTRN, LTRZ) 1034 Store (PMLN, LMSL) 1035 Store (PNLN, LNSL) 1036 Store (OBFN, OBFZ) 1037 } 1038 Include("PchPcie.asl") 1039 Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 state 1040 Method(_PRT, 0) { 1041 If(PICM) { Return(AR06) }// APIC mode 1042 Return (PR06) // PIC Mode 1043 } // end _PRT 1044 } // end "PCIE Root Port #23" 1045 1046 // 1047 // PCIE Root Port #21 1048 // 1049 Device(RP24) { 1050 Method (_ADR, 0) { 1051 If (LNotEqual(RPAO,0)) { 1052 Return (RPAO) 1053 } Else { 1054 Return (0x001B0007) 1055 } 1056 } 1057 // 1058 // Pass LTRx to LTRZ so PchPcie.asl can be reused for PCIes. 1059 // 1060 Method(_INI) 1061 { 1062 Store (LTRO, LTRZ) 1063 Store (PMLO, LMSL) 1064 Store (PNLO, LNSL) 1065 Store (OBFO, OBFZ) 1066 } 1067 Include("PchPcie.asl") 1068 Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 state 1069 Method(_PRT, 0) { 1070 If(PICM) { Return(AR07) }// APIC mode 1071 Return (PR07) // PIC Mode 1072 } // end _PRT 1073 } // end "PCIE Root Port #24" 1074 1075 // 1076 // Serial ATA Host Controller - Device 31, Function 2 1077 // 1078 Include ("PchSata.asl") 1079 1080 // 1081 // CIO2 ACPI device - Device 20, Function 3 1082 // 1083 Device (CIO2) { 1084 Method (_STA) { 1085 If (LEqual(CIOE,1)){ Return (0x0F) } 1086 Else { Return (0x00) } 1087 } 1088 Name(_HID, "INT343E") 1089 Method(_CRS, 0, NotSerialized) { 1090 Name(CBUF, ResourceTemplate () { 1091 Interrupt(ResourceConsumer, Level, ActiveLow, Shared,,,CIOD) {0x10} 1092 Memory32Fixed (ReadWrite, PCH_CIO2_BASE_ADDRESS, PCH_CIO2_MMIO_SIZE) 1093 }) 1094 CreateDWordField(CBUF,CIOD._INT,CIOV) 1095 Store(CIOI, CIOV) 1096 Return (CBUF) 1097 } 1098 } 1099 1100 // 1101 // Thermal Device 1102 // 1103 Device(TERM) { 1104 Name (_HID, "INT343D") 1105 Name (_UID, 1) 1106 1107 Method (_CRS, 0x0, NotSerialized) { 1108 Name (RBUF, ResourceTemplate () { 1109 Memory32Fixed (ReadWrite, PCH_THERMAL_BASE_ADDRESS, PCH_THERMAL_MMIO_SIZE, BAR0) 1110 Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , IRQ) { 18 } 1111 }) 1112 1113 CreateDWordField(RBUF,IRQ._INT,IRQN) 1114 1115 Store(TIRQ, IRQN) 1116 1117 Return (RBUF) 1118 } 1119 1120 Method (_STA, 0x0, NotSerialized) 1121 { 1122 If(LEqual(TAEN, 0)) { Return(0x0) } // device not enabled in ACPI mode 1123 If(LEqual(TIRQ, 0)) { Return(0x0) } // IRQ number not updated 1124 Return(0xF) 1125 } 1126 } 1127} 1128 1129 1130// 1131// Serial IO Controllers definitions 1132// 1133#define SERIAL_SCOPE \_SB.PCI0 1134Include ("PchSerialIo.asl") 1135 1136// 1137// Storage and Communication Subsystems definitions 1138// 1139Include ("PchScs.asl") 1140 1141// 1142// Integrated Sensor Hub definition 1143// 1144Include ("PchIsh.asl") 1145 1146// 1147// MEI 1 definition 1148// 1149Include ("PchHeci.asl") 1150 1151