1 /** @file 2 Header file for GpioConfig structure used by GPIO library. 3 4 Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> 5 SPDX-License-Identifier: BSD-2-Clause-Patent 6 **/ 7 #ifndef _GPIO_CONFIG_H_ 8 #define _GPIO_CONFIG_H_ 9 10 #pragma pack(push, 1) 11 12 /// 13 /// For any GpioPad usage in code use GPIO_PAD type 14 /// 15 typedef UINT32 GPIO_PAD; 16 17 /// 18 /// GpioPad with additional native function information. 19 /// This type is used to represent signal muxing alternatives. Platform will provide such value to 20 /// identify muxing selection for given signal on a specific SOC. 21 /// Please refer to the board layout 22 /// 23 typedef UINT32 GPIO_NATIVE_PAD; 24 25 26 /// 27 /// For any GpioGroup usage in code use GPIO_GROUP type 28 /// 29 typedef UINT32 GPIO_GROUP; 30 31 /** 32 GPIO configuration structure used for pin programming. 33 Structure contains fields that can be used to configure pad. 34 **/ 35 typedef struct { 36 /** 37 Pad Mode 38 Pad can be set as GPIO or one of its native functions. 39 When in native mode setting Direction (except Inversion), OutputState, 40 InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary. 41 Refer to definition of GPIO_PAD_MODE. 42 Refer to EDS for each native mode according to the pad. 43 **/ 44 UINT32 PadMode : 5; 45 /** 46 Host Software Pad Ownership 47 Set pad to ACPI mode or GPIO Driver Mode. 48 Refer to definition of GPIO_HOSTSW_OWN. 49 **/ 50 UINT32 HostSoftPadOwn : 2; 51 /** 52 GPIO Direction 53 Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both. 54 Refer to definition of GPIO_DIRECTION for supported settings. 55 **/ 56 UINT32 Direction : 6; 57 /** 58 Output State 59 Set Pad output value. 60 Refer to definition of GPIO_OUTPUT_STATE for supported settings. 61 This setting takes place when output is enabled. 62 **/ 63 UINT32 OutputState : 2; 64 /** 65 GPIO Interrupt Configuration 66 Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). 67 This setting is applicable only if GPIO is in GpioMode with input enabled. 68 Refer to definition of GPIO_INT_CONFIG for supported settings. 69 **/ 70 UINT32 InterruptConfig : 9; 71 /** 72 GPIO Power Configuration. 73 This setting controls Pad Reset Configuration. 74 Refer to definition of GPIO_RESET_CONFIG for supported settings. 75 **/ 76 UINT32 PowerConfig : 8; 77 /** 78 GPIO Electrical Configuration 79 This setting controls pads termination. 80 Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings. 81 **/ 82 UINT32 ElectricalConfig : 9; 83 /** 84 GPIO Lock Configuration 85 This setting controls pads lock. 86 Refer to definition of GPIO_LOCK_CONFIG for supported settings. 87 **/ 88 UINT32 LockConfig : 4; 89 /** 90 Additional GPIO configuration 91 Refer to definition of GPIO_OTHER_CONFIG for supported settings. 92 **/ 93 UINT32 OtherSettings : 9; 94 95 UINT32 RsvdBits : 10; ///< Reserved bits for future extension 96 } GPIO_CONFIG; 97 98 99 typedef enum { 100 GpioHardwareDefault = 0x0 ///< Leave setting unmodified 101 } GPIO_HARDWARE_DEFAULT; 102 103 /** 104 GPIO Pad Mode 105 Refer to GPIO documentation on native functions available for certain pad. 106 If GPIO is set to one of NativeX modes then following settings are not applicable 107 and can be skipped: 108 - Interrupt related settings 109 - Host Software Ownership 110 - Output/Input enabling/disabling 111 - Output lock 112 **/ 113 typedef enum { 114 GpioPadModeHwDefault = 0x0, 115 GpioPadModeGpio = 0x1, 116 GpioPadModeNative1 = 0x3, 117 GpioPadModeNative2 = 0x5, 118 GpioPadModeNative3 = 0x7, 119 GpioPadModeNative4 = 0x9, 120 GpioPadModeNative5 = 0xB, 121 GpioPadModeNative6 = 0xD, 122 GpioPadModeNative7 = 0xF 123 } GPIO_PAD_MODE; 124 125 /** 126 Host Software Pad Ownership modes 127 This setting affects GPIO interrupt status registers. Depending on chosen ownership 128 some GPIO Interrupt status register get updated and other masked. 129 Please refer to EDS for HOSTSW_OWN register description. 130 **/ 131 typedef enum { 132 GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified 133 /** 134 Set HOST ownership to ACPI. 135 Use this setting if pad is not going to be used by GPIO OS driver. 136 If GPIO is configured to generate SCI/SMI/NMI then this setting must be 137 used for interrupts to work 138 **/ 139 GpioHostOwnAcpi = 0x1, 140 /** 141 Set HOST ownership to GPIO Driver mode. 142 Use this setting only if GPIO pad should be controlled by GPIO OS Driver. 143 GPIO OS Driver will be able to control the pad if appropriate entry in 144 ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors) 145 **/ 146 GpioHostOwnGpio = 0x3 147 } GPIO_HOSTSW_OWN; 148 149 /// 150 /// GPIO Direction 151 /// 152 typedef enum { 153 GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified 154 GpioDirInOut = (0x1 | (0x1 << 3)), ///< Set pad for both output and input 155 GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion 156 GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only 157 GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion 158 GpioDirOut = 0x5, ///< Set pad for output only 159 GpioDirNone = 0x7 ///< Disable both output and input 160 } GPIO_DIRECTION; 161 162 /** 163 GPIO Output State 164 This field is relevant only if output is enabled 165 **/ 166 typedef enum { 167 GpioOutDefault = 0x0, ///< Leave output value unmodified 168 GpioOutLow = 0x1, ///< Set output to low 169 GpioOutHigh = 0x3 ///< Set output to high 170 } GPIO_OUTPUT_STATE; 171 172 /** 173 GPIO interrupt configuration 174 This setting is applicable only if pad is in GPIO mode and has input enabled. 175 GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI) 176 and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in 177 EDS for details on this settings. 178 Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge 179 to describe an interrupt e.g. GpioIntApic | GpioIntLevel 180 If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad. 181 If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad. 182 Not all GPIO are capable of generating an SMI or NMI interrupt. 183 When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this 184 interrupt cannot be shared and its IRQn number is not configurable. 185 Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel) 186 If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor 187 exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge). 188 This type of GPIO Driver interrupt doesn't have any additional routing setting 189 required to be set by BIOS. Interrupt is handled by GPIO OS Driver. 190 **/ 191 192 typedef enum { 193 GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified 194 GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation 195 GpioIntNmi = 0x3, ///< Enable NMI interrupt only 196 GpioIntSmi = 0x5, ///< Enable SMI interrupt only 197 GpioIntSci = 0x9, ///< Enable SCI interrupt only 198 GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only 199 GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered 200 GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion) 201 GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger 202 GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered 203 } GPIO_INT_CONFIG; 204 205 #define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source 206 #define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type 207 208 /** 209 GPIO Power Configuration 210 GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will 211 be used to reset certain GPIO settings. 212 Refer to EDS for settings that are controllable by PadRstCfg. 213 **/ 214 typedef enum { 215 GpioResetDefault = 0x00, ///< Leave value of pad reset unmodified 216 /** 217 Resume Reset (RSMRST) 218 GPP: PadRstCfg = 00b = "Powergood" 219 GPD: PadRstCfg = 11b = "Resume Reset" 220 Pad setting will reset on: 221 - DeepSx transition 222 - G3 223 Pad settings will not reset on: 224 - S3/S4/S5 transition 225 - Warm/Cold/Global reset 226 **/ 227 GpioResumeReset = 0x01, 228 /** 229 Host Deep Reset 230 PadRstCfg = 01b = "Deep GPIO Reset" 231 Pad settings will reset on: 232 - Warm/Cold/Global reset 233 - DeepSx transition 234 - G3 235 Pad settings will not reset on: 236 - S3/S4/S5 transition 237 **/ 238 GpioHostDeepReset = 0x03, 239 /** 240 Platform Reset (PLTRST) 241 PadRstCfg = 10b = "GPIO Reset" 242 Pad settings will reset on: 243 - S3/S4/S5 transition 244 - Warm/Cold/Global reset 245 - DeepSx transition 246 - G3 247 **/ 248 GpioPlatformReset = 0x05, 249 /** 250 Deep Sleep Well Reset (DSW_PWROK) 251 GPP: not applicable 252 GPD: PadRstCfg = 00b = "Powergood" 253 Pad settings will reset on: 254 - G3 255 Pad settings will not reset on: 256 - S3/S4/S5 transition 257 - Warm/Cold/Global reset 258 - DeepSx transition 259 **/ 260 GpioDswReset = 0x07 261 } GPIO_RESET_CONFIG; 262 263 /** 264 GPIO Electrical Configuration 265 Configuration options for GPIO termination setting 266 **/ 267 typedef enum { 268 GpioTermDefault = 0x0, ///< Leave termination setting unmodified 269 GpioTermNone = 0x1, ///< none 270 GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down 271 GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down 272 GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up 273 GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up 274 GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up 275 GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up 276 GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up 277 /** 278 Native function controls pads termination 279 This setting is applicable only to some native modes. 280 Please check EDS to determine which native functionality 281 can control pads termination 282 **/ 283 GpioTermNative = 0x1F 284 } GPIO_ELECTRICAL_CONFIG; 285 286 #define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value 287 288 /** 289 GPIO LockConfiguration 290 Set GPIO configuration lock and output state lock. 291 GpioPadConfigUnlock/Lock and GpioOutputStateUnlock can be OR'ed. 292 By default GPIO pads will be locked unless GPIO lib is explicitly 293 informed that certain pad is to be left unlocked. 294 Lock settings reset is in Powergood domain. Care must be taken when using this setting 295 as fields it locks may be reset by a different signal and can be controlled 296 by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides 297 functions which allow to unlock a GPIO pad. If possible each GPIO lib function will try to unlock 298 an already locked pad upon request for reconfiguration 299 **/ 300 typedef enum { 301 /** 302 Perform default action 303 - if pad is an GPO, lock configuration but leave output unlocked 304 - if pad is an GPI, lock everything 305 - if pad is in native, lock everything 306 **/ 307 GpioLockDefault = 0x0, 308 GpioPadConfigUnlock = 0x3, ///< Leave Pad configuration unlocked 309 GpioPadConfigLock = 0x1, ///< Lock Pad configuration 310 GpioOutputStateUnlock = 0xC, ///< Leave Pad output control unlocked 311 GpioPadUnlock = 0xF, ///< Leave both Pad configuration and output control unlocked 312 GpioPadLock = 0x5, ///< Lock both Pad configuration and output control 313 /** 314 Below statuses are used for 315 return from GpioGetPadConfig function 316 **/ 317 GpioLockTxLockCfgUnLock = 0x7, ///< Tx State locked, Pad Configuration unlocked 318 GpioLockTxUnLockCfgLock = 0xD ///< Tx State unlocked, Pad Configuration locked 319 } GPIO_LOCK_CONFIG; 320 321 #define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock 322 #define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0xC ///< Mask for GPIO_LOCK_CONFIG for Pad Output Lock 323 324 /** 325 Other GPIO Configuration 326 GPIO_OTHER_CONFIG is used for less often settings and for future extensions 327 Supported settings: 328 - RX raw override to '1' - allows to override input value to '1' 329 This setting is applicable only if in input mode (both in GPIO and native usage). 330 The override takes place at the internal pad state directly from buffer and before the RXINV. 331 **/ 332 typedef enum { 333 GpioRxRaw1Default = 0x0, ///< Use default input override value 334 GpioRxRaw1Dis = 0x1, ///< Don't override input 335 GpioRxRaw1En = 0x3 ///< Override input to '1' 336 } GPIO_OTHER_CONFIG; 337 338 #define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for GPIO_OTHER_CONFIG for RxRaw1 setting 339 340 #pragma pack(pop) 341 342 #endif //_GPIO_CONFIG_H_ 343